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[/] [sparc64soc/] [trunk/] [T1-CPU/] [lsu/] [lsu_qctl2.v] - Blame information for rev 2

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1 2 dmitryr
// ========== Copyright Header Begin ==========================================
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// 
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// OpenSPARC T1 Processor File: lsu_qctl2.v
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// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// 
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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// 
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// The above named program is distributed in the hope that it will be 
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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// General Public License for more details.
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// 
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
18
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// 
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// ========== Copyright Header End ============================================
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/////////////////////////////////////////////////////////////////////
22
/*
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//  Description:  LSU Queue Control for Sparc Core
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//      - includes monitoring for pcx queues
25
//      - control for lsu datapath
26
//      - rd/wr control of dfq
27
//
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*/
29
////////////////////////////////////////////////////////////////////////
30
// header file includes
31
////////////////////////////////////////////////////////////////////////
32
`include  "sys.h" // system level definition file which contains the 
33
                  // time scale definition
34
`include  "iop.h"
35
 
36
`include  "lsu.h"
37
 
38
////////////////////////////////////////////////////////////////////////
39
// Local header file includes / local defines
40
////////////////////////////////////////////////////////////////////////
41
 
42
module lsu_qctl2 ( /*AUTOARG*/
43
   // Outputs
44
   so, lsu_fwd_rply_sz1_unc, lsu_dcache_iob_rd_w, ldd_in_dfq_out,
45
   lsu_dfq_rd_vld_d1, dfq_byp_ff_en, lsu_dfill_data_sel_hi,
46
   lsu_ifill_pkt_vld, cpx_fwd_pkt_en_cx, lsu_cpxpkt_type_dcd_cx,
47
   lsu_cpu_dcd_sel, lsu_cpu_uhlf_sel, lsu_iobrdge_rply_data_sel,
48
   lsu_iobrdge_fwd_pkt_vld, lsu_tlu_cpx_vld, lsu_tlu_cpx_req,
49
   lsu_tlu_intpkt, ld_sec_active, dfq_byp_sel,
50
   lsu_cpx_ld_dtag_perror_e, lsu_cpx_ld_dcache_perror_e,
51
   lsu_exu_rd_m, lsu_spu_strm_ack_cmplt, lsu_atm_st_cmplt_e,
52
   dva_svld_e, dfq_wptr_vld, dfq_wptr, lsu_dfq_flsh_cmplt,
53
   dfq_rptr_vld, dfq_rptr, lsu_ifu_stallreq, dva_snp_addr_e,
54
   lsu_st_ack_dq_stb, lsu_cpx_rmo_st_ack, lsu_st_wr_dcache,
55
   cpx_st_ack_tid0, cpx_st_ack_tid1, cpx_st_ack_tid2,
56
   cpx_st_ack_tid3, lsu_tlu_l2_dmiss, lsu_l2fill_vld,
57
   lsu_byp_ldd_oddrd_m, lsu_pcx_fwd_reply, lsu_fwdpkt_vld,
58
   lsu_dcfill_active_e, lsu_dfq_ld_vld, lsu_fldd_vld_en,
59
   lsu_dfill_dcd_thrd, lsu_fwdpkt_dest, dva_snp_bit_wr_en_e,
60
   lsu_cpx_spc_inv_vld, lsu_cpx_thrdid, lsu_cpx_stack_dcfill_vld,
61
   lsu_dfq_vld_entry_w, lsu_cpx_stack_icfill_vld, lsu_dfq_st_vld,
62
   lsu_dfq_ldst_vld, lsu_qdp2_dfq_ld_vld, lsu_qdp2_dfq_st_vld,
63
   lsu_cpx_stack_dcfill_vld_b130, lsu_dfq_vld, lsu_dfq_byp_ff_en,
64
   // Inputs
65
   rclk, grst_l, arst_l, si, se, rst_tri_en, ld_inst_vld_e,
66
   ifu_pcx_pkt_b51, ifu_pcx_pkt_b41t40, ifu_pcx_pkt_b10t5,
67
   lsu_dfq_rdata_flush_bit, lsu_dfq_rdata_b17_b0,
68
   cpx_spc_data_cx_b144to140, cpx_spc_data_cx_b138,
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   cpx_spc_data_cx_b135to134,
70
   cpx_spc_data_cx_b133, cpx_spc_data_cx_b130, cpx_spc_data_cx_b129,
71
   cpx_spc_data_cx_b128, cpx_spc_data_cx_b125,
72
   cpx_spc_data_cx_b124to123, cpx_spc_data_cx_b120to118,
73
   cpx_spc_data_cx_b71to70, cpx_spc_data_cx_b0, cpx_spc_data_cx_b4,
74
   cpx_spc_data_cx_b8, cpx_spc_data_cx_b12, cpx_spc_data_cx_b16,
75
   cpx_spc_data_cx_b20, cpx_spc_data_cx_b24, cpx_spc_data_cx_b28,
76
   cpx_spc_data_cx_b32, cpx_spc_data_cx_b35, cpx_spc_data_cx_b38,
77
   cpx_spc_data_cx_b41, cpx_spc_data_cx_b44, cpx_spc_data_cx_b47,
78
   cpx_spc_data_cx_b50, cpx_spc_data_cx_b53, cpx_spc_data_cx_b56,
79
   cpx_spc_data_cx_b60, cpx_spc_data_cx_b64, cpx_spc_data_cx_b68,
80
   cpx_spc_data_cx_b72, cpx_spc_data_cx_b76, cpx_spc_data_cx_b80,
81
   cpx_spc_data_cx_b84, cpx_spc_data_cx_b88, cpx_spc_data_cx_b91,
82
   cpx_spc_data_cx_b94, cpx_spc_data_cx_b97, cpx_spc_data_cx_b100,
83
   cpx_spc_data_cx_b103, cpx_spc_data_cx_b106, cpx_spc_data_cx_b109,
84
   cpx_spc_data_cx_b1, cpx_spc_data_cx_b5, cpx_spc_data_cx_b9,
85
   cpx_spc_data_cx_b13, cpx_spc_data_cx_b17, cpx_spc_data_cx_b21,
86
   cpx_spc_data_cx_b25, cpx_spc_data_cx_b29, cpx_spc_data_cx_b57,
87
   cpx_spc_data_cx_b61, cpx_spc_data_cx_b65, cpx_spc_data_cx_b69,
88
   cpx_spc_data_cx_b73, cpx_spc_data_cx_b77, cpx_spc_data_cx_b81,
89
   cpx_spc_data_cx_b85, ifu_lsu_rd_e, lmq_ld_rd1, lmq_ldd_vld,
90
   dfq_tid, const_cpuid, lmq_ld_addr_b3, ifu_lsu_ibuf_busy,
91
   ifu_lsu_inv_clear, lsu_byp_misc_sz_e, lsu_dfq_byp_tid,
92
   lsu_cpx_pkt_atm_st_cmplt, lsu_cpx_pkt_l2miss, lsu_cpx_pkt_tid,
93
   lsu_cpx_pkt_invwy, lsu_dfq_byp_flush, lsu_dfq_byp_type,
94
   lsu_dfq_byp_invwy_vld, lsu_cpu_inv_data_b13to9,
95
   lsu_cpu_inv_data_b7to2, lsu_cpu_inv_data_b0, lsu_cpx_pkt_inv_pa,
96
   lsu_cpx_pkt_ifill_type, lsu_cpx_pkt_atomic, lsu_cpx_pkt_binit_st,
97
   lsu_cpx_pkt_prefetch, lsu_dfq_byp_binit_st, lsu_tlbop_force_swo,
98
   lsu_iobrdge_tap_rq_type, lsu_dcache_tag_perror_g,
99
   lsu_dcache_data_perror_g, lsu_cpx_pkt_perror_iinv,
100
   lsu_cpx_pkt_perror_dinv, lsu_cpx_pkt_perror_set,
101
   lsu_l2fill_fpld_e, lsu_cpx_pkt_strm_ack, ifu_lsu_memref_d,
102
   lsu_fwdpkt_pcx_rq_sel, lsu_imiss_pcx_rq_sel_d1,
103
   lsu_dfq_byp_cpx_inv, lsu_dfq_byp_stack_adr_b54,
104
   lsu_dfq_byp_stack_wrway, lsu_dfq_rdata_st_ack_type,
105
   lsu_dfq_rdata_stack_dcfill_vld, lsu_dfq_rdata_stack_iinv_vld,
106
   lsu_dfq_rdata_cpuid, lsu_dfq_byp_atm, lsu_ld_inst_vld_g,
107
   lsu_dfq_rdata_type, lsu_dfq_rdata_invwy_vld, ifu_lsu_fwd_data_vld,
108
   ifu_lsu_fwd_wr_ack, lsu_dfq_rdata_rq_type, lsu_dfq_rdata_b103,
109
   sehold
110
   ) ;
111
 
112
 
113
input     rclk ;
114
input     grst_l;
115
input     arst_l;
116
input     si;
117
input     se;
118
input     rst_tri_en;
119
output    so;
120
 
121
input                   ld_inst_vld_e;        // valid ld inst; d-stage
122
input                   ifu_pcx_pkt_b51;        // pcx pkt from ifu on imiss
123
input [1:0]             ifu_pcx_pkt_b41t40;     // pcx pkt from ifu on imiss
124
input [5:0]             ifu_pcx_pkt_b10t5;      // pcx pkt from ifu on imiss
125
//input                   cpx_spc_data_rdy_cx ;   // data ready to processor
126
//input [`CPX_WIDTH-1:71] cpx_spc_data_cx ;       // cpx to processor packet
127
//input [`CPX_WIDTH-1:0] cpx_spc_data_cx ;       // cpx to processor packet
128
//input [17:0]            cpx_spc_data_b17t0_cx ; // cpx to processor packet
129
   input                lsu_dfq_rdata_flush_bit;
130
   input [17:0]         lsu_dfq_rdata_b17_b0;
131
 
132
input [`CPX_WIDTH-1:140] cpx_spc_data_cx_b144to140 ;       // vld, req type
133
input                   cpx_spc_data_cx_b138 ;
134
//input                   cpx_spc_data_cx_b136 ;  
135
input [`CPX_TH_HI:`CPX_TH_LO] cpx_spc_data_cx_b135to134 ;  // thread id
136
input                   cpx_spc_data_cx_b133 ;
137
input                   cpx_spc_data_cx_b130 ;
138
input                   cpx_spc_data_cx_b129 ;
139
input                   cpx_spc_data_cx_b128 ;
140
input                   cpx_spc_data_cx_b125 ;
141
input [`CPX_PERR_DINV+1:`CPX_PERR_DINV] cpx_spc_data_cx_b124to123 ;  // inv packet iinv,dinv
142
input [`CPX_INV_CID_HI:`CPX_INV_CID_LO] cpx_spc_data_cx_b120to118 ;  // inv packet cpu id
143
input [1:0]             cpx_spc_data_cx_b71to70 ;
144
 
145
input        cpx_spc_data_cx_b0 ;
146
input        cpx_spc_data_cx_b4 ;
147
input        cpx_spc_data_cx_b8 ;
148
input        cpx_spc_data_cx_b12 ;
149
input        cpx_spc_data_cx_b16 ;
150
input        cpx_spc_data_cx_b20 ;
151
input        cpx_spc_data_cx_b24 ;
152
input        cpx_spc_data_cx_b28 ;
153
 
154
input        cpx_spc_data_cx_b32 ;
155
input        cpx_spc_data_cx_b35 ;
156
input        cpx_spc_data_cx_b38 ;
157
input        cpx_spc_data_cx_b41 ;
158
input        cpx_spc_data_cx_b44 ;
159
input        cpx_spc_data_cx_b47 ;
160
input        cpx_spc_data_cx_b50 ;
161
input        cpx_spc_data_cx_b53 ;
162
 
163
input        cpx_spc_data_cx_b56 ;
164
input        cpx_spc_data_cx_b60 ;
165
input        cpx_spc_data_cx_b64 ;
166
input        cpx_spc_data_cx_b68 ;
167
input        cpx_spc_data_cx_b72 ;
168
input        cpx_spc_data_cx_b76 ;
169
input        cpx_spc_data_cx_b80 ;
170
input        cpx_spc_data_cx_b84 ;
171
 
172
input        cpx_spc_data_cx_b88 ;
173
input        cpx_spc_data_cx_b91 ;
174
input        cpx_spc_data_cx_b94 ;
175
input        cpx_spc_data_cx_b97 ;
176
input        cpx_spc_data_cx_b100 ;
177
input        cpx_spc_data_cx_b103 ;
178
input        cpx_spc_data_cx_b106 ;
179
input        cpx_spc_data_cx_b109 ;
180
 
181
input        cpx_spc_data_cx_b1 ;
182
input        cpx_spc_data_cx_b5 ;
183
input        cpx_spc_data_cx_b9 ;
184
input        cpx_spc_data_cx_b13 ;
185
input        cpx_spc_data_cx_b17 ;
186
input        cpx_spc_data_cx_b21 ;
187
input        cpx_spc_data_cx_b25 ;
188
input        cpx_spc_data_cx_b29 ;
189
 
190
input        cpx_spc_data_cx_b57 ;
191
input        cpx_spc_data_cx_b61 ;
192
input        cpx_spc_data_cx_b65 ;
193
input        cpx_spc_data_cx_b69 ;
194
input        cpx_spc_data_cx_b73 ;
195
input        cpx_spc_data_cx_b77 ;
196
input        cpx_spc_data_cx_b81 ;
197
input        cpx_spc_data_cx_b85 ;
198
 
199
input [4:0]             ifu_lsu_rd_e ;          // rd for current load request.
200
//input                   lsu_ld_miss_g ;         // load misses in dcache.
201
input  [4:0]            lmq_ld_rd1 ;            // rd for all loads
202
input                   lmq_ldd_vld ;           // ld double   
203
//input                   ld_stb_full_raw_g ;    // full raw for load - thread0
204
//input                   ld_stb_partial_raw_g ; // partial raw for load - thread0
205
/*
206
input                   ld_sec_hit_thrd0 ;      // ld has sec. hit against th0
207
input                   ld_sec_hit_thrd1 ;      // ld has sec. hit against th1
208
input                   ld_sec_hit_thrd2 ;      // ld has sec. hit against th2
209
input                   ld_sec_hit_thrd3 ;      // ld has sec. hit against th3
210
*/
211
input   [1:0]           dfq_tid ;               // thread-id for load at head of DFQ. 
212
//input   [1:0]           dfq_byp_tid ;           // in-flight thread-id for load at head of DFQ. 
213
//input                   ldxa_internal ;         // internal ldxa, stg g 
214
//input [3:0]             ld_thrd_byp_sel ;       // stb,ldxa thread byp sel
215
input [2:0]             const_cpuid ;           // cpu id
216
input                   lmq_ld_addr_b3 ;        // bit3 of addr at head of queue.
217
//input                   ifu_tlu_inst_vld_m ;    // inst is vld - wstage
218
//input                   tlu_ifu_flush_pipe_w ;  // flush event in wstage
219
//input                   lsu_ldstub_g ;          // ldstub(a) instruction
220
//input                   lsu_swap_g ;            // swap(a) instruction 
221
//input                   tlu_lsu_pcxpkt_vld ;
222
//input [11:10]           tlu_lsu_pcxpkt_l2baddr ;
223
//input [19:18]           tlu_lsu_pcxpkt_tid ;
224
input                   ifu_lsu_ibuf_busy ;
225
input                   ifu_lsu_inv_clear ;
226
input   [1:0]           lsu_byp_misc_sz_e ;     // size for ldxa/raw etc
227
input   [1:0]           lsu_dfq_byp_tid ;
228
input                   lsu_cpx_pkt_atm_st_cmplt ;
229
input                   lsu_cpx_pkt_l2miss ;
230
input   [1:0]           lsu_cpx_pkt_tid ;
231
input   [1:0]           lsu_cpx_pkt_invwy ;     // invalidate way
232
input                   lsu_dfq_byp_flush ;
233
input   [5:0]           lsu_dfq_byp_type ;
234
input                   lsu_dfq_byp_invwy_vld ;
235
//input   [13:0]          lsu_cpu_inv_data ;
236
input   [13:9]          lsu_cpu_inv_data_b13to9 ;
237
input   [7:2]           lsu_cpu_inv_data_b7to2 ;
238
input                   lsu_cpu_inv_data_b0 ;
239
//input   [2:0]           lsu_dfq_byp_cpuid ;
240
input   [4:0]           lsu_cpx_pkt_inv_pa ;    // invalidate pa [10:6]
241
input                   lsu_cpx_pkt_ifill_type ;
242
//input                   stb_cam_hit ; REMOVED
243
input                   lsu_cpx_pkt_atomic ;
244
//input                   lsu_dfq_byp_stquad_pkt2 ;
245
//input                   lsu_cpx_pkt_stquad_pkt2 ;
246
input                   lsu_cpx_pkt_binit_st ;
247
input                   lsu_cpx_pkt_prefetch ;
248
input                   lsu_dfq_byp_binit_st ;
249
//input   [3:0]           lsu_stb_empty ;
250
input                   lsu_tlbop_force_swo ;
251
input   [7:3]           lsu_iobrdge_tap_rq_type ;
252
input                   lsu_dcache_tag_perror_g ;  // dcache tag parity error
253
input                   lsu_dcache_data_perror_g ; // dcache data parity error
254
//input                   lsu_dfq_byp_perror_dinv ;  // dtag perror corr. st ack
255
//input                   lsu_dfq_byp_perror_iinv ;  // itag perror corr. st ack
256
 
257
 
258
input                   lsu_cpx_pkt_perror_iinv ;   // itag perror corr. st ack
259
input                   lsu_cpx_pkt_perror_dinv ;   // dtag perror corr. st ack
260
input   [1:0]           lsu_cpx_pkt_perror_set ;   // dtag perror - spec. b54
261
//input                   lsu_diagnstc_wr_src_sel_e ;// dcache/dtag/vld
262
input                   lsu_l2fill_fpld_e ;      // fp load
263
input                   lsu_cpx_pkt_strm_ack ;
264
 
265
input                   ifu_lsu_memref_d ;
266
//input   [3:0]           lmq_enable;
267
//input   [3:0]           ld_pcx_rq_sel ;
268
input                   lsu_fwdpkt_pcx_rq_sel ;
269
//input                   lsu_ld0_pcx_rq_sel_d1, lsu_ld1_pcx_rq_sel_d1 ;
270
//input                   lsu_ld2_pcx_rq_sel_d1, lsu_ld3_pcx_rq_sel_d1 ;
271
input                   lsu_imiss_pcx_rq_sel_d1 ;
272
 
273
//input                   lsu_dc_iob_access_e;
274
 
275
//   input                mbist_dcache_write;
276
//   input                mbist_dcache_read;
277
 
278
 
279
input                   lsu_dfq_byp_cpx_inv ;
280
//input                 lsu_dfq_byp_stack_dcfill_vld ;
281
input  [1:0]            lsu_dfq_byp_stack_adr_b54;
282
input  [1:0]            lsu_dfq_byp_stack_wrway;
283
 
284
input                   lsu_dfq_rdata_st_ack_type;
285
input                   lsu_dfq_rdata_stack_dcfill_vld;
286
 
287
input                   lsu_dfq_rdata_stack_iinv_vld;
288
 
289
input  [2:0]            lsu_dfq_rdata_cpuid;
290
 
291
input                   lsu_dfq_byp_atm;
292
 
293
input   [3:0]            lsu_ld_inst_vld_g ;
294
 
295
input   [5:0]            lsu_dfq_rdata_type ;
296
input                   lsu_dfq_rdata_invwy_vld ;
297
 
298
input                   ifu_lsu_fwd_data_vld ; // icache ramtest read cmplt
299
input                   ifu_lsu_fwd_wr_ack ;   // icache ramtest wr cmplt
300
 
301
input   [3:0]            lsu_dfq_rdata_rq_type ;
302
input                   lsu_dfq_rdata_b103 ;
303
 
304
input                   sehold ;
305
 
306
output                  lsu_fwd_rply_sz1_unc ;
307
output                  lsu_dcache_iob_rd_w ;
308
 
309
output                  ldd_in_dfq_out;
310
 
311
output                  lsu_dfq_rd_vld_d1 ;
312
output                  dfq_byp_ff_en ;
313
output                  lsu_dfill_data_sel_hi;// select hi or low order 8B. 
314
output                  lsu_ifill_pkt_vld ;   // ifill pkt vld
315
output                  cpx_fwd_pkt_en_cx ;
316
output  [5:0]           lsu_cpxpkt_type_dcd_cx ;
317
output  [7:0]           lsu_cpu_dcd_sel ;
318
output                  lsu_cpu_uhlf_sel ;
319
//output                  lsu_st_wr_sel_e ;
320
//output  [1:0]           lsu_st_ack_addr_b54 ;
321
//output  [1:0]           lsu_st_ack_wrwy ;       // cache set way to write to.
322
 
323
output  [2:0]           lsu_iobrdge_rply_data_sel ;
324
output                  lsu_iobrdge_fwd_pkt_vld ;
325
output                  lsu_tlu_cpx_vld;    // cpx pkt vld
326
output  [3:0]           lsu_tlu_cpx_req;    // cpx pkt rq type
327
output  [17:0]          lsu_tlu_intpkt;     // cpx interrupt pkt
328
//output                  lsu_tlu_pcxpkt_ack; // ack for intr pkt.
329
//output  [3:0]           lsu_intrpt_cmplt ;      // intrpt can restart thread
330
//output                  lsu_ld_sec_hit_l2access_g ;
331
//output  [1:0]           lsu_ld_sec_hit_wy_g ;
332
output                  ld_sec_active ;     // secondary bypassing
333
output  [3:0]           dfq_byp_sel ;
334
//output  [3:0]           lsu_dfq_byp_mxsel ; // to qdp1
335
//output  [3:0]           lmq_byp_misc_sel ;    // select g-stage lmq source
336
//output                  lsu_pcx_ld_dtag_perror_w2 ;
337
output                  lsu_cpx_ld_dtag_perror_e ;
338
output                  lsu_cpx_ld_dcache_perror_e ;
339
//output  [1:0]           lsu_cpx_atm_st_err ;
340
//output                  lsu_ignore_fill ;
341
//output  [4:0]           lsu_exu_rd_w2 ;
342
output  [4:0]           lsu_exu_rd_m ;
343
output  [1:0]           lsu_spu_strm_ack_cmplt ;
344
output                  lsu_atm_st_cmplt_e ;  // atm st ack will restart thread
345
output                  dva_svld_e ;        // snoop is valid
346
output                  dfq_wptr_vld ;          // write pointer valid
347
output  [4:0]           dfq_wptr ;              // encoded write pointer
348
output  [3:0]           lsu_dfq_flsh_cmplt ;
349
output                  dfq_rptr_vld ;          // read pointer valid
350
output  [4:0]           dfq_rptr ;              // encoded read pointer
351
output                  lsu_ifu_stallreq ;      // cfq has crossed high-water mark
352
output  [4:0]           dva_snp_addr_e;         // Upper 5b of cache set index PA[10:6]
353
//output  [3:0]           dva_snp_set_vld_e;      // Lower 2b of cache set index - decoded
354
//output  [1:0]           dva_snp_wy0_e ;         // way for addr<5:4>=00
355
//output  [1:0]           dva_snp_wy1_e ;         // way for addr<5:4>=01
356
//output  [1:0]           dva_snp_wy2_e ;         // way for addr<5:4>=10
357
//output  [1:0]           dva_snp_wy3_e ;         // way for addr<5:4>=11
358
//output  [3:0]           lsu_st_ack_rq_stb ;
359
output  [3:0]           lsu_st_ack_dq_stb ;
360
output  [3:0]           lsu_cpx_rmo_st_ack ;    // rmo ack clears
361
output                  lsu_st_wr_dcache ;
362
output                  cpx_st_ack_tid0 ;   // st ack for thread0
363
output                  cpx_st_ack_tid1 ;   // st ack for thread1
364
output                  cpx_st_ack_tid2 ;   // st ack for thread2
365
output                  cpx_st_ack_tid3 ;   // st ack for thread3
366
output  [3:0]           lsu_tlu_l2_dmiss ;       // performance cntr
367
//output  [3:0]           lsu_ifu_stq_busy ;         // thread is busy with 1 stq - not used
368
output                  lsu_l2fill_vld ;        // dfill data vld
369
output                  lsu_byp_ldd_oddrd_m ; // rd fill for non-alt ldd
370
output                  lsu_pcx_fwd_reply ;   // fwd reply on pcx pkt
371
//output                  lsu_intrpt_pkt_vld ;
372
output                  lsu_fwdpkt_vld;
373
//output  [3:0]           lsu_error_rst ;
374
output                  lsu_dcfill_active_e;    // not same as dcfill_active_e; qual'ed w/ ignore_fill
375
//output                  lsu_dfq_byp_vld ;
376
output                  lsu_dfq_ld_vld;
377
output                  lsu_fldd_vld_en;
378
output  [3:0]           lsu_dfill_dcd_thrd ;
379
output  [4:0]           lsu_fwdpkt_dest ;
380
//output                  dcfill_src_dfq_sel ;    // ld-inv is src
381
output [15:0]        dva_snp_bit_wr_en_e;
382
 
383
//output [3:0]         lsu_dcfill_mx_sel_e;
384
//output               lsu_dcfill_addr_mx_sel_e;
385
//output               lsu_dcfill_data_mx_sel_e;
386
//output               lsu_dcfill_size_mx_sel_e;
387
 
388
output               lsu_cpx_spc_inv_vld;  // dfq write data in[152]
389
output [3:0]         lsu_cpx_thrdid;
390
output               lsu_cpx_stack_dcfill_vld ;
391
 
392
//output        [3:0]           lsu_dtag_perror_w2 ;
393
 
394
output                  lsu_dfq_vld_entry_w ;
395
 
396
output                  lsu_cpx_stack_icfill_vld ;
397
 
398
output                  lsu_dfq_st_vld;
399
output                  lsu_dfq_ldst_vld;
400
   //pref counter
401
//   output [3:0] lsu_cpx_pref_ack;
402
 
403
output                  lsu_qdp2_dfq_ld_vld;
404
output                  lsu_qdp2_dfq_st_vld;
405
 
406
output                  lsu_cpx_stack_dcfill_vld_b130;
407
 
408
output                  lsu_dfq_vld ;
409
 
410
output                  lsu_dfq_byp_ff_en ;
411
 
412
/*AUTOWIRE*/
413
// Beginning of automatic wires (for undeclared instantiated-module outputs)
414
// End of automatics
415
 
416
 
417
wire        cpx_local_st_ack_type ;
418
wire  [3:0] cpx_pkt_thrd_sel ;
419
//wire  [3:0] tap_thread ;
420
wire      cpx_reverse_req , cpx_reverse_req_d1 ;
421
wire    cpx_fwd_req,cpx_fwd_reply;
422
wire    fwdpkt_reset ;
423
wire        dfq_inv_vld ;
424
//wire    intrpt_vld_reset ;
425
//wire    intrpt_vld_en ;
426
//wire    ld0_sec_hit_g,ld1_sec_hit_g,ld2_sec_hit_g,ld3_sec_hit_g;
427
//wire  [3:0] intrpt_thread ;
428
wire    dfq_byp_ld_vld ;
429
//wire    intrpt_clr ;
430
wire    dfq_rptr_vld_d1 ;
431
wire    dfq_rd_advance ;
432
wire        dfq_wr_en, dfq_byp_full, dcfill_active_e ;
433
wire    dfq_thread0,dfq_thread1,dfq_thread2,dfq_thread3;
434
//wire    ld_any_thrd_byp_sel ;
435
wire    stwr_active_e,stdq_active_e ;
436
wire  [3:0] error_en ;
437
wire        ldd_vld_reset, ldd_vld_en, ldd_in_dfq_out ;
438
wire    ldd_non_alt_space ;
439
wire    ldd_oddrd_e ;
440
wire        inv_active_e ;
441
wire    dfq_st_vld ;
442
//wire    local_inv ;
443
wire    dfq_local_inv ;
444
//wire    st_ack_rq_stb_d1 ;
445
//wire    cpx_inv ;
446
wire    dfq_byp_inv_vld ;
447
wire    dfq_invwy_vld;
448
wire    local_pkt ;
449
wire    dfq_byp_st_vld ;
450
wire        dfq_vld_reset, dfq_vld_en ;
451
//wire  [3:0] st_wrwy_sel ;
452
//wire  [13:0]  cpx_cpu_inv_data ;
453
wire        dfq_vld_entry_exists ;
454
wire    cpx_st_ack_type,cpx_strm_st_ack_type,cpx_int_type;
455
wire    cpx_ld_type,cpx_ifill_type,cpx_evict_type;
456
wire  [5:0]     dfq_wptr_new_w_wrap ;   // 5b ptr with wrap bit.
457
wire  [5:0]     dfq_rptr_new_w_wrap ;   // 5b ptr with wrap bit.
458
wire  [5:0]     dfq_wptr_w_wrap ;   // 5b ptr with wrap bit.
459
//wire    i_and_d_codepend ;
460
wire    dfq_ld_type,dfq_ifill_type,dfq_evict_type ;
461
wire    dfq_st_ack_type,dfq_strm_st_ack_type,dfq_int_type;
462
wire  [5:0]     dfq_rptr_w_wrap ;   // 3b ptr with wrap bit.
463
wire  [3:0]   imiss_dcd_b54 ;
464
//wire    st_ack_rq_stb ;
465
//wire  [1:0] st_ack_tid ;
466
wire  [3:0] cpu_sel ;
467
wire  [1:0] fwdpkt_l2bnk_addr ;
468
//wire  [2:0] intrpt_l2bnk_addr ;
469
//wire  [3:0] dfq_byp_sel_m, dfq_byp_sel_g ;
470
//wire  [1:0] ld_error0,ld_error1,ld_error2,ld_error3 ;
471
//wire  [4:0] ld_l1hit_rd_m,ld_l1hit_rd_g;
472
wire  [4:0] ld_l1hit_rd_m;
473
//wire  [13:0]  dfq_inv_data ;
474
wire  [13:9]  dfq_inv_data_b13to9 ;
475
wire  [7:2]   dfq_inv_data_b7to2 ;
476
wire          dfq_inv_data_b0 ;
477
wire          fwdpkt_vld;
478
wire  [3:0]   dfill_dcd_thrd ;
479
wire  [3:0]   error_rst ;
480
wire          dfq_ld_vld;
481
wire          dfq_byp_vld ;
482
wire          reset;
483
wire          st_rd_advance;
484
wire    vld_dfq_pkt ;
485
wire          dfq_vld_entry_exists_w;
486
wire          dfq_rdata_local_pkt;
487
wire          dfq_st_cmplt ;
488
wire          cpx_fp_type ;
489
wire    dfq_stall, dfq_stall_d1 ;
490
wire          cpx_error_type ;
491
wire          dfq_error_type ;
492
wire          cpx_fwd_req_ic ;
493
wire          dfq_fwd_req_ic_type ;
494
wire          dfq_rd_vld_d1 ;
495
 
496
 
497
    dffrl_async rstff(.din (grst_l),
498
                        .q   (dbb_reset_l),
499
                        .clk (clk), .se(se), .si(), .so(),
500
                        .rst_l (arst_l));
501
 
502
assign  reset  =  ~dbb_reset_l;
503
assign  clk = rclk;
504
 
505
 
506
 
507
//wire                   lsu_bist_wvld_e;
508
//wire                   lsu_bist_rvld_e;
509
 
510
//dff #(2) mbist_stge (
511
//   .din ({mbist_dcache_write, mbist_dcache_read}),
512
//   .q   ({lsu_bist_wvld_e,    lsu_bist_rvld_e  }),
513
//   .clk (clk),
514
//   .se  (1'b0),       .si (),          .so ()
515
//);   
516
 
517
//=================================================================================================
518
// SHADOW SCAN
519
//=================================================================================================
520
 
521
// Monitors whether there is a valid entry in the dfq.
522
assign  lsu_dfq_vld_entry_w = dfq_vld_entry_exists_w ;
523
// Monitors whether dfq_byp flop remains full
524
//assign        lsu_sscan_data[?] = dfq_byp_full ;
525
 
526
//=================================================================================================
527
//
528
// QDP2 Specific Control
529
//
530
//=================================================================================================
531
 
532
// Need to be careful. This may prevent stores
533
//assign  dcfill_src_dfq_sel = dcfill_active_e ;
534
 
535
 
536
 
537
 
538
 
539
//=================================================================================================
540
//  IMISS X-INVALIDATION
541
//=================================================================================================
542
 
543
// Assume all imisses are alligned to a 32B boundary in L2 ?
544
 
545
wire  imiss0_inv_en, imiss1_inv_en ;
546
wire  imiss2_inv_en, imiss3_inv_en ;
547
wire  [10:5] imiss0_set_index,imiss1_set_index ;
548
wire  [10:5] imiss2_set_index,imiss3_set_index ;
549
//8/28/03 - vlint cleanup
550
//wire  [10:4] imiss0_set_index,imiss1_set_index ;
551
//wire  [10:4] imiss2_set_index,imiss3_set_index ;
552
 
553
assign  imiss0_inv_en = ifu_pcx_pkt_b51 & ~ifu_pcx_pkt_b41t40[1] & ~ifu_pcx_pkt_b41t40[0] & lsu_imiss_pcx_rq_sel_d1 ;
554
assign  imiss1_inv_en = ifu_pcx_pkt_b51 & ~ifu_pcx_pkt_b41t40[1] &  ifu_pcx_pkt_b41t40[0] & lsu_imiss_pcx_rq_sel_d1 ;
555
assign  imiss2_inv_en = ifu_pcx_pkt_b51 &  ifu_pcx_pkt_b41t40[1] & ~ifu_pcx_pkt_b41t40[0] & lsu_imiss_pcx_rq_sel_d1 ;
556
assign  imiss3_inv_en = ifu_pcx_pkt_b51 &  ifu_pcx_pkt_b41t40[1] &  ifu_pcx_pkt_b41t40[0] & lsu_imiss_pcx_rq_sel_d1 ;
557
 
558
dffe_s #(6) imiss_inv0 (
559
        .din    ({ifu_pcx_pkt_b10t5[5:0]}),
560
        .q      ({imiss0_set_index[10:5]}),
561
        .en (imiss0_inv_en),
562
        .clk  (clk),
563
        .se     (1'b0),       .si (),          .so ()
564
        );
565
 
566
dffe_s #(6) imiss_inv1 (
567
        .din    ({ifu_pcx_pkt_b10t5[5:0]}),
568
        .q      ({imiss1_set_index[10:5]}),
569
        .en (imiss1_inv_en),
570
        .clk  (clk),
571
        .se     (1'b0),       .si (),          .so ()
572
        );
573
 
574
dffe_s #(6) imiss_inv2 (
575
        .din    ({ifu_pcx_pkt_b10t5[5:0]}),
576
        .q      ({imiss2_set_index[10:5]}),
577
        .en (imiss2_inv_en),
578
        .clk  (clk),
579
        .se     (1'b0),       .si (),          .so ()
580
        );
581
 
582
dffe_s #(6) imiss_inv3 (
583
        .din    ({ifu_pcx_pkt_b10t5[5:0]}),
584
        .q      ({imiss3_set_index[10:5]}),
585
        .en (imiss3_inv_en),
586
        .clk  (clk),
587
        .se     (1'b0),       .si (),          .so ()
588
        );
589
 
590
assign  cpx_pkt_thrd_sel[0] = ~lsu_cpx_pkt_tid[1] & ~lsu_cpx_pkt_tid[0] ;
591
assign  cpx_pkt_thrd_sel[1] = ~lsu_cpx_pkt_tid[1] &  lsu_cpx_pkt_tid[0] ;
592
assign  cpx_pkt_thrd_sel[2] =  lsu_cpx_pkt_tid[1] & ~lsu_cpx_pkt_tid[0] ;
593
assign  cpx_pkt_thrd_sel[3] =  lsu_cpx_pkt_tid[1] &  lsu_cpx_pkt_tid[0] ;
594
// This needs to be included once the change for the stb bug is complete
595
wire  [6:1] imiss_inv_set_index ;
596
assign  imiss_inv_set_index[6:1] =
597
  cpx_pkt_thrd_sel[0] ? imiss0_set_index[10:5] :
598
    cpx_pkt_thrd_sel[1] ? imiss1_set_index[10:5] :
599
      cpx_pkt_thrd_sel[2] ? imiss2_set_index[10:5] :
600
        cpx_pkt_thrd_sel[3] ? imiss3_set_index[10:5] : 6'bxx_xxxx ;
601
 
602
 
603
 
604
//=================================================================================================
605
//  FWD REPLY/REQUEST
606
//=================================================================================================
607
 
608
// cpx pkt decode. fwd req/reply do not go into dfq.
609
 
610
 
611
//assign  tap_thread[0] = ~lsu_iobrdge_tap_rq_type[1] & ~lsu_iobrdge_tap_rq_type[0] ;
612
//assign  tap_thread[1] = ~lsu_iobrdge_tap_rq_type[1] &  lsu_iobrdge_tap_rq_type[0] ;
613
//assign  tap_thread[2] =  lsu_iobrdge_tap_rq_type[1] & ~lsu_iobrdge_tap_rq_type[0] ;
614
//assign  tap_thread[3] =  lsu_iobrdge_tap_rq_type[1] &  lsu_iobrdge_tap_rq_type[0] ;
615
 
616
// This is the pkt from the TAP to be returned to the TAP
617
//assign  cpx_reverse_req = cpx_spc_data_cx[130] ;
618
assign  cpx_reverse_req = cpx_spc_data_cx_b130;
619
 
620
// removed tap_rq_type[2] from the data_sel logic
621
assign  lsu_iobrdge_rply_data_sel[0] =  // defeature, margin, bist
622
  (|lsu_iobrdge_tap_rq_type[5:3]) & cpx_reverse_req_d1 ;
623
assign  lsu_iobrdge_rply_data_sel[1] =  // i/dcache
624
  (|lsu_iobrdge_tap_rq_type[7:6] & ~(|lsu_iobrdge_tap_rq_type[5:3])) & cpx_reverse_req_d1 ;
625
// regular fwd pkt
626
//  - sothea - 0in bug - can be 0-hot
627
//assign  lsu_iobrdge_rply_data_sel[2] = ~((|lsu_iobrdge_tap_rq_type[7:3]) & cpx_reverse_req_d1) ;
628
assign  lsu_iobrdge_rply_data_sel[2] = ~|lsu_iobrdge_rply_data_sel[1:0] ;
629
 
630
wire dcache_iob_rd,dcache_iob_rd_e, dcache_iob_rd_m, dcache_iob_rd_w ;
631
assign  dcache_iob_rd = lsu_iobrdge_tap_rq_type[6] & lsu_iobrdge_fwd_pkt_vld ;
632
 
633
dff_s  dciob_rd_e (
634
        .din    (dcache_iob_rd),
635
        .q      (dcache_iob_rd_e),
636
        .clk    (clk),
637
        .se     (1'b0),       .si (),          .so ()
638
        );
639
 
640
dff_s  dciob_rd_m (
641
        .din    (dcache_iob_rd_e),
642
        .q      (dcache_iob_rd_m),
643
        .clk    (clk),
644
        .se     (1'b0),       .si (),          .so ()
645
        );
646
 
647
dff_s  dciob_rd_w (
648
        .din    (dcache_iob_rd_m),
649
        .q      (dcache_iob_rd_w),
650
        .clk    (clk),
651
        .se     (1'b0),       .si (),          .so ()
652
        );
653
 
654
assign  lsu_dcache_iob_rd_w = dcache_iob_rd_w ;
655
 
656
wire  cpx_fwd_rq_type ;
657
assign  cpx_fwd_rq_type =
658
        cpx_spc_data_cx_b144to140[`CPX_RQ_HI]   & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+2] & // fwd req
659
        cpx_spc_data_cx_b144to140[`CPX_RQ_LO+1] & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO];
660
wire  cpx_fwd_rply_type ;
661
assign  cpx_fwd_rply_type =
662
        cpx_spc_data_cx_b144to140[`CPX_RQ_HI]   & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+2] & // fwd reply
663
        cpx_spc_data_cx_b144to140[`CPX_RQ_LO+1] &  cpx_spc_data_cx_b144to140[`CPX_RQ_LO] ;
664
 
665
// cpx pkt decode. fwd req/reply do not go into dfq.
666
assign  cpx_fwd_req =
667
         cpx_spc_data_cx_b144to140[`CPX_VLD] & ~cpx_reverse_req & cpx_fwd_rq_type ;
668
 
669
//8/25/03: add fwd req to L1I$ for RAMTEST to dfq_wr_en, dfq_rd_dvance
670
//bug4293 - set fwd_req_ic based on cpx_fwd_req_type and not based on cpx_fwd_req. this causes the request to 
671
//          de dropped i.e. not written into dfq 'cos cpx_fwd_req_ic is not set
672
//assign  cpx_fwd_req_ic =  cpx_fwd_req & cpx_spc_data_cx_b103 ;
673
 
674
assign  cpx_fwd_req_ic =  cpx_spc_data_cx_b144to140[`CPX_VLD] & cpx_fwd_rq_type &
675
                          cpx_reverse_req & cpx_spc_data_cx_b103 ;
676
 
677
assign  cpx_fwd_pkt_en_cx = cpx_fwd_req | cpx_fwd_reply ;
678
 
679
assign  cpx_fwd_reply =
680
         cpx_spc_data_cx_b144to140[`CPX_VLD] & (cpx_fwd_rply_type | (cpx_fwd_rq_type & cpx_reverse_req)) ;
681
 
682
dff_s #(1) fwdpkt_stgd1 (
683
        .din    (fwd_reply_vld),
684
        .q      (lsu_pcx_fwd_reply),
685
        .clk    (clk),
686
        .se     (1'b0),       .si (),          .so ()
687
        );
688
 
689
 
690
// Requests from iobrdge will not be speculative as core is expected to be quiescent.
691
assign  fwdpkt_reset =
692
  (reset | lsu_fwdpkt_pcx_rq_sel) ;
693
  // (reset | (lsu_fwdpkt_pcx_rq_sel & ~pcx_req_squash)) ; 
694
wire    fwdpkt_vld_unmasked,fwdpkt_vld_unmasked_d1 ;
695
wire    fwd_unc_err ;
696
// There can be only one outstanding fwd reply or request.
697
dffre_s #(7)  fwdpkt_ff (
698
        .din    ({cpx_fwd_pkt_en_cx,cpx_fwd_req,cpx_fwd_reply,
699
                cpx_spc_data_cx_b138,cpx_spc_data_cx_b71to70[1:0], cpx_reverse_req}),
700
        .q      ({fwdpkt_vld_unmasked,fwd_req_vld,fwd_reply_vld,
701
                fwd_unc_err,fwdpkt_l2bnk_addr[1:0],cpx_reverse_req_d1}),
702
  .rst  (fwdpkt_reset), .en (cpx_fwd_pkt_en_cx),
703
        .clk  (clk),
704
        .se     (1'b0),       .si (),          .so ()
705
        );
706
 
707
wire    fwd_rply_sz1_unc ; // Either size[1] for fwd-rq or unc-err for fwd-rply.
708
assign  fwd_rply_sz1_unc = fwd_reply_vld ? fwd_unc_err : 1'b1 ;
709
 
710
dff_s  fpktunc_d1 (
711
        .din    (fwd_rply_sz1_unc),
712
        .q      (lsu_fwd_rply_sz1_unc),
713
        .clk    (clk),
714
        .se     (1'b0),       .si (),          .so ()
715
        );
716
 
717
dff_s  fpktv_d1 (
718
        .din    (fwdpkt_vld_unmasked),
719
        .q      (fwdpkt_vld_unmasked_d1),
720
        .clk    (clk),
721
        .se     (1'b0),       .si (),          .so ()
722
        );
723
 
724
 
725
wire icache_rd_done,icache_wr_done ;
726
dff_s #(2) ifwd_d1 (
727
        .din    ({ifu_lsu_fwd_data_vld,ifu_lsu_fwd_wr_ack}),
728
        .q      ({icache_rd_done,icache_wr_done}),
729
        .clk    (clk),
730
        .se     (1'b0),       .si (),          .so ()
731
        );
732
 
733
// make one-shot : read data may be off.
734
assign  lsu_iobrdge_fwd_pkt_vld = fwdpkt_vld_unmasked & ~fwdpkt_vld_unmasked_d1 & cpx_reverse_req_d1 ;
735
//assign  lsu_iobrdge_fwd_pkt_vld = fwdpkt_vld ;
736
assign  fwdpkt_vld =
737
        // immediate for all but dcache rd.
738
        (fwdpkt_vld_unmasked & ~((|lsu_iobrdge_tap_rq_type[7:6]) & cpx_reverse_req_d1)) |
739
        // dcache rd - wait until w.
740
        (fwdpkt_vld_unmasked &  lsu_iobrdge_tap_rq_type[6] & cpx_reverse_req_d1 &
741
                ~(dcache_iob_rd | dcache_iob_rd_e | dcache_iob_rd_m | dcache_iob_rd_w)) |
742
        // icache rd - wait for rd & wr 
743
        (fwdpkt_vld_unmasked &  lsu_iobrdge_tap_rq_type[7] & cpx_reverse_req_d1 &
744
                        (icache_rd_done | icache_wr_done)) ;
745
 
746
assign  lsu_fwdpkt_vld  =  fwdpkt_vld;
747
 
748
assign  lsu_fwdpkt_dest[0] = fwd_req_vld & ~fwdpkt_l2bnk_addr[1] & ~fwdpkt_l2bnk_addr[0] ; // l2bank=0
749
assign  lsu_fwdpkt_dest[1] = fwd_req_vld & ~fwdpkt_l2bnk_addr[1] &  fwdpkt_l2bnk_addr[0] ; // l2bank=1
750
assign  lsu_fwdpkt_dest[2] = fwd_req_vld &  fwdpkt_l2bnk_addr[1] & ~fwdpkt_l2bnk_addr[0] ; // l2bank=2
751
assign  lsu_fwdpkt_dest[3] = fwd_req_vld &  fwdpkt_l2bnk_addr[1] &  fwdpkt_l2bnk_addr[0] ; // l2bank=3
752
assign  lsu_fwdpkt_dest[4] = fwd_reply_vld ; // reply always goes back to IO Bridge
753
 
754
//=================================================================================================
755
//  INTERRUPT CPX PKT REQ CTL
756
//=================================================================================================
757
 
758
//bug6322
759
//assign  lsu_tlu_cpx_vld = cpx_spc_data_cx_b144to140[`CPX_VLD] & ~cpx_spc_data_cx_b136 ;
760
//assign  lsu_tlu_cpx_req[3:0] = cpx_spc_data_cx_b144to140[`CPX_RQ_HI:`CPX_RQ_LO] ;
761
//assign  lsu_tlu_intpkt[17:0] = cpx_spc_data_b17t0_cx[17:0] ;
762
 
763
   wire lsu_tlu_cpx_vld_din_l;
764
   wire [17:0] lsu_tlu_intpkt_din;
765
   wire [3:0]  lsu_tlu_cpx_req_din_l;
766
 
767
assign  lsu_tlu_cpx_vld_din_l = ~(dfq_int_type & ~lsu_dfq_rdata_flush_bit & dfq_rd_advance) ;
768
assign  lsu_tlu_intpkt_din[17:0] = lsu_dfq_rdata_b17_b0[17:0] ;
769
assign  lsu_tlu_cpx_req_din_l[3:0] = ~ lsu_dfq_rdata_rq_type[3:0];
770
 
771
   wire lsu_tlu_cpx_vld_l;
772
   wire [3:0] lsu_tlu_cpx_req_l;
773
 
774
dff_s  #(23) lsu_tlu_stg (
775
        .din    ({lsu_tlu_cpx_vld_din_l, lsu_tlu_intpkt_din[17:0], lsu_tlu_cpx_req_din_l[3:0]}),
776
        .q      ({lsu_tlu_cpx_vld_l,     lsu_tlu_intpkt[17:0], lsu_tlu_cpx_req_l[3:0]}),
777
        .clk    (clk),
778
        .se     (1'b0),       .si (),          .so ()
779
        );
780
 
781
   assign     lsu_tlu_cpx_vld = ~lsu_tlu_cpx_vld_l;
782
   assign     lsu_tlu_cpx_req[3:0] = ~lsu_tlu_cpx_req_l[3:0];
783
 
784
//=================================================================================================
785
//  STQUAD PKT CONTROL
786
//=================================================================================================
787
 
788
 
789
 
790
 
791
 
792
//=================================================================================================
793
// SECONDARY VS. PRIMARY LOADS
794
//=================================================================================================
795
 
796
 
797
// NOT USED
798
//wire  [1:0] dfq_sel_tid ;
799
//assign  dfq_sel_tid[1:0] = 
800
//  // select byp tid if ld from cfq or cpx will be latched in byp ff next cycle
801
//  (dfq_byp_ld_vld & ((dfq_rptr_vld_d1 & dfq_rd_advance) | (cpx_spc_data_cx_b144to140[`CPX_VLD] & ~dfq_wr_en))) ? 
802
//  dfq_byp_tid[1:0] : dfq_tid[1:0] ;
803
 
804
//temp, send to dctl, phase 2     
805
assign  ld_sec_active = 1'b0 ;
806
 
807
assign  dfq_thread0 = ~dfq_tid[1] & ~dfq_tid[0] ;
808
assign  dfq_thread1 = ~dfq_tid[1] &  dfq_tid[0] ;
809
assign  dfq_thread2 =  dfq_tid[1] & ~dfq_tid[0] ;
810
assign  dfq_thread3 =  dfq_tid[1] &  dfq_tid[0] ;
811
 
812
// NOT USED
813
//assign  ld_any_thrd_byp_sel = |(ld_thrd_byp_sel[3:0]);
814
 
815
// phase 2 change   
816
// L2$ sends response for both prim and sec requests. Both will go into DFQ
817
// and fill D$
818
// can we eliminate dcfill_active_e ?
819
 
820
//11/7/03 - add rst_tri_en
821
wire  [3:0]  dfq_byp_sel_tmp ;
822
   assign dfq_byp_sel_tmp[0]  = dfq_thread0  & dcfill_active_e & ~lsu_cpx_pkt_prefetch;
823
   assign dfq_byp_sel_tmp[1]  = dfq_thread1  & dcfill_active_e & ~lsu_cpx_pkt_prefetch;
824
   assign dfq_byp_sel_tmp[2]  = dfq_thread2  & dcfill_active_e & ~lsu_cpx_pkt_prefetch;
825
   assign dfq_byp_sel_tmp[3]  = dfq_thread3  & dcfill_active_e & ~lsu_cpx_pkt_prefetch;
826
 
827
   assign dfq_byp_sel[2:0]  =  dfq_byp_sel_tmp[2:0]  & {3{~rst_tri_en}} ;
828
   assign dfq_byp_sel[3]    =  dfq_byp_sel_tmp[3]    | rst_tri_en ;
829
 
830
//   assign lsu_dfq_byp_mxsel[0]  = dfq_thread0  & dcfill_active_e;
831
//   assign lsu_dfq_byp_mxsel[1]  = dfq_thread1  & dcfill_active_e;
832
//   assign lsu_dfq_byp_mxsel[2]  = dfq_thread2  & dcfill_active_e;
833
//   assign lsu_dfq_byp_mxsel[3]  = ~|lsu_dfq_byp_mxsel[2:0];
834
 
835
// includes store cmplt tid also. 
836
assign  dfill_dcd_thrd[0] =   dfq_byp_sel[0] |    // for load
837
        (dfq_thread0 & stdq_active_e)  ;// for store
838
assign  dfill_dcd_thrd[1] =   dfq_byp_sel[1] |    // for load
839
        (dfq_thread1 & stdq_active_e)  ;// for store
840
assign  dfill_dcd_thrd[2] =   dfq_byp_sel[2] |    // for load
841
        (dfq_thread2 & stdq_active_e)  ;// for store
842
assign  dfill_dcd_thrd[3] =   dfq_byp_sel[3] |    // for load
843
        (dfq_thread3 & stdq_active_e)  ;// for store
844
 
845
assign  lsu_dfill_dcd_thrd[3:0]  =  dfill_dcd_thrd[3:0];
846
 
847
//=================================================================================================
848
//  Error Related Logic
849
//=================================================================================================
850
 
851
// Equivalent of lmq but lmq has run out of bits
852
// Following bits need to be logged.
853
// Dtag parity error 
854
//  - output on bit 130 of equivalent ld pkt
855
//  - when cpx pkt is at head of cfq, then log error
856
//  and take corresponding trap synchronous to pipe.
857
// DCache parity error
858
//  - when cpx pkt is at head of cfq, then log error
859
//  and take corresponding trap synchronous to pipe.
860
 
861
 
862
// The load component of the cpx response for an atomic will
863
// save it's error info for the store component. The store
864
// component will take the trap in the g stage, depending
865
// on the error information from the ld. However, it can
866
// always override the parity error info initially written,
867
// as atomics do not lookup the cache or tag.
868
 
869
 
870
//assign  error_en[0] = lmq_enable[0] | (lsu_cpx_pkt_atm_st_cmplt & dcfill_active_e & dfq_byp_sel[0]);
871
assign  error_en[0] =
872
        //lsu_ld_inst_vld_g[0] | (lsu_cpx_pkt_atm_st_cmplt & dcfill_active_e & dfq_byp_sel[0]); // Bug 3624
873
        lsu_ld_inst_vld_g[0] ;
874
assign  error_en[1] =
875
        lsu_ld_inst_vld_g[1] ;
876
assign  error_en[2] =
877
        lsu_ld_inst_vld_g[2] ;
878
assign  error_en[3] =
879
        lsu_ld_inst_vld_g[3] ;
880
 
881
// 10/15/03: error reset is set only by reset. lsu_ld[0-3]_pcx_rq_sel_d1 is not needed because the
882
//           the flop is used only for reporting error to ifu. Also, the error_en is set for new requests.
883
//tmp fix for reset
884
//wire              lsu_pcx_ld_dtag_perror_w2 ;
885
//assign lsu_pcx_ld_dtag_perror_w2  = 1'b0;
886
 
887
//assign  error_rst[0] = reset | (lsu_ld0_pcx_rq_sel_d1 & lsu_pcx_ld_dtag_perror_w2) ;
888
//assign  error_rst[1] = reset | (lsu_ld1_pcx_rq_sel_d1 & lsu_pcx_ld_dtag_perror_w2) ;
889
//assign  error_rst[2] = reset | (lsu_ld2_pcx_rq_sel_d1 & lsu_pcx_ld_dtag_perror_w2) ;
890
//assign  error_rst[3] = reset | (lsu_ld3_pcx_rq_sel_d1 & lsu_pcx_ld_dtag_perror_w2) ;
891
 
892
assign  error_rst[0] = reset ;
893
assign  error_rst[1] = reset ;
894
assign  error_rst[2] = reset ;
895
assign  error_rst[3] = reset ;
896
 
897
//assign  lsu_error_rst[3:0]  =  error_rst[3:0];
898
 
899
wire    dtag_perror3,dtag_perror2,dtag_perror1,dtag_perror0;
900
 
901
// Thread 0
902
dffre_s  #(2) error_t0 (
903
        .din    ({lsu_dcache_tag_perror_g,lsu_dcache_data_perror_g}),
904
    //lsu_cpx_pkt_ld_err[1:0]}),
905
        .q      ({dtag_perror0,dcache_perror0}),
906
        //.q      ({dtag_perror0,dcache_perror0,ld_error0[1:0]}),
907
        .rst  (error_rst[0]), .en     (error_en[0]),
908
        .clk    (clk),
909
        .se     (1'b0),       .si (),          .so ()
910
        );
911
 
912
// Thread 1
913
dffre_s  #(2) error_t1 (
914
        .din    ({lsu_dcache_tag_perror_g,lsu_dcache_data_perror_g}),
915
    //lsu_cpx_pkt_ld_err[1:0]}),
916
        .q      ({dtag_perror1,dcache_perror1}),
917
        //.q      ({dtag_perror1,dcache_perror1,ld_error1[1:0]}),
918
        .rst  (error_rst[1]), .en     (error_en[1]),
919
        .clk    (clk),
920
        .se     (1'b0),       .si (),          .so ()
921
        );
922
 
923
// Thread 2
924
dffre_s  #(2) error_t2 (
925
        .din    ({lsu_dcache_tag_perror_g,lsu_dcache_data_perror_g}),
926
    //lsu_cpx_pkt_ld_err[1:0]}),
927
        .q      ({dtag_perror2,dcache_perror2}),
928
        //.q      ({dtag_perror2,dcache_perror2,ld_error2[1:0]}),
929
        .rst  (error_rst[2]), .en     (error_en[2]),
930
        .clk    (clk),
931
        .se     (1'b0),       .si (),          .so ()
932
        );
933
 
934
// Thread 3
935
dffre_s  #(2) error_t3 (
936
        .din    ({lsu_dcache_tag_perror_g,lsu_dcache_data_perror_g}),
937
    //lsu_cpx_pkt_ld_err[1:0]}),
938
        .q      ({dtag_perror3,dcache_perror3}),
939
        //.q      ({dtag_perror3,dcache_perror3,ld_error3[1:0]}),
940
        .rst  (error_rst[3]), .en     (error_en[3]),
941
        .clk    (clk),
942
        .se     (1'b0),       .si (),          .so ()
943
        );
944
 
945
//assign        lsu_dtag_perror_w2[3] = dtag_perror3 ;
946
//assign        lsu_dtag_perror_w2[2] = dtag_perror2 ;
947
//assign        lsu_dtag_perror_w2[1] = dtag_perror1 ;
948
//assign        lsu_dtag_perror_w2[0] = dtag_perror0 ;
949
 
950
// Determine if ld pkt requires correction due to dtag parity error.
951
//5/22/03: moved to qctl1
952
//assign  lsu_pcx_ld_dtag_perror_w2 =
953
//  ld_pcx_rq_sel[0] ? dtag_perror0 :
954
//    ld_pcx_rq_sel[1] ? dtag_perror1 :
955
//      ld_pcx_rq_sel[2] ? dtag_perror2 : dtag_perror3 ;
956
 
957
// Now post sparc related errors and take traps
958
// error is reset after it is sent to pcx. the logic below will never be set!!
959
assign  lsu_cpx_ld_dtag_perror_e =
960
  dfq_byp_sel[0] ? dtag_perror0 :
961
    dfq_byp_sel[1] ? dtag_perror1 :
962
      dfq_byp_sel[2] ? dtag_perror2 : (dfq_byp_sel[3] & dtag_perror3) ; // Bug 4655
963
 
964
assign  lsu_cpx_ld_dcache_perror_e =
965
  dfq_byp_sel[0] ? dcache_perror0 :
966
    dfq_byp_sel[1] ? dcache_perror1 :
967
      dfq_byp_sel[2] ? dcache_perror2 : (dfq_byp_sel[3] & dcache_perror3) ; // Bug 4655
968
 
969
//Bug 3624
970
/*
971
assign  lsu_cpx_atm_st_err[1:0] =
972
  cpx_pkt_thrd_sel[0] ? ld_error0[1:0] :
973
    cpx_pkt_thrd_sel[1] ? ld_error1[1:0] :
974
      cpx_pkt_thrd_sel[2] ? ld_error2[1:0] : ld_error3[1:0] ;*/
975
 
976
//===
977
wire memref_e;
978
 
979
dff_s #(1) stge_ad_e (
980
  .din (ifu_lsu_memref_d),
981
  .q   (memref_e),
982
  .clk (clk),
983
  .se     (1'b0),       .si (),          .so ()
984
);
985
 
986
 
987
 
988
 
989
//=================================================================================================
990
//  LDD HANDLING
991
//=================================================================================================
992
 
993
assign ldd_vld_reset =
994
        (reset | (dcfill_active_e & ldd_in_dfq_out));
995
 
996
// prefetch qual is required for case where prefetch may get interference
997
// from lmq contents set by a later load that issues before the prefetch
998
// is returned.
999
// integer
1000
assign ldd_vld_en = lmq_ldd_vld & ~lsu_cpx_pkt_prefetch & dcfill_active_e ;
1001
// fp
1002
assign lsu_fldd_vld_en = lmq_ldd_vld & ~lsu_cpx_pkt_prefetch & lsu_l2fill_fpld_e & dcfill_active_e ;
1003
 
1004
 
1005
dffre_s   ldd_in_dfq_ff (
1006
        .din    (lmq_ldd_vld), .q  (ldd_in_dfq_out),
1007
        .rst    (ldd_vld_reset),        .en     (ldd_vld_en),
1008
        .clk  (clk),
1009
        .se     (1'b0),       .si (),          .so ()
1010
        );
1011
 
1012
 
1013
wire lsu_ignore_fill;
1014
//dfq_ld_vld is redundant   
1015
assign lsu_ignore_fill = dfq_ld_vld & lmq_ldd_vld & ~ldd_in_dfq_out & dcfill_active_e ;
1016
 
1017
 
1018
dff_s #(5)   dfq_rd_m (
1019
        .din    (ifu_lsu_rd_e[4:0]), .q  (ld_l1hit_rd_m[4:0]),
1020
        .clk  (clk),
1021
        .se     (1'b0),       .si (),          .so ()
1022
        );
1023
 
1024
//dff #(5)   dfq_rd_g (
1025
//        .din    (ld_l1hit_rd_m[4:0]), .q  (ld_l1hit_rd_g[4:0]),
1026
//        .clk  (clk),
1027
//        .se     (1'b0),       .si (),          .so ()
1028
//        ); 
1029
 
1030
 
1031
dff_s #(1)   stgd1_lrd (
1032
        .din    (ldd_in_dfq_out),
1033
  .q    (ldd_in_dfq_out_d1),
1034
        .clk  (clk),
1035
        .se     (1'b0),       .si (),          .so ()
1036
        );
1037
 
1038
//dff #(1)   stgd2_lrd (
1039
//        .din    (ldd_in_dfq_out_d1), 
1040
//  .q    (ldd_in_dfq_out_d2),
1041
//        .clk  (clk),
1042
//        .se     (1'b0),       .si (),          .so ()
1043
//        ); 
1044
 
1045
 
1046
//wire [4:0] lmq_ld_rd1_g;   
1047
//dff #(5) ff_lmq_ld_rd1 (
1048
//        .din  (lmq_ld_rd1[4:0]), 
1049
//        .q    (lmq_ld_rd1_g[4:0]),
1050
//        .clk  (clk),
1051
//        .se   (1'b0),       .si (),          .so ()
1052
//        ); 
1053
 
1054
 
1055
// Stage l2fill vld
1056
//wire  l2fill_vld_m, l2fill_vld_g ;
1057
wire    l2fill_vld_e,l2fill_vld_m ;
1058
dff_s           l2fv_stgm (
1059
        .din  (l2fill_vld_e),
1060
        .q    (l2fill_vld_m),
1061
        .clk  (clk),
1062
        .se   (1'b0),       .si (),          .so ()
1063
        );
1064
 
1065
//dff           l2fv_stgg (
1066
//        .din  (l2fill_vld_m), 
1067
//      .q    (l2fill_vld_g),
1068
//        .clk  (clk),
1069
//        .se   (1'b0),       .si (),          .so ()
1070
//        ); 
1071
 
1072
wire    ld_inst_vld_m ;
1073
dff_s           lvld_stgm (
1074
        .din  (ld_inst_vld_e),
1075
        .q    (ld_inst_vld_m),
1076
        .clk  (clk),
1077
        .se   (1'b0),       .si (),          .so ()
1078
        );
1079
 
1080
//wire  ld_inst_vld_g ;
1081
//dff           lvld_stgg (
1082
//        .din  (ld_inst_vld_m), 
1083
//      .q    (ld_inst_vld_g),
1084
//        .clk  (clk),
1085
//        .se   (1'b0),       .si (),          .so ()
1086
//        ); 
1087
 
1088
wire    ldd_in_dfq_out_vld ;
1089
assign  ldd_in_dfq_out_vld = ldd_in_dfq_out_d1 & l2fill_vld_m ;
1090
assign lsu_exu_rd_m[4:0] =
1091
  ld_inst_vld_m ? ld_l1hit_rd_m[4:0] :
1092
                ldd_in_dfq_out_vld ?  {lmq_ld_rd1[4:1],~lmq_ld_rd1[0]}
1093
                                                : lmq_ld_rd1[4:0];
1094
/*wire  ldd_in_dfq_out_vld ;
1095
assign  ldd_in_dfq_out_vld = ldd_in_dfq_out_d2 & l2fill_vld_g ;
1096
assign lsu_exu_rd_w2[4:0] =
1097
  ld_inst_vld_g ? ld_l1hit_rd_g[4:0] :
1098
                ldd_in_dfq_out_vld ?  {lmq_ld_rd1_g[4:1],~lmq_ld_rd1_g[0]}
1099
                                                : lmq_ld_rd1_g[4:0];*/
1100
 
1101
 
1102
// Generate data select for 128b. ldd will cause hi-order 8B followed by low order
1103
// 8B to be selected.
1104
 
1105
// ldd will select from same 64b dw.
1106
assign  lsu_dfill_data_sel_hi = ~lmq_ld_addr_b3 ^ (ldd_in_dfq_out & ~ldd_non_alt_space) ;
1107
 
1108
// ldd non-alternate space. sz distinguishes between quad, fp ldd and int ldd.
1109
// quad ldd, fp ldd sz = 2'b11, int ldd sz = 2'b10   
1110
assign  ldd_non_alt_space = lsu_byp_misc_sz_e[1] & ~lsu_byp_misc_sz_e[0] ;
1111
 
1112
assign  ldd_oddrd_e = ldd_in_dfq_out & ldd_non_alt_space ;
1113
 
1114
dff_s   ldd_stgm (
1115
        .din    (ldd_oddrd_e),
1116
  .q    (lsu_byp_ldd_oddrd_m),
1117
        .clk  (clk),
1118
        .se     (1'b0),       .si (),          .so ()
1119
        );
1120
 
1121
// all incoming ld and inv packets must be written to dfq or its bypass flop.
1122
// wrt ptr must be updated in cycle that cpx pkt is sent.
1123
 
1124
// invalidate does not need bubble, only ld bypass and/or fill.
1125
// fill bypass can only occur if bubble is in pipeline.
1126
 
1127
//------
1128
// strm ack cmplt - needs to be visible in dcache
1129
//------
1130
 
1131
//bug4460 - qualify stream store ack w/ local packet
1132
//Bug4969
1133
wire    dfq_local_pkt ;
1134
wire    strmack_cmplt1, strmack_cmplt2, strmack_cmplt3 ;
1135
wire    strmack_cmplt1_d1, strmack_cmplt2_d1, strmack_cmplt3_d1 ;
1136
//wire  strm_ack_cmplt ;
1137
assign  strmack_cmplt1 =
1138
        // check inflight, no inv. if inv, write to dfq_byp.
1139
        (cpx_strm_st_ack_type & ~(dfq_wr_en | lsu_cpx_spc_inv_vld) &
1140
         (const_cpuid[2:0] == cpx_spc_data_cx_b120to118[`CPX_INV_CID_HI:`CPX_INV_CID_LO])) ;
1141
assign  strmack_cmplt2 =
1142
        // check dfq-rd - no inv, gets dropped.
1143
        (lsu_dfq_byp_type[1] & dfq_rd_advance & ~lsu_dfq_byp_cpx_inv & local_pkt) ;
1144
assign  strmack_cmplt3 =
1145
        // check dfq-rd - inv, and thus process from dfq_bypass.
1146
        (lsu_cpx_pkt_strm_ack & inv_active_e & dfq_inv_vld & dfq_local_pkt) ;
1147
 
1148
/*assign        strm_ack_cmplt =
1149
        // check inflight, no inv. if inv, write to dfq_byp.
1150
        (cpx_strm_st_ack_type & ~(dfq_wr_en | lsu_cpx_spc_inv_vld) &
1151
         (const_cpuid[2:0] == cpx_spc_data_cx_b120to118[`CPX_INV_CID_HI:`CPX_INV_CID_LO])) |
1152
        // check dfq-rd - no inv, gets dropped.
1153
        (lsu_dfq_byp_type[1] & dfq_rd_advance & ~lsu_dfq_byp_cpx_inv & local_pkt) |
1154
        // check dfq-rd - inv, and thus process from dfq_bypass.
1155
        (lsu_cpx_pkt_strm_ack & inv_active_e & dfq_inv_vld & dfq_local_pkt) ;*/
1156
 
1157
dff_s #(3)   strmackcnt_stg (
1158
        .din    ({strmack_cmplt3,strmack_cmplt2,strmack_cmplt1}),
1159
        .q      ({strmack_cmplt3_d1,strmack_cmplt2_d1,strmack_cmplt1_d1}),
1160
        .clk    (clk),
1161
        .se     (1'b0),       .si (),          .so ()
1162
        );
1163
 
1164
assign  lsu_spu_strm_ack_cmplt[0] =      // lsb  of cnt, 1 or 3.
1165
        (~strmack_cmplt1_d1 & ~strmack_cmplt2_d1 &  strmack_cmplt3_d1) | //001
1166
        (~strmack_cmplt1_d1 &  strmack_cmplt2_d1 & ~strmack_cmplt3_d1) | //010
1167
        ( strmack_cmplt1_d1 &  strmack_cmplt2_d1 &  strmack_cmplt3_d1) | //111
1168
        ( strmack_cmplt1_d1 & ~strmack_cmplt2_d1 & ~strmack_cmplt3_d1) ; //100
1169
 
1170
assign  lsu_spu_strm_ack_cmplt[1] =     // msb  of cnt, 2 or 3.
1171
        (strmack_cmplt1_d1 & strmack_cmplt2_d1) |
1172
        (strmack_cmplt2_d1 & strmack_cmplt3_d1) |
1173
        (strmack_cmplt1_d1 & strmack_cmplt3_d1) ;
1174
 
1175
/*dff   strmack_d1 (
1176
        .din  (strm_ack_cmplt),
1177
        .q    (lsu_spu_strm_ack_cmplt),
1178
        .clk  (clk),
1179
        .se     (1'b0),       .si (),          .so ()
1180
        ); */
1181
 
1182
// Active as soon as it is visible in dfq byp ff.
1183
assign  inv_active_e = dfq_inv_vld ;      // evict/icache/strm-st
1184
//wire  st_atm_err ;
1185
// An atomic st is forced to punch a bubble in the pipe if
1186
// an error is encountered on the load. error en is not checked
1187
// at this point.
1188
/*assign  st_atm_err =
1189
  ((|lsu_cpx_atm_st_err[1:0]) & lsu_cpx_pkt_atm_st_cmplt) ;*/
1190
 
1191
assign  stwr_active_e =
1192
  dfq_st_vld & dfq_local_inv  & ~memref_e &
1193
  ~lsu_cpx_pkt_atm_st_cmplt & ~lsu_cpx_pkt_binit_st ;
1194
// & ~lsu_cpx_pkt_stquad_pkt2 ;  // fix for ifill_pkt_vld -b[130]
1195
//  dfq_st_vld & local_inv & ~st_ack_rq_stb_d1 & ~memref_e & //st ack timing fix
1196
//  ~lsu_cpx_pkt_stquad_pkt2 // bug 2942
1197
 
1198
assign  stdq_active_e =
1199
  dfq_st_vld &
1200
  //((~dfq_local_inv & (~st_atm_err | (st_atm_err & ~memref_e))) | //Bug 3624
1201
  ((~dfq_local_inv) |
1202
   (dfq_local_inv & ~memref_e)) ;
1203
//  ((~local_inv & (~st_atm_err | (st_atm_err & ~memref_e))) | 
1204
//   (local_inv & (~st_ack_rq_stb_d1 & ~memref_e))) ;
1205
 
1206
 
1207
assign  dfq_st_cmplt = stdq_active_e | (inv_active_e & dfq_st_vld) ;
1208
 
1209
wire    atm_st_cmplt ;
1210
assign  atm_st_cmplt = dfq_st_cmplt & lsu_cpx_pkt_atm_st_cmplt ;
1211
assign  lsu_atm_st_cmplt_e = atm_st_cmplt ;
1212
 
1213
assign  dcfill_active_e = dfq_ld_vld & ~memref_e ;
1214
 
1215
//bug3753 - qualify ld*_fill_reset w/ dcfill_active & ~ignore_fill
1216
//          in qctl1 this is qual'ed w/ dfq_ld_vld
1217
assign  lsu_dcfill_active_e  =  dcfill_active_e & ~lsu_ignore_fill;
1218
//assign  lsu_dcfill_active_e  =  dcfill_active_e;
1219
 
1220
assign  dva_svld_e =
1221
  inv_active_e |      // evict/icache/strm-st
1222
  (dfq_st_vld & lsu_cpx_pkt_perror_dinv) |      // dtag parity error invalidation.
1223
  (dfq_local_inv & dfq_st_vld & // local st - atomic
1224
  lsu_cpx_pkt_atomic ) ;
1225
  //lsu_cpx_pkt_atomic & ~lsu_cpx_pkt_stquad_pkt2) ; // store quad pkt not present - cmp1_regr fail
1226
  //(local_inv & dfq_st_vld & // local st - stquad/atomic
1227
assign  l2fill_vld_e  = dcfill_active_e &
1228
                        ~lsu_cpx_pkt_prefetch ; // prefetch will not fill
1229
 
1230
assign  lsu_l2fill_vld = dcfill_active_e ;
1231
 
1232
//=================================================================================================
1233
//  DFQ RD/WR CONTROL
1234
//=================================================================================================
1235
 
1236
//assign  cpx_inv =
1237
//  lsu_cpu_inv_data[`CPX_AX0_INV_DVLD]   |   // line 0
1238
//  lsu_cpu_inv_data[`CPX_AX1_INV_DVLD+4] |   // line 1
1239
//  lsu_cpu_inv_data[`CPX_AX0_INV_DVLD+7] |   // line 2
1240
//  lsu_cpu_inv_data[`CPX_AX1_INV_DVLD+11] ;  // line 3
1241
 
1242
// All invalidates go into byp buffer
1243
assign  dfq_byp_ld_vld = lsu_dfq_byp_type[5] ;
1244
// local store inv path is separate.
1245
assign  dfq_byp_inv_vld =
1246
       (lsu_dfq_byp_type[4] & dfq_invwy_vld)    | // icache x-inv
1247
       (lsu_dfq_byp_type[3]                     | // evict
1248
       (lsu_dfq_byp_type[2] & ~local_pkt)       | // sparc st-ack - non-local
1249
        lsu_dfq_byp_type[1]                     | // strm st-ack
1250
        (lsu_dfq_byp_type[2] & local_pkt & lsu_dfq_byp_binit_st)) &
1251
                                // blk init st invalidates L1
1252
        lsu_dfq_byp_cpx_inv ;         // local invalidate
1253
        //cpx_inv ;         // local invalidate
1254
 
1255
// Local store which writes to cache
1256
//timing fix: 7/14/03 - to improve setup of dfq_st_vld and dfq_ld_vld and move the flop to qdp2 -
1257
//            to eventually improve dcache_fill_data timing
1258
//            add byp mux for cpuid in qctl2
1259
wire  [2:0]  dfq_byp_cpuid ;
1260
assign  dfq_byp_cpuid[2:0]  =  dfq_rd_vld_d1 ? lsu_dfq_rdata_cpuid[2:0] :
1261
                                   cpx_spc_data_cx_b120to118[`CPX_INV_CID_HI:`CPX_INV_CID_LO] ;
1262
 
1263
//assign  local_pkt =  &(const_cpuid[2:0] ~^ lsu_dfq_byp_cpuid[2:0]) ;
1264
assign  local_pkt =  &(const_cpuid[2:0] ~^ dfq_byp_cpuid[2:0]) ;
1265
assign  dfq_rdata_local_pkt =  &(const_cpuid[2:0] ~^ lsu_dfq_rdata_cpuid[2:0]) ;
1266
assign  dfq_byp_st_vld = lsu_dfq_byp_type[2] & local_pkt ;
1267
 
1268
// Add ifill invalidate
1269
// screen cpx data which gets written to dfq
1270
assign  dfq_byp_vld =
1271
(dfq_byp_ld_vld | dfq_byp_inv_vld | dfq_byp_st_vld) &
1272
(dfq_rd_vld_d1 | (~dfq_rd_vld_d1 & ~dfq_wr_en))  ;
1273
 
1274
//assign  lsu_dfq_byp_vld  =  dfq_byp_vld;
1275
 
1276
/*assign dfq_vld_reset =
1277
        reset | ((dcfill_active_e | inv_active_e | stdq_active_e) &
1278
    ~dfq_vld_en & // dside pkt in waiting
1279
    ~lsu_ignore_fill &  // ldd
1280
    ~ld_ignore_sec  // secondary loads
1281
    ) ; */
1282
 
1283
/*wire  ld_sec_rst, ld_sec_rst_d1 ;
1284
assign  ld_sec_rst = dcfill_active_e & ld_ignore_sec_last ;
1285
dff_s   secl_d1 (
1286
        .din    (ld_sec_rst), .q  (ld_sec_rst_d1),
1287
        .clk  (clk),
1288
        .se     (1'b0),       .si (),          .so ()
1289
        ); */
1290
 
1291
/* phase 2 change
1292
assign dfq_vld_reset =
1293
    // dside pkt in waiting, ldd, secondary loads
1294
        reset | (dcfill_active_e & ~(dfq_vld_en | lsu_ignore_fill | (ld_ignore_sec & ~ld_ignore_sec_last))) |
1295
    // dside pkt in waiting
1296
          ((inv_active_e | stdq_active_e) & ~dfq_vld_en) ;
1297
*/
1298
 
1299
assign dfq_vld_reset =
1300
    // dside pkt in waiting, ldd, no need secondary loads waiting
1301
        reset | (dcfill_active_e & ~(dfq_vld_en | (lsu_ignore_fill & ~lsu_cpx_pkt_prefetch))) |
1302
    // dside pkt in waiting
1303
          ((inv_active_e | stdq_active_e) & ~dfq_vld_en) ;
1304
 
1305
// vld is enabled only if both i and d side buffers are clear
1306
// for co-dependent events. co-dependent events are rare.
1307
wire    dfq_rd_advance_buf1 ;
1308
assign dfq_vld_en = dfq_byp_vld &
1309
                (dfq_rd_advance_buf1 |
1310
                (cpx_spc_data_cx_b144to140[`CPX_VLD] & vld_dfq_pkt & ~dfq_wr_en)) ;
1311
 
1312
/* phase 2 change
1313
assign  dfq_byp_ff_en =
1314
  (~dfq_byp_full |
1315
  ( dfq_byp_full & ((dcfill_active_e & ~(lsu_ignore_fill | ld_ignore_sec)) |
1316
       (inv_active_e | stdq_active_e)))) ;
1317
*/
1318
 
1319
assign  dfq_byp_ff_en =
1320
  (~dfq_byp_full |
1321
  ( dfq_byp_full & ((dcfill_active_e & ~lsu_ignore_fill) |
1322
       (inv_active_e | stdq_active_e)))) ;
1323
 
1324
//bug4576: add sehold to the flop enable in qdp2
1325
assign lsu_dfq_byp_ff_en  =  sehold | dfq_byp_ff_en ;
1326
 
1327
   // i.e., byp currently filling.
1328
 
1329
/*
1330
assign  dfq_byp_ff_en =
1331
  (~dfq_byp_full |
1332
  (dfq_byp_full & (dcfill_active_e | inv_active_e | stdq_active_e) & ~(lsu_ignore_fill | ld_ignore_sec))) ;
1333
  // i.e., byp currently filling.
1334
*/
1335
 
1336
// dfq bypass valid
1337
//timing fix: 6/6/03: add duplicate flop for dfq_byp_ld_vld and dfq_byp_st_vld
1338
//timing fix: 10/3/03 - add separate flop for lsu_dfq_vld lsu_dfq_st_vld to dctl
1339
//bug4460:  qualify stream store ack w/ local packet - add local pkt flop
1340
dffre_s  #(10) dfq_vld (
1341
        .din({local_pkt,dfq_byp_st_vld,dfq_byp_vld,dfq_byp_vld,
1342
              dfq_byp_ld_vld,dfq_byp_inv_vld,dfq_byp_st_vld,
1343
              lsu_dfq_byp_cpx_inv,dfq_byp_ld_vld,dfq_byp_st_vld}),
1344
        .q  ({dfq_local_pkt,lsu_dfq_st_vld,lsu_dfq_vld,dfq_byp_full,
1345
              dfq_ld_vld,dfq_inv_vld,dfq_st_vld,
1346
              dfq_local_inv,lsu_qdp2_dfq_ld_vld,lsu_qdp2_dfq_st_vld}),
1347
//.din    ({dfq_byp_vld,dfq_byp_ld_vld,dfq_byp_inv_vld,dfq_byp_st_vld,cpx_inv,lsu_dfq_byp_cpx_inv}),
1348
//.q      ({dfq_byp_full,dfq_ld_vld,dfq_inv_vld,dfq_st_vld,local_inv,dfq_local_inv}),
1349
        .rst    (dfq_vld_reset),        .en     (dfq_vld_en),
1350
        .clk    (clk),
1351
        .se     (1'b0),       .si (),          .so ()
1352
        );
1353
 
1354
//bug4057: kill diagnostic write if dfq has valid requests to l1d$
1355
//timing fix: 10/3/03 - add separate flop for lsu_dfq_vld
1356
//assign  lsu_dfq_vld  =  dfq_byp_full ;
1357
 
1358
assign  lsu_dfq_ld_vld  =  dfq_ld_vld;
1359
//timing fix: 9/29/03 - instantiate buffer for dfq_st_vld to dctl
1360
//timing fix: 10/3/03 - remove buffer and add separate flop
1361
//assign  lsu_dfq_st_vld  =  dfq_st_vld;
1362
//bw_u1_buf_30x UZsize_lsu_dfq_st_vld_buf1 ( .a(dfq_st_vld), .z(lsu_dfq_st_vld) );
1363
assign  lsu_dfq_ldst_vld  =  lsu_qdp2_dfq_ld_vld | lsu_qdp2_dfq_st_vld;
1364
 
1365
 
1366
// Flop invalidate bits
1367
dffe_s  #(12) dfq_inv (
1368
        .din    ({lsu_cpu_inv_data_b13to9,lsu_cpu_inv_data_b7to2,lsu_cpu_inv_data_b0}),
1369
        .q    ({dfq_inv_data_b13to9,dfq_inv_data_b7to2,dfq_inv_data_b0}),
1370
        //.din    (lsu_cpu_inv_data[13:0]),
1371
        //.q      (dfq_inv_data[13:0]),
1372
        .en     (dfq_vld_en),
1373
        .clk    (clk),
1374
        .se     (1'b0),       .si (),          .so ()
1375
        );
1376
 
1377
 
1378
/*
1379
assign  lsu_st_ack_addr_b54[0] = dfq_inv_data[4] | dfq_inv_data[11] ;
1380
assign  lsu_st_ack_addr_b54[1] = dfq_inv_data[7] | dfq_inv_data[11] ;
1381
 
1382
 
1383
assign  st_wrwy_sel[0] = ~lsu_st_ack_addr_b54[1] & ~lsu_st_ack_addr_b54[0] ;
1384
assign  st_wrwy_sel[1] = ~lsu_st_ack_addr_b54[1] &  lsu_st_ack_addr_b54[0] ;
1385
assign  st_wrwy_sel[2] =  lsu_st_ack_addr_b54[1] & ~lsu_st_ack_addr_b54[0] ;
1386
assign  st_wrwy_sel[3] =  lsu_st_ack_addr_b54[1] &  lsu_st_ack_addr_b54[0] ;
1387
 
1388
assign  lsu_st_ack_wrwy[1:0]   =
1389
st_wrwy_sel[0] ? dfq_inv_data[`CPX_AX0_INV_WY_HI:`CPX_AX0_INV_WY_LO] :
1390
  st_wrwy_sel[1] ? dfq_inv_data[`CPX_AX1_INV_WY_HI+4:`CPX_AX1_INV_WY_LO+4] :
1391
    st_wrwy_sel[2] ? dfq_inv_data[`CPX_AX0_INV_WY_HI+7:`CPX_AX0_INV_WY_LO+7] :
1392
      st_wrwy_sel[3] ? dfq_inv_data[`CPX_AX1_INV_WY_HI+11:`CPX_AX1_INV_WY_LO+11] :
1393
            2'bxx ;
1394
*/
1395
 
1396
// cpx invalidate data obtained via the cfq.
1397
// b[8[ and b[1] are unused
1398
//8/28/03: vlint cleanup - remove cpx_cpu_inv_data and use dfq_inv_data directly
1399
//assign  cpx_cpu_inv_data[13:0] =  {dfq_inv_data_b13to9,1'b0,dfq_inv_data_b7to2,1'b0,dfq_inv_data_b0} ;
1400
//assign  cpx_cpu_inv_data[13:0] =  dfq_inv_data[13:0] ;
1401
 
1402
// write control set up.   
1403
// All cpx pkts are written.
1404
// - unwanted pkts are explicity overwritten by next incoming pkt.
1405
 
1406
   /*wire stb_cam_hit_w2;
1407
 
1408
dff_s #(1)  stb_cam_hit_stg_w2  (
1409
  .din (stb_cam_hit),
1410
  .q   (stb_cam_hit_w2),
1411
  .clk (clk),
1412
  .se  (1'b0), .si (), .so ()
1413
  ); */
1414
 
1415
// Need to include error pkt !!
1416
//8/25/03: add error type to dfq_wr_en, dfq_rd_advance
1417
//8/25/03: add fwd req to L1I$ for RAMTEST to dfq_wr_en, dfq_rd_dvance
1418
assign  vld_dfq_pkt =
1419
cpx_int_type | cpx_ld_type | cpx_ifill_type | cpx_evict_type | cpx_st_ack_type | cpx_strm_st_ack_type | cpx_error_type | cpx_fwd_req_ic ;
1420
 
1421
//NOTE: restore cpx_inv qualification after adding cpx_inv part of dfq read - done
1422
 
1423
assign  dfq_wr_en =
1424
  // local st wr which writes to cache is put in dfq if cam-hit occurs.
1425
  //(cpx_local_st_ack_type & stb_cam_hit_w2 & cpx_inv) |
1426
  //(cpx_local_st_ack_type & stb_cam_hit_w2 & lsu_dfq_byp_cpx_inv) |
1427
  //(cpx_local_st_ack_type) |  //bug2623
1428
  (cpx_st_ack_type) |
1429
  // always write under these conditions
1430
  //(vld_dfq_pkt & (dfq_vld_entry_exists | dfq_rptr_vld_d1)) | 
1431
  (vld_dfq_pkt & (dfq_vld_entry_exists_w | dfq_rptr_vld_d1)) |
1432
  //(cpx_spc_data_cx_b144to140[`CPX_VLD] & (dfq_vld_entry_exists | dfq_rptr_vld_d1)) | 
1433
  // interrupts always write to queue
1434
    cpx_int_type |
1435
  // error type or forward request to l1i$ - bypass
1436
   ((cpx_error_type | cpx_fwd_req_ic) & ifu_lsu_ibuf_busy)  |
1437
  // selectively write under these conditions
1438
   ((cpx_ld_type & ~dfq_byp_ff_en)          |
1439
    (cpx_ld_type &  cpx_spc_data_cx_b133 & ifu_lsu_ibuf_busy)  |
1440
    (cpx_ifill_type & ifu_lsu_ibuf_busy)          |
1441
    (cpx_ifill_type & cpx_spc_data_cx_b133 & ~dfq_byp_ff_en) |
1442
    // the evictions/acks will wr to the dfq if any buffer is full
1443
    ((cpx_evict_type | cpx_st_ack_type | cpx_strm_st_ack_type) & (ifu_lsu_ibuf_busy | ~dfq_byp_ff_en))) ;
1444
 
1445
assign  dfq_wptr_new_w_wrap[5:0]  = dfq_wptr_w_wrap[5:0] + {5'b00000, dfq_wr_en} ;
1446
//assign  dfq_wptr_vld = dfq_wr_en ;
1447
// every pkt is to be written to dfq. The pkt may be rejected by not updating
1448
// write ptr based on certain conditions.
1449
assign  dfq_wptr_vld = cpx_spc_data_cx_b144to140[`CPX_VLD] ;
1450
 
1451
dffre_s  #(6) dfq_wptr_ff (
1452
        .din    (dfq_wptr_new_w_wrap[5:0]), .q  (dfq_wptr_w_wrap[5:0]),
1453
        .rst    (reset), .en (dfq_wr_en), .clk (clk),
1454
        .se     (1'b0),       .si (),          .so ()
1455
        );
1456
 
1457
//1/20/04: mintime fix - add minbuf to dfq_wptr
1458
//assign  dfq_wptr[4:0] = dfq_wptr_w_wrap[4:0] ;
1459
 
1460
wire  [4:0]  dfq_wptr_minbuf ;
1461
bw_u1_minbuf_5x UZfix_dfq_wptr_b0_minbuf (.a(dfq_wptr_w_wrap[0]), .z(dfq_wptr_minbuf[0]));
1462
bw_u1_minbuf_5x UZfix_dfq_wptr_b1_minbuf (.a(dfq_wptr_w_wrap[1]), .z(dfq_wptr_minbuf[1]));
1463
bw_u1_minbuf_5x UZfix_dfq_wptr_b2_minbuf (.a(dfq_wptr_w_wrap[2]), .z(dfq_wptr_minbuf[2]));
1464
bw_u1_minbuf_5x UZfix_dfq_wptr_b3_minbuf (.a(dfq_wptr_w_wrap[3]), .z(dfq_wptr_minbuf[3]));
1465
bw_u1_minbuf_5x UZfix_dfq_wptr_b4_minbuf (.a(dfq_wptr_w_wrap[4]), .z(dfq_wptr_minbuf[4]));
1466
 
1467
bw_u1_buf_10x UZsize_dfq_wptr_b0_buf2 ( .a(dfq_wptr_minbuf[0]), .z(dfq_wptr[0]) );
1468
bw_u1_buf_10x UZsize_dfq_wptr_b1_buf2 ( .a(dfq_wptr_minbuf[1]), .z(dfq_wptr[1]) );
1469
bw_u1_buf_10x UZsize_dfq_wptr_b2_buf2 ( .a(dfq_wptr_minbuf[2]), .z(dfq_wptr[2]) );
1470
bw_u1_buf_10x UZsize_dfq_wptr_b3_buf2 ( .a(dfq_wptr_minbuf[3]), .z(dfq_wptr[3]) );
1471
bw_u1_buf_10x UZsize_dfq_wptr_b4_buf2 ( .a(dfq_wptr_minbuf[4]), .z(dfq_wptr[4]) );
1472
 
1473
// Bit3 of both pointers is a wrap bit. Including this in the compare
1474
// will tell us whether the queue is empty or not. It is assumed that
1475
// the wptr will never runover the rptr because of flow control.
1476
// This will have to be fine-tuned once dfq is accurate !!!
1477
assign  dfq_vld_entry_exists = (dfq_rptr_new_w_wrap[5:0] != dfq_wptr_w_wrap[5:0]) ;
1478
 
1479
assign  dfq_vld_entry_exists_w = (dfq_rptr_w_wrap[5:0] != dfq_wptr_w_wrap[5:0]) ;
1480
 
1481
// dfq is read iff bypass flop is empty and valid entry in dfq available. 
1482
// i.e., we need to initialize bypass ff such that it always contains
1483
// latest entry.
1484
//  (dfq_rptr_vld_d1 & (~i_and_d_codepend | (i_and_d_codepend & dfq_rd_advance))) |
1485
 
1486
//assign  lsu_ifill_pkt_vld =   
1487
//  (dfq_rptr_vld_d1 & ~(dfq_st_ack_type & lsu_dfq_byp_stack_dcfill_vld) & (~i_and_d_codepend | (i_and_d_codepend & dfq_byp_ff_en))) |
1488
//        (cpx_spc_data_cx[`CPX_VLD] & ~dfq_wr_en) ;
1489
//
1490
//  (dfq_rptr_vld_d1 & ~(dfq_st_ack_type & lsu_dfq_byp_stack_dcfill_vld) & ~ifill_pkt_fwd_done_d1) |
1491
//
1492
//  (dfq_rptr_vld_d1 & ~(lsu_dfq_rdata_st_ack_type & lsu_dfq_rdata_stack_dcfill_vld) & ~ifill_pkt_fwd_done_d1) | // bug:2767
1493
//  change lsu_dfq_rdata_stack_dcfill_vld from b[87] to b[151] in the top level 
1494
//
1495
//timing fix: 6/16/03 - fix for ifill_pkt_vld - use b130 if store_ack_dcfill_vld=1
1496
//            change lsu_dfq_rdata_stack_dcfill_vld from b[151] to b[130] in the top level 
1497
//  (dfq_rptr_vld_d1 & ~(lsu_dfq_rdata_st_ack_type & dfq_rdata_local_pkt & lsu_dfq_rdata_stack_dcfill_vld) & ~ifill_pkt_fwd_done_d1) |
1498
//
1499
//bug3657 - kill ifill vld in bypass path when cpxtype=fp/fwd_reply
1500
//NOTE: stream loads should also be included
1501
//bug5080 - kill ifill vld in bypass path when cpxtype=strm load - similar to bug3657
1502
//          kill bypass when dfq_rptr_vld_d1=1
1503
//  (cpx_spc_data_cx_b144to140[`CPX_VLD] & ~(dfq_wr_en | cpx_fwd_rply_type | cpx_fp_type)) ;
1504
//
1505
//bug6372: ifill dcache x-inv causes incorrect dcache index to be invalidated.
1506
//         - this occurs 'cos the imiss index gets overwritten by another imiss to the same thread.
1507
//           the dcache x-inv(head of dfq) is stalled in dfq 'cos of load in bypass flop being stalled by memref_e=1
1508
//           but the ifill pkt vld is set to 1 and ifu starts issuing the next imiss for same thread
1509
//         
1510
//  (dfq_rptr_vld_d1 & ~(lsu_dfq_rdata_st_ack_type & lsu_dfq_rdata_stack_dcfill_vld) & ~ifill_pkt_fwd_done_d1) |
1511
 
1512
wire   ifill_pkt_fwd_done,ifill_pkt_fwd_done_d1;
1513
wire   ifill_dinv_head_of_dfq_pend ;
1514
 
1515
 
1516
assign  ifill_dinv_head_of_dfq_pend  =  lsu_dfq_rdata_type[4] & lsu_dfq_rdata_invwy_vld & ~dfq_byp_ff_en ;
1517
 
1518
assign  lsu_ifill_pkt_vld =
1519
  (dfq_rptr_vld_d1 & ~(lsu_dfq_rdata_st_ack_type & lsu_dfq_rdata_stack_dcfill_vld) &
1520
                     ~ifill_dinv_head_of_dfq_pend &
1521
                     ~ifill_pkt_fwd_done_d1 ) |
1522
  (~dfq_rptr_vld_d1 & cpx_spc_data_cx_b144to140[`CPX_VLD] & ~(dfq_wr_en | cpx_fwd_rply_type | cpx_fp_type)) ;
1523
 
1524
// this signal acts as a mask i.e. fill valid will be asserted until the ifu_lsu_ibuf_busy=0. But certain packets need
1525
// both busy=0 and memref_e=0 - in which case it is safer to mask until the dfq_rd_advance=1.
1526
 
1527
//bug5309: add reset to the flop; x's get recycled from flop o/p until a dfq_rd_advance occurs i.e. flop reset
1528
//         after first ifill; failed in cmp1.92 cmp8 regression w/ vcs7.1
1529
 
1530
assign  ifill_pkt_fwd_done  =  ~reset &
1531
                               (((dfq_rptr_vld_d1 & ~ifu_lsu_ibuf_busy & ~ifill_dinv_head_of_dfq_pend) |
1532
                                ifill_pkt_fwd_done_d1)   // set|hold
1533
                                & ~dfq_rd_advance);                                               // reset
1534
 
1535
dff_s  #(1) ifill_pkt_fwd_done_ff (
1536
        .din    (ifill_pkt_fwd_done),
1537
        .q      (ifill_pkt_fwd_done_d1),
1538
        .clk    (clk),
1539
        .se     (1'b0),       .si (),          .so ()
1540
        );
1541
 
1542
 
1543
 
1544
// Note that this becomes valid in cycle of read. Flush will be continuously read
1545
// out of dfq until all intermmediate buffers are clear.
1546
 
1547
// timing fix: 06/04/03: dfq_rd_advance uses byp_mux output; instead use dfq read output
1548
//             i.e. dfq_rd_advance is valid only when there is a valid entry in dfq
1549
//             it is already qual'ed w/ dfq_rd_vld_d1 to determine this.
1550
 
1551
//assign  dfq_ld_type     = lsu_dfq_byp_type[5] ;
1552
//assign  dfq_ifill_type    = lsu_dfq_byp_type[4] ;
1553
//assign  dfq_evict_type    = lsu_dfq_byp_type[3] ;
1554
//assign  dfq_st_ack_type   = lsu_dfq_byp_type[2] ;
1555
//assign  dfq_strm_st_ack_type  = lsu_dfq_byp_type[1] ;
1556
//assign  dfq_int_type    = lsu_dfq_byp_type[0] ;
1557
 
1558
assign  dfq_ld_type     = lsu_dfq_rdata_type[5] ;
1559
assign  dfq_ifill_type    = lsu_dfq_rdata_type[4] ;
1560
assign  dfq_evict_type    = lsu_dfq_rdata_type[3] ;
1561
assign  dfq_st_ack_type   = lsu_dfq_rdata_type[2] ;
1562
assign  dfq_strm_st_ack_type  = lsu_dfq_rdata_type[1] ;
1563
assign  dfq_int_type    = lsu_dfq_rdata_type[0] ;
1564
 
1565
//8/25/03: add error type to dfq_wr_en, dfq_rd_advance
1566
assign  dfq_error_type    = (lsu_dfq_rdata_rq_type[3:0]==4'b1100) ;
1567
//8/25/03: add fwd req to L1I$ for RAMTEST to dfq_wr_en, dfq_rd_dvance
1568
assign  dfq_fwd_req_ic_type  = (lsu_dfq_rdata_rq_type[3:0]==4'b1010) & lsu_dfq_rdata_b103;
1569
 
1570
assign  dfq_invwy_vld     = lsu_dfq_byp_invwy_vld ;
1571
 
1572
// if the there is a co-dependent event, then the ifu will not
1573
// be signalled vld until rd_advance is asserted.
1574
//assign  i_and_d_codepend = 
1575
//    ((dfq_ld_type | dfq_ifill_type) &  dfq_invwy_vld)   |
1576
//    (dfq_evict_type | dfq_st_ack_type | dfq_strm_st_ack_type) |
1577
//    dfq_int_type ;
1578
 
1579
//NOTE: restore cpx_inv qualification after adding cpx_inv part of dfq read - done
1580
//assign  st_rd_advance  =  dfq_byp_st_vld & (~lsu_dfq_byp_cpx_inv | (lsu_dfq_byp_cpx_inv & ~stb_cam_hit_w2)) & dfq_byp_ff_en;
1581
//assign  st_rd_advance  =  dfq_byp_st_vld & dfq_byp_ff_en; // bug:2770
1582
//                          (dfq_byp_st_vld &  lsu_dfq_rdata_stack_iinv_vld & ~ifu_lsu_ibuf_busy) ; // bug:2775
1583
 
1584
// timing fix: 06/04/03: dfq_rd_advance uses byp_mux output; instead use dfq read output
1585
//             i.e. dfq_rd_advance is valid only when there is a valid entry in dfq
1586
//             it is already qual'ed w/ dfq_rd_vld_d1 to determine this.
1587
 
1588
 
1589
assign  st_rd_advance  =
1590
        (dfq_st_ack_type & dfq_rdata_local_pkt & ~lsu_dfq_rdata_stack_iinv_vld & dfq_byp_ff_en) |
1591
        (dfq_st_ack_type & dfq_rdata_local_pkt &  lsu_dfq_rdata_stack_iinv_vld & ~ifu_lsu_ibuf_busy & dfq_byp_ff_en) ;
1592
 
1593
// The pointer is advanced based on pre-flop bypass data.
1594
 
1595
wire inv_clear_d1 ;
1596
dff_s  #(1) invclr_d1 (
1597
        .din    (ifu_lsu_inv_clear),
1598
        .q      (inv_clear_d1),
1599
        .clk    (clk),
1600
        .se     (1'b0),       .si (),          .so ()
1601
        );
1602
 
1603
//---
1604
// Dealing with skid involving invalidate clear.
1605
// 1. No stall asserted. If the int is immed. preceeded by an inv,
1606
// then the the inv will not be visible thru inv_clear. For this
1607
// reason, int will always wait an additional cycle before examining
1608
// inv_clear.
1609
// 2. In case int has been dispatched to the ifu with stall asserted,
1610
// stalls are conditionally inserted. 
1611
// Note : interrupts are always written into dfq.
1612
//---
1613
 
1614
wire    dfq_rd_advance_d1 ;
1615
dff_s   rda_d1 (
1616
        .din    (dfq_rd_advance),
1617
        .q      (dfq_rd_advance_d1),
1618
        .clk    (clk),
1619
        .se     (1'b0),       .si (),          .so ()
1620
        );
1621
 
1622
 
1623
// Begin Bug 5583
1624
wire    dfq_int_type_d1 ;
1625
wire    int_skid_c1,int_skid_c2;
1626
wire    int_skid_stall ;
1627
dff_s   itype_d1 (
1628
        .din    (dfq_int_type),
1629
        .q      (dfq_int_type_d1),
1630
        .clk    (clk),
1631
        .se     (1'b0),       .si (),          .so ()
1632
        );
1633
 
1634
// decision made to issue intrpt from dfq even though 
1635
// intr-clear was not high, thus introduce stall for
1636
// 2 more cycles.
1637
assign int_skid_c1 =
1638
        dfq_int_type_d1 & dfq_rd_advance_d1 & ~inv_clear_d1 ;
1639
 
1640
dff_s   iskid_c2 (
1641
        .din    (int_skid_c1),
1642
        .q      (int_skid_c2),
1643
        .clk    (clk),
1644
        .se     (1'b0),       .si (),          .so ()
1645
        );
1646
 
1647
assign  int_skid_stall = int_skid_c1 | int_skid_c2 ;
1648
 
1649
// End Bug 5583
1650
 
1651
// timing fix: 06/04/03: dfq_rd_advance uses byp_mux output; instead use dfq read output
1652
//             i.e. dfq_rd_advance is valid only when there is a valid entry in dfq
1653
//             it is already qual'ed w/ dfq_rd_vld_d1 to determine this.
1654
//8/25/03: add error type to dfq_wr_en, dfq_rd_advance
1655
//8/25/03: add fwd req to L1I$ for RAMTEST to dfq_wr_en, dfq_rd_dvance
1656
 
1657
assign  dfq_rd_advance   =
1658
  // local st which writes to cache cannot advance if simultaneous cam hit. 
1659
  //((dfq_byp_st_vld & (~cpx_inv | (cpx_inv & ~stb_cam_hit_w2)) & dfq_byp_ff_en)  | 
1660
  (st_rd_advance |
1661
  // advance beyond a dside ld if it can be written to the byp ff
1662
  (dfq_ld_type & ~lsu_dfq_rdata_invwy_vld & dfq_byp_ff_en) |
1663
  // advance beyond a dside & iside ld if it can be written to the byp ff/ibuf clr
1664
  (dfq_ld_type &  lsu_dfq_rdata_invwy_vld & (dfq_byp_ff_en & ~ifu_lsu_ibuf_busy))   |
1665
  // advance beyond a iside ifill if it can be written to the ibuf
1666
  (dfq_ifill_type & ~lsu_dfq_rdata_invwy_vld & ~ifu_lsu_ibuf_busy)      |
1667
  // advance beyond a dside & iside ifill if it can be written to the byp ff/ibuf clr
1668
  (dfq_ifill_type &  lsu_dfq_rdata_invwy_vld & (dfq_byp_ff_en & ~ifu_lsu_ibuf_busy))  |
1669
  // any form of invalidate could invalidate both i and dside.
1670
  ((dfq_evict_type | (dfq_st_ack_type & ~dfq_rdata_local_pkt) | dfq_strm_st_ack_type) &
1671
        (dfq_byp_ff_en & ~ifu_lsu_ibuf_busy)) |
1672
  // interrupts and flushes have to ensure invalidates are visible in caches.
1673
  // interrupts do not enter d-side byp buffer.  flush needs to look at inv clear.
1674
  (dfq_int_type & (dfq_byp_ff_en & ~ifu_lsu_ibuf_busy & ((inv_clear_d1 & ~dfq_rd_advance_d1) | dfq_stall_d1))) | // Bug 3820.
1675
  //(dfq_int_type & (dfq_byp_ff_en & ~ifu_lsu_ibuf_busy & ((inv_clear_d1 & ~dfq_rd_advance_d1) | dfq_stall_d2))) | // Bug 3820.
1676
  ((dfq_error_type | dfq_fwd_req_ic_type) & ~ifu_lsu_ibuf_busy))
1677
    & dfq_rptr_vld_d1 & ~reset ;
1678
 
1679
//timing fix: 9/16/03 - dfq_rd_advance is late signal; use it as mux select to pick the correct read pointer
1680
//            add duplicate signal for dfq_rd_advance - has FO16 - adds 3inv to this path
1681
//            fix for dfq_read -> dfq_rd_advance -> dfq_rptr to dfq
1682
wire   dfq_rd_advance_dup ;
1683
assign dfq_rd_advance_dup =  dfq_rd_advance ;
1684
 
1685
//timing fix: 9/29/03 - instantiate buffer for dfq_rd_advance to dfq_vld_en
1686
bw_u1_buf_30x UZsize_dfq_rd_advance_buf1 ( .a(dfq_rd_advance), .z(dfq_rd_advance_buf1) );
1687
 
1688
wire    local_flush ;
1689
assign  local_flush = lsu_dfq_byp_type[0] & lsu_dfq_byp_flush & local_pkt & dfq_rd_advance ;
1690
 
1691
wire    [3:0]    dfq_flsh_cmplt ;
1692
assign  dfq_flsh_cmplt[0] = local_flush & ~lsu_dfq_byp_tid[1] & ~lsu_dfq_byp_tid[0] ;
1693
assign  dfq_flsh_cmplt[1] = local_flush & ~lsu_dfq_byp_tid[1] &  lsu_dfq_byp_tid[0] ;
1694
assign  dfq_flsh_cmplt[2] = local_flush &  lsu_dfq_byp_tid[1] & ~lsu_dfq_byp_tid[0] ;
1695
assign  dfq_flsh_cmplt[3] = local_flush &  lsu_dfq_byp_tid[1] &  lsu_dfq_byp_tid[0] ;
1696
 
1697
dff_s  #(4) flshcmplt (
1698
        .din    (dfq_flsh_cmplt[3:0]),
1699
        .q      (lsu_dfq_flsh_cmplt[3:0]),
1700
        .clk    (clk),
1701
        .se     (1'b0),       .si (),          .so ()
1702
        );
1703
 
1704
 
1705
// Check for extra bubbles in pipeline.
1706
//timing fix: 10/3/03 - use dfq_rd_advance as mux select
1707
//assign  dfq_rptr_new_w_wrap[5:0] =  dfq_rptr_w_wrap[5:0] + {5'b00000, dfq_rd_advance} ;
1708
wire  [5:0]  dfq_rptr_new_w_wrap_inc ;
1709
assign  dfq_rptr_new_w_wrap_inc[5:0] =  dfq_rptr_w_wrap[5:0] + 6'b000001 ;
1710
assign  dfq_rptr_new_w_wrap[5:0]  =  dfq_rd_advance ? dfq_rptr_new_w_wrap_inc[5:0] : dfq_rptr_w_wrap[5:0] ;
1711
 
1712
// The dfq will always read as long as there is a valid entry.
1713
// ** Design note : If dfq output is held at latches, this is not longer required !! **
1714
//assign  dfq_rptr_vld  =   dfq_vld_entry_exists ;
1715
assign  dfq_rptr_vld  =   dfq_vld_entry_exists_w ;
1716
 
1717
wire   dfq_rptr_vld_w_d1;
1718
 
1719
 
1720
dff_s   rvld_stgd1_new (
1721
        .din    (dfq_vld_entry_exists), .q  (dfq_vld_entry_exists_d1),
1722
        .clk  (clk),
1723
        .se     (1'b0),       .si (),          .so ()
1724
        );
1725
dff_s   rvld_stgd1 (
1726
        .din    (dfq_rptr_vld), .q  (dfq_rptr_vld_w_d1),
1727
        //.din    (dfq_rptr_vld), .q  (dfq_rptr_vld_d1),
1728
        .clk  (clk),
1729
        .se     (1'b0),       .si (),          .so ()
1730
        );
1731
//dff   rdad_stgd1 (
1732
//        .din    (dfq_rd_advance), .q  (dfq_rd_advance_d1),
1733
//        .clk  (clk),
1734
//        .se     (1'b0),       .si (),          .so ()
1735
//        ); 
1736
 
1737
dffre_s  #(6) dfq_rptr_ff (
1738
        .din    (dfq_rptr_new_w_wrap[5:0]), .q  (dfq_rptr_w_wrap[5:0]),
1739
        .rst    (reset), .en (dfq_rd_advance), .clk (clk),
1740
        .se     (1'b0),       .si (),          .so ()
1741
        );
1742
 
1743
assign  dfq_rptr_vld_d1 = dfq_rptr_vld_w_d1 & dfq_vld_entry_exists_d1;
1744
assign  dfq_rd_vld_d1 = dfq_rptr_vld_d1 ;
1745
//bug4576: add sehold to the dfq_rdata mux select
1746
assign  lsu_dfq_rd_vld_d1 = sehold | dfq_rptr_vld_d1 ;
1747
 
1748
//timing fix: 9/16/03 - dfq_rd_advance is late signal; use it as mux select to pick the correct read pointer
1749
//            add duplicate signal for dfq_rd_advance - has FO16 - adds 3inv to this path
1750
//            fix for dfq_read -> dfq_rd_advance -> dfq_rptr to dfq
1751
//assign  dfq_rptr[4:0] = dfq_rptr_w_wrap[4:0] + {4'b0000, dfq_rd_advance} ;
1752
 
1753
//1/20/04: mintime fix - add minbuf to dfq_rptr_w_wrap in dfq_rptr
1754
wire  [4:0]  dfq_rptr_w_wrap_minbuf ;
1755
 
1756
bw_u1_minbuf_5x UZfix_dfq_rptr_b0 (.a(dfq_rptr_w_wrap[0]), .z(dfq_rptr_w_wrap_minbuf[0]));
1757
bw_u1_minbuf_5x UZfix_dfq_rptr_b1 (.a(dfq_rptr_w_wrap[1]), .z(dfq_rptr_w_wrap_minbuf[1]));
1758
bw_u1_minbuf_5x UZfix_dfq_rptr_b2 (.a(dfq_rptr_w_wrap[2]), .z(dfq_rptr_w_wrap_minbuf[2]));
1759
bw_u1_minbuf_5x UZfix_dfq_rptr_b3 (.a(dfq_rptr_w_wrap[3]), .z(dfq_rptr_w_wrap_minbuf[3]));
1760
bw_u1_minbuf_5x UZfix_dfq_rptr_b4 (.a(dfq_rptr_w_wrap[4]), .z(dfq_rptr_w_wrap_minbuf[4]));
1761
 
1762
wire  [4:0]  dfq_rptr_inc ;
1763
assign dfq_rptr_inc[4:0]  =  dfq_rptr_w_wrap[4:0] + 5'b00001 ;
1764
assign  dfq_rptr[4:0] = dfq_rd_advance_dup ? dfq_rptr_inc[4:0] : dfq_rptr_w_wrap_minbuf[4:0] ;
1765
//assign  dfq_rptr[4:0] = dfq_rd_advance_dup ? dfq_rptr_inc[4:0] : dfq_rptr_w_wrap[4:0] ;
1766
 
1767
// Determine whether cfq has crossed high-water mark. IFU must switchout all threads
1768
// for every cycle that this is valid.
1769
// Need to change wptr size once new cfq array description incorporated.
1770
// Wrap bit may not be needed !!!
1771
wire  [5:0] dfq_vld_entries ;
1772
assign  dfq_vld_entries[5:0] = (dfq_wptr_w_wrap[5:0] - dfq_rptr_w_wrap[5:0]) ;
1773
/*assign  dfq_vld_entries[3:0] =
1774
  (dfq_rptr_w_wrap[4] ^ dfq_wptr_w_wrap[4]) ?
1775
  (dfq_rptr_w_wrap[3:0] - dfq_wptr_w_wrap[3:0]) : (dfq_wptr_w_wrap[3:0] - dfq_rptr_w_wrap[3:0]) ;*/
1776
 
1777
// High water mark conservatively put at 16-4 = 12
1778
assign  dfq_stall = (dfq_vld_entries[5:0] >= 6'd4) ;
1779
assign  lsu_ifu_stallreq =
1780
        dfq_stall |  int_skid_stall | lsu_tlbop_force_swo ;
1781
        //dfq_stall | dfq_stall_d1 | dfq_stall_d2 | int_skid_stall | lsu_tlbop_force_swo ; 
1782
 
1783
dff_s   dfqst_d1 (
1784
        .din  (dfq_stall), .q  (dfq_stall_d1),
1785
        .clk  (clk),
1786
        .se     (1'b0),       .si (),          .so ()
1787
        );
1788
 
1789
//=================================================================================================
1790
//  INVALIDATE PROCESSING
1791
//=================================================================================================
1792
 
1793
assign  dva_snp_addr_e[4:0]  =
1794
  lsu_cpx_pkt_ifill_type ? imiss_inv_set_index[6:2] : {lsu_cpx_pkt_inv_pa[4:0]} ;
1795
 
1796
//bug3356 - b4 never changed to invalidate the 2nd offset of the i$ fill.
1797
//          l2 now generates b4 in b129 of cpx ifill packet. for ifill pkt
1798
//          b[129] = 0 for 1st ifill packet, b[129]=1 for 2nd ifill packet.
1799
 
1800
wire    cpxpkt_ifill_b4 ;
1801
assign  cpxpkt_ifill_b4  =  lsu_cpx_pkt_atm_st_cmplt & lsu_cpx_pkt_ifill_type ;
1802
 
1803
assign  imiss_dcd_b54[0] = ~imiss_inv_set_index[1] & ~cpxpkt_ifill_b4 ;
1804
assign  imiss_dcd_b54[1] = ~imiss_inv_set_index[1] &  cpxpkt_ifill_b4 ;
1805
assign  imiss_dcd_b54[2] =  imiss_inv_set_index[1] & ~cpxpkt_ifill_b4 ;
1806
assign  imiss_dcd_b54[3] =  imiss_inv_set_index[1] &  cpxpkt_ifill_b4 ;
1807
 
1808
wire  [3:0] perror_dcd_b54 ;
1809
assign  perror_dcd_b54[0] = ~lsu_cpx_pkt_perror_set[1] & ~lsu_cpx_pkt_perror_set[0] ;
1810
assign  perror_dcd_b54[1] = ~lsu_cpx_pkt_perror_set[1] &  lsu_cpx_pkt_perror_set[0] ;
1811
assign  perror_dcd_b54[2] =  lsu_cpx_pkt_perror_set[1] & ~lsu_cpx_pkt_perror_set[0] ;
1812
assign  perror_dcd_b54[3] =  lsu_cpx_pkt_perror_set[1] &  lsu_cpx_pkt_perror_set[0] ;
1813
 
1814
wire   [3:0]           dva_snp_set_vld_e;      // Lower 2b of cache set index - decoded
1815
wire   [1:0]           dva_snp_wy0_e ;         // way for addr<5:4>=00
1816
wire   [1:0]           dva_snp_wy1_e ;         // way for addr<5:4>=01
1817
wire   [1:0]           dva_snp_wy2_e ;         // way for addr<5:4>=10
1818
wire   [1:0]           dva_snp_wy3_e ;         // way for addr<5:4>=11
1819
 
1820
 
1821
 
1822
/*
1823
assign  dva_snp_set_vld_e[0] =
1824
lsu_cpx_pkt_ifill_type ? imiss_dcd_b54[0] :
1825
  lsu_cpx_pkt_perror_dinv ? perror_dcd_b54[0] : cpx_cpu_inv_data[`CPX_AX0_INV_DVLD] ;
1826
assign  dva_snp_set_vld_e[1] =
1827
lsu_cpx_pkt_ifill_type ? imiss_dcd_b54[1] :
1828
  lsu_cpx_pkt_perror_dinv ? perror_dcd_b54[1] : cpx_cpu_inv_data[`CPX_AX1_INV_DVLD+4] ;
1829
assign  dva_snp_set_vld_e[2] =
1830
lsu_cpx_pkt_ifill_type ? imiss_dcd_b54[2] :
1831
  lsu_cpx_pkt_perror_dinv ? perror_dcd_b54[2] : cpx_cpu_inv_data[`CPX_AX0_INV_DVLD+7] ;
1832
assign  dva_snp_set_vld_e[3] =
1833
lsu_cpx_pkt_ifill_type ? imiss_dcd_b54[3] :
1834
  lsu_cpx_pkt_perror_dinv ? perror_dcd_b54[3] : cpx_cpu_inv_data[`CPX_AX1_INV_DVLD+11] ;
1835
 
1836
assign  dva_snp_wy0_e[1:0]   =
1837
lsu_cpx_pkt_ifill_type ? lsu_cpx_pkt_invwy[1:0] : cpx_cpu_inv_data[`CPX_AX0_INV_WY_HI:`CPX_AX0_INV_WY_LO];
1838
assign  dva_snp_wy1_e[1:0]   =
1839
lsu_cpx_pkt_ifill_type ? lsu_cpx_pkt_invwy[1:0] : cpx_cpu_inv_data[`CPX_AX1_INV_WY_HI+4:`CPX_AX1_INV_WY_LO+4];
1840
assign  dva_snp_wy2_e[1:0]   =
1841
lsu_cpx_pkt_ifill_type ? lsu_cpx_pkt_invwy[1:0] : cpx_cpu_inv_data[`CPX_AX0_INV_WY_HI+7:`CPX_AX0_INV_WY_LO+7];
1842
assign  dva_snp_wy3_e[1:0]   =
1843
lsu_cpx_pkt_ifill_type ? lsu_cpx_pkt_invwy[1:0] : cpx_cpu_inv_data[`CPX_AX1_INV_WY_HI+11:`CPX_AX1_INV_WY_LO+11];
1844
*/
1845
 
1846
wire    stack_type_dcfill_vld,
1847
        stack_type_dcfill_vld_d1;
1848
//assign  stack_type_dcfill_vld  =  dfq_st_ack_type & lsu_dfq_byp_stack_dcfill_vld; // bug 2767
1849
//--------------------------------------------------------------
1850
// st_ack_type  local_pkt   b[87]  dcfill_vld==b[151]
1851
//--------------------------------------------------------------
1852
//   1           0          0          -      pkt not modified
1853
//   1           0          1          -      pkt not modified
1854
//--------------------------------------------------------------
1855
//   1           1          0          0      pkt not modified
1856
//   1           1          0          1      pkt modified
1857
//--------------------------------------------------------------
1858
//   1           1          1          0      pkt not modified  <---using b[87] will fail even w/ local pkt qual; hence use b[151]
1859
//   1           1          1          1      pkt modified 
1860
//--------------------------------------------------------------
1861
 
1862
// 4/7/03: set dcfill_vld only for local dcache data write and not for invalidate
1863
//         atomic and bis do not write dcache and hence dont set dcfill_vld
1864
assign  stack_type_dcfill_vld  =  lsu_dfq_byp_type[2] & local_pkt & lsu_dfq_byp_cpx_inv & ~(lsu_dfq_byp_atm | lsu_dfq_byp_binit_st) ;
1865
 
1866
wire  [1:0]  lsu_dfq_byp_stack_adr_b54_d1,
1867
             lsu_dfq_byp_stack_wrway_d1;
1868
 
1869
// bug3375: add enable to this flop - dfq_vld_en
1870
dffe_s #(5)  dfq_by_wrway_ad54_ff (
1871
        .din    ({stack_type_dcfill_vld,lsu_dfq_byp_stack_adr_b54[1:0],lsu_dfq_byp_stack_wrway[1:0]}),
1872
        .q      ({stack_type_dcfill_vld_d1,lsu_dfq_byp_stack_adr_b54_d1[1:0],lsu_dfq_byp_stack_wrway_d1[1:0]}),
1873
        .en     (dfq_vld_en),
1874
        .clk  (clk),
1875
        .se     (1'b0),       .si (),          .so ()
1876
        );
1877
 
1878
//cpx_cpu_inv_data[13:0] =  {dfq_inv_data_b13to9,1'b0,dfq_inv_data_b7to2,1'b0,dfq_inv_data_b0} 
1879
//CPX_AX0_INV_DVLD 0
1880
//CPX_AX0_INV_WY_LO 2
1881
//CPX_AX0_INV_WY_HI 3
1882
//CPX_AX1_INV_DVLD 0
1883
//CPX_AX1_INV_WY_LO 1
1884
//CPX_AX1_INV_WY_HI 2
1885
 
1886
assign  dva_snp_set_vld_e[0] =
1887
lsu_cpx_pkt_ifill_type ? imiss_dcd_b54[0] :
1888
  lsu_cpx_pkt_perror_dinv ? perror_dcd_b54[0] :
1889
     stack_type_dcfill_vld_d1 ? (lsu_dfq_byp_stack_adr_b54_d1[1:0]==2'b00) : dfq_inv_data_b0 ;
1890
     //stack_type_dcfill_vld_d1 ? (lsu_dfq_byp_stack_adr_b54_d1[1:0]==2'b00) : cpx_cpu_inv_data[`CPX_AX0_INV_DVLD] ;
1891
assign  dva_snp_set_vld_e[1] =
1892
lsu_cpx_pkt_ifill_type ? imiss_dcd_b54[1] :
1893
  lsu_cpx_pkt_perror_dinv ? perror_dcd_b54[1] :
1894
     stack_type_dcfill_vld_d1 ? (lsu_dfq_byp_stack_adr_b54_d1[1:0]==2'b01) : dfq_inv_data_b7to2[4] ;
1895
     //stack_type_dcfill_vld_d1 ? (lsu_dfq_byp_stack_adr_b54_d1[1:0]==2'b01) : cpx_cpu_inv_data[`CPX_AX1_INV_DVLD+4] ;
1896
assign  dva_snp_set_vld_e[2] =
1897
lsu_cpx_pkt_ifill_type ? imiss_dcd_b54[2] :
1898
  lsu_cpx_pkt_perror_dinv ? perror_dcd_b54[2] :
1899
     stack_type_dcfill_vld_d1 ? (lsu_dfq_byp_stack_adr_b54_d1[1:0]==2'b10) : dfq_inv_data_b7to2[7] ;
1900
     //stack_type_dcfill_vld_d1 ? (lsu_dfq_byp_stack_adr_b54_d1[1:0]==2'b10) : cpx_cpu_inv_data[`CPX_AX0_INV_DVLD+7] ;
1901
assign  dva_snp_set_vld_e[3] =
1902
lsu_cpx_pkt_ifill_type ? imiss_dcd_b54[3] :
1903
  lsu_cpx_pkt_perror_dinv ? perror_dcd_b54[3] :
1904
      stack_type_dcfill_vld_d1 ? (lsu_dfq_byp_stack_adr_b54_d1[1:0]==2'b11) : dfq_inv_data_b13to9[11] ;
1905
      //stack_type_dcfill_vld_d1 ? (lsu_dfq_byp_stack_adr_b54_d1[1:0]==2'b11) : cpx_cpu_inv_data[`CPX_AX1_INV_DVLD+11] ; 
1906
 
1907
assign  dva_snp_wy0_e[1:0]   =
1908
lsu_cpx_pkt_ifill_type ? lsu_cpx_pkt_invwy[1:0] :
1909
   stack_type_dcfill_vld_d1 ? lsu_dfq_byp_stack_wrway_d1[1:0] : dfq_inv_data_b7to2[3:2] ;
1910
   //stack_type_dcfill_vld_d1 ? lsu_dfq_byp_stack_wrway_d1[1:0] : cpx_cpu_inv_data[`CPX_AX0_INV_WY_HI:`CPX_AX0_INV_WY_LO] ;
1911
assign  dva_snp_wy1_e[1:0]   =
1912
lsu_cpx_pkt_ifill_type ? lsu_cpx_pkt_invwy[1:0] :
1913
   stack_type_dcfill_vld_d1 ? lsu_dfq_byp_stack_wrway_d1[1:0] : dfq_inv_data_b7to2[6:5] ;
1914
   //stack_type_dcfill_vld_d1 ? lsu_dfq_byp_stack_wrway_d1[1:0] : cpx_cpu_inv_data[`CPX_AX1_INV_WY_HI+4:`CPX_AX1_INV_WY_LO+4] ;
1915
assign  dva_snp_wy2_e[1:0]   =
1916
lsu_cpx_pkt_ifill_type ? lsu_cpx_pkt_invwy[1:0] :
1917
   stack_type_dcfill_vld_d1 ? lsu_dfq_byp_stack_wrway_d1[1:0] : dfq_inv_data_b13to9[10:9] ;
1918
   //stack_type_dcfill_vld_d1 ? lsu_dfq_byp_stack_wrway_d1[1:0] : cpx_cpu_inv_data[`CPX_AX0_INV_WY_HI+7:`CPX_AX0_INV_WY_LO+7] ;
1919
assign  dva_snp_wy3_e[1:0]   =
1920
lsu_cpx_pkt_ifill_type ? lsu_cpx_pkt_invwy[1:0] :
1921
   stack_type_dcfill_vld_d1 ? lsu_dfq_byp_stack_wrway_d1[1:0] : dfq_inv_data_b13to9[13:12] ;
1922
   //stack_type_dcfill_vld_d1 ? lsu_dfq_byp_stack_wrway_d1[1:0] : cpx_cpu_inv_data[`CPX_AX1_INV_WY_HI+11:`CPX_AX1_INV_WY_LO+11] ;
1923
 
1924
 
1925
 
1926
//   wire [1:0] dva_snp_way_e;
1927
//assign dva_snp_way_e[1:0] =  
1928
//  dva_snp_set_vld_e[0] ?  dva_snp_wy0_e[1:0]:
1929
//  dva_snp_set_vld_e[1] ?  dva_snp_wy1_e[1:0]:
1930
//  dva_snp_set_vld_e[2] ?  dva_snp_wy2_e[1:0]:
1931
//  dva_snp_set_vld_e[3] ?  dva_snp_wy3_e[1:0]: 2'bxx;
1932
 
1933
//bug 2333 fix
1934
//06/09/03: bug 3420 - add logic for dtag parity error invalidate - inv all 4 ways of the index that had error
1935
//bug 3608 - qualify perror_dinv w/ dfq_st_vld
1936
wire     derror_inv_vld ;
1937
assign   derror_inv_vld  =  dfq_st_vld & lsu_cpx_pkt_perror_dinv ;
1938
 
1939
   assign dva_snp_bit_wr_en_e [15] =  dva_snp_set_vld_e[3] &  (( dva_snp_wy3_e [1] &  dva_snp_wy3_e[0]) | derror_inv_vld ) ;
1940
   assign dva_snp_bit_wr_en_e [14] =  dva_snp_set_vld_e[3] &  (( dva_snp_wy3_e [1] & ~dva_snp_wy3_e[0]) | derror_inv_vld );
1941
   assign dva_snp_bit_wr_en_e [13] =  dva_snp_set_vld_e[3] &  ((~dva_snp_wy3_e [1] &  dva_snp_wy3_e[0]) | derror_inv_vld );
1942
   assign dva_snp_bit_wr_en_e [12] =  dva_snp_set_vld_e[3] &  ((~dva_snp_wy3_e [1] & ~dva_snp_wy3_e[0]) | derror_inv_vld );
1943
 
1944
   assign dva_snp_bit_wr_en_e [11] =  dva_snp_set_vld_e[2] &  (( dva_snp_wy2_e [1] &  dva_snp_wy2_e[0]) | derror_inv_vld );
1945
   assign dva_snp_bit_wr_en_e [10] =  dva_snp_set_vld_e[2] &  (( dva_snp_wy2_e [1] & ~dva_snp_wy2_e[0]) | derror_inv_vld );
1946
   assign dva_snp_bit_wr_en_e [09] =  dva_snp_set_vld_e[2] &  ((~dva_snp_wy2_e [1] &  dva_snp_wy2_e[0]) | derror_inv_vld );
1947
   assign dva_snp_bit_wr_en_e [08] =  dva_snp_set_vld_e[2] &  ((~dva_snp_wy2_e [1] & ~dva_snp_wy2_e[0]) | derror_inv_vld );
1948
 
1949
   assign dva_snp_bit_wr_en_e [07] =  dva_snp_set_vld_e[1] &  (( dva_snp_wy1_e [1] &  dva_snp_wy1_e[0]) | derror_inv_vld );
1950
   assign dva_snp_bit_wr_en_e [06] =  dva_snp_set_vld_e[1] &  (( dva_snp_wy1_e [1] & ~dva_snp_wy1_e[0]) | derror_inv_vld );
1951
   assign dva_snp_bit_wr_en_e [05] =  dva_snp_set_vld_e[1] &  ((~dva_snp_wy1_e [1] &  dva_snp_wy1_e[0]) | derror_inv_vld );
1952
   assign dva_snp_bit_wr_en_e [04] =  dva_snp_set_vld_e[1] &  ((~dva_snp_wy1_e [1] & ~dva_snp_wy1_e[0]) | derror_inv_vld );
1953
 
1954
   assign dva_snp_bit_wr_en_e [03] =  dva_snp_set_vld_e[0] &  (( dva_snp_wy0_e [1] &  dva_snp_wy0_e[0]) | derror_inv_vld );
1955
   assign dva_snp_bit_wr_en_e [02] =  dva_snp_set_vld_e[0] &  (( dva_snp_wy0_e [1] & ~dva_snp_wy0_e[0]) | derror_inv_vld );
1956
   assign dva_snp_bit_wr_en_e [01] =  dva_snp_set_vld_e[0] &  ((~dva_snp_wy0_e [1] &  dva_snp_wy0_e[0]) | derror_inv_vld );
1957
   assign dva_snp_bit_wr_en_e [00] =  dva_snp_set_vld_e[0] &  ((~dva_snp_wy0_e [1] & ~dva_snp_wy0_e[0]) | derror_inv_vld );
1958
 
1959
 
1960
//=================================================================================================
1961
//  LOCAL ST ACK PROCESSING
1962
//=================================================================================================
1963
 
1964
// st-ack at head of cfq may write to cache if not indicated as invalid 
1965
// L2.
1966
 
1967
//wire  byp_tag_perror ;
1968
//assign        byp_tag_perror = lsu_dfq_byp_perror_dinv | lsu_dfq_byp_perror_iinv ;
1969
 
1970
// one-shot rd-enable for stb for st data.
1971
// st-quad pkt2 will not rd stb
1972
//NOTE: restore cpx_inv qualification after adding cpx_inv part of dfq read - done
1973
/*
1974
assign  st_ack_rq_stb =
1975
   (dfq_byp_st_vld & st_rd_advance & ~byp_tag_perror)   // local st ack from dfq
1976
  & lsu_dfq_byp_cpx_inv ;
1977
*/
1978
  //((cpx_local_st_ack_type & ~dfq_wr_en & ~(|cpx_spc_data_cx[`CPX_PERR_DINV+1:`CPX_PERR_DINV])) | // local st ack from cpx
1979
  //(dfq_byp_st_vld & dfq_rd_advance & ~byp_tag_perror))   // local st ack from dfq
1980
  //(dfq_byp_st_vld & dfq_rd_advance_d1)) // local st ack from dfq
1981
 
1982
/*assign  st_ack_rq_stb =
1983
  ((cpx_local_st_ack_type & ~dfq_wr_en & ~cpx_spc_data_cx[107]) | // local st ack from cpx
1984
  (dfq_byp_st_vld & dfq_rd_advance & ~lsu_dfq_byp_stquad_pkt2))   // local st ack from dfq
1985
  //(dfq_byp_st_vld & dfq_rd_advance_d1)) // local st ack from dfq
1986
  & cpx_inv ; */
1987
 
1988
/*
1989
dff_s #(1)  stackr_d1 (
1990
        .din    (st_ack_rq_stb),
1991
        .q      (st_ack_rq_stb_d1),
1992
        .clk  (clk),
1993
        .se     (1'b0),       .si (),          .so ()
1994
        );
1995
*/
1996
 
1997
// Mux's control signal can be flipped - TIMING
1998
//assign  st_ack_tid[1:0] =
1999
//  (dfq_byp_st_vld & dfq_rd_advance) ?  
2000
//      lsu_dfq_byp_tid[1:0] : cpx_spc_data_cx[`CPX_TH_HI:`CPX_TH_LO] ;
2001
 
2002
// This can be critical !!!
2003
//assign  lsu_st_ack_rq_stb[0] = ~st_ack_tid[1] & ~st_ack_tid[0] & st_ack_rq_stb ;
2004
//assign  lsu_st_ack_rq_stb[1] = ~st_ack_tid[1] &  st_ack_tid[0] & st_ack_rq_stb ;
2005
//assign  lsu_st_ack_rq_stb[2] =  st_ack_tid[1] & ~st_ack_tid[0] & st_ack_rq_stb ;
2006
//assign  lsu_st_ack_rq_stb[3] =  st_ack_tid[1] &  st_ack_tid[0] & st_ack_rq_stb ;
2007
 
2008
// the ack decode can be combined with the above (grape)
2009
 
2010
assign  lsu_st_ack_dq_stb[0] =
2011
        cpx_pkt_thrd_sel[0] & dfq_st_cmplt &
2012
        ~(lsu_cpx_pkt_perror_dinv | lsu_cpx_pkt_perror_iinv | lsu_cpx_pkt_binit_st) ;
2013
assign  lsu_st_ack_dq_stb[1] =
2014
        cpx_pkt_thrd_sel[1] & dfq_st_cmplt &
2015
        ~(lsu_cpx_pkt_perror_dinv | lsu_cpx_pkt_perror_iinv | lsu_cpx_pkt_binit_st) ;
2016
assign  lsu_st_ack_dq_stb[2] =
2017
        cpx_pkt_thrd_sel[2] & dfq_st_cmplt &
2018
        ~(lsu_cpx_pkt_perror_dinv | lsu_cpx_pkt_perror_iinv | lsu_cpx_pkt_binit_st) ;
2019
assign  lsu_st_ack_dq_stb[3] =
2020
        cpx_pkt_thrd_sel[3] & dfq_st_cmplt &
2021
        ~(lsu_cpx_pkt_perror_dinv | lsu_cpx_pkt_perror_iinv | lsu_cpx_pkt_binit_st) ;
2022
 
2023
// Signal rmo ack completion.
2024
assign  lsu_cpx_rmo_st_ack[0] =
2025
        cpx_pkt_thrd_sel[0] & dfq_st_cmplt  & lsu_cpx_pkt_binit_st ;
2026
assign  lsu_cpx_rmo_st_ack[1] =
2027
        cpx_pkt_thrd_sel[1] & dfq_st_cmplt  & lsu_cpx_pkt_binit_st ;
2028
assign  lsu_cpx_rmo_st_ack[2] =
2029
        cpx_pkt_thrd_sel[2] & dfq_st_cmplt  & lsu_cpx_pkt_binit_st ;
2030
assign  lsu_cpx_rmo_st_ack[3] =
2031
        cpx_pkt_thrd_sel[3] & dfq_st_cmplt  & lsu_cpx_pkt_binit_st ;
2032
 
2033
assign  lsu_st_wr_dcache = stwr_active_e ;
2034
 
2035
//assign  lsu_st_wr_sel_e = stwr_active_e |  lsu_diagnstc_wr_src_sel_e ;
2036
 
2037
//=================================================================================================
2038
//  CPX PKT DECODE
2039
//=================================================================================================
2040
 
2041
// The decode is meant to qualify writes into the dfq.
2042
// These values are also stored in the dfq to save on decode at the head of the queue.
2043
 
2044
assign lsu_cpxpkt_type_dcd_cx[5:0] =
2045
{cpx_ld_type,cpx_ifill_type,cpx_evict_type,cpx_st_ack_type,cpx_strm_st_ack_type,cpx_int_type};
2046
 
2047
assign  cpx_ld_type =
2048
         cpx_spc_data_cx_b144to140[`CPX_VLD] &
2049
        ((~cpx_spc_data_cx_b144to140[`CPX_RQ_HI]   & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+2] & // 0000
2050
          ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+1] & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO]));
2051
 
2052
assign  cpx_ifill_type =
2053
         cpx_spc_data_cx_b144to140[`CPX_VLD] &
2054
        ((~cpx_spc_data_cx_b144to140[`CPX_RQ_HI]   & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+2] & // 0001
2055
          ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+1] &  cpx_spc_data_cx_b144to140[`CPX_RQ_LO]));
2056
 
2057
assign  cpx_evict_type =
2058
         cpx_spc_data_cx_b144to140[`CPX_VLD] &
2059
        ((~cpx_spc_data_cx_b144to140[`CPX_RQ_HI]   & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+2] & // 0011
2060
           cpx_spc_data_cx_b144to140[`CPX_RQ_LO+1] &  cpx_spc_data_cx_b144to140[`CPX_RQ_LO]));
2061
 
2062
assign  cpx_st_ack_type =
2063
         cpx_spc_data_cx_b144to140[`CPX_VLD] &
2064
        ((~cpx_spc_data_cx_b144to140[`CPX_RQ_HI]  &   cpx_spc_data_cx_b144to140[`CPX_RQ_LO+2] & // 0100
2065
          ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+1] & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO]));
2066
         //~cpx_spc_data_cx[108] ;  // 1st stquad ack is rejected
2067
 
2068
assign  cpx_strm_st_ack_type =
2069
         cpx_spc_data_cx_b144to140[`CPX_VLD] &
2070
        ((~cpx_spc_data_cx_b144to140[`CPX_RQ_HI]   &  cpx_spc_data_cx_b144to140[`CPX_RQ_LO+2] & // 0110
2071
           cpx_spc_data_cx_b144to140[`CPX_RQ_LO+1] & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO]));
2072
 
2073
assign  cpx_int_type =
2074
         cpx_spc_data_cx_b144to140[`CPX_VLD] &
2075
        ((~cpx_spc_data_cx_b144to140[`CPX_RQ_HI]   &  cpx_spc_data_cx_b144to140[`CPX_RQ_LO+2] & // 0111
2076
           cpx_spc_data_cx_b144to140[`CPX_RQ_LO+1] &  cpx_spc_data_cx_b144to140[`CPX_RQ_LO]));
2077
 
2078
//bug3657  - kill ifill vld in bypass path when cpxtype=fp/fwd_reply
2079
 
2080
assign  cpx_fp_type =
2081
         cpx_spc_data_cx_b144to140[`CPX_VLD] &
2082
        (( cpx_spc_data_cx_b144to140[`CPX_RQ_HI]   & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+2] & // 1000
2083
          ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+1] & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO]));
2084
 
2085
//8/25/03: add error type to dfq_wr_en, dfq_rd_advance
2086
assign  cpx_error_type =
2087
         cpx_spc_data_cx_b144to140[`CPX_VLD] &
2088
        (( cpx_spc_data_cx_b144to140[`CPX_RQ_HI]   &  cpx_spc_data_cx_b144to140[`CPX_RQ_LO+2] & // 1100
2089
          ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO+1] & ~cpx_spc_data_cx_b144to140[`CPX_RQ_LO]));
2090
 
2091
// Miscellaneous cpu based decode
2092
 
2093
assign  lsu_cpu_dcd_sel[7:0]  = {cpu_sel[3:0],cpu_sel[3:0]} ;
2094
assign  lsu_cpu_uhlf_sel  = const_cpuid[2] ;
2095
 
2096
// removed cpu_id[2] qual in the eqn.
2097
assign  cpu_sel[0] =  ~const_cpuid[1] & ~const_cpuid[0] ;
2098
assign  cpu_sel[1] =  ~const_cpuid[1] &  const_cpuid[0] ;
2099
assign  cpu_sel[2] =   const_cpuid[1] & ~const_cpuid[0] ;
2100
assign  cpu_sel[3] =   const_cpuid[1] &  const_cpuid[0] ;
2101
 
2102
 
2103
// st ack to respective stb's. will not be generated for blk init stores
2104
// as such stores have already been deallocated.
2105
 
2106
assign  cpx_local_st_ack_type =
2107
  cpx_st_ack_type & (const_cpuid[2:0] == cpx_spc_data_cx_b120to118[`CPX_INV_CID_HI:`CPX_INV_CID_LO]) ;
2108
 // & ~(cpx_spc_data_cx[`CPX_BINIT_STACK] | (|cpx_spc_data_cx[`CPX_PERR_DINV+1:`CPX_PERR_DINV])) ;
2109
 
2110
wire    squash_ack ;
2111
assign squash_ack =
2112
(cpx_spc_data_cx_b125 | (|cpx_spc_data_cx_b124to123[`CPX_PERR_DINV+1:`CPX_PERR_DINV])) ;
2113
 
2114
assign  cpx_st_ack_tid0 = cpx_local_st_ack_type & ~squash_ack &
2115
                        ~cpx_spc_data_cx_b135to134[`CPX_TH_HI] & ~cpx_spc_data_cx_b135to134[`CPX_TH_LO] ;
2116
                        //~cpx_spc_data_cx[125] ; // rmo st will not ack
2117
                        //~cpx_spc_data_cx[`CPX_WY_LO] ; // stquad1 will not ack - just invalidate.
2118
                                                      // b131 of cpx pkt used.  
2119
 
2120
assign  cpx_st_ack_tid1 = cpx_local_st_ack_type & ~squash_ack &
2121
                        ~cpx_spc_data_cx_b135to134[`CPX_TH_HI] &  cpx_spc_data_cx_b135to134[`CPX_TH_LO] ;
2122
                        //~cpx_spc_data_cx[125] ; // rmo st will not ack
2123
                        //~cpx_spc_data_cx[`CPX_WY_LO] ; // stquad1 will not ack - just invalidate.
2124
                                                      // b131 of cpx pkt used.
2125
 
2126
assign  cpx_st_ack_tid2 = cpx_local_st_ack_type & ~squash_ack &
2127
                         cpx_spc_data_cx_b135to134[`CPX_TH_HI] & ~cpx_spc_data_cx_b135to134[`CPX_TH_LO] ;
2128
                        //~cpx_spc_data_cx[125] ; // rmo st will not ack
2129
                        //~cpx_spc_data_cx[`CPX_WY_LO] ; // stquad1 will not ack - just invalidate.
2130
                                                      // b131 of cpx pkt used. 
2131
 
2132
assign  cpx_st_ack_tid3 = cpx_local_st_ack_type & ~squash_ack &
2133
                         cpx_spc_data_cx_b135to134[`CPX_TH_HI] & cpx_spc_data_cx_b135to134[`CPX_TH_LO] ;
2134
                        //~cpx_spc_data_cx[125] ; // rmo st will not ack
2135
                        //~cpx_spc_data_cx[`CPX_WY_LO] ; // stquad1 will not ack - just invalidate.
2136
                                                      // b131 of cpx pkt used.
2137
 
2138
// Performance Ctr Info
2139
//assign lsu_tlu_l2_dmiss[0] =  dfill_dcd_thrd[0] & dcfill_active_e & lsu_cpx_pkt_l2miss ;
2140
assign lsu_tlu_l2_dmiss[0] =  dfq_thread0 & dcfill_active_e & lsu_cpx_pkt_l2miss ;
2141
assign lsu_tlu_l2_dmiss[1] =  dfq_thread1 & dcfill_active_e & lsu_cpx_pkt_l2miss ;
2142
assign lsu_tlu_l2_dmiss[2] =  dfq_thread2 & dcfill_active_e & lsu_cpx_pkt_l2miss ;
2143
assign lsu_tlu_l2_dmiss[3] =  dfq_thread3 & dcfill_active_e & lsu_cpx_pkt_l2miss ;
2144
 
2145
//=================================================================================================
2146
//  GENERATE b[151] of DFQ WRITE DATA
2147
//=================================================================================================
2148
wire  [7:0]  cpx_inv_vld;
2149
wire  [7:0]  cpu_sel_dcd;
2150
 
2151
assign  cpx_inv_vld[0] = cpx_spc_data_cx_b88 |
2152
                         cpx_spc_data_cx_b56 |
2153
                         cpx_spc_data_cx_b32 |
2154
                         cpx_spc_data_cx_b0 ;
2155
 
2156
assign  cpx_inv_vld[1] = cpx_spc_data_cx_b91 |
2157
                         cpx_spc_data_cx_b60 |
2158
                         cpx_spc_data_cx_b35 |
2159
                         cpx_spc_data_cx_b4 ;
2160
 
2161
assign  cpx_inv_vld[2] = cpx_spc_data_cx_b94 |
2162
                         cpx_spc_data_cx_b64 |
2163
                         cpx_spc_data_cx_b38 |
2164
                         cpx_spc_data_cx_b8 ;
2165
 
2166
assign  cpx_inv_vld[3] = cpx_spc_data_cx_b97 |
2167
                         cpx_spc_data_cx_b68 |
2168
                         cpx_spc_data_cx_b41 |
2169
                         cpx_spc_data_cx_b12 ;
2170
 
2171
assign  cpx_inv_vld[4] = cpx_spc_data_cx_b100 |
2172
                         cpx_spc_data_cx_b72  |
2173
                         cpx_spc_data_cx_b44  |
2174
                         cpx_spc_data_cx_b16  ;
2175
 
2176
assign  cpx_inv_vld[5] = cpx_spc_data_cx_b103 |
2177
                         cpx_spc_data_cx_b76  |
2178
                         cpx_spc_data_cx_b47  |
2179
                         cpx_spc_data_cx_b20  ;
2180
 
2181
assign  cpx_inv_vld[6] = cpx_spc_data_cx_b106 |
2182
                         cpx_spc_data_cx_b80  |
2183
                         cpx_spc_data_cx_b50  |
2184
                         cpx_spc_data_cx_b24  ;
2185
 
2186
assign  cpx_inv_vld[7] = cpx_spc_data_cx_b109 |
2187
                         cpx_spc_data_cx_b84  |
2188
                         cpx_spc_data_cx_b53  |
2189
                         cpx_spc_data_cx_b28  ;
2190
 
2191
assign cpu_sel_dcd[7:4] =  ({4{ lsu_cpu_uhlf_sel}} & cpu_sel[3:0]);
2192
assign cpu_sel_dcd[3:0] =  ({4{~lsu_cpu_uhlf_sel}} & cpu_sel[3:0]);
2193
 
2194
assign lsu_cpx_spc_inv_vld  =  |(cpx_inv_vld[7:0] & cpu_sel_dcd[7:0]);
2195
 
2196
//=================================================================================================
2197
//  GENERATE ICACHE INVALIDATE VALID (bug:2770)
2198
//=================================================================================================
2199
 
2200
wire  [7:0]  cpx_iinv_vld;
2201
wire         cpx_spc_iinv_vld;
2202
 
2203
assign  cpx_iinv_vld[0] = cpx_spc_data_cx_b57 |
2204
                          cpx_spc_data_cx_b1  ;
2205
 
2206
assign  cpx_iinv_vld[1] = cpx_spc_data_cx_b61 |
2207
                          cpx_spc_data_cx_b5  ;
2208
 
2209
assign  cpx_iinv_vld[2] = cpx_spc_data_cx_b65 |
2210
                          cpx_spc_data_cx_b9  ;
2211
 
2212
assign  cpx_iinv_vld[3] = cpx_spc_data_cx_b69 |
2213
                          cpx_spc_data_cx_b13 ;
2214
 
2215
assign  cpx_iinv_vld[4] = cpx_spc_data_cx_b73 |
2216
                          cpx_spc_data_cx_b17 ;
2217
 
2218
assign  cpx_iinv_vld[5] = cpx_spc_data_cx_b77 |
2219
                          cpx_spc_data_cx_b21 ;
2220
 
2221
assign  cpx_iinv_vld[6] = cpx_spc_data_cx_b81 |
2222
                          cpx_spc_data_cx_b25 ;
2223
 
2224
assign  cpx_iinv_vld[7] = cpx_spc_data_cx_b85 |
2225
                          cpx_spc_data_cx_b29 ;
2226
 
2227
//bug3701 - include i$ parity error invalidate - b[124]
2228
assign cpx_spc_iinv_vld  =  |( (cpx_iinv_vld[7:0] | {8{cpx_spc_data_cx_b124to123[`CPX_PERR_DINV+1]}}) & cpu_sel_dcd[7:0] )  ;
2229
 
2230
 
2231
// dfq_rd_advance - local st ack not qualified w/ ifu_lsu_ibuf_busy
2232
// qualify ifu_busy w/ local_st_ack=1 and iinv=1
2233
 
2234
assign lsu_cpx_stack_icfill_vld  =
2235
                  ( cpx_local_st_ack_type & cpx_spc_iinv_vld) |        //if local st_ack=1, b[128]=iinv
2236
                  (~cpx_local_st_ack_type & cpx_spc_data_cx_b128) ;    //if local st_ack=0, b[128]=cpx_data[128]
2237
 
2238
//=================================================================================================
2239
//  MISC QDP2 MUX SELECTS
2240
//=================================================================================================
2241
 
2242
//assign  lsu_dcfill_mx_sel_e[0]  =  lsu_dc_iob_access_e;
2243
//assign  lsu_dcfill_mx_sel_e[1]  =  lsu_bist_wvld_e | lsu_bist_rvld_e;
2244
//assign  lsu_dcfill_mx_sel_e[2]  =  lsu_diagnstc_wr_src_sel_e;
2245
//assign  lsu_dcfill_mx_sel_e[3]  =  ~|lsu_dcfill_mx_sel_e[2:0];
2246
 
2247
//assign  lsu_dcfill_addr_mx_sel_e  =  ~|lsu_dcfill_mx_sel_e[1:0];
2248
 
2249
//assign  lsu_dcfill_data_mx_sel_e  =  lsu_dc_iob_access_e | lsu_bist_wvld_e;
2250
 
2251
assign lsu_cpx_thrdid[0]  =  ~cpx_spc_data_cx_b135to134[`CPX_TH_HI] & ~cpx_spc_data_cx_b135to134[`CPX_TH_LO] ;
2252
assign lsu_cpx_thrdid[1]  =  ~cpx_spc_data_cx_b135to134[`CPX_TH_HI] &  cpx_spc_data_cx_b135to134[`CPX_TH_LO] ;
2253
assign lsu_cpx_thrdid[2]  =   cpx_spc_data_cx_b135to134[`CPX_TH_HI] & ~cpx_spc_data_cx_b135to134[`CPX_TH_LO] ;
2254
assign lsu_cpx_thrdid[3]  =   cpx_spc_data_cx_b135to134[`CPX_TH_HI] &  cpx_spc_data_cx_b135to134[`CPX_TH_LO] ;
2255
 
2256
// modify cpx packet only if dcache update from stb has to be made. 
2257
// lsu_cpx_spc_inv_vld = 1 => invalidate dcache for atomic- b[129] and bst- b[125]
2258
//                            update dcache for other requests
2259
//
2260
// i.e. cpx_pkt==st_ack and local and dcfill_vld=1; if dcfill_vld==0, ifill info
2261
// has to be left as is. hence no pkt modification
2262
 
2263
assign lsu_cpx_stack_dcfill_vld  =
2264
                       (cpx_local_st_ack_type & ~(cpx_spc_data_cx_b129 | cpx_spc_data_cx_b125))  &
2265
                       lsu_cpx_spc_inv_vld ;
2266
 
2267
//timing fix: 6/16/03 - fix for ifill_pkt_vld - use b130 if store_ack_dcfill_vld=1
2268
//bug3582 - b[130] for store ack is a dont-care i.e. capture b[130] only if packet type is not store ack
2269
assign lsu_cpx_stack_dcfill_vld_b130  =  // if lsu_cpx_stack_dcfill_vld=1 b[130]=lsu_cpx_stack_dcfill_vld
2270
                                         // if cpx_st_ack=0 b[130]=cpx_data[130]
2271
                                       lsu_cpx_stack_dcfill_vld |
2272
                                       (~cpx_st_ack_type & cpx_spc_data_cx_b130) ;
2273
endmodule

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