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[/] [sparc64soc/] [trunk/] [T1-CPU/] [lsu/] [lsu_qdp1.v] - Blame information for rev 2

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1 2 dmitryr 
// ========== Copyright Header Begin ==========================================
2 
//
3 
// OpenSPARC T1 Processor File: lsu_qdp1.v
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// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
5 
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6 
//
7 
// The above named program is free software; you can redistribute it and/or
8 
// modify it under the terms of the GNU General Public
9 
// License version 2 as published by the Free Software Foundation.
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//
11 
// The above named program is distributed in the hope that it will be
12 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14 
// General Public License for more details.
15 
//
16 
// You should have received a copy of the GNU General Public
17 
// License along with this work; if not, write to the Free Software
18 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19 
//
20 
// ========== Copyright Header End ============================================
21 
///////////////////////////////////////////////////////////////////////
22 
/*
23 
//  Description:  LSU PCX Datapath - QDP1
24 
*/
25 
////////////////////////////////////////////////////////////////////////
26 
// header file includes
27 
////////////////////////////////////////////////////////////////////////
28 
`include  "sys.h" // system level definition file which contains the
29 
          // time scale definition
30 
`include  "iop.h"
31 
`include  "lsu.h"
32 
 
33 
////////////////////////////////////////////////////////////////////////
34 
// Local header file includes / local defines
35 
////////////////////////////////////////////////////////////////////////
36 
 
37 
//FPGA_SYN enables all FPGA related modifications
38 
`ifdef FPGA_SYN
39 
`define FPGA_SYN_CLK_EN
40 
`define FPGA_SYN_CLK_DFF
41 
`endif
42 
 
43 
module lsu_qdp1 ( /*AUTOARG*/
44 
   // Outputs
45 
   so, lsu_va_match_b47_b32_m, lsu_va_match_b31_b3_m, lsu_va_wtchpt_addr, spc_pcx_data_pa,
46 
   dtag_wdata_m, lmq0_byp_misc_sz, lmq1_byp_misc_sz,
47 
   lmq2_byp_misc_sz, lmq3_byp_misc_sz, lsu_byp_misc_sz_e,
48 
   lsu_l2fill_sign_extend_m, lsu_l2fill_bendian_m, lmq0_l2fill_fpld,
49 
   lmq1_l2fill_fpld, lmq2_l2fill_fpld, lmq3_l2fill_fpld, lmq_ld_rd1,
50 
   lmq0_ncache_ld, lmq1_ncache_ld, lmq2_ncache_ld, lmq3_ncache_ld,
51 
   lmq0_ld_rq_type, lmq1_ld_rq_type, lmq2_ld_rq_type,
52 
   lmq3_ld_rq_type, lmq0_ldd_vld, lmq1_ldd_vld, lmq2_ldd_vld,
53 
   lmq3_ldd_vld, ld_sec_hit_thrd0, ld_sec_hit_thrd1,
54 
   ld_sec_hit_thrd2, ld_sec_hit_thrd3, lmq0_pcx_pkt_addr,
55 
   lmq1_pcx_pkt_addr, lmq2_pcx_pkt_addr, lmq3_pcx_pkt_addr,
56 
   lsu_mmu_rs3_data_g, lsu_tlu_rs3_data_g, lsu_diagnstc_wr_data_b0,
57 
   lsu_diagnstc_wr_data_e, lsu_ifu_stxa_data,
58 
   lsu_ifu_ld_icache_index, lsu_ifu_ld_pcxpkt_tid, lsu_error_pa_m,
59 
   lsu_pref_pcx_req, st_rs3_data_g, lsu_ldst_va_way_g,
60 
   dcache_alt_data_w0_m,
61 
   // Inputs
62 
   rclk, si, se, lsu_dcache_iob_rd_w, lsu_ramtest_rd_w,
63 
   lsu_pcx_rq_sz_b3, lsu_diagnstc_data_sel, pcx_pkt_src_sel,
64 
   lsu_stb_pcx_rvld_d1, imiss_pcx_mx_sel, fwd_int_fp_pcx_mx_sel,
65 
   spu_lsu_ldst_pckt, tlu_lsu_pcxpkt, const_cpuid, ifu_pcx_pkt,
66 
   lmq_byp_data_en_w2, lmq_byp_data_sel0, lmq_byp_data_sel1,
67 
   lmq_byp_data_sel2, lmq_byp_data_sel3, lmq_byp_ldxa_sel0,
68 
   lmq_byp_ldxa_sel1, lmq_byp_ldxa_sel2, lmq_byp_ldxa_sel3,
69 
   lmq_byp_data_fmx_sel, exu_lsu_rs3_data_e, ifu_lsu_ldxa_data_w2,
70 
   tlu_lsu_int_ldxa_data_w2, spu_lsu_ldxa_data_w2, stb_rdata_ramd,
71 
   stb_rdata_ramc, lmq_byp_misc_sel, dfq_byp_sel, ld_pcx_rq_sel,
72 
   ld_pcx_thrd, lmq_enable, ld_pcx_pkt_g, ffu_lsu_data,
73 
   lsu_tlb_st_sel_m, lsu_pcx_fwd_pkt, lsu_pcx_fwd_reply,
74 
   lsu_diagnstc_dtagv_prty_invrt_e, lsu_misc_rdata_w2,
75 
   lsu_stb_rd_tid, lsu_iobrdge_rply_data_sel, lsu_iobrdge_rd_data,
76 
   lsu_atomic_pkt2_bsel_g, lsu_pcx_ld_dtag_perror_w2,
77 
   lsu_dcache_rdata_w, lsu_va_wtchpt0_wr_en_l,
78 
   lsu_va_wtchpt1_wr_en_l, lsu_va_wtchpt2_wr_en_l,
79 
   lsu_va_wtchpt3_wr_en_l, thread0_m, thread1_m, thread2_m,
80 
   thread3_m, lsu_thread_g, lsu_ldst_va_m, tlb_pgnum, lsu_bld_pcx_rq,
81 
   lsu_bld_rq_addr, lmq0_pcx_pkt_way, lmq1_pcx_pkt_way,
82 
   lmq2_pcx_pkt_way, lmq3_pcx_pkt_way, lsu_dfq_ld_vld,
83 
   lsu_ifu_asi_data_en_l, lsu_ld0_spec_vld_kill_w2,
84 
   lsu_ld1_spec_vld_kill_w2, lsu_ld2_spec_vld_kill_w2,
85 
   lsu_ld3_spec_vld_kill_w2, lsu_fwd_rply_sz1_unc, rst_tri_en,
86 
   lsu_l2fill_data, l2fill_vld_m, ld_thrd_byp_sel_m, sehold
87 
   ) ;
88 
 
89 
input                     rclk ;
90 
input                     si;
91 
input                     se;
92 
input                     sehold;
93 
//input                   tmb_l;
94 
 
95 
output                    so;
96 
input                     lsu_dcache_iob_rd_w ;
97 
input                     lsu_ramtest_rd_w ;
98 
 
99 
input                    lsu_pcx_rq_sz_b3 ;
100 
 
101 
input  [3:0]               lsu_diagnstc_data_sel ;
102 
 
103 
input   [3:0]             pcx_pkt_src_sel ;       // sel 1/4 pkt src for pcx.
104 
input                     lsu_stb_pcx_rvld_d1 ;   // stb has been read-delayby1cycle
105 
input                     imiss_pcx_mx_sel ;      // select imiss over spu.
106 
input   [2:0]             fwd_int_fp_pcx_mx_sel ; // select fwd/intrpt/fpop
107 
 
108 
input   [`PCX_WIDTH-1:0]  spu_lsu_ldst_pckt ;     // stream ld/st pkt for pcx.
109 
input   [25:0]            tlu_lsu_pcxpkt ;        // truncated pcx interrupt pkt.
110 
input   [2:0]             const_cpuid ;           // cpu id
111 
input   [51:0]            ifu_pcx_pkt ;           // ifu imiss request.
112 
input   [3:0]             lmq_byp_data_en_w2 ;
113 
input   [3:0]             lmq_byp_data_sel0 ;     // ldxa/stb/cas bypass data sel.
114 
input   [3:0]             lmq_byp_data_sel1 ;     // ldxa/stb/cas bypass data sel.
115 
input   [3:0]             lmq_byp_data_sel2 ;     // ldxa/stb/cas bypass data sel.
116 
input   [3:0]             lmq_byp_data_sel3 ;     // ldxa/stb/cas bypass data sel.
117 
input   [2:0]             lmq_byp_ldxa_sel0 ;     // ldxa data sel - thread0
118 
input   [2:0]             lmq_byp_ldxa_sel1 ;     // ldxa data sel - thread1
119 
input   [2:0]             lmq_byp_ldxa_sel2 ;     // ldxa data sel - thread2
120 
input   [2:0]             lmq_byp_ldxa_sel3 ;     // ldxa data sel - thread3
121 
input   [3:0]              lmq_byp_data_fmx_sel ;  // final sel for lmq data.
122 
input   [63:0]            exu_lsu_rs3_data_e ;    // rs3_data for cas pkt 2.
123 
input   [63:0]            ifu_lsu_ldxa_data_w2 ;  // ldxa data from ifu.
124 
//input   [63:0]            tlu_lsu_ldxa_data_w2 ;  // ldxa data from tlu (mmu)
125 
input   [63:0]            tlu_lsu_int_ldxa_data_w2 ;  // ldxa data from tlu (intrpt/scpd)
126 
input   [63:0]            spu_lsu_ldxa_data_w2 ;  // ldxa data from spu
127 
input   [75:0]            stb_rdata_ramd ;        // stb0 data ram output.
128 
input   [44:9]            stb_rdata_ramc ;        // stb0 tag ram output.
129 
input   [3:0]             lmq_byp_misc_sel ;      // select g-stage lmq source
130 
input   [3:0]             dfq_byp_sel ;
131 
input   [3:0]             ld_pcx_rq_sel ;
132 
input   [1:0]             ld_pcx_thrd ;
133 
 
134 
input   [3:0]             lmq_enable ;             // 4 enables for lmq.
135 
input   [`LMQ_WIDTH-1:40]  ld_pcx_pkt_g ;           // ld miss pkt for thread.
136 
input   [80:0]            ffu_lsu_data ;
137 
input   [3:0]             lsu_tlb_st_sel_m ;
138 
//input   [3:0]             lsu_tlb_st_sel_g ;
139 
//input                     lsu_tlb_st_vld_g ;
140 
input   [107:0]           lsu_pcx_fwd_pkt ;         // local fwd reply/req
141 
input                     lsu_pcx_fwd_reply ;       // fwd reply on pcx pkt
142 
input                     lsu_diagnstc_dtagv_prty_invrt_e ;
143 
//input                     lsu_diagnstc_wr_src_sel_e ;// dcache/dtag/v write - diag
144 
//input   [47:0]            lsu_local_ldxa_data_w2 ;   // local ldxa data
145 
input   [63:0]            lsu_misc_rdata_w2 ;   // local ldxa data
146 
input   [1:0]             lsu_stb_rd_tid ;           // thread for which stb rd occurs
147 
input   [2:0]             lsu_iobrdge_rply_data_sel ;
148 
input   [43:0]            lsu_iobrdge_rd_data ;
149 
input   [2:0]             lsu_atomic_pkt2_bsel_g ;
150 
input                     lsu_pcx_ld_dtag_perror_w2 ;
151 
input   [63:0]             lsu_dcache_rdata_w ;
152 
//input   [47:0]            tlu_lsu_iobrdge_pc_data ;  // NOTE: unused: remove this in sync w/ tlu
153 
 
154 
input         lsu_va_wtchpt0_wr_en_l;
155 
input         lsu_va_wtchpt1_wr_en_l;
156 
input         lsu_va_wtchpt2_wr_en_l;
157 
input         lsu_va_wtchpt3_wr_en_l;
158 
input         thread0_m;
159 
input         thread1_m;
160 
input         thread2_m;
161 
input         thread3_m;
162 
 
163 
   input [3:0] lsu_thread_g;
164 
 
165 
 
166 
//input         lsu_pa_wtchpt_wr_en_l;
167 
input [47:0]  lsu_ldst_va_m;
168 
input [39:13] tlb_pgnum;
169 
input         lsu_bld_pcx_rq ;        // cycle after request
170 
input [1:0]   lsu_bld_rq_addr ;       // cycle after request
171 
 
172 
//input  [1:0]           lsu_lmq_pkt_way_g;
173 
input  [1:0]           lmq0_pcx_pkt_way;
174 
input  [1:0]           lmq1_pcx_pkt_way;
175 
input  [1:0]           lmq2_pcx_pkt_way;
176 
input  [1:0]           lmq3_pcx_pkt_way;
177 
 
178 
input           lsu_dfq_ld_vld ;
179 
input           lsu_ifu_asi_data_en_l ;
180 
 
181 
input           lsu_ld0_spec_vld_kill_w2 ;
182 
input           lsu_ld1_spec_vld_kill_w2 ;
183 
input           lsu_ld2_spec_vld_kill_w2 ;
184 
input           lsu_ld3_spec_vld_kill_w2 ;
185 
 
186 
input           lsu_fwd_rply_sz1_unc ;
187 
 
188 
input           rst_tri_en ;
189 
 
190 
output        lsu_va_match_b47_b32_m;
191 
output        lsu_va_match_b31_b3_m;
192 
 
193 
//output        lsu_pa_match_b39_13_g;
194 
//output        lsu_pa_match_b12_3_m;
195 
output [47:3] lsu_va_wtchpt_addr;
196 
//output [39:3] lsu_pa_wtchpt_addr;
197 
 
198 
//output  [63:0]            ld_stb_bypass_data ;  // st to load bypass data.
199 
 
200 
output  [`PCX_WIDTH-1:0]  spc_pcx_data_pa ;
201 
output  [29:0]            dtag_wdata_m ;            // tag to write to dtag.
202 
//output  [3:0]             lsu_byp_misc_addr_m ;     // lower 3bits of addr for ldxa/raw etc
203 
//output  [1:0]             lsu_byp_misc_sz_m ;       // size for ldxa/raw etc
204 
output  [1:0]             lmq0_byp_misc_sz ;
205 
output  [1:0]             lmq1_byp_misc_sz ;
206 
output  [1:0]             lmq2_byp_misc_sz ;
207 
output  [1:0]             lmq3_byp_misc_sz ;
208 
 
209 
output  [1:0]             lsu_byp_misc_sz_e ;       // size for ldxa/raw etc
210 
output                    lsu_l2fill_sign_extend_m ;// requires sign-extend else zero extend
211 
output                    lsu_l2fill_bendian_m ;    // big endian fill/bypass.
212 
//output                    lsu_l2fill_fpld_e ;       // fp load
213 
output                    lmq0_l2fill_fpld ;       // fp load
214 
output                    lmq1_l2fill_fpld ;       // fp load
215 
output                    lmq2_l2fill_fpld ;       // fp load
216 
output                    lmq3_l2fill_fpld ;       // fp load
217 
 
218 
output  [4:0]             lmq_ld_rd1 ;              // rd for all loads
219 
//output                    lsu_ncache_ld_e ;         // non-cacheable ld from dfq
220 
output                    lmq0_ncache_ld ;         // non-cacheable ld from dfq
221 
output                    lmq1_ncache_ld ;         // non-cacheable ld from dfq
222 
output                    lmq2_ncache_ld ;         // non-cacheable ld from dfq
223 
output                    lmq3_ncache_ld ;         // non-cacheable ld from dfq
224 
//output  [2:0]             lsu_ld_rq_type_e ;        // for identifying atomic ld.
225 
 
226 
output  [2:0]             lmq0_ld_rq_type ;        // for identifying atomic ld.
227 
output  [2:0]             lmq1_ld_rq_type ;        // for identifying atomic ld.
228 
output  [2:0]             lmq2_ld_rq_type ;        // for identifying atomic ld.
229 
output  [2:0]             lmq3_ld_rq_type ;        // for identifying atomic ld.
230 
 
231 
output                    lmq0_ldd_vld ;             // ld double
232 
output                    lmq1_ldd_vld ;             // ld double
233 
output                    lmq2_ldd_vld ;             // ld double
234 
output                    lmq3_ldd_vld ;             // ld double
235 
 
236 
output                    ld_sec_hit_thrd0 ;        // ld has sec. hit against th0
237 
output                    ld_sec_hit_thrd1 ;        // ld has sec. hit against th1
238 
output                    ld_sec_hit_thrd2 ;        // ld has sec. hit against th2
239 
output                    ld_sec_hit_thrd3 ;        // ld has sec. hit against th3
240 
//output  [1:0]             lmq_pcx_pkt_sz ;
241 
//output  [39:0]            lmq_pcx_pkt_addr ;
242 
output  [10:0]            lmq0_pcx_pkt_addr;
243 
output  [10:0]            lmq1_pcx_pkt_addr;
244 
output  [10:0]            lmq2_pcx_pkt_addr;
245 
output  [10:0]            lmq3_pcx_pkt_addr;
246 
 
247 
//output  [63:0]            lsu_tlu_st_rs3_data_g ;
248 
output  [63:0]            lsu_mmu_rs3_data_g ;
249 
output  [63:0]            lsu_tlu_rs3_data_g ;
250 
 
251 
output                    lsu_diagnstc_wr_data_b0 ; // diagnostic wr data - bit 0
252 
output  [63:0]            lsu_diagnstc_wr_data_e ;
253 
 
254 
output  [47:0]            lsu_ifu_stxa_data ;       // stxa related data
255 
 
256 
output  [11:5]            lsu_ifu_ld_icache_index ;
257 
output  [1:0]             lsu_ifu_ld_pcxpkt_tid ;
258 
 
259 
//output  [1:0]             lmq_ld_way ;              // cache set way for ld fill
260 
 
261 
output  [28:0]            lsu_error_pa_m ;          // error phy addr
262 
//output  [13:0]            lsu_spu_rsrv_data_m ;     // rs3 data for reserved fields.
263 
output                    lsu_pref_pcx_req ;        // pref sent to pcx
264 
 
265 
   output [63:0]          st_rs3_data_g;
266 
 
267 
output  [1:0]             lsu_ldst_va_way_g ;          // 12:11 for direct map
268 
//====================================================================
269 
//dc_fill CP
270 
 
271 
   input [63:0]           lsu_l2fill_data; //from qdp2
272 
   input                  l2fill_vld_m;    //from dctl
273 
   input   [3:0]          ld_thrd_byp_sel_m;//from dctl
274 
 
275 
   output [63:0]          dcache_alt_data_w0_m;  //to d$
276 
//   output [7:0]           lsu_l2fill_or_byp_msb_m;   //to dctl
277 
//====================================================================
278 
 
279 
 
280 
wire  [`STB_PCX_WIDTH-1:0]  store_pcx_pkt ;
281 
wire  [`PCX_WIDTH-1:0]  pcx_pkt_data ;
282 
wire  [`STB_PCX_WIDTH-1:0]  stb_pcx_pkt ;
283 
wire  [`PCX_WIDTH-1:0]  imiss_strm_pcx_pkt ;
284 
wire  [`PCX_WIDTH-1:0]  intrpt_full_pcxpkt ;
285 
wire  [`PCX_WIDTH-1:0]  ifu_full_pcx_pkt_e ;
286 
wire  [51:0]      ifu_pcx_pkt_e ;
287 
wire  [63:0]      cas_pkt2_data ;
288 
wire  [63:0]      lmq0_bypass_data_in,lmq1_bypass_data_in ;
289 
wire  [63:0]      lmq2_bypass_data_in,lmq3_bypass_data_in ;
290 
wire  [63:0]      lmq0_bypass_data, lmq1_bypass_data ;
291 
wire  [63:0]      lmq2_bypass_data, lmq3_bypass_data ;
292 
wire  [39:0]      lmq_ld_addr ;
293 
wire  [`LMQ_WIDTH:0]    load_pcx_pkt ;
294 
wire  [`LMQ_WIDTH-1:0]  lmq0_pcx_pkt, lmq1_pcx_pkt ;
295 
wire  [`LMQ_WIDTH-1:0]  lmq2_pcx_pkt, lmq3_pcx_pkt ;
296 
wire  [`PCX_WIDTH-1:0]  fpop_full_pcxpkt ;
297 
wire  [63:0]      tlb_st_data ;
298 
//wire    [63:0]      formatted_tte_tag ;
299 
//wire    [63:0]      formatted_tte_data ;
300 
wire  [63:0]      lmq0_bypass_ldxa_data ;
301 
wire  [63:0]      lmq1_bypass_ldxa_data ;
302 
wire  [63:0]      lmq2_bypass_ldxa_data ;
303 
wire  [63:0]      lmq3_bypass_ldxa_data ;
304 
wire  [`PCX_WIDTH-1:0]  fwd_full_pcxpkt ;
305 
wire  [47:3]            lsu_tlu_st_rs3_data_g ;
306 
 
307 
 
308 
//===================================================
309 
//  clock buffer
310 
//===================================================
311 
//wire   lsu_qdp1_clk ;
312 
wire   clk;
313 
assign  clk = rclk;
314 
 
315 
wire         thread0_g;
316 
wire         thread1_g;
317 
wire         thread2_g;
318 
wire         thread3_g;
319 
 
320 
   assign    thread0_g = lsu_thread_g[0];
321 
   assign    thread1_g = lsu_thread_g[1];
322 
   assign    thread2_g = lsu_thread_g[2];
323 
   assign    thread3_g = lsu_thread_g[3];
324 
 
325 
//=================================================================================================
326 
//    LMQ DP
327 
//=================================================================================================
328 
 
329 
wire  [12:0]  ldst_va_g;
330 
 
331 
dff_s  #(13) ff_ldst_va_g (
332 
        .din    (lsu_ldst_va_m[12:0]),
333 
        .q      (ldst_va_g[12:0]),
334 
        .clk    (clk),
335 
        .se     (1'b0),       .si (),          .so ()
336 
        );
337 
 
338 
assign  lsu_ldst_va_way_g[1:0] =  ldst_va_g[12:11];
339 
 
340 
wire  [`LMQ_VLD:0]  ld_pcx_pkt_g_tmp;
341 
 
342 
assign ld_pcx_pkt_g_tmp[`LMQ_VLD:0] =  {ld_pcx_pkt_g[`LMQ_WIDTH-1:44],
343 
                                        2'b00,      // done after the flop
344 
                                        //lsu_lmq_pkt_way_g[1:0],
345 
                                        ld_pcx_pkt_g[41:40],
346 
                                        tlb_pgnum[39:13],ldst_va_g[12:0]};
347 
 
348 
// Unfortunately ld_pcx_pkt_g is now 65 bits wide. Grape-mapper needs to give feedback.
349 
// THREAD 0.
350 
/*
351 
dffe_s  #(`LMQ_WIDTH) lmq0 (
352 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
353 
        .q      (lmq0_pcx_pkt[`LMQ_VLD:0]),
354 
        .en     (lmq_enable[0]), .clk (clk),
355 
        .se     (1'b0),       .si (),          .so ()
356 
        );
357 
*/
358 
wire lmq0_clk;
359 
`ifdef FPGA_SYN_CLK_EN
360 
`else
361 
clken_buf lmq0_clkbuf (
362 
                .rclk   (clk),
363 
                .enb_l  (~lmq_enable[0]),
364 
                .tmb_l  (~se),
365 
                .clk    (lmq0_clk)
366 
                ) ;
367 
`endif
368 
wire  [`LMQ_VLD:0]  lmq0_pcx_pkt_tmp ;
369 
 
370 
`ifdef FPGA_SYN_CLK_DFF
371 
dffe_s  #(`LMQ_WIDTH) lmq0 (
372 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
373 
        .q      (lmq0_pcx_pkt_tmp[`LMQ_VLD:0]),
374 
        .en (~(~lmq_enable[0])), .clk(clk),
375 
        .se     (1'b0),       .si (),          .so ()
376 
        );
377 
`else
378 
dff_s  #(`LMQ_WIDTH) lmq0 (
379 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
380 
        .q      (lmq0_pcx_pkt_tmp[`LMQ_VLD:0]),
381 
        .clk    (lmq0_clk),
382 
        .se     (1'b0),       .si (),          .so ()
383 
        );
384 
`endif
385 
 
386 
//bug2705 - speculative pick in w-cycle
387 
wire    lmq0_pcx_pkt_vld ;
388 
assign  lmq0_pcx_pkt_vld  =  lmq0_pcx_pkt_tmp[`LMQ_VLD] & ~lsu_ld0_spec_vld_kill_w2 ;
389 
 
390 
assign  lmq0_pcx_pkt[`LMQ_VLD:0]  = {lmq0_pcx_pkt_vld,
391 
                                     lmq0_pcx_pkt_tmp[`LMQ_VLD-1:44],
392 
                                     lmq0_pcx_pkt_way[1:0],
393 
                                     lmq0_pcx_pkt_tmp[41:0]};
394 
 
395 
// Needs to be multi-threaded.
396 
//assign lmq_pcx_pkt_sz[1:0] = lmq0_pcx_pkt[`LMQ_SZ_HI:`LMQ_SZ_LO]  ;
397 
 
398 
assign  ld_sec_hit_thrd0 =
399 
(ld_pcx_pkt_g_tmp[`LMQ_AD_HI:`LMQ_AD_LO+4] == lmq0_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO+4]) ;
400 
 
401 
`ifdef FPGA_SYN_1THREAD
402 
  assign load_pcx_pkt[`LMQ_WIDTH-1:0] = lmq0_pcx_pkt[`LMQ_WIDTH-1:0];
403 
`else
404 
// THREAD 1.
405 
/*
406 
dffe_s  #(`LMQ_WIDTH) lmq1 (
407 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
408 
        .q      (lmq1_pcx_pkt[`LMQ_VLD:0]),
409 
        .en     (lmq_enable[1]), .clk (clk),
410 
        .se     (1'b0),       .si (),          .so ()
411 
        );
412 
*/
413 
wire lmq1_clk;
414 
`ifdef FPGA_SYN_CLK_EN
415 
`else
416 
clken_buf lmq1_clkbuf (
417 
                .rclk   (clk),
418 
                .enb_l  (~lmq_enable[1]),
419 
                .tmb_l  (~se),
420 
                .clk    (lmq1_clk)
421 
                ) ;
422 
`endif
423 
 
424 
wire  [`LMQ_VLD:0]  lmq1_pcx_pkt_tmp;
425 
 
426 
`ifdef FPGA_SYN_CLK_DFF
427 
dffe_s  #(`LMQ_WIDTH) lmq1 (
428 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
429 
        .q      (lmq1_pcx_pkt_tmp[`LMQ_VLD:0]),
430 
        .en (~(~lmq_enable[1])), .clk(clk),
431 
        .se     (1'b0),       .si (),          .so ()
432 
        );
433 
`else
434 
dff_s  #(`LMQ_WIDTH) lmq1 (
435 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
436 
        .q      (lmq1_pcx_pkt_tmp[`LMQ_VLD:0]),
437 
        .clk    (lmq1_clk),
438 
        .se     (1'b0),       .si (),          .so ()
439 
        );
440 
`endif
441 
 
442 
//bug2705 - speculative pick in w-cycle
443 
wire    lmq1_pcx_pkt_vld ;
444 
assign  lmq1_pcx_pkt_vld  =  lmq1_pcx_pkt_tmp[`LMQ_VLD] & ~lsu_ld1_spec_vld_kill_w2 ;
445 
 
446 
assign  lmq1_pcx_pkt[`LMQ_VLD:0]  =  {lmq1_pcx_pkt_vld,
447 
                                      lmq1_pcx_pkt_tmp[`LMQ_VLD-1:44],
448 
                                      lmq1_pcx_pkt_way[1:0],
449 
                                      lmq1_pcx_pkt_tmp[41:0]};
450 
 
451 
assign  ld_sec_hit_thrd1 =
452 
(ld_pcx_pkt_g_tmp[`LMQ_AD_HI:`LMQ_AD_LO+4] == lmq1_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO+4]) ;
453 
 
454 
// THREAD 2.
455 
/*
456 
dffe_s  #(`LMQ_WIDTH) lmq2 (
457 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
458 
        .q      (lmq2_pcx_pkt[`LMQ_VLD:0]),
459 
        .en     (lmq_enable[2]), .clk (clk),
460 
        .se     (1'b0),       .si (),          .so ()
461 
        );
462 
*/
463 
wire lmq2_clk;
464 
`ifdef FPGA_SYN_CLK_EN
465 
`else
466 
clken_buf lmq2_clkbuf (
467 
                .rclk   (clk),
468 
                .enb_l  (~lmq_enable[2]),
469 
                .tmb_l  (~se),
470 
                .clk    (lmq2_clk)
471 
                ) ;
472 
`endif
473 
 
474 
wire  [`LMQ_VLD:0]  lmq2_pcx_pkt_tmp;
475 
 
476 
`ifdef FPGA_SYN_CLK_DFF
477 
dffe_s  #(`LMQ_WIDTH) lmq2 (
478 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
479 
        .q      (lmq2_pcx_pkt_tmp[`LMQ_VLD:0]),
480 
        .en (~(~lmq_enable[2])), .clk(clk),
481 
        .se     (1'b0),       .si (),          .so ()
482 
        );
483 
`else
484 
dff_s  #(`LMQ_WIDTH) lmq2 (
485 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
486 
        .q      (lmq2_pcx_pkt_tmp[`LMQ_VLD:0]),
487 
        .clk    (lmq2_clk),
488 
        .se     (1'b0),       .si (),          .so ()
489 
        );
490 
`endif
491 
 
492 
//bug2705 - speculative pick in w-cycle
493 
wire    lmq2_pcx_pkt_vld ;
494 
assign  lmq2_pcx_pkt_vld  =  lmq2_pcx_pkt_tmp[`LMQ_VLD] & ~lsu_ld2_spec_vld_kill_w2 ;
495 
 
496 
 
497 
assign  lmq2_pcx_pkt[`LMQ_VLD:0]  =  {lmq2_pcx_pkt_vld,
498 
                                      lmq2_pcx_pkt_tmp[`LMQ_VLD-1:44],
499 
                                      lmq2_pcx_pkt_way[1:0],
500 
                                      lmq2_pcx_pkt_tmp[41:0]};
501 
 
502 
assign  ld_sec_hit_thrd2 =
503 
(ld_pcx_pkt_g_tmp[`LMQ_AD_HI:`LMQ_AD_LO+4] == lmq2_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO+4]) ;
504 
 
505 
// THREAD 3.
506 
/*
507 
dffe_s  #(`LMQ_WIDTH) lmq3 (
508 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
509 
        .q      (lmq3_pcx_pkt[`LMQ_VLD:0]),
510 
        .en     (lmq_enable[3]), .clk (clk),
511 
        .se     (1'b0),       .si (),          .so ()
512 
        );
513 
*/
514 
wire lmq3_clk;
515 
`ifdef FPGA_SYN_CLK_EN
516 
`else
517 
clken_buf lmq3_clkbuf (
518 
                .rclk   (clk),
519 
                .enb_l  (~lmq_enable[3]),
520 
                .tmb_l  (~se),
521 
                .clk    (lmq3_clk)
522 
                ) ;
523 
`endif
524 
 
525 
wire  [`LMQ_VLD:0]  lmq3_pcx_pkt_tmp;
526 
 
527 
`ifdef FPGA_SYN_CLK_DFF
528 
dffe_s  #(`LMQ_WIDTH) lmq3 (
529 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
530 
        .q      (lmq3_pcx_pkt_tmp[`LMQ_VLD:0]),
531 
        .en (~(~lmq_enable[3])), .clk(clk),
532 
        .se     (1'b0),       .si (),          .so ()
533 
        );
534 
`else
535 
dff_s  #(`LMQ_WIDTH) lmq3 (
536 
        .din    (ld_pcx_pkt_g_tmp[`LMQ_VLD:0]),
537 
        .q      (lmq3_pcx_pkt_tmp[`LMQ_VLD:0]),
538 
        .clk    (lmq3_clk),
539 
        .se     (1'b0),       .si (),          .so ()
540 
        );
541 
`endif
542 
 
543 
//bug2705 - speculative pick in w-cycle
544 
wire    lmq3_pcx_pkt_vld ;
545 
assign  lmq3_pcx_pkt_vld  =  lmq3_pcx_pkt_tmp[`LMQ_VLD] & ~lsu_ld3_spec_vld_kill_w2 ;
546 
 
547 
 
548 
assign  lmq3_pcx_pkt[`LMQ_VLD:0]  =  {lmq3_pcx_pkt_vld,
549 
                                      lmq3_pcx_pkt_tmp[`LMQ_VLD-1:44],
550 
                                      lmq3_pcx_pkt_way[1:0],
551 
                                      lmq3_pcx_pkt_tmp[41:0]};
552 
 
553 
 
554 
assign  ld_sec_hit_thrd3 =
555 
(ld_pcx_pkt_g_tmp[`LMQ_AD_HI:`LMQ_AD_LO+4] == lmq3_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO+4]) ;
556 
 
557 
// Select 1 of 4 LMQ Contents.
558 
// selection is based on which thread's load is chosen for pcx.
559 
mux4ds  #(`LMQ_WIDTH) lmq_pthrd_sel (
560 
  .in0  (lmq0_pcx_pkt[`LMQ_WIDTH-1:0]),
561 
  .in1  (lmq1_pcx_pkt[`LMQ_WIDTH-1:0]),
562 
  .in2  (lmq2_pcx_pkt[`LMQ_WIDTH-1:0]),
563 
  .in3  (lmq3_pcx_pkt[`LMQ_WIDTH-1:0]),
564 
  .sel0 (ld_pcx_rq_sel[0]),
565 
  .sel1   (ld_pcx_rq_sel[1]),
566 
  .sel2 (ld_pcx_rq_sel[2]),
567 
  .sel3   (ld_pcx_rq_sel[3]),
568 
  .dout (load_pcx_pkt[`LMQ_WIDTH-1:0])
569 
);
570 
`endif
571 
 
572 
assign  lsu_pref_pcx_req = load_pcx_pkt[`LMQ_PREF] ;
573 
 
574 
// Choose data to src for fill/bypass.
575 
// E-stage muxing : required for fills specifically.
576 
 
577 
   assign lmq0_ldd_vld =   lmq0_pcx_pkt[`LMQ_RD2_VLD];
578 
`ifdef FPGA_SYN_1THREAD
579 
   assign lmq1_ldd_vld =   1'b0;
580 
   assign lmq2_ldd_vld =   1'b0;
581 
   assign lmq3_ldd_vld =   1'b0;
582 
`else
583 
   assign lmq1_ldd_vld =   lmq1_pcx_pkt[`LMQ_RD2_VLD];
584 
   assign lmq2_ldd_vld =   lmq2_pcx_pkt[`LMQ_RD2_VLD];
585 
   assign lmq3_ldd_vld =   lmq3_pcx_pkt[`LMQ_RD2_VLD];
586 
`endif
587 
 
588 
   assign lmq0_pcx_pkt_addr[10:0] =  lmq0_pcx_pkt[`LMQ_AD_LO + 10 :`LMQ_AD_LO];
589 
`ifdef FPGA_SYN_1THREAD
590 
   assign lmq1_pcx_pkt_addr[10:0] =  11'b0;
591 
   assign lmq2_pcx_pkt_addr[10:0] =  11'b0;
592 
   assign lmq3_pcx_pkt_addr[10:0] =  11'b0;
593 
`else
594 
   assign lmq1_pcx_pkt_addr[10:0] =  lmq1_pcx_pkt[`LMQ_AD_LO + 10 :`LMQ_AD_LO];
595 
   assign lmq2_pcx_pkt_addr[10:0] =  lmq2_pcx_pkt[`LMQ_AD_LO + 10 :`LMQ_AD_LO];
596 
   assign lmq3_pcx_pkt_addr[10:0] =  lmq3_pcx_pkt[`LMQ_AD_LO + 10 :`LMQ_AD_LO];
597 
`endif
598 
 
599 
   assign lmq0_ld_rq_type[2:0] = lmq0_pcx_pkt[`LMQ_RQ_HI:`LMQ_RQ_LO];
600 
`ifdef FPGA_SYN_1THREAD
601 
   assign lmq1_ld_rq_type[2:0] = 3'b0;
602 
   assign lmq2_ld_rq_type[2:0] = 3'b0;
603 
   assign lmq3_ld_rq_type[2:0] = 3'b0;
604 
`else
605 
   assign lmq1_ld_rq_type[2:0] = lmq1_pcx_pkt[`LMQ_RQ_HI:`LMQ_RQ_LO];
606 
   assign lmq2_ld_rq_type[2:0] = lmq2_pcx_pkt[`LMQ_RQ_HI:`LMQ_RQ_LO];
607 
   assign lmq3_ld_rq_type[2:0] = lmq3_pcx_pkt[`LMQ_RQ_HI:`LMQ_RQ_LO];
608 
`endif
609 
 
610 
    assign lmq0_l2fill_fpld =  lmq0_pcx_pkt[`LMQ_FPLD];
611 
`ifdef FPGA_SYN_1THREAD
612 
    assign lmq1_l2fill_fpld =  1'b0;
613 
    assign lmq2_l2fill_fpld =  1'b0;
614 
    assign lmq3_l2fill_fpld =  1'b0;
615 
`else
616 
    assign lmq1_l2fill_fpld =  lmq1_pcx_pkt[`LMQ_FPLD];
617 
    assign lmq2_l2fill_fpld =  lmq2_pcx_pkt[`LMQ_FPLD];
618 
    assign lmq3_l2fill_fpld =  lmq3_pcx_pkt[`LMQ_FPLD];
619 
`endif
620 
/*
621 
   wire    lsu_l2fill_fpld_e;
622 
 
623 
mux4ds  #(44) lmq_dthrd_sel1 (
624 
  .in0  ({lmq0_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO], lmq0_pcx_pkt[`LMQ_NC],
625 
          lmq0_pcx_pkt[`LMQ_FPLD],lmq0_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}),
626 
  .in1  ({lmq1_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO], lmq1_pcx_pkt[`LMQ_NC],
627 
          lmq1_pcx_pkt[`LMQ_FPLD],lmq1_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}),
628 
  .in2  ({lmq2_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO], lmq2_pcx_pkt[`LMQ_NC],
629 
          lmq2_pcx_pkt[`LMQ_FPLD],lmq2_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}),
630 
  .in3  ({lmq3_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO], lmq3_pcx_pkt[`LMQ_NC],
631 
          lmq3_pcx_pkt[`LMQ_FPLD],lmq3_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}),
632 
  .sel0 (dfq_byp_sel[0]),
633 
  .sel1 (dfq_byp_sel[1]),
634 
  .sel2 (dfq_byp_sel[2]),
635 
  .sel3 (dfq_byp_sel[3]),
636 
  .dout ({lmq_ld_addr[39:0], lsu_ncache_ld_e,
637 
          lsu_l2fill_fpld_e, lsu_byp_misc_sz_e[1:0]})
638 
);
639 
*/
640 
 
641 
   assign  lmq0_ncache_ld =   lmq0_pcx_pkt[`LMQ_NC];
642 
`ifdef FPGA_SYN_1THREAD
643 
   assign  lmq1_ncache_ld =   1'b0;
644 
   assign  lmq2_ncache_ld =   1'b0;
645 
   assign  lmq3_ncache_ld =   1'b0;
646 
`else
647 
   assign  lmq1_ncache_ld =   lmq1_pcx_pkt[`LMQ_NC];
648 
   assign  lmq2_ncache_ld =   lmq2_pcx_pkt[`LMQ_NC];
649 
   assign  lmq3_ncache_ld =   lmq3_pcx_pkt[`LMQ_NC];
650 
`endif
651 
 
652 
`ifdef FPGA_SYN_1THREAD
653 
   assign lmq_ld_addr[39:0] =  lmq0_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO];
654 
   assign lsu_byp_misc_sz_e[1:0] = lmq0_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO];
655 
   assign lmq_ld_rd1[4:0] = lmq0_pcx_pkt[`LMQ_RD1_HI: `LMQ_RD1_LO];
656 
   assign lsu_l2fill_bendian_m = lmq0_pcx_pkt[`LMQ_BIGEND];
657 
   assign lsu_l2fill_sign_extend_m = lmq0_pcx_pkt[`LMQ_SIGNEXT];
658 
`else
659 
mux4ds  #(42) lmq_dthrd_sel1 (
660 
  .in0  ({lmq0_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO],
661 
          lmq0_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}),
662 
  .in1  ({lmq1_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO],
663 
          lmq1_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}),
664 
  .in2  ({lmq2_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO],
665 
          lmq2_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}),
666 
  .in3  ({lmq3_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO],
667 
          lmq3_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO]}),
668 
  .sel0 (dfq_byp_sel[0]),
669 
  .sel1 (dfq_byp_sel[1]),
670 
  .sel2 (dfq_byp_sel[2]),
671 
  .sel3 (dfq_byp_sel[3]),
672 
  .dout ({lmq_ld_addr[39:0], lsu_byp_misc_sz_e[1:0]})
673 
);
674 
 
675 
// POR
676 
// M-stage muxing : require for alignment and bypassing to exu.
677 
// flopped then used in qctl/dctl G-stage
678 
// lmq_ld_rd1 to lsu_qctl
679 
// others to lsu_dctl
680 
 
681 
// M-Stage Muxing
682 
 
683 
mux4ds  #(7) lmq_dthrd_sel2 (
684 
  .in0  ({lmq0_pcx_pkt[`LMQ_RD1_HI: `LMQ_RD1_LO],lmq0_pcx_pkt[`LMQ_BIGEND],
685 
    lmq0_pcx_pkt[`LMQ_SIGNEXT]}),
686 
  .in1  ({lmq1_pcx_pkt[`LMQ_RD1_HI: `LMQ_RD1_LO],lmq1_pcx_pkt[`LMQ_BIGEND],
687 
    lmq1_pcx_pkt[`LMQ_SIGNEXT]}),
688 
  .in2  ({lmq2_pcx_pkt[`LMQ_RD1_HI: `LMQ_RD1_LO],lmq2_pcx_pkt[`LMQ_BIGEND],
689 
    lmq2_pcx_pkt[`LMQ_SIGNEXT]}),
690 
  .in3  ({lmq3_pcx_pkt[`LMQ_RD1_HI: `LMQ_RD1_LO],lmq3_pcx_pkt[`LMQ_BIGEND],
691 
    lmq3_pcx_pkt[`LMQ_SIGNEXT]}),
692 
  .sel0 (lmq_byp_misc_sel[0]),
693 
  .sel1 (lmq_byp_misc_sel[1]),
694 
  .sel2 (lmq_byp_misc_sel[2]),
695 
  .sel3 (lmq_byp_misc_sel[3]),
696 
  .dout ({lmq_ld_rd1[4:0],lsu_l2fill_bendian_m,lsu_l2fill_sign_extend_m})
697 
);
698 
`endif
699 
 
700 
   assign  lmq0_byp_misc_sz[1:0] = lmq0_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO];
701 
`ifdef FPGA_SYN_1THREAD
702 
   assign  lmq1_byp_misc_sz[1:0] = 2'b0;
703 
   assign  lmq2_byp_misc_sz[1:0] = 2'b0;
704 
   assign  lmq3_byp_misc_sz[1:0] = 2'b0;
705 
`else
706 
   assign  lmq1_byp_misc_sz[1:0] = lmq1_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO];
707 
   assign  lmq2_byp_misc_sz[1:0] = lmq2_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO];
708 
   assign  lmq3_byp_misc_sz[1:0] = lmq3_pcx_pkt[`LMQ_SZ_HI: `LMQ_SZ_LO];
709 
`endif
710 
 
711 
 
712 
//assign  lmq_pcx_pkt_addr[10:0] = lmq_ld_addr[10:0] ;
713 
 
714 
 
715 
   wire [28:0] dtag_wdata_e;
716 
 
717 
assign  dtag_wdata_e[28:0] =
718 
        ~lsu_dfq_ld_vld ?
719 
        lsu_diagnstc_wr_data_e[29:1] : lmq_ld_addr[39:11] ;
720 
 
721 
// Parity Generation for Tag. Match with macro.
722 
wire    dtag_wr_parity ;
723 
//assign  dtag_wr_parity = ^dtag_wdata_e[28:0] ;
724 
//assign  dtag_wdata_e[29] =
725 
//        ~lsu_dfq_ld_vld ?
726 
//        lsu_diagnstc_dtagv_prty_invrt_e^dtag_wr_parity : dtag_wr_parity ;
727 
 
728 
   wire dtag_wr_parity_7_0, dtag_wr_parity_15_8,
729 
        dtag_wr_parity_23_16,  dtag_wr_parity_28_24;
730 
 
731 
   assign dtag_wr_parity_7_0  =  ^dtag_wdata_e[7:0];   //zzpar8
732 
   assign dtag_wr_parity_15_8 =  ^dtag_wdata_e[15:8];  //zzpar8
733 
   assign dtag_wr_parity_23_16 = ^dtag_wdata_e[23:16]; //zzpar8
734 
   assign dtag_wr_parity_28_24 = ^dtag_wdata_e[28:24]; //zzpar8
735 
 
736 
   wire   dtag_wr_parity_28_24_with_invrt;
737 
 
738 
   assign dtag_wr_parity_28_24_with_invrt =
739 
           (^dtag_wdata_e[28:24]) ^ lsu_diagnstc_dtagv_prty_invrt_e; //zzpar8
740 
 
741 
 
742 
   wire dtag_wr_parity_7_0_m, dtag_wr_parity_15_8_m,
743 
        dtag_wr_parity_23_16_m,  dtag_wr_parity_28_24_m;
744 
   wire lsu_dfq_ld_vld_m;
745 
   wire dtag_wr_parity_28_24_with_invrt_m;
746 
 
747 
 
748 
// 12/12/03 : Change for Macrotest. I didn't mention
749 
// these 4 bits ! Pls check for a max time violation.
750 
wire    dtag_wr_parity_7_0_din, dtag_wr_parity_15_8_din ;
751 
wire    dtag_wr_parity_23_16_din, dtag_wr_parity_28_24_din ;
752 
assign  dtag_wr_parity_7_0_din =
753 
sehold ? dtag_wr_parity_7_0_m : dtag_wr_parity_7_0 ;
754 
assign  dtag_wr_parity_15_8_din =
755 
sehold ? dtag_wr_parity_15_8_m : dtag_wr_parity_15_8 ;
756 
assign  dtag_wr_parity_23_16_din =
757 
sehold ? dtag_wr_parity_23_16_m : dtag_wr_parity_23_16 ;
758 
assign  dtag_wr_parity_28_24_din =
759 
sehold ? dtag_wr_parity_28_24_m : dtag_wr_parity_28_24 ;
760 
 
761 
dff_s #(6) tag_parity_m (
762 
     .din ({dtag_wr_parity_7_0_din, dtag_wr_parity_15_8_din,
763 
            dtag_wr_parity_23_16_din, dtag_wr_parity_28_24_din,
764 
            lsu_dfq_ld_vld,   dtag_wr_parity_28_24_with_invrt}),
765 
     .q   ({dtag_wr_parity_7_0_m, dtag_wr_parity_15_8_m,
766 
            dtag_wr_parity_23_16_m, dtag_wr_parity_28_24_m,
767 
            lsu_dfq_ld_vld_m, dtag_wr_parity_28_24_with_invrt_m}),
768 
     .clk  (clk),
769 
     .se   (1'b0),     .si (),          .so ()
770 
);
771 
 
772 
assign dtag_wr_parity = dtag_wr_parity_7_0_m ^ dtag_wr_parity_15_8_m ^
773 
                        dtag_wr_parity_23_16_m ^ dtag_wr_parity_28_24_m;
774 
 
775 
   wire dtag_wr_parity_with_invrt;
776 
 
777 
assign dtag_wr_parity_with_invrt =
778 
       dtag_wr_parity_7_0_m ^ dtag_wr_parity_15_8_m ^
779 
       dtag_wr_parity_23_16_m ^ dtag_wr_parity_28_24_with_invrt_m;
780 
 
781 
wire [29:0] dtag_wdata_m;
782 
 
783 
// 12/12/03 : Change for Macrotest.
784 
assign dtag_wdata_m[29] =
785 
        ~(lsu_dfq_ld_vld_m | sehold) ?
786 
        dtag_wr_parity_with_invrt : dtag_wr_parity ;
787 
 
788 
// 12/12/03 : Change for Macrotest.
789 
wire [28:0] dtag_wdata_e_din ;
790 
assign  dtag_wdata_e_din[28:0] =
791 
sehold ? dtag_wdata_m[28:0] : dtag_wdata_e[28:0] ;
792 
 
793 
dff_s  #(29) tag_stgm (
794 
        .din  (dtag_wdata_e_din[28:0]),
795 
        .q    (dtag_wdata_m[28:0]),
796 
        .clk  (clk),
797 
        .se   (1'b0),     .si (),          .so ()
798 
        );
799 
 
800 
   assign      lsu_error_pa_m[28:0] =  dtag_wdata_m[28:0];
801 
 
802 
 
803 
//=================================================================================================
804 
//    RS3 DATA ALIGNMENT FOR CAS
805 
//=================================================================================================
806 
 
807 
wire  [7:0] rs3_byte0, rs3_byte1, rs3_byte2, rs3_byte3 ;
808 
wire  [7:0] rs3_byte4, rs3_byte5, rs3_byte6, rs3_byte7 ;
809 
wire  [63:0]  atm_byte_g ;
810 
wire  [63:0]  st_rs3_data_m,st_rs3_data_g ;
811 
 
812 
dff_s  #(64) rs3_stgm (
813 
        .din  (exu_lsu_rs3_data_e[63:0]),
814 
        .q    (st_rs3_data_m[63:0]),
815 
        .clk  (clk),
816 
        .se   (1'b0),     .si (),          .so ()
817 
        );
818 
 
819 
// rm (along with spu).
820 
//assign  lsu_spu_rsrv_data_m[13:0] =
821 
//  {st_rs3_data_m[27:23],st_rs3_data_m[21:16],st_rs3_data_m[8:6]} ;
822 
 
823 
dff_s  #(64) rs3_stgg (
824 
        .din  (st_rs3_data_m[63:0]),
825 
        .q    (st_rs3_data_g[63:0]),
826 
        .clk  (clk),
827 
        .se   (1'b0),     .si (),          .so ()
828 
        );
829 
 
830 
assign  rs3_byte0[7:0] = st_rs3_data_g[7:0] ;
831 
assign  rs3_byte1[7:0] = st_rs3_data_g[15:8] ;
832 
assign  rs3_byte2[7:0] = st_rs3_data_g[23:16] ;
833 
assign  rs3_byte3[7:0] = st_rs3_data_g[31:24] ;
834 
assign  rs3_byte4[7:0] = st_rs3_data_g[39:32] ;
835 
assign  rs3_byte5[7:0] = st_rs3_data_g[47:40] ;
836 
assign  rs3_byte6[7:0] = st_rs3_data_g[55:48] ;
837 
assign  rs3_byte7[7:0] = st_rs3_data_g[63:56] ;
838 
 
839 
//assign  atm_byte_g[7:0] =
840 
//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte0[7:0] :
841 
//  lsu_atomic_pkt2_bsel_g[1] ? rs3_byte3[7:0] :
842 
//    lsu_atomic_pkt2_bsel_g[0] ? rs3_byte7[7:0] : 8'bxxxx_xxxx ;
843 
 
844 
mux3ds #(8) mx_atm_byte_g_7_0 (
845 
    .in0 (rs3_byte0[7:0]),
846 
    .in1 (rs3_byte3[7:0]),
847 
    .in2 (rs3_byte7[7:0]),
848 
    .sel0(lsu_atomic_pkt2_bsel_g[2]),
849 
    .sel1(lsu_atomic_pkt2_bsel_g[1]),
850 
    .sel2(lsu_atomic_pkt2_bsel_g[0]),
851 
    .dout(atm_byte_g[7:0]));
852 
 
853 
 
854 
//assign  atm_byte_g[15:8] =
855 
//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte1[7:0] :
856 
//  lsu_atomic_pkt2_bsel_g[1] ? rs3_byte2[7:0] :
857 
//    lsu_atomic_pkt2_bsel_g[0] ? rs3_byte6[7:0] : 8'bxxxx_xxxx ;
858 
 
859 
mux3ds #(8) mx_atm_byte_g_15_8 (
860 
    .in0 (rs3_byte1[7:0]),
861 
    .in1 (rs3_byte2[7:0]),
862 
    .in2 (rs3_byte6[7:0]),
863 
    .sel0(lsu_atomic_pkt2_bsel_g[2]),
864 
    .sel1(lsu_atomic_pkt2_bsel_g[1]),
865 
    .sel2(lsu_atomic_pkt2_bsel_g[0]),
866 
    .dout(atm_byte_g[15:8]));
867 
 
868 
//assign  atm_byte_g[23:16] =
869 
//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte2[7:0] :
870 
//  lsu_atomic_pkt2_bsel_g[1] ? rs3_byte1[7:0] :
871 
//    lsu_atomic_pkt2_bsel_g[0] ? rs3_byte5[7:0] : 8'bxxxx_xxxx ;
872 
 
873 
mux3ds #(8) mx_atm_byte_g_23_16 (
874 
    .in0 (rs3_byte2[7:0]),
875 
    .in1 (rs3_byte1[7:0]),
876 
    .in2 (rs3_byte5[7:0]),
877 
    .sel0(lsu_atomic_pkt2_bsel_g[2]),
878 
    .sel1(lsu_atomic_pkt2_bsel_g[1]),
879 
    .sel2(lsu_atomic_pkt2_bsel_g[0]),
880 
    .dout(atm_byte_g[23:16]));
881 
 
882 
//assign  atm_byte_g[31:24] =
883 
//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte3[7:0] :
884 
//  lsu_atomic_pkt2_bsel_g[1] ? rs3_byte0[7:0] :
885 
//    lsu_atomic_pkt2_bsel_g[0] ? rs3_byte4[7:0] : 8'bxxxx_xxxx ;
886 
 
887 
mux3ds #(8) mx_atm_byte_g_31_24 (
888 
    .in0 (rs3_byte3[7:0]),
889 
    .in1 (rs3_byte0[7:0]),
890 
    .in2 (rs3_byte4[7:0]),
891 
    .sel0(lsu_atomic_pkt2_bsel_g[2]),
892 
    .sel1(lsu_atomic_pkt2_bsel_g[1]),
893 
    .sel2(lsu_atomic_pkt2_bsel_g[0]),
894 
    .dout(atm_byte_g[31:24]));
895 
 
896 
//assign  atm_byte_g[39:32] =
897 
//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte4[7:0] :
898 
//  lsu_atomic_pkt2_bsel_g[1] ? rs3_byte0[7:0] :
899 
//    lsu_atomic_pkt2_bsel_g[0] ? rs3_byte3[7:0] : 8'bxxxx_xxxx ;
900 
 
901 
mux3ds #(8) mx_atm_byte_g_39_32 (
902 
    .in0 (rs3_byte4[7:0]),
903 
    .in1 (rs3_byte0[7:0]),
904 
    .in2 (rs3_byte3[7:0]),
905 
    .sel0(lsu_atomic_pkt2_bsel_g[2]),
906 
    .sel1(lsu_atomic_pkt2_bsel_g[1]),
907 
    .sel2(lsu_atomic_pkt2_bsel_g[0]),
908 
    .dout(atm_byte_g[39:32]));
909 
 
910 
//assign  atm_byte_g[47:40] =
911 
//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte5[7:0] :
912 
//  lsu_atomic_pkt2_bsel_g[1] ? rs3_byte1[7:0] :
913 
//    lsu_atomic_pkt2_bsel_g[0] ? rs3_byte2[7:0] : 8'bxxxx_xxxx ;
914 
 
915 
mux3ds #(8) mx_atm_byte_g_47_40(
916 
    .in0 (rs3_byte5[7:0]),
917 
    .in1 (rs3_byte1[7:0]),
918 
    .in2 (rs3_byte2[7:0]),
919 
    .sel0(lsu_atomic_pkt2_bsel_g[2]),
920 
    .sel1(lsu_atomic_pkt2_bsel_g[1]),
921 
    .sel2(lsu_atomic_pkt2_bsel_g[0]),
922 
    .dout(atm_byte_g[47:40]));
923 
 
924 
//assign  atm_byte_g[55:48] =
925 
//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte6[7:0] :
926 
//  lsu_atomic_pkt2_bsel_g[1] ? rs3_byte2[7:0] :
927 
//    lsu_atomic_pkt2_bsel_g[0] ? rs3_byte1[7:0] : 8'bxxxx_xxxx ;
928 
 
929 
mux3ds #(8) mx_atm_byte_g_55_48(
930 
    .in0 (rs3_byte6[7:0]),
931 
    .in1 (rs3_byte2[7:0]),
932 
    .in2 (rs3_byte1[7:0]),
933 
    .sel0(lsu_atomic_pkt2_bsel_g[2]),
934 
    .sel1(lsu_atomic_pkt2_bsel_g[1]),
935 
    .sel2(lsu_atomic_pkt2_bsel_g[0]),
936 
    .dout(atm_byte_g[55:48]));
937 
 
938 
//assign  atm_byte_g[63:56] =
939 
//lsu_atomic_pkt2_bsel_g[2] ? rs3_byte7[7:0] :
940 
//  lsu_atomic_pkt2_bsel_g[1] ? rs3_byte3[7:0] :
941 
//    lsu_atomic_pkt2_bsel_g[0] ? rs3_byte0[7:0] : 8'bxxxx_xxxx ;
942 
 
943 
mux3ds #(8) mx_atm_byte_g_63_56 (
944 
    .in0 (rs3_byte7[7:0]),
945 
    .in1 (rs3_byte3[7:0]),
946 
    .in2 (rs3_byte0[7:0]),
947 
    .sel0(lsu_atomic_pkt2_bsel_g[2]),
948 
    .sel1(lsu_atomic_pkt2_bsel_g[1]),
949 
    .sel2(lsu_atomic_pkt2_bsel_g[0]),
950 
    .dout(atm_byte_g[63:56]));
951 
 
952 
//=================================================================================================
953 
//    STB/LDXA DATA BYPASSING
954 
//=================================================================================================
955 
 
956 
// Add STB to load bypass data flops.
957 
// Attempt is made to bypass data in G-stage for load. If not
958 
// possible then flop data and wait for next available bubble.
959 
// Once bypass occurs then load can be considered resolved.
960 
// Load Full Raw bypassing does not have to use DFQ.
961 
 
962 
// ldxa data will reside in bypass flops until an opportunity
963 
// is available to write to irf. ldxa's must write to lmq
964 
// in order to provide information such as rd to irf.
965 
 
966 
// ** The two conditions are mutually exclusive. **
967 
 
968 
// lsu_local_ldxa_data_w2 w/ lsu_misc_rdata_w2 for all 4 threads
969 
 
970 
// 1-hot fix: 8/1/03 - can be multihot during scan
971 
// grape mapper convert the 1 of the inverter used for the select to the logic below
972 
wire  [2:0]  lmq_byp_ldxa_sel0_1hot ;
973 
assign  lmq_byp_ldxa_sel0_1hot[0]  =  lmq_byp_ldxa_sel0[0] & ~rst_tri_en;
974 
assign  lmq_byp_ldxa_sel0_1hot[1]  =  lmq_byp_ldxa_sel0[1] & ~rst_tri_en;
975 
assign  lmq_byp_ldxa_sel0_1hot[2]  =  lmq_byp_ldxa_sel0[2] |  rst_tri_en;
976 
 
977 
 
978 
// THREAD 0
979 
mux3ds  #(64) ldbyp0_ldxa_mx (
980 
  .in0  (ifu_lsu_ldxa_data_w2[63:0]), // ifu-ldxa bypass data
981 
  //.in1  (tlu_lsu_ldxa_data_w2[63:0]), // tlu-ldxa bypass data
982 
  .in1  (spu_lsu_ldxa_data_w2[63:0]), // spu-ldxa bypass data
983 
  .in2  (lsu_misc_rdata_w2[63:0]),    // local asi bypass data
984 
  .sel0 (lmq_byp_ldxa_sel0_1hot[0]),
985 
  //.sel1 (lmq_byp_ldxa_sel0[1]),
986 
  .sel1 (lmq_byp_ldxa_sel0_1hot[1]),
987 
  .sel2 (lmq_byp_ldxa_sel0_1hot[2]),
988 
  .dout (lmq0_bypass_ldxa_data[63:0])
989 
);
990 
 
991 
// 1-hot fix: 8/1/03 - can be multihot during scan
992 
// grape mapper convert the 1 of the inverter used for the select to the logic below
993 
wire  [3:0]  lmq_byp_data_sel0_1hot ;
994 
assign  lmq_byp_data_sel0_1hot[0]  =  lmq_byp_data_sel0[0] ;
995 
assign  lmq_byp_data_sel0_1hot[1]  =  lmq_byp_data_sel0[1] ;
996 
assign  lmq_byp_data_sel0_1hot[2]  =  lmq_byp_data_sel0[2] ;
997 
assign  lmq_byp_data_sel0_1hot[3]  =  lmq_byp_data_sel0[3] ;
998 
 
999 
wire    [63:0]   lmq0_bypass_misc_data ;
1000 
mux4ds  #(64) ldbyp0_data_mx (
1001 
  .in0  (stb_rdata_ramd[63:0]),   // stb bypass data
1002 
  .in1  (exu_lsu_rs3_data_e[63:0]), // rs3 data
1003 
  .in2  (atm_byte_g[63:0]),   // cas formatted data
1004 
  .in3  (lmq0_bypass_ldxa_data[63:0]),  // ldxa bypass data
1005 
  .sel0 (lmq_byp_data_sel0_1hot[0]),
1006 
  .sel1 (lmq_byp_data_sel0_1hot[1]),
1007 
  .sel2 (lmq_byp_data_sel0_1hot[2]),
1008 
  .sel3 (lmq_byp_data_sel0_1hot[3]),
1009 
  .dout (lmq0_bypass_misc_data[63:0])
1010 
);
1011 
 
1012 
 
1013 
// 2:1 mux for additional data bus from tlu.
1014 
// Grape : merge into mux-flop.
1015 
mux2ds  #(64) ldbyp0_fmx (
1016 
  .in0  (lmq0_bypass_misc_data[63:0]),
1017 
  .in1  (tlu_lsu_int_ldxa_data_w2[63:0]),
1018 
  .sel0 (~lmq_byp_data_fmx_sel[0]),
1019 
  .sel1 (lmq_byp_data_fmx_sel[0]),
1020 
  .dout (lmq0_bypass_data_in[63:0])
1021 
);
1022 
 
1023 
/*
1024 
dffe_s  #(64) ldbyp0_data_ff (
1025 
        .din    (lmq0_bypass_data_in[63:0]),
1026 
        .q      (lmq0_bypass_data[63:0]),
1027 
        .en     (lmq_byp_data_en_w2[0]), .clk (clk),
1028 
        .se     (1'b0),       .si (),          .so ()
1029 
        );
1030 
*/
1031 
wire ldbyp0_data_clk;
1032 
`ifdef FPGA_SYN_CLK_EN
1033 
`else
1034 
clken_buf ldbyp0_data_clkbuf (
1035 
                .rclk   (clk),
1036 
                .enb_l  (~lmq_byp_data_en_w2[0]),
1037 
                .tmb_l  (~se),
1038 
                .clk    (ldbyp0_data_clk)
1039 
                ) ;
1040 
`endif
1041 
 
1042 
`ifdef FPGA_SYN_CLK_DFF
1043 
dffe_s  #(64) ldbyp0_data_ff (
1044 
        .din    (lmq0_bypass_data_in[63:0]),
1045 
        .q      (lmq0_bypass_data[63:0]),
1046 
        .en (~(~lmq_byp_data_en_w2[0])), .clk(clk),
1047 
        .se     (1'b0),       .si (),          .so ()
1048 
        );
1049 
`else
1050 
dff_s  #(64) ldbyp0_data_ff (
1051 
        .din    (lmq0_bypass_data_in[63:0]),
1052 
        .q      (lmq0_bypass_data[63:0]),
1053 
        .clk    (ldbyp0_data_clk),
1054 
        .se     (1'b0),       .si (),          .so ()
1055 
        );
1056 
`endif
1057 
 
1058 
`ifdef FPGA_SYN_1THREAD
1059 
`else
1060 
 
1061 
// THREAD 1
1062 
// 1-hot fix: 8/1/03 - can be multihot during scan
1063 
// grape mapper convert the 1 of the inverter used for the select to the logic below
1064 
wire  [2:0]  lmq_byp_ldxa_sel1_1hot ;
1065 
assign  lmq_byp_ldxa_sel1_1hot[0]  =  lmq_byp_ldxa_sel1[0] & ~rst_tri_en;
1066 
assign  lmq_byp_ldxa_sel1_1hot[1]  =  lmq_byp_ldxa_sel1[1] & ~rst_tri_en;
1067 
assign  lmq_byp_ldxa_sel1_1hot[2]  =  lmq_byp_ldxa_sel1[2] |  rst_tri_en;
1068 
 
1069 
 
1070 
mux3ds  #(64) ldbyp1_ldxa_mx (
1071 
        .in0    (ifu_lsu_ldxa_data_w2[63:0]),   // ifu-ldxa bypass data
1072 
        //.in1    (tlu_lsu_ldxa_data_w2[63:0]),   // tlu-ldxa bypass data
1073 
        .in1    (spu_lsu_ldxa_data_w2[63:0]), // spu-ldxa bypass data
1074 
        .in2    (lsu_misc_rdata_w2[63:0]),// local asi bypass data
1075 
        .sel0   (lmq_byp_ldxa_sel1_1hot[0]),
1076 
        //.sel1   (lmq_byp_ldxa_sel1[1]),
1077 
        .sel1   (lmq_byp_ldxa_sel1_1hot[1]),
1078 
        .sel2   (lmq_byp_ldxa_sel1_1hot[2]),
1079 
        .dout   (lmq1_bypass_ldxa_data[63:0])
1080 
);
1081 
 
1082 
// 1-hot fix: 8/1/03 - can be multihot during scan
1083 
// grape mapper convert the 1 of the inverter used for the select to the logic below
1084 
wire  [3:0]  lmq_byp_data_sel1_1hot ;
1085 
assign  lmq_byp_data_sel1_1hot[0]  =  lmq_byp_data_sel1[0] ;
1086 
assign  lmq_byp_data_sel1_1hot[1]  =  lmq_byp_data_sel1[1] ;
1087 
assign  lmq_byp_data_sel1_1hot[2]  =  lmq_byp_data_sel1[2] ;
1088 
assign  lmq_byp_data_sel1_1hot[3]  =  lmq_byp_data_sel1[3] ;
1089 
 
1090 
 
1091 
wire    [63:0]   lmq1_bypass_misc_data ;
1092 
mux4ds  #(64) ldbyp1_data_mx (
1093 
  .in0  (stb_rdata_ramd[63:0]),   // stb bypass data
1094 
  .in1  (exu_lsu_rs3_data_e[63:0]), // rs3 data
1095 
  .in2  (atm_byte_g[63:0]),   // cas formatted data
1096 
  .in3  (lmq1_bypass_ldxa_data[63:0]),  // ldxa bypass data
1097 
  .sel0 (lmq_byp_data_sel1_1hot[0]),
1098 
  .sel1 (lmq_byp_data_sel1_1hot[1]),
1099 
  .sel2 (lmq_byp_data_sel1_1hot[2]),
1100 
  .sel3 (lmq_byp_data_sel1_1hot[3]),
1101 
  .dout (lmq1_bypass_misc_data[63:0])
1102 
);
1103 
 
1104 
// 2:1 mux for additional data bus from tlu.
1105 
// Grape : merge into mux-flop.
1106 
mux2ds  #(64) ldbyp1_fmx (
1107 
  .in0  (lmq1_bypass_misc_data[63:0]),
1108 
  .in1  (tlu_lsu_int_ldxa_data_w2[63:0]),
1109 
  .sel0 (~lmq_byp_data_fmx_sel[1]),
1110 
  .sel1 (lmq_byp_data_fmx_sel[1]),
1111 
  .dout (lmq1_bypass_data_in[63:0])
1112 
);
1113 
 
1114 
/*
1115 
dffe_s  #(64) ldbyp1_data_ff (
1116 
        .din    (lmq1_bypass_data_in[63:0]),
1117 
        .q      (lmq1_bypass_data[63:0]),
1118 
        .en     (lmq_byp_data_en_w2[1]), .clk (clk),
1119 
        .se     (1'b0),       .si (),          .so ()
1120 
        );
1121 
*/
1122 
wire ldbyp1_data_clk;
1123 
`ifdef FPGA_SYN_CLK_EN
1124 
`else
1125 
clken_buf ldbyp1_data_clkbuf (
1126 
                .rclk   (clk),
1127 
                .enb_l  (~lmq_byp_data_en_w2[1]),
1128 
                .tmb_l  (~se),
1129 
                .clk    (ldbyp1_data_clk)
1130 
                ) ;
1131 
`endif
1132 
 
1133 
`ifdef FPGA_SYN_CLK_DFF
1134 
dffe_s  #(64) ldbyp1_data_ff (
1135 
        .din    (lmq1_bypass_data_in[63:0]),
1136 
        .q      (lmq1_bypass_data[63:0]),
1137 
        .en (~(~lmq_byp_data_en_w2[1])), .clk(clk),
1138 
        .se     (1'b0),       .si (),          .so ()
1139 
        );
1140 
`else
1141 
dff_s  #(64) ldbyp1_data_ff (
1142 
        .din    (lmq1_bypass_data_in[63:0]),
1143 
        .q      (lmq1_bypass_data[63:0]),
1144 
        .clk    (ldbyp1_data_clk),
1145 
        .se     (1'b0),       .si (),          .so ()
1146 
        );
1147 
`endif
1148 
 
1149 
// THREAD 2
1150 
// 1-hot fix: 8/1/03 - can be multihot during scan
1151 
// grape mapper convert the 1 of the inverter used for the select to the logic below
1152 
wire  [2:0]  lmq_byp_ldxa_sel2_1hot ;
1153 
assign  lmq_byp_ldxa_sel2_1hot[0]  =  lmq_byp_ldxa_sel2[0] & ~rst_tri_en;
1154 
assign  lmq_byp_ldxa_sel2_1hot[1]  =  lmq_byp_ldxa_sel2[1] & ~rst_tri_en;
1155 
assign  lmq_byp_ldxa_sel2_1hot[2]  =  lmq_byp_ldxa_sel2[2] |  rst_tri_en;
1156 
 
1157 
 
1158 
mux3ds  #(64) ldbyp2_data_mx (
1159 
        .in0    (ifu_lsu_ldxa_data_w2[63:0]),   // ifu-ldxa bypass data
1160 
        //.in1    (tlu_lsu_ldxa_data_w2[63:0]),   // tlu-ldxa bypass data
1161 
        .in1    (spu_lsu_ldxa_data_w2[63:0]), // spu-ldxa bypass data
1162 
        .in2    (lsu_misc_rdata_w2[63:0]),// local asi bypass data
1163 
        .sel0   (lmq_byp_ldxa_sel2_1hot[0]),
1164 
        //.sel1   (lmq_byp_ldxa_sel2[1]),
1165 
        .sel1 (lmq_byp_ldxa_sel2_1hot[1]),
1166 
        .sel2 (lmq_byp_ldxa_sel2_1hot[2]),
1167 
        .dout   (lmq2_bypass_ldxa_data[63:0])
1168 
);
1169 
 
1170 
// 1-hot fix: 8/1/03 - can be multihot during scan
1171 
// grape mapper convert the 1 of the inverter used for the select to the logic below
1172 
wire  [3:0]  lmq_byp_data_sel2_1hot ;
1173 
assign  lmq_byp_data_sel2_1hot[0]  =  lmq_byp_data_sel2[0] ;
1174 
assign  lmq_byp_data_sel2_1hot[1]  =  lmq_byp_data_sel2[1] ;
1175 
assign  lmq_byp_data_sel2_1hot[2]  =  lmq_byp_data_sel2[2] ;
1176 
assign  lmq_byp_data_sel2_1hot[3]  =  lmq_byp_data_sel2[3] ;
1177 
 
1178 
 
1179 
wire    [63:0]   lmq2_bypass_misc_data ;
1180 
mux4ds  #(64) ldbyp2_ldxa_mx (
1181 
  .in0  (stb_rdata_ramd[63:0]),   // stb bypass data
1182 
  .in1  (exu_lsu_rs3_data_e[63:0]), // rs3 data
1183 
  .in2  (atm_byte_g[63:0]),   // cas formatted data
1184 
  .in3  (lmq2_bypass_ldxa_data[63:0]),  // ldxa bypass data
1185 
  .sel0 (lmq_byp_data_sel2_1hot[0]),
1186 
  .sel1 (lmq_byp_data_sel2_1hot[1]),
1187 
  .sel2 (lmq_byp_data_sel2_1hot[2]),
1188 
  .sel3 (lmq_byp_data_sel2_1hot[3]),
1189 
  .dout (lmq2_bypass_misc_data[63:0])
1190 
);
1191 
 
1192 
// 2:1 mux for additional data bus from tlu.
1193 
// Grape : merge into mux-flop.
1194 
mux2ds  #(64) ldbyp2_fmx (
1195 
  .in0  (lmq2_bypass_misc_data[63:0]),
1196 
  .in1  (tlu_lsu_int_ldxa_data_w2[63:0]),
1197 
  .sel0 (~lmq_byp_data_fmx_sel[2]),
1198 
  .sel1 (lmq_byp_data_fmx_sel[2]),
1199 
  .dout (lmq2_bypass_data_in[63:0])
1200 
);
1201 
 
1202 
/*
1203 
dffe_s  #(64) ldbyp2_data_ff (
1204 
        .din    (lmq2_bypass_data_in[63:0]),
1205 
        .q      (lmq2_bypass_data[63:0]),
1206 
        .en     (lmq_byp_data_en_w2[2]), .clk (clk),
1207 
        .se     (1'b0),       .si (),          .so ()
1208 
        );
1209 
*/
1210 
wire ldbyp2_data_clk;
1211 
`ifdef FPGA_SYN_CLK_EN
1212 
`else
1213 
clken_buf ldbyp2_data_clkbuf (
1214 
                .rclk   (clk),
1215 
                .enb_l  (~lmq_byp_data_en_w2[2]),
1216 
                .tmb_l  (~se),
1217 
                .clk    (ldbyp2_data_clk)
1218 
                ) ;
1219 
`endif
1220 
 
1221 
`ifdef FPGA_SYN_CLK_DFF
1222 
dffe_s  #(64) ldbyp2_data_ff (
1223 
        .din    (lmq2_bypass_data_in[63:0]),
1224 
        .q      (lmq2_bypass_data[63:0]),
1225 
        .en (~(~lmq_byp_data_en_w2[2])), .clk(clk),
1226 
        .se     (1'b0),       .si (),          .so ()
1227 
        );
1228 
`else
1229 
dff_s  #(64) ldbyp2_data_ff (
1230 
        .din    (lmq2_bypass_data_in[63:0]),
1231 
        .q      (lmq2_bypass_data[63:0]),
1232 
        .clk    (ldbyp2_data_clk),
1233 
        .se     (1'b0),       .si (),          .so ()
1234 
        );
1235 
`endif
1236 
 
1237 
// THREAD 3
1238 
// 1-hot fix: 8/1/03 - can be multihot during scan
1239 
// grape mapper convert the 1 of the inverter used for the select to the logic below
1240 
wire  [2:0]  lmq_byp_ldxa_sel3_1hot ;
1241 
assign  lmq_byp_ldxa_sel3_1hot[0]  =  lmq_byp_ldxa_sel3[0] & ~rst_tri_en;
1242 
assign  lmq_byp_ldxa_sel3_1hot[1]  =  lmq_byp_ldxa_sel3[1] & ~rst_tri_en;
1243 
assign  lmq_byp_ldxa_sel3_1hot[2]  =  lmq_byp_ldxa_sel3[2] |  rst_tri_en;
1244 
 
1245 
 
1246 
mux3ds  #(64) ldbyp3_data_mx (
1247 
        .in0    (ifu_lsu_ldxa_data_w2[63:0]),   // ifu-ldxa bypass data
1248 
        //.in1    (tlu_lsu_ldxa_data_w2[63:0]),   // tlu-ldxa bypass data
1249 
        .in1    (spu_lsu_ldxa_data_w2[63:0]), // spu-ldxa bypass data
1250 
        .in2    (lsu_misc_rdata_w2[63:0]),// local asi bypass data
1251 
        .sel0   (lmq_byp_ldxa_sel3_1hot[0]),
1252 
        //.sel1   (lmq_byp_ldxa_sel3[1]),
1253 
        .sel1   (lmq_byp_ldxa_sel3_1hot[1]),
1254 
        .sel2   (lmq_byp_ldxa_sel3_1hot[2]),
1255 
        .dout   (lmq3_bypass_ldxa_data[63:0])
1256 
);
1257 
 
1258 
// 1-hot fix: 8/1/03 - can be multihot during scan
1259 
// grape mapper convert the 1 of the inverter used for the select to the logic below
1260 
wire  [3:0]  lmq_byp_data_sel3_1hot ;
1261 
assign  lmq_byp_data_sel3_1hot[0]  =  lmq_byp_data_sel3[0] ;
1262 
assign  lmq_byp_data_sel3_1hot[1]  =  lmq_byp_data_sel3[1] ;
1263 
assign  lmq_byp_data_sel3_1hot[2]  =  lmq_byp_data_sel3[2] ;
1264 
assign  lmq_byp_data_sel3_1hot[3]  =  lmq_byp_data_sel3[3] ;
1265 
 
1266 
 
1267 
wire    [63:0]   lmq3_bypass_misc_data ;
1268 
mux4ds  #(64) ldbyp3_ldxa_mx (
1269 
  .in0  (stb_rdata_ramd[63:0]),   // stb bypass data
1270 
  .in1  (exu_lsu_rs3_data_e[63:0]), // rs3 data
1271 
  .in2  (atm_byte_g[63:0]),   // cas formatted data
1272 
  .in3  (lmq3_bypass_ldxa_data[63:0]),  // ldxa bypass data
1273 
  .sel0 (lmq_byp_data_sel3_1hot[0]),
1274 
  .sel1 (lmq_byp_data_sel3_1hot[1]),
1275 
  .sel2 (lmq_byp_data_sel3_1hot[2]),
1276 
  .sel3 (lmq_byp_data_sel3_1hot[3]),
1277 
  .dout (lmq3_bypass_misc_data[63:0])
1278 
);
1279 
 
1280 
// 2:1 mux for additional data bus from tlu.
1281 
// Grape : merge into mux-flop.
1282 
mux2ds  #(64) ldbyp3_fmx (
1283 
  .in0  (lmq3_bypass_misc_data[63:0]),
1284 
  .in1  (tlu_lsu_int_ldxa_data_w2[63:0]),
1285 
  .sel0 (~lmq_byp_data_fmx_sel[3]),
1286 
  .sel1 (lmq_byp_data_fmx_sel[3]),
1287 
  .dout (lmq3_bypass_data_in[63:0])
1288 
);
1289 
 
1290 
/*
1291 
dffe_s  #(64) ldbyp3_data_ff (
1292 
        .din    (lmq3_bypass_data_in[63:0]),
1293 
        .q      (lmq3_bypass_data[63:0]),
1294 
        .en     (lmq_byp_data_en_w2[3]), .clk (clk),
1295 
        .se     (1'b0),       .si (),          .so ()
1296 
        );
1297 
*/
1298 
wire ldbyp3_data_clk;
1299 
`ifdef FPGA_SYN_CLK_EN
1300 
`else
1301 
clken_buf ldbyp3_data_clkbuf (
1302 
                .rclk   (clk),
1303 
                .enb_l  (~lmq_byp_data_en_w2[3]),
1304 
                .tmb_l  (~se),
1305 
                .clk    (ldbyp3_data_clk)
1306 
                ) ;
1307 
`endif
1308 
 
1309 
`ifdef FPGA_SYN_CLK_DFF
1310 
dffe_s  #(64) ldbyp3_data_ff (
1311 
        .din    (lmq3_bypass_data_in[63:0]),
1312 
        .q      (lmq3_bypass_data[63:0]),
1313 
        .en (~(~lmq_byp_data_en_w2[3])), .clk(clk),
1314 
        .se     (1'b0),       .si (),          .so ()
1315 
        );
1316 
`else
1317 
dff_s  #(64) ldbyp3_data_ff (
1318 
        .din    (lmq3_bypass_data_in[63:0]),
1319 
        .q      (lmq3_bypass_data[63:0]),
1320 
        .clk    (ldbyp3_data_clk),
1321 
        .se     (1'b0),       .si (),          .so ()
1322 
        );
1323 
`endif
1324 
 
1325 
`endif
1326 
 
1327 
`ifdef FPGA_SYN_1THREAD
1328 
  assign cas_pkt2_data[63:0] = lmq0_bypass_data[63:0];
1329 
  assign tlb_st_data[63:0] = lmq0_bypass_data[63:0];
1330 
`else
1331 
// This can be merged with above mux !!!!
1332 
mux4ds  #(64) ld_byp_cas_mx (
1333 
  .in0  (lmq0_bypass_data[63:0]),
1334 
  .in1  (lmq1_bypass_data[63:0]),
1335 
  .in2  (lmq2_bypass_data[63:0]),
1336 
  .in3  (lmq3_bypass_data[63:0]),
1337 
  .sel0 (ld_pcx_rq_sel[0]),
1338 
  .sel1   (ld_pcx_rq_sel[1]),
1339 
  .sel2 (ld_pcx_rq_sel[2]),
1340 
  .sel3   (ld_pcx_rq_sel[3]),
1341 
  .dout (cas_pkt2_data[63:0])
1342 
);
1343 
 
1344 
// Can this be merged with above muxes ?
1345 
mux4ds  #(64) tlb_st_mx (
1346 
  .in0  (lmq0_bypass_data[63:0]),
1347 
  .in1  (lmq1_bypass_data[63:0]),
1348 
  .in2  (lmq2_bypass_data[63:0]),
1349 
  .in3  (lmq3_bypass_data[63:0]),
1350 
  .sel0 (lsu_tlb_st_sel_m[0]),
1351 
  .sel1   (lsu_tlb_st_sel_m[1]),
1352 
  .sel2 (lsu_tlb_st_sel_m[2]),
1353 
  .sel3   (lsu_tlb_st_sel_m[3]),
1354 
  .dout (tlb_st_data[63:0])
1355 
);
1356 
`endif
1357 
 
1358 
/*mux4ds  #(64) tlb_st_mx (
1359 
  .in0  (lmq0_bypass_data[63:0]),
1360 
  .in1  (lmq1_bypass_data[63:0]),
1361 
  .in2  (lmq2_bypass_data[63:0]),
1362 
  .in3  (lmq3_bypass_data[63:0]),
1363 
  .sel0 (lsu_tlb_st_sel_g[0]),
1364 
  .sel1   (lsu_tlb_st_sel_g[1]),
1365 
  .sel2 (lsu_tlb_st_sel_g[2]),
1366 
  .sel3   (lsu_tlb_st_sel_g[3]),
1367 
  .dout (tlb_st_data[63:0])
1368 
);*/
1369 
 
1370 
wire    [63:0] tlb_st_data_d1 ;
1371 
dff_s  #(64) std_d1 (
1372 
        .din    (tlb_st_data[63:0]),
1373 
        .q      (tlb_st_data_d1[63:0]),
1374 
        .clk    (clk),
1375 
        .se     (1'b0),     .si (),          .so ()
1376 
        );
1377 
 
1378 
// Begin - Bug3487.
1379 
 
1380 
 
1381 
wire asi_data_clk;
1382 
`ifdef FPGA_SYN_CLK_EN
1383 
`else
1384 
clken_buf asid_clkbuf (
1385 
                .rclk   (clk),
1386 
                .enb_l  (lsu_ifu_asi_data_en_l),
1387 
                .tmb_l  (~se),
1388 
                .clk    (asi_data_clk)
1389 
                ) ;
1390 
`endif
1391 
 
1392 
`ifdef FPGA_SYN_CLK_DFF
1393 
dffe_s  #(48) ifu_std_d1 (
1394 
        .din    (tlb_st_data[47:0]),
1395 
        .q      (lsu_ifu_stxa_data[47:0]),
1396 
        .en (~(lsu_ifu_asi_data_en_l)), .clk(clk),
1397 
        .se     (1'b0),     .si (),          .so ()
1398 
        );
1399 
`else
1400 
dff_s  #(48) ifu_std_d1 (
1401 
        .din    (tlb_st_data[47:0]),
1402 
        .q      (lsu_ifu_stxa_data[47:0]),
1403 
        .clk    (asi_data_clk),
1404 
        .se     (1'b0),     .si (),          .so ()
1405 
        );
1406 
`endif
1407 
 
1408 
// select is now a stage earlier, which should be
1409 
// fine as selects stay constant.
1410 
//assign  lsu_ifu_stxa_data[47:0] = tlb_st_data_d1[47:0] ;
1411 
 
1412 
// End - Bug3487.
1413 
 
1414 
 
1415 
//wire    [3:0]   lsu_diag_access_sel_d1 ;
1416 
 
1417 
//dff #(4)  diagsel_stgd1 (
1418 
//        .din    (lsu_diag_access_sel[3:0]),
1419 
//        .q      (lsu_diag_access_sel_d1[3:0]),
1420 
//        .clk    (clk),
1421 
//        .se     (1'b0),       .si (),          .so ()
1422 
//        );
1423 
 
1424 
//mux4ds  #(64) diag_st_mx (
1425 
//  .in0  (lmq0_bypass_data[63:0]),
1426 
//  .in1  (lmq1_bypass_data[63:0]),
1427 
//  .in2  (lmq2_bypass_data[63:0]),
1428 
//  .in3  (lmq3_bypass_data[63:0]),
1429 
//  .sel0 (lsu_diag_access_sel_d1[0]),
1430 
//  .sel1 (lsu_diag_access_sel_d1[1]),
1431 
//  .sel2 (lsu_diag_access_sel_d1[2]),
1432 
//  .sel3 (lsu_diag_access_sel_d1[3]),
1433 
//  .dout (lsu_diagnstc_wr_data_e[63:0])
1434 
//);
1435 
 
1436 
// 1-hot fix: 8/1/03 - can be multihot during scan
1437 
// grape mapper convert the 1 of the inverter used for the select to the logic below
1438 
wire  [3:0]  lsu_diagnstc_data_sel_1hot ;
1439 
assign  lsu_diagnstc_data_sel_1hot[0]  =  lsu_diagnstc_data_sel[0] & ~rst_tri_en;
1440 
assign  lsu_diagnstc_data_sel_1hot[1]  =  lsu_diagnstc_data_sel[1] & ~rst_tri_en;
1441 
assign  lsu_diagnstc_data_sel_1hot[2]  =  lsu_diagnstc_data_sel[2] & ~rst_tri_en;
1442 
assign  lsu_diagnstc_data_sel_1hot[3]  =  lsu_diagnstc_data_sel[3] |  rst_tri_en;
1443 
 
1444 
 
1445 
`ifdef FPGA_SYN_1THREAD
1446 
  assign lsu_diagnstc_wr_data_e[63:0] = lmq0_bypass_data[63:0];
1447 
`else
1448 
mux4ds  #(64) diag_st_mx (
1449 
  .in0  (lmq0_bypass_data[63:0]),
1450 
  .in1  (lmq1_bypass_data[63:0]),
1451 
  .in2  (lmq2_bypass_data[63:0]),
1452 
  .in3  (lmq3_bypass_data[63:0]),
1453 
  .sel0 (lsu_diagnstc_data_sel_1hot[0]),
1454 
  .sel1 (lsu_diagnstc_data_sel_1hot[1]),
1455 
  .sel2 (lsu_diagnstc_data_sel_1hot[2]),
1456 
  .sel3 (lsu_diagnstc_data_sel_1hot[3]),
1457 
  .dout (lsu_diagnstc_wr_data_e[63:0])
1458 
);
1459 
`endif
1460 
 
1461 
// Remove flops
1462 
/*dff  #(64) dgndt_d1 (
1463 
        .din    (tlb_st_data[63:0]),
1464 
        .q      (lsu_diagnstc_wr_data_e[63:0]),
1465 
        .clk    (clk),
1466 
        .se     (1'b0),     .si (),          .so ()
1467 
        ); */
1468 
 
1469 
assign lsu_diagnstc_wr_data_b0 = lsu_diagnstc_wr_data_e[0] ;
1470 
 
1471 
// Move tte format and parity calc to tlbdp
1472 
 
1473 
//assign lsu_tlu_st_rs3_data_g[63:0] = tlb_st_data_d1[63:0];
1474 
assign lsu_tlu_st_rs3_data_g[47:3] = tlb_st_data_d1[47:3];
1475 
assign lsu_mmu_rs3_data_g[63:0] = tlb_st_data_d1[63:0];
1476 
assign lsu_tlu_rs3_data_g[63:0] = tlb_st_data_d1[63:0];
1477 
 
1478 
// Removed Fast bypass as penalty is negligible.
1479 
 
1480 
//=================================================================================================
1481 
//    STQ PKT2 DATA
1482 
//=================================================================================================
1483 
 
1484 
//** stquad support removed **
1485 
 
1486 
//=================================================================================================
1487 
//    IMISS/SPU DP
1488 
//=================================================================================================
1489 
 
1490 
// Format of IFU pcx packet (50b) :
1491 
//  b49 - valid
1492 
//  b48:44 - req type
1493 
//  b43:42 - rep way (for "eviction" - maintains directory consistency )
1494 
//  b41:40 - mil id
1495 
//  b39:0  - imiss address
1496 
 
1497 
 
1498 
// Align ifu pkt with ldst pkt - temporary !
1499 
// Does this need to be enabled ?!!!! No.
1500 
assign  ifu_pcx_pkt_e[51:0] = ifu_pcx_pkt[51:0] ;
1501 
 
1502 
// Form pcx-wide ifu request packet.
1503 
assign  ifu_full_pcx_pkt_e[`PCX_VLD] = ifu_pcx_pkt_e[51] ;
1504 
assign  ifu_full_pcx_pkt_e[`PCX_RQ_HI:`PCX_RQ_LO] = ifu_pcx_pkt_e[48:44];
1505 
assign  ifu_full_pcx_pkt_e[`PCX_NC] = ifu_pcx_pkt_e[49] ;
1506 
assign  ifu_full_pcx_pkt_e[`PCX_CP_HI:`PCX_CP_LO] = const_cpuid[2:0] ;
1507 
// thread-id unused - use mil id instead.
1508 
assign  ifu_full_pcx_pkt_e[`PCX_TH_HI:`PCX_TH_LO] = ifu_pcx_pkt_e[41:40] ;
1509 
assign  ifu_full_pcx_pkt_e[`PCX_BF_HI] =  ifu_pcx_pkt_e[50] ;
1510 
assign  ifu_full_pcx_pkt_e[`PCX_BF_HI-1:`PCX_BF_LO] =  2'b00;
1511 
assign  ifu_full_pcx_pkt_e[`PCX_WY_HI:`PCX_WY_LO] =  ifu_pcx_pkt_e[43:42] ;
1512 
// unused - always infer 32b
1513 
assign  ifu_full_pcx_pkt_e[`PCX_SZ_HI:`PCX_SZ_LO] =  3'b000 ;
1514 
assign  ifu_full_pcx_pkt_e[`PCX_AD_HI:`PCX_AD_LO] =  ifu_pcx_pkt_e[39:0] ;
1515 
// no data
1516 
assign  ifu_full_pcx_pkt_e[`PCX_DA_HI:`PCX_DA_LO] =  64'd0 ;
1517 
 
1518 
// Form pcx-wide interrupt request packet.
1519 
assign  intrpt_full_pcxpkt[`PCX_VLD] = tlu_lsu_pcxpkt[25] ;
1520 
assign  intrpt_full_pcxpkt[`PCX_RQ_HI:`PCX_RQ_LO] = tlu_lsu_pcxpkt[24:20];
1521 
assign  intrpt_full_pcxpkt[`PCX_NC] = 1'b0 ;
1522 
 
1523 
//tlu_lsu_pcxpkt[12:8] is the 5 bit interrupt destination thread id,
1524 
//so [12:10] is the cpu id, and [9:8] is the thread id.
1525 
assign  intrpt_full_pcxpkt[`PCX_CP_HI:`PCX_CP_LO] = tlu_lsu_pcxpkt[12:10];
1526 
 
1527 
// or should thread-id be 19:18 ?
1528 
assign  intrpt_full_pcxpkt[`PCX_TH_HI:`PCX_TH_LO] = tlu_lsu_pcxpkt[19:18] ;
1529 
// May actually make undriven fields x.
1530 
assign  intrpt_full_pcxpkt[`PCX_BF_HI:`PCX_BF_LO] =  3'b000;
1531 
assign  intrpt_full_pcxpkt[`PCX_WY_HI:`PCX_WY_LO] =  2'b00 ;
1532 
assign  intrpt_full_pcxpkt[`PCX_SZ_HI:`PCX_SZ_LO] =  3'b000 ;
1533 
assign  intrpt_full_pcxpkt[`PCX_AD_HI:`PCX_AD_LO] =  40'd0 ;
1534 
assign  intrpt_full_pcxpkt[`PCX_DA_HI:`PCX_DA_LO] =  {46'd0,tlu_lsu_pcxpkt[17:0]} ;
1535 
 
1536 
// Format fpop_full_pcxpkt.
1537 
 
1538 
assign  fpop_full_pcxpkt[`PCX_VLD] = ffu_lsu_data[80] ;
1539 
assign  fpop_full_pcxpkt[`PCX_RQ_HI:`PCX_RQ_LO] = {4'b0101,ffu_lsu_data[78]} ;
1540 
assign  fpop_full_pcxpkt[`PCX_NC] = 1'b0 ;
1541 
assign  fpop_full_pcxpkt[`PCX_CP_HI:`PCX_CP_LO] = const_cpuid[2:0] ;
1542 
assign  fpop_full_pcxpkt[`PCX_TH_HI:`PCX_TH_LO] = ffu_lsu_data[77:76] ;
1543 
assign  fpop_full_pcxpkt[`PCX_BF_HI:`PCX_SZ_LO] = 8'd0 ;
1544 
assign  fpop_full_pcxpkt[`PCX_AD_HI:`PCX_AD_LO+16] = 24'd0 ;
1545 
assign  fpop_full_pcxpkt[`PCX_AD_LO+15:`PCX_AD_LO+8] = ffu_lsu_data[75:68]; // 79:72
1546 
assign  fpop_full_pcxpkt[`PCX_AD_LO+7:`PCX_AD_LO+4] = 4'b0000;      // 71:68
1547 
assign  fpop_full_pcxpkt[`PCX_AD_LO+3:`PCX_AD_LO] = ffu_lsu_data[67:64] ; // 67:64
1548 
assign  fpop_full_pcxpkt[`PCX_DA_HI:`PCX_DA_LO] = ffu_lsu_data[63:0] ;
1549 
 
1550 
 
1551 
// RAMTest Data Merging.
1552 
wire cacherd_clk;
1553 
`ifdef FPGA_SYN_CLK_EN
1554 
`else
1555 
clken_buf cacherd_clkbuf (
1556 
                .rclk   (clk),
1557 
                .enb_l  (~lsu_ramtest_rd_w),
1558 
                .tmb_l  (~se),
1559 
                .clk    (cacherd_clk)
1560 
                ) ;
1561 
`endif
1562 
 
1563 
wire  [63:0]  cache_rdata_w,cache_rdata_w2 ;
1564 
 
1565 
mux2ds  #(64) cacherd_sel (
1566 
  .in0  (ifu_lsu_ldxa_data_w2[63:0]),
1567 
  .in1  (lsu_dcache_rdata_w[63:0]),
1568 
  .sel0 (~lsu_dcache_iob_rd_w),
1569 
  .sel1 (lsu_dcache_iob_rd_w),
1570 
  .dout (cache_rdata_w[63:0])
1571 
);
1572 
 
1573 
`ifdef FPGA_SYN_CLK_DFF
1574 
dffe_s  #(64) cachedata (
1575 
        .din    (cache_rdata_w[63:0]),
1576 
        .q      (cache_rdata_w2[63:0]), // references dcache rd staging
1577 
        .en (~(~lsu_ramtest_rd_w)), .clk(clk),
1578 
        .se     (1'b0),       .si (),          .so ()
1579 
        );
1580 
`else
1581 
dff_s  #(64) cachedata (
1582 
        .din    (cache_rdata_w[63:0]),
1583 
        .q      (cache_rdata_w2[63:0]), // references dcache rd staging
1584 
        .clk    (cacherd_clk),
1585 
        .se     (1'b0),       .si (),          .so ()
1586 
        );
1587 
`endif
1588 
 
1589 
assign  fwd_full_pcxpkt[`PCX_VLD] = 1'b1 ;
1590 
assign  fwd_full_pcxpkt[`PCX_RQ_HI:`PCX_RQ_LO] = {3'b011,lsu_pcx_fwd_reply,~lsu_pcx_fwd_reply} ;
1591 
assign  fwd_full_pcxpkt[`PCX_NC] = lsu_pcx_fwd_pkt[107] ;
1592 
assign  fwd_full_pcxpkt[`PCX_CP_HI:`PCX_CP_LO] = lsu_pcx_fwd_pkt[106:104] ;
1593 
assign  fwd_full_pcxpkt[`PCX_TH_HI:`PCX_TH_LO] = 2'b00 ;
1594 
assign  fwd_full_pcxpkt[`PCX_BF_HI:`PCX_SZ_LO] =
1595 
                        {6'b000000,lsu_fwd_rply_sz1_unc,1'b1} ;
1596 
// All address bits should not be required !!!
1597 
assign  fwd_full_pcxpkt[`PCX_AD_HI:`PCX_AD_LO] = lsu_pcx_fwd_pkt[103:64] ;
1598 
 
1599 
//  Mux sources of TAP request data - margin,pc,defeature/debug/bist.
1600 
// Be careful about pc - could be a critical path.
1601 
// ** Assume read-data stays constant at output latches of dcache **
1602 
//assign  fwd_full_pcxpkt[`PCX_DA_HI:`PCX_DA_LO] =
1603 
//lsu_iobrdge_rply_data_sel[0] ?  {20'd0,lsu_iobrdge_rd_data[43:0]} :
1604 
//      lsu_iobrdge_rply_data_sel[1] ?  cache_rdata_w2[63:0] :
1605 
//                      lsu_iobrdge_rply_data_sel[2] ?  lsu_pcx_fwd_pkt[63:0] :
1606 
//                                                      64'hxxxx_xxxx_xxxx_xxxx ;
1607 
 
1608 
mux3ds #(64) mx_fwd_full_pcxpkt (
1609 
    .in0 ({20'd0,lsu_iobrdge_rd_data[43:0]}),
1610 
    .in1 (cache_rdata_w2[63:0]),
1611 
    .in2 (lsu_pcx_fwd_pkt[63:0]),
1612 
    .sel0(lsu_iobrdge_rply_data_sel[0]),
1613 
    .sel1(lsu_iobrdge_rply_data_sel[1]),
1614 
    .sel2(lsu_iobrdge_rply_data_sel[2]),
1615 
    .dout(fwd_full_pcxpkt[`PCX_DA_HI:`PCX_DA_LO]));
1616 
 
1617 
 
1618 
wire  [`PCX_WIDTH-1:0]  spu_lsu_ldst_pckt_d1 ;
1619 
dff_s  #(`PCX_WIDTH) ff_spu_lsu_ldst_pckt_d1 (
1620 
        .din  (spu_lsu_ldst_pckt[`PCX_WIDTH-1:0]),
1621 
        .q    (spu_lsu_ldst_pckt_d1[`PCX_WIDTH-1:0]),
1622 
        .clk  (clk),
1623 
        .se   (1'b0),     .si (),          .so ()
1624 
        );
1625 
 
1626 
assign  imiss_strm_pcx_pkt[`PCX_WIDTH-1:0] = imiss_pcx_mx_sel ?
1627 
          ifu_full_pcx_pkt_e[`PCX_WIDTH-1:0] : spu_lsu_ldst_pckt_d1[`PCX_WIDTH-1:0] ;
1628 
 
1629 
wire  [`PCX_WIDTH-1:0]  fwd_int_fp_pcx_pkt ;
1630 
mux3ds #(`PCX_WIDTH) mux_fwd_int_fp_pcx_pkt (
1631 
     .in0  (fwd_full_pcxpkt[`PCX_WIDTH-1:0]),
1632 
     .in1  (intrpt_full_pcxpkt[`PCX_WIDTH-1:0]),
1633 
     .in2  (fpop_full_pcxpkt[`PCX_WIDTH-1:0]),
1634 
     .sel0 (fwd_int_fp_pcx_mx_sel[0]),
1635 
     .sel1 (fwd_int_fp_pcx_mx_sel[1]),
1636 
     .sel2 (fwd_int_fp_pcx_mx_sel[2]),
1637 
     .dout (fwd_int_fp_pcx_pkt [`PCX_WIDTH-1:0])
1638 
);
1639 
 
1640 
//=================================================================================================
1641 
//    PCX PKT SELECTION
1642 
//=================================================================================================
1643 
 
1644 
assign stb_pcx_pkt[`STB_PCX_VLD] = lsu_stb_pcx_rvld_d1 ;                // Valid
1645 
// Support stores for now.
1646 
assign stb_pcx_pkt[`STB_PCX_RQ_HI:`STB_PCX_RQ_LO] = stb_rdata_ramd[74:72] ;     // Rq-type
1647 
assign stb_pcx_pkt[`STB_PCX_NC] =
1648 
        // Mina the OR gate has been extended to a 3 input gate
1649 
        stb_rdata_ramd[74] | stb_rdata_ramd[73] |       // atomics
1650 
        stb_rdata_ramd[71] ;                            // flush inst
1651 
// cpu-id will be inserted on way out of core.
1652 
assign  stb_pcx_pkt[`STB_PCX_TH_HI:`STB_PCX_TH_LO] = lsu_stb_rd_tid[1:0] ;    // TID
1653 
// bf-id is not required.
1654 
// mux will have to be placed elsewhere. (grape)
1655 
assign  stb_pcx_pkt[`STB_PCX_FLSH] = stb_rdata_ramd[71] ;       // flush
1656 
assign  stb_pcx_pkt[`STB_PCX_FLSH-1] = 1'b0 ;
1657 
//assign  stb_pcx_pkt[`STB_PCX_WY_HI:`STB_PCX_WY_LO] = 2'b00 ;
1658 
 
1659 
//bug 2511
1660 
assign  stb_pcx_pkt[`STB_PCX_SZ_HI:`STB_PCX_SZ_LO] =
1661 
                        stb_rdata_ramd[69:68];                          // Size
1662 
 
1663 
//assign  stb_pcx_pkt[`STB_PCX_AD_HI:`STB_PCX_AD_LO] = stb_pcx_pkt[`STB_PCX_FLSH] ? 40'b0 :
1664 
//                        {stb_rdata_ramc[44:9],stb_rdata_ramd[67:64]} ;// Addr
1665 
 
1666 
assign  stb_pcx_pkt[`STB_PCX_AD_HI:`STB_PCX_AD_LO] =
1667 
                        {stb_rdata_ramc[44:9],stb_rdata_ramd[67:64]} ;// Addr
1668 
 
1669 
 
1670 
assign  stb_pcx_pkt[`STB_PCX_DA_HI:`STB_PCX_DA_LO] =
1671 
                        stb_rdata_ramd[63:0];                           // Data
1672 
 
1673 
assign  store_pcx_pkt[`STB_PCX_WIDTH-1:0] = stb_pcx_pkt[`STB_PCX_WIDTH-1:0] ;
1674 
 
1675 
// bld addr select.
1676 
wire [1:0] bld_addr_b54 ;
1677 
assign  bld_addr_b54[1:0] =
1678 
        lsu_bld_pcx_rq ? lsu_bld_rq_addr[1:0] : load_pcx_pkt[`LMQ_AD_LO+5:`LMQ_AD_LO+4] ;
1679 
 
1680 
// Select between load and store outbound pkt.
1681 
// *** cpu-id currently hardwired in pkt
1682 
// *** Thrd id currently hardwired.
1683 
mux4ds  #(124) pcx_pkt_src (
1684 
  .in0  ({load_pcx_pkt[`LMQ_VLD],2'b00,
1685 
    load_pcx_pkt[`LMQ_RQ_HI: `LMQ_RQ_LO],
1686 
    load_pcx_pkt[`LMQ_NC],const_cpuid[2:0],
1687 
    ld_pcx_thrd[1:0],lsu_pcx_ld_dtag_perror_w2,
1688 
    load_pcx_pkt[`LMQ_PREF],load_pcx_pkt[`LMQ_DFLUSH],
1689 
    load_pcx_pkt[`LMQ_WY_HI:`LMQ_WY_LO],lsu_pcx_rq_sz_b3,
1690 
    //load_pcx_pkt[`LMQ_WY_HI:`LMQ_WY_LO],1'b0,
1691 
    //load_pcx_pkt[`LMQ_SZ_HI:0],cas_pkt2_data[63:0]}), // load
1692 
    load_pcx_pkt[`LMQ_SZ_HI:`LMQ_AD_LO+6], bld_addr_b54[1:0],
1693 
    load_pcx_pkt[`LMQ_AD_LO+3:`LMQ_AD_LO],cas_pkt2_data[63:0]}), // load
1694 
  .in1  ({store_pcx_pkt[`STB_PCX_VLD],1'b0,
1695 
  store_pcx_pkt[`STB_PCX_FLSH], // turn into interrupt request.
1696 
    store_pcx_pkt[`STB_PCX_RQ_HI:`STB_PCX_RQ_LO],
1697 
    store_pcx_pkt[`STB_PCX_NC], const_cpuid[2:0],
1698 
    store_pcx_pkt[`STB_PCX_TH_HI:`STB_PCX_TH_LO],
1699 
    1'b0,
1700 
    stb_rdata_ramd[70], // blk-st : Bug 3395
1701 
    stb_rdata_ramd[75],
1702 
    2'b00,
1703 
    //store_pcx_pkt[`STB_PCX_WY_HI:`STB_PCX_WY_LO],
1704 
    1'b0,store_pcx_pkt[`STB_PCX_SZ_HI:0]}),     // store
1705 
  .in2  (imiss_strm_pcx_pkt[`PCX_WIDTH-1:0]),   // alt src : imiss,stream.
1706 
  .in3  (fwd_int_fp_pcx_pkt[`PCX_WIDTH-1:0]),   // fwd, interrupt, fpop
1707 
  .sel0 (pcx_pkt_src_sel[0]),
1708 
  .sel1 (pcx_pkt_src_sel[1]),
1709 
  .sel2 (pcx_pkt_src_sel[2]),
1710 
  .sel3 (pcx_pkt_src_sel[3]),
1711 
  .dout (pcx_pkt_data[`PCX_WIDTH-1:0])
1712 
);
1713 
 
1714 
dff_s  #(124) pcx_xmit_ff (
1715 
        .din  (pcx_pkt_data[`PCX_WIDTH-1:0]),
1716 
        .q    (spc_pcx_data_pa[`PCX_WIDTH-1:0]),
1717 
        .clk  (clk),
1718 
        .se     (1'b0),     .si (),          .so ()
1719 
        );
1720 
 
1721 
//  Stage to avoid critical path
1722 
/*assign  lsu_ifu_ld_icache_index[11:5] = pcx_pkt_data[`PCX_AD_LO+11:`PCX_AD_LO+5] ;
1723 
assign  lsu_ifu_ld_pcxpkt_tid[1:0] = pcx_pkt_data[`PCX_TH_HI:`PCX_TH_LO] ;*/
1724 
 
1725 
dff_s  #(9) stg_icindx (
1726 
        .din  ({pcx_pkt_data[`PCX_AD_LO+11:`PCX_AD_LO+5],pcx_pkt_data[`PCX_TH_HI:`PCX_TH_LO]}),
1727 
        .q    ({lsu_ifu_ld_icache_index[11:5],lsu_ifu_ld_pcxpkt_tid[1:0]}),
1728 
        .clk  (clk),
1729 
        .se     (1'b0),     .si (),          .so ()
1730 
        );
1731 
 
1732 
//=========================================================================================
1733 
//  VA Watchpt Reg per thread
1734 
//=========================================================================================
1735 
 
1736 
//VA_watchpoint_thread0
1737 
   wire        va_wtchpt0_clk ;
1738 
   wire [47:3] va_wtchpt0_addr;
1739 
 
1740 
`ifdef FPGA_SYN_CLK_EN
1741 
`else
1742 
clken_buf clkbf_va_wtchpt0 (
1743 
                .rclk   (clk),
1744 
                .enb_l  (lsu_va_wtchpt0_wr_en_l),
1745 
                .tmb_l  (~se),
1746 
                .clk    (va_wtchpt0_clk)
1747 
                ) ;
1748 
`endif
1749 
 
1750 
`ifdef FPGA_SYN_CLK_DFF
1751 
dffe_s #(45) va_wtchpt0_ff (
1752 
        .din    (lsu_tlu_st_rs3_data_g[47:3]),
1753 
        .q      (va_wtchpt0_addr[47:3]),
1754 
        .en (~(lsu_va_wtchpt0_wr_en_l)), .clk(clk),
1755 
        .se     (1'b0),       .si (),          .so ()
1756 
        );
1757 
`else
1758 
dff_s #(45) va_wtchpt0_ff (
1759 
        .din    (lsu_tlu_st_rs3_data_g[47:3]),
1760 
        .q      (va_wtchpt0_addr[47:3]),
1761 
        .clk    (va_wtchpt0_clk),
1762 
        .se     (1'b0),       .si (),          .so ()
1763 
        );
1764 
`endif
1765 
 
1766 
//VA_watchpoint_thread1
1767 
   wire        va_wtchpt1_clk ;
1768 
   wire [47:3] va_wtchpt1_addr;
1769 
 
1770 
`ifdef FPGA_SYN_CLK_EN
1771 
`else
1772 
clken_buf clkbf_va_wtchpt1 (
1773 
                .rclk   (clk),
1774 
                .enb_l  (lsu_va_wtchpt1_wr_en_l),
1775 
                .tmb_l  (~se),
1776 
                .clk    (va_wtchpt1_clk)
1777 
                ) ;
1778 
`endif
1779 
 
1780 
`ifdef FPGA_SYN_CLK_DFF
1781 
dffe_s #(45) va_wtchpt1_ff (
1782 
        .din    (lsu_tlu_st_rs3_data_g[47:3]),
1783 
        .q      (va_wtchpt1_addr[47:3]),
1784 
        .en (~(lsu_va_wtchpt1_wr_en_l)), .clk(clk),
1785 
        .se     (1'b0),       .si (),          .so ()
1786 
        );
1787 
`else
1788 
dff_s #(45) va_wtchpt1_ff (
1789 
        .din    (lsu_tlu_st_rs3_data_g[47:3]),
1790 
        .q      (va_wtchpt1_addr[47:3]),
1791 
        .clk    (va_wtchpt1_clk),
1792 
        .se     (1'b0),       .si (),          .so ()
1793 
        );
1794 
`endif
1795 
 
1796 
//VA_watchpoint_thread2
1797 
   wire        va_wtchpt2_clk ;
1798 
   wire [47:3] va_wtchpt2_addr;
1799 
 
1800 
`ifdef FPGA_SYN_CLK_EN
1801 
`else
1802 
clken_buf clkbf_va_wtchpt2 (
1803 
                .rclk   (clk),
1804 
                .enb_l  (lsu_va_wtchpt2_wr_en_l),
1805 
                .tmb_l  (~se),
1806 
                .clk    (va_wtchpt2_clk)
1807 
                ) ;
1808 
`endif
1809 
 
1810 
`ifdef FPGA_SYN_CLK_DFF
1811 
dffe_s #(45) va_wtchpt2_ff (
1812 
        .din    (lsu_tlu_st_rs3_data_g[47:3]),
1813 
        .q      (va_wtchpt2_addr[47:3]),
1814 
        .en (~(lsu_va_wtchpt2_wr_en_l)), .clk(clk),
1815 
        .se     (1'b0),       .si (),          .so ()
1816 
        );
1817 
`else
1818 
dff_s #(45) va_wtchpt2_ff (
1819 
        .din    (lsu_tlu_st_rs3_data_g[47:3]),
1820 
        .q      (va_wtchpt2_addr[47:3]),
1821 
        .clk    (va_wtchpt2_clk),
1822 
        .se     (1'b0),       .si (),          .so ()
1823 
        );
1824 
`endif
1825 
 
1826 
//VA_watchpoint_thread3
1827 
   wire        va_wtchpt3_clk ;
1828 
   wire [47:3] va_wtchpt3_addr;
1829 
 
1830 
`ifdef FPGA_SYN_CLK_EN
1831 
`else
1832 
clken_buf clkbf_va_wtchpt3 (
1833 
                .rclk   (clk),
1834 
                .enb_l  (lsu_va_wtchpt3_wr_en_l),
1835 
                .tmb_l  (~se),
1836 
                .clk    (va_wtchpt3_clk)
1837 
                ) ;
1838 
`endif
1839 
 
1840 
`ifdef FPGA_SYN_CLK_DFF
1841 
dffe_s #(45) va_wtchpt3_ff (
1842 
        .din    (lsu_tlu_st_rs3_data_g[47:3]),
1843 
        .q      (va_wtchpt3_addr[47:3]),
1844 
        .en (~(lsu_va_wtchpt3_wr_en_l)), .clk(clk),
1845 
        .se     (1'b0),       .si (),          .so ()
1846 
        );
1847 
`else
1848 
dff_s #(45) va_wtchpt3_ff (
1849 
        .din    (lsu_tlu_st_rs3_data_g[47:3]),
1850 
        .q      (va_wtchpt3_addr[47:3]),
1851 
        .clk    (va_wtchpt3_clk),
1852 
        .se     (1'b0),       .si (),          .so ()
1853 
        );
1854 
`endif
1855 
 
1856 
   wire [47:3] va_wtchpt_addr;
1857 
 
1858 
mux4ds #(45)     va_wtchpt_mx_m (
1859 
        .in0    (va_wtchpt0_addr[47:3]),
1860 
        .in1    (va_wtchpt1_addr[47:3]),
1861 
        .in2    (va_wtchpt2_addr[47:3]),
1862 
        .in3    (va_wtchpt3_addr[47:3]),
1863 
        .sel0   (thread0_m),
1864 
        .sel1   (thread1_m),
1865 
        .sel2   (thread2_m),
1866 
        .sel3   (thread3_m),
1867 
        .dout   (va_wtchpt_addr[47:3])
1868 
        );
1869 
 
1870 
mux4ds #(45)     va_wtchpt_mx_g (
1871 
        .in0    (va_wtchpt0_addr[47:3]),
1872 
        .in1    (va_wtchpt1_addr[47:3]),
1873 
        .in2    (va_wtchpt2_addr[47:3]),
1874 
        .in3    (va_wtchpt3_addr[47:3]),
1875 
        .sel0   (thread0_g),
1876 
        .sel1   (thread1_g),
1877 
        .sel2   (thread2_g),
1878 
        .sel3   (thread3_g),
1879 
        .dout   (lsu_va_wtchpt_addr[47:3])
1880 
        );
1881 
 
1882 
//VA wtchpt comparison at M stage
1883 
//assign lsu_va_match_m = (lsu_ldst_va_m[47:3] == va_wtchpt_addr[47:3]);
1884 
//bug6480/eco6623
1885 
assign lsu_va_match_b47_b32_m = (lsu_ldst_va_m[47:32] == va_wtchpt_addr[47:32]);
1886 
assign lsu_va_match_b31_b3_m =  (lsu_ldst_va_m[31:3 ] == va_wtchpt_addr[31:3 ]);
1887 
 
1888 
//====================================================================
1889 
//dc_fill CP
1890 
   wire [63:0] l2fill_data_m;
1891 
 
1892 
//dff #(64) stgm_l2fd (
1893 
//        .din    (lsu_l2fill_data[63:0]),
1894 
//        .q      (l2fill_data_m[63:0]),
1895 
//        .clk    (clk),
1896 
//        .se     (se),       .si (),          .so ()
1897 
//        );
1898 
   assign      l2fill_data_m[63:0] = lsu_l2fill_data[63:0];
1899 
 
1900 
 
1901 
   wire [63:0] ld_byp_data_m;
1902 
 
1903 
`ifdef FPGA_SYN_1THREAD
1904 
  assign ld_byp_data_m[63:0] = lmq0_bypass_data[63:0];
1905 
`else
1906 
mux4ds  #(64) ld_byp_mx (
1907 
  .in0  (lmq0_bypass_data[63:0]),
1908 
  .in1  (lmq1_bypass_data[63:0]),
1909 
  .in2  (lmq2_bypass_data[63:0]),
1910 
  .in3  (lmq3_bypass_data[63:0]),
1911 
  .sel0 (ld_thrd_byp_sel_m[0]),
1912 
  .sel1 (ld_thrd_byp_sel_m[1]),
1913 
  .sel2 (ld_thrd_byp_sel_m[2]),
1914 
  .sel3 (ld_thrd_byp_sel_m[3]),
1915 
  .dout (ld_byp_data_m[63:0])
1916 
);
1917 
`endif
1918 
 
1919 
assign dcache_alt_data_w0_m[63:0] =
1920 
       l2fill_vld_m ? l2fill_data_m[63:0] :
1921 
                      ld_byp_data_m[63:0];
1922 
 
1923 
//assign        lsu_l2fill_or_byp_msb_m[7:0]
1924 
//      = {lsu_l2fill_or_byp_data_m[63],
1925 
//     lsu_l2fill_or_byp_data_m[55],
1926 
//     lsu_l2fill_or_byp_data_m[47],
1927 
//     lsu_l2fill_or_byp_data_m[39],
1928 
//         lsu_l2fill_or_byp_data_m[31],
1929 
//     lsu_l2fill_or_byp_data_m[23],
1930 
//     lsu_l2fill_or_byp_data_m[15],
1931 
//     lsu_l2fill_or_byp_data_m[07]} ;
1932 
//====================================================================
1933 
 
1934 
endmodule

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