1 |
2 |
dmitryr |
// ========== Copyright Header Begin ==========================================
|
2 |
|
|
//
|
3 |
|
|
// OpenSPARC T1 Processor File: lsu_qdp2.v
|
4 |
|
|
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
|
5 |
|
|
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
|
6 |
|
|
//
|
7 |
|
|
// The above named program is free software; you can redistribute it and/or
|
8 |
|
|
// modify it under the terms of the GNU General Public
|
9 |
|
|
// License version 2 as published by the Free Software Foundation.
|
10 |
|
|
//
|
11 |
|
|
// The above named program is distributed in the hope that it will be
|
12 |
|
|
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 |
|
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 |
|
|
// General Public License for more details.
|
15 |
|
|
//
|
16 |
|
|
// You should have received a copy of the GNU General Public
|
17 |
|
|
// License along with this work; if not, write to the Free Software
|
18 |
|
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
19 |
|
|
//
|
20 |
|
|
// ========== Copyright Header End ============================================
|
21 |
|
|
///////////////////////////////////////////////////////////////////////
|
22 |
|
|
/*
|
23 |
|
|
// Module Name: LSU_QDP2
|
24 |
|
|
// Description: LSU CPX Datapath.
|
25 |
|
|
*/
|
26 |
|
|
////////////////////////////////////////////////////////////////////////
|
27 |
|
|
// header file includes
|
28 |
|
|
////////////////////////////////////////////////////////////////////////
|
29 |
|
|
`include "sys.h" // system level definition file which contains the
|
30 |
|
|
// time scale definition
|
31 |
|
|
`include "iop.h"
|
32 |
|
|
|
33 |
|
|
`include "lsu.h"
|
34 |
|
|
|
35 |
|
|
////////////////////////////////////////////////////////////////////////
|
36 |
|
|
// Local header file includes / local defines
|
37 |
|
|
////////////////////////////////////////////////////////////////////////
|
38 |
|
|
|
39 |
|
|
//FPGA_SYN enables all FPGA related modifications
|
40 |
|
|
`ifdef FPGA_SYN
|
41 |
|
|
`define FPGA_SYN_CLK_EN
|
42 |
|
|
`define FPGA_SYN_CLK_DFF
|
43 |
|
|
`endif
|
44 |
|
|
|
45 |
|
|
module lsu_qdp2 ( /*AUTOARG*/
|
46 |
|
|
// Outputs
|
47 |
|
|
so, lsu_l2fill_data, dfq_wdata, dfq_tid, lsu_dcache_fill_data_e,
|
48 |
|
|
lsu_ifill_pkt, lsu_pcx_fwd_pkt, lsu_cpx_pkt_strm_ack,
|
49 |
|
|
lsu_cpx_pkt_vld, lsu_cpx_pkt_atm_st_cmplt, lsu_cpx_pkt_tid,
|
50 |
|
|
lsu_cpx_pkt_invwy, lsu_cpx_pkt_inv_pa, lsu_cpx_pkt_l2miss,
|
51 |
|
|
lsu_dfq_byp_invwy_vld, lsu_dfq_byp_type, lsu_dfq_byp_flush,
|
52 |
|
|
lsu_dfq_byp_tid, lsu_cpu_inv_data_b13to9, lsu_cpu_inv_data_b7to2,
|
53 |
|
|
lsu_cpu_inv_data_b0, lsu_iobrdge_wr_data, lsu_iobrdge_tap_rq_type,
|
54 |
|
|
lsu_cpx_pkt_perror_dinv, lsu_cpx_pkt_perror_iinv,
|
55 |
|
|
lsu_cpx_pkt_perror_set, lsu_cpx_pkt_ld_err, lsu_dfq_byp_binit_st,
|
56 |
|
|
lsu_cpx_pkt_binit_st, lsu_cpx_pkt_prefetch, lsu_cpx_pkt_prefetch2,
|
57 |
|
|
lsu_dfq_byp_cpx_inv, lsu_dfq_byp_stack_adr_b54,
|
58 |
|
|
lsu_dfq_byp_stack_wrway, lsu_dfq_byp_atm, dcache_iob_addr_e,
|
59 |
|
|
st_dcfill_addr, lsu_st_way_e, lsu_dcache_iob_way_e,
|
60 |
|
|
lsu_st_dcfill_size_e, lsu_cpx_pkt_ifill_type, lsu_cpx_pkt_atomic,
|
61 |
|
|
// Inputs
|
62 |
|
|
rst_tri_en, rclk, si, se, lsu_dfill_data_sel_hi, dfq_byp_ff_en,
|
63 |
|
|
dfq_rd_vld_d1, dfq_rdata, cpx_spc_data_cx, stb_rdata_ramd_buf,
|
64 |
|
|
stb_rdata_ramd_b74_buf, stb_rdata_ramc_buf, lsu_stb_pcx_rvld_d1,
|
65 |
|
|
lsu_diagnstc_wr_data_e, lsu_diagnstc_dc_prty_invrt_e,
|
66 |
|
|
mbist_write_data, cpx_fwd_pkt_en_cx, lsu_cpu_dcd_sel,
|
67 |
|
|
lsu_cpu_uhlf_sel, lsu_cpxpkt_type_dcd_cx, lsu_dc_iob_access_e,
|
68 |
|
|
lsu_dcfill_data_mx_sel_e, lsu_cpx_spc_inv_vld, lsu_cpx_thrdid,
|
69 |
|
|
lsu_cpx_stack_dcfill_vld, pcx_rq_for_stb_d1, lsu_dfq_ld_vld,
|
70 |
|
|
lsu_dfq_st_vld, lsu_dfq_ldst_vld
|
71 |
|
|
) ;
|
72 |
|
|
|
73 |
|
|
/*AUTOINPUT*/
|
74 |
|
|
// Beginning of automatic inputs (from unused autoinst inputs)
|
75 |
|
|
// End of automatics
|
76 |
|
|
//
|
77 |
|
|
input rst_tri_en;
|
78 |
|
|
|
79 |
|
|
input rclk ;
|
80 |
|
|
input si;
|
81 |
|
|
input se;
|
82 |
|
|
output so;
|
83 |
|
|
|
84 |
|
|
input lsu_dfill_data_sel_hi ; // select hi or low order 8B.
|
85 |
|
|
//input dcfill_src_dfq_sel ;
|
86 |
|
|
input dfq_byp_ff_en ;
|
87 |
|
|
input dfq_rd_vld_d1 ;
|
88 |
|
|
input [`DFQ_WIDTH:0] dfq_rdata ; // dfq rd output
|
89 |
|
|
input [`CPX_WIDTH-1:0] cpx_spc_data_cx; // cpx to processor pkt
|
90 |
|
|
//input [2:0] stb_dfq_rd_id ; // stb entry id
|
91 |
|
|
input [69:0] stb_rdata_ramd_buf ; // stb0 data ram output.
|
92 |
|
|
input stb_rdata_ramd_b74_buf ; // stb0 data ram output.
|
93 |
|
|
input [14:9] stb_rdata_ramc_buf ; // stb0 tag ram output.
|
94 |
|
|
input lsu_stb_pcx_rvld_d1 ; // stb has been read-delayby1cycle
|
95 |
|
|
//input lsu_stb_dfq_rvld ; // wr to dfq stb bypass ff
|
96 |
|
|
//input [1:0] lmq_pcx_pkt_sz ;
|
97 |
|
|
//input [39:0] lmq_pcx_pkt_addr ;
|
98 |
|
|
|
99 |
|
|
// diagnostic write information
|
100 |
|
|
//input lsu_diagnstc_wr_src_sel_e ; // diagnstc write - diag/store
|
101 |
|
|
input [63:0] lsu_diagnstc_wr_data_e ; // Store data
|
102 |
|
|
input [7:0] lsu_diagnstc_dc_prty_invrt_e ; // invert parity of dw
|
103 |
|
|
//input [3:0] lsu_diagnstc_wr_way_e ; // cache way to be written
|
104 |
|
|
//input [10:0] lsu_diagnstc_wr_addr_e ; // address
|
105 |
|
|
|
106 |
|
|
//input lsu_ifill_pkt_vld ; // ifill pkt vld
|
107 |
|
|
//input lsu_bist_wvld_e ; // bist write to dcache
|
108 |
|
|
//input lsu_bist_rvld_e ; // bist read from dcache
|
109 |
|
|
|
110 |
|
|
//input [6:0] mbist_dcache_index ; // bist rd/wr address
|
111 |
|
|
//input mbist_dcache_word;
|
112 |
|
|
//input [1:0] mbist_dcache_way;
|
113 |
|
|
input [7:0] mbist_write_data ; // bist wdata
|
114 |
|
|
|
115 |
|
|
input cpx_fwd_pkt_en_cx ; // cpx fwd reply/req
|
116 |
|
|
input [7:0] lsu_cpu_dcd_sel ;
|
117 |
|
|
input lsu_cpu_uhlf_sel ;
|
118 |
|
|
input [5:0] lsu_cpxpkt_type_dcd_cx ;
|
119 |
|
|
//input lsu_st_wr_sel_e ;
|
120 |
|
|
//input [1:0] lmq_ld_way ;
|
121 |
|
|
//input [1:0] lsu_st_ack_wrwy ; // cache set way to write to.
|
122 |
|
|
//input [1:0] lsu_st_ack_addr_b54 ;
|
123 |
|
|
//input [1:0] lsu_stb_rd_tid ;
|
124 |
|
|
input lsu_dc_iob_access_e ; // iob read/write of dcache
|
125 |
|
|
|
126 |
|
|
//input tmb_l;
|
127 |
|
|
//input [3:0] lsu_dcfill_mx_sel_e;
|
128 |
|
|
//input lsu_dcfill_addr_mx_sel_e;
|
129 |
|
|
input lsu_dcfill_data_mx_sel_e;
|
130 |
|
|
|
131 |
|
|
input lsu_cpx_spc_inv_vld;
|
132 |
|
|
input [3:0] lsu_cpx_thrdid;
|
133 |
|
|
input lsu_cpx_stack_dcfill_vld ;
|
134 |
|
|
input [3:0] pcx_rq_for_stb_d1;
|
135 |
|
|
|
136 |
|
|
input lsu_dfq_ld_vld ;
|
137 |
|
|
input lsu_dfq_st_vld ;
|
138 |
|
|
input lsu_dfq_ldst_vld ;
|
139 |
|
|
|
140 |
|
|
/*AUTOOUTPUT*/
|
141 |
|
|
// Beginning of automatic outputs (from unused autoinst outputs)
|
142 |
|
|
// End of automatics
|
143 |
|
|
//
|
144 |
|
|
|
145 |
|
|
output [63:0] lsu_l2fill_data ; // dfill data for write to irf
|
146 |
|
|
|
147 |
|
|
output [`DFQ_WIDTH:0] dfq_wdata ;
|
148 |
|
|
output [1:0] dfq_tid ; // thread-id for load at head of DFQ.
|
149 |
|
|
|
150 |
|
|
output [143:0] lsu_dcache_fill_data_e ;// store-write/ld-miss fill
|
151 |
|
|
|
152 |
|
|
output [`CPX_VLD-1:0] lsu_ifill_pkt ;
|
153 |
|
|
output [107:0] lsu_pcx_fwd_pkt ; // local fwd reply/req
|
154 |
|
|
output lsu_cpx_pkt_strm_ack ;
|
155 |
|
|
output lsu_cpx_pkt_vld ;
|
156 |
|
|
output lsu_cpx_pkt_atm_st_cmplt ;
|
157 |
|
|
output [1:0] lsu_cpx_pkt_tid ;
|
158 |
|
|
output [1:0] lsu_cpx_pkt_invwy ; // invalidate way
|
159 |
|
|
output [4:0] lsu_cpx_pkt_inv_pa ; // invalidate pa [10:6]
|
160 |
|
|
output lsu_cpx_pkt_l2miss ; // ld req missed in L2
|
161 |
|
|
output lsu_dfq_byp_invwy_vld ;
|
162 |
|
|
output [5:0] lsu_dfq_byp_type ;
|
163 |
|
|
output lsu_dfq_byp_flush ;
|
164 |
|
|
//output [2:0] lsu_dfq_byp_cpuid ;
|
165 |
|
|
output [1:0] lsu_dfq_byp_tid ;
|
166 |
|
|
//output [13:0] lsu_cpu_inv_data ;
|
167 |
|
|
output [13:9] lsu_cpu_inv_data_b13to9 ;
|
168 |
|
|
output [7:2] lsu_cpu_inv_data_b7to2 ;
|
169 |
|
|
output lsu_cpu_inv_data_b0 ;
|
170 |
|
|
//output lsu_dfq_byp_stquad_pkt2 ;
|
171 |
|
|
//output lsu_cpx_pkt_stquad_pkt2 ;
|
172 |
|
|
output [43:0] lsu_iobrdge_wr_data ;
|
173 |
|
|
output [8:0] lsu_iobrdge_tap_rq_type ;
|
174 |
|
|
//output lsu_dfq_byp_perror_dinv ; // dtag perror corr. st ack
|
175 |
|
|
//output lsu_dfq_byp_perror_iinv ; // itag perror corr. st ack
|
176 |
|
|
output lsu_cpx_pkt_perror_dinv ; // dtag perror corr. st ack
|
177 |
|
|
output lsu_cpx_pkt_perror_iinv ; // itag perror corr. st ack
|
178 |
|
|
output [1:0] lsu_cpx_pkt_perror_set ; // dtag perror - spec. b54
|
179 |
|
|
output [1:0] lsu_cpx_pkt_ld_err ; // err field - cpx ld pkt
|
180 |
|
|
output lsu_dfq_byp_binit_st ; // blk-init st in bypass.
|
181 |
|
|
output lsu_cpx_pkt_binit_st ; // blk-init store
|
182 |
|
|
output lsu_cpx_pkt_prefetch; // prefetch
|
183 |
|
|
output lsu_cpx_pkt_prefetch2; // prefetch - for dctl
|
184 |
|
|
|
185 |
|
|
output lsu_dfq_byp_cpx_inv;
|
186 |
|
|
//output lsu_dfq_byp_stack_dcfill_vld;
|
187 |
|
|
output [1:0] lsu_dfq_byp_stack_adr_b54;
|
188 |
|
|
output [1:0] lsu_dfq_byp_stack_wrway;
|
189 |
|
|
output lsu_dfq_byp_atm;
|
190 |
|
|
|
191 |
|
|
//dcache_fill_addr_e change
|
192 |
|
|
output [7:0] dcache_iob_addr_e;
|
193 |
|
|
output [10:0] st_dcfill_addr;
|
194 |
|
|
|
195 |
|
|
output [1:0] lsu_st_way_e;
|
196 |
|
|
output [1:0] lsu_dcache_iob_way_e;
|
197 |
|
|
|
198 |
|
|
output [1:0] lsu_st_dcfill_size_e;
|
199 |
|
|
|
200 |
|
|
/*AUTOWIRE*/
|
201 |
|
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
202 |
|
|
// End of automatics
|
203 |
|
|
wire [13:0] cpx_cpulo_inv_data ;
|
204 |
|
|
wire [13:0] cpx_cpuhi_inv_data ;
|
205 |
|
|
//wire [`STB_PCX_WIDTH-1:0] stb_pcx_pkt ;
|
206 |
|
|
//wire [`STB_DFQ_WIDTH-1:0] stb_dfq_pkt_data ;
|
207 |
|
|
wire [`STB_DFQ_WIDTH-1:0] stb_dfq_data_in ;
|
208 |
|
|
//wire [`DFQ_WIDTH-1:0] cpx_dfq_data ;
|
209 |
|
|
//wire [`DFQ_WIDTH-1:0] cpx_dfq_data_d1 ;
|
210 |
|
|
//wire [`CPX_WIDTH-1:0] cpx_data_cx_d1 ;
|
211 |
|
|
//wire cpx_st_cmplt_d1 ;
|
212 |
|
|
wire [`DFQ_WIDTH:0] dfq_byp_mx_data ;
|
213 |
|
|
wire [`DFQ_WIDTH-1:0] dfq_byp_ff_data ;
|
214 |
|
|
//wire [`STB_DFQ_WIDTH-1:0] store_dfq_pkt ;
|
215 |
|
|
wire [127:0] st_dcfill_data ;
|
216 |
|
|
wire [63:0] dcache_wr_data ;
|
217 |
|
|
wire [127:0] ldinv_dcfill_data ;
|
218 |
|
|
//wire [`LMQ_WIDTH-1:0] lmq0_pcx_pkt, lmq1_pcx_pkt ;
|
219 |
|
|
//wire [`LMQ_WIDTH-1:0] lmq2_pcx_pkt, lmq3_pcx_pkt ;
|
220 |
|
|
wire [127:0] lsu_dcfill_data ;
|
221 |
|
|
wire [15:0] dcache_wr_parity_mod ;
|
222 |
|
|
//wire [3:0] bist_rsel_way_e ;
|
223 |
|
|
wire [107:0] cpx_fwd_pkt_din ;
|
224 |
|
|
|
225 |
|
|
//wire [3:0] bist_rsel_way_m ;
|
226 |
|
|
//wire [3:0] lsu_bist_rsel_way_wb ; // way select for read
|
227 |
|
|
wire [1:0] cpx_st_dcfill_wrway;
|
228 |
|
|
wire [`STB_DFQ_VLD:0] stb_dcfill_data_mx;
|
229 |
|
|
wire clk;
|
230 |
|
|
wire [13:0] lsu_cpu_inv_data ;
|
231 |
|
|
|
232 |
|
|
assign clk = rclk;
|
233 |
|
|
|
234 |
|
|
|
235 |
|
|
//=================================================================================================
|
236 |
|
|
// STB Datapath
|
237 |
|
|
//=================================================================================================
|
238 |
|
|
|
239 |
|
|
// PCX PKT FORMATTING
|
240 |
|
|
// THREAD0
|
241 |
|
|
//assign stb_pcx_pkt[`STB_PCX_VLD] = lsu_stb_pcx_rvld_d1 ; // Valid
|
242 |
|
|
// Support stores for now.
|
243 |
|
|
//assign stb_pcx_pkt[`STB_PCX_RQ_HI:`STB_PCX_RQ_LO] = stb_rdata_ramd[74:72] ; // Rq-type
|
244 |
|
|
//assign stb_pcx_pkt[`STB_PCX_NC] = stb_rdata_ramd[74] ; // NC
|
245 |
|
|
// cpu-id will be inserted on way out of core.
|
246 |
|
|
//assign stb_pcx_pkt[`STB_PCX_TH_HI:`STB_PCX_TH_LO] = lsu_stb_rd_tid[1:0] ; // TID
|
247 |
|
|
// bf-id is not required.
|
248 |
|
|
//assign stb_pcx_pkt[`STB_PCX_WY_HI:`STB_PCX_WY_LO] = stb_rdata_ramd[71:70] ; // WAY
|
249 |
|
|
//assign stb_pcx_pkt[`STB_PCX_SZ_HI:`STB_PCX_SZ_LO] =
|
250 |
|
|
// stb_rdata_ramd[69:68]; // Size
|
251 |
|
|
//assign stb_pcx_pkt[`STB_PCX_AD_HI:`STB_PCX_AD_LO] =
|
252 |
|
|
// {stb_rdata_ramc[44:9],stb_rdata_ramd[67:64]} ;// Addr
|
253 |
|
|
//assign stb_pcx_pkt[`STB_PCX_DA_HI:`STB_PCX_DA_LO] =
|
254 |
|
|
// stb_rdata_ramd[63:0]; // Data
|
255 |
|
|
|
256 |
|
|
// STB to DFQ Data Formatting
|
257 |
|
|
// THREAD0
|
258 |
|
|
assign stb_dfq_data_in[`STB_DFQ_WIDTH-1:0] =
|
259 |
|
|
{lsu_stb_pcx_rvld_d1, // 82:82 vld //stb_pcx_pkt[`STB_PCX_VLD],
|
260 |
|
|
stb_rdata_ramd_b74_buf, // 81:81 ?? //stb_rdata_ramd[74],
|
261 |
|
|
2'b00, // 80:79 not used
|
262 |
|
|
//stb_pcx_pkt[`STB_PCX_WY_HI:`STB_PCX_WY_LO],
|
263 |
|
|
3'b000, // 78:76 instead of stb_dfq_rd_id[2:0],
|
264 |
|
|
stb_rdata_ramd_buf[69:68], // 75:74 size //stb_pcx_pkt[`STB_PCX_SZ_HI:`STB_PCX_SZ_LO],
|
265 |
|
|
{stb_rdata_ramc_buf[14:9],stb_rdata_ramd_buf[67:64]}, // 73:64 Addr //stb_pcx_pkt[`STB_PCX_AD_LO+9:`STB_PCX_AD_LO],
|
266 |
|
|
stb_rdata_ramd_buf[63:0]}; // 63:0 data //stb_pcx_pkt[`STB_PCX_DA_HI:`STB_PCX_DA_LO]};
|
267 |
|
|
|
268 |
|
|
|
269 |
|
|
// STB DATA BYPASS FLOP
|
270 |
|
|
// Data is read out on read for pcx. The data is then
|
271 |
|
|
// bypassed to the dfq when the st-ack is received.
|
272 |
|
|
//wire [3:0] pcx_rq_for_stb_d1;
|
273 |
|
|
wire [3:0] clk_stb_data;
|
274 |
|
|
wire [`STB_DFQ_VLD:0] stb_dfq_pkt_data0,
|
275 |
|
|
stb_dfq_pkt_data1,
|
276 |
|
|
stb_dfq_pkt_data2,
|
277 |
|
|
stb_dfq_pkt_data3;
|
278 |
|
|
|
279 |
|
|
// timing fix: 9/15/03 - reduce loading on pcx_rq_for_stb[3:0] to stb_clt[0-3]. it had FO2 (stb_ctl,qdp2 - cap=0.5-0.8)
|
280 |
|
|
// move the flop from qdp2 to qctl1
|
281 |
|
|
|
282 |
|
|
//flop pcx rq to read stb data
|
283 |
|
|
//dff #(4) pcx_rq_for_stb_ff (
|
284 |
|
|
// .din (pcx_rq_for_stb[3:0]),
|
285 |
|
|
// .q (pcx_rq_for_stb_d1[3:0]),
|
286 |
|
|
// .clk (clk),
|
287 |
|
|
// .se (1'b0), .si (), .so ());
|
288 |
|
|
|
289 |
|
|
//dffe #(83) stb_dfq_byp_ff (
|
290 |
|
|
// .din (stb_dfq_data_in[`STB_DFQ_VLD:0]),
|
291 |
|
|
// .q (stb_dfq_pkt_data[`STB_DFQ_VLD:0]),
|
292 |
|
|
// .en (lsu_stb_dfq_rvld), .clk (clk),
|
293 |
|
|
// .se (1'b0), .si (), .so ()
|
294 |
|
|
// );
|
295 |
|
|
|
296 |
|
|
//THREAD0
|
297 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
298 |
|
|
`else
|
299 |
|
|
clken_buf stb_dfq_byp0_clken(
|
300 |
|
|
.clk(clk_stb_data[0]),
|
301 |
|
|
.rclk(clk),
|
302 |
|
|
.enb_l(~pcx_rq_for_stb_d1[0]),
|
303 |
|
|
.tmb_l(~se));
|
304 |
|
|
`endif
|
305 |
|
|
|
306 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
307 |
|
|
dffe_s #(83) stb_dfq_byp0_ff (
|
308 |
|
|
.din (stb_dfq_data_in[`STB_DFQ_VLD:0]),
|
309 |
|
|
.q (stb_dfq_pkt_data0[`STB_DFQ_VLD:0]),
|
310 |
|
|
.en (~(~pcx_rq_for_stb_d1[0])), .clk(clk),
|
311 |
|
|
.se (1'b0), .si (), .so ());
|
312 |
|
|
`else
|
313 |
|
|
dff_s #(83) stb_dfq_byp0_ff (
|
314 |
|
|
.din (stb_dfq_data_in[`STB_DFQ_VLD:0]),
|
315 |
|
|
.q (stb_dfq_pkt_data0[`STB_DFQ_VLD:0]),
|
316 |
|
|
.clk (clk_stb_data[0]),
|
317 |
|
|
.se (1'b0), .si (), .so ());
|
318 |
|
|
`endif
|
319 |
|
|
|
320 |
|
|
//THREAD1
|
321 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
322 |
|
|
`else
|
323 |
|
|
clken_buf stb_dfq_byp1_clken(
|
324 |
|
|
.clk(clk_stb_data[1]),
|
325 |
|
|
.rclk(clk),
|
326 |
|
|
.enb_l(~pcx_rq_for_stb_d1[1]),
|
327 |
|
|
.tmb_l(~se));
|
328 |
|
|
`endif
|
329 |
|
|
|
330 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
331 |
|
|
dffe_s #(83) stb_dfq_byp1_ff (
|
332 |
|
|
.din (stb_dfq_data_in[`STB_DFQ_VLD:0]),
|
333 |
|
|
.q (stb_dfq_pkt_data1[`STB_DFQ_VLD:0]),
|
334 |
|
|
.en (~(~pcx_rq_for_stb_d1[1])), .clk(clk),
|
335 |
|
|
.se (1'b0), .si (), .so ());
|
336 |
|
|
`else
|
337 |
|
|
dff_s #(83) stb_dfq_byp1_ff (
|
338 |
|
|
.din (stb_dfq_data_in[`STB_DFQ_VLD:0]),
|
339 |
|
|
.q (stb_dfq_pkt_data1[`STB_DFQ_VLD:0]),
|
340 |
|
|
.clk (clk_stb_data[1]),
|
341 |
|
|
.se (1'b0), .si (), .so ());
|
342 |
|
|
`endif
|
343 |
|
|
|
344 |
|
|
//THREAD2
|
345 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
346 |
|
|
`else
|
347 |
|
|
clken_buf stb_dfq_byp2_clken(
|
348 |
|
|
.clk(clk_stb_data[2]),
|
349 |
|
|
.rclk(clk),
|
350 |
|
|
.enb_l(~pcx_rq_for_stb_d1[2]),
|
351 |
|
|
.tmb_l(~se));
|
352 |
|
|
`endif
|
353 |
|
|
|
354 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
355 |
|
|
dffe_s #(83) stb_dfq_byp2_ff (
|
356 |
|
|
.din (stb_dfq_data_in[`STB_DFQ_VLD:0]),
|
357 |
|
|
.q (stb_dfq_pkt_data2[`STB_DFQ_VLD:0]),
|
358 |
|
|
.en (~(~pcx_rq_for_stb_d1[2])), .clk(clk),
|
359 |
|
|
.se (1'b0), .si (), .so ());
|
360 |
|
|
`else
|
361 |
|
|
dff_s #(83) stb_dfq_byp2_ff (
|
362 |
|
|
.din (stb_dfq_data_in[`STB_DFQ_VLD:0]),
|
363 |
|
|
.q (stb_dfq_pkt_data2[`STB_DFQ_VLD:0]),
|
364 |
|
|
.clk (clk_stb_data[2]),
|
365 |
|
|
.se (1'b0), .si (), .so ());
|
366 |
|
|
`endif
|
367 |
|
|
|
368 |
|
|
//THREAD3
|
369 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
370 |
|
|
`else
|
371 |
|
|
clken_buf stb_dfq_byp3_clken(
|
372 |
|
|
.clk(clk_stb_data[3]),
|
373 |
|
|
.rclk(clk),
|
374 |
|
|
.enb_l(~pcx_rq_for_stb_d1[3]),
|
375 |
|
|
.tmb_l(~se));
|
376 |
|
|
`endif
|
377 |
|
|
|
378 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
379 |
|
|
dffe_s #(83) stb_dfq_byp3_ff (
|
380 |
|
|
.din (stb_dfq_data_in[`STB_DFQ_VLD:0]),
|
381 |
|
|
.q (stb_dfq_pkt_data3[`STB_DFQ_VLD:0]),
|
382 |
|
|
.en (~(~pcx_rq_for_stb_d1[3])), .clk(clk),
|
383 |
|
|
.se (1'b0), .si (), .so ());
|
384 |
|
|
`else
|
385 |
|
|
dff_s #(83) stb_dfq_byp3_ff (
|
386 |
|
|
.din (stb_dfq_data_in[`STB_DFQ_VLD:0]),
|
387 |
|
|
.q (stb_dfq_pkt_data3[`STB_DFQ_VLD:0]),
|
388 |
|
|
.clk (clk_stb_data[3]),
|
389 |
|
|
.se (1'b0), .si (), .so ());
|
390 |
|
|
`endif
|
391 |
|
|
|
392 |
|
|
// MUX the store data if cpx_pkt==st_ack w/ dcfill vld=1
|
393 |
|
|
mux4ds #(`STB_DFQ_VLD+1) stb_data_mx (
|
394 |
|
|
.in0 (stb_dfq_pkt_data0[`STB_DFQ_VLD:0]),
|
395 |
|
|
.in1 (stb_dfq_pkt_data1[`STB_DFQ_VLD:0]),
|
396 |
|
|
.in2 (stb_dfq_pkt_data2[`STB_DFQ_VLD:0]),
|
397 |
|
|
.in3 (stb_dfq_pkt_data3[`STB_DFQ_VLD:0]),
|
398 |
|
|
.sel0 (lsu_cpx_thrdid[0]),
|
399 |
|
|
.sel1 (lsu_cpx_thrdid[1]),
|
400 |
|
|
.sel2 (lsu_cpx_thrdid[2]),
|
401 |
|
|
.sel3 (lsu_cpx_thrdid[3]),
|
402 |
|
|
.dout (stb_dcfill_data_mx[`STB_DFQ_VLD:0])
|
403 |
|
|
);
|
404 |
|
|
|
405 |
|
|
//NOTE: mux this raw data w/ modified data to generate dfq input and feed into dfq_wdata
|
406 |
|
|
|
407 |
|
|
|
408 |
|
|
|
409 |
|
|
|
410 |
|
|
//=================================================================================================
|
411 |
|
|
// FWD PKT - REQ/REPLY
|
412 |
|
|
//=================================================================================================
|
413 |
|
|
|
414 |
|
|
// Design Note !! - Bus can be decreased - do not have to keep tag.
|
415 |
|
|
|
416 |
|
|
// TAP ACCESS FORMAT
|
417 |
|
|
// BEGIN (OLD)
|
418 |
|
|
// Control bits :
|
419 |
|
|
// R/W,TID,BIST,MARGIN,DEFEATURE,PC (R=1,W=0)
|
420 |
|
|
// These 7b are mapped to bits 70:64 of the cpx pkt.
|
421 |
|
|
// (R/W is the highest order bit).
|
422 |
|
|
// *Note that a write to pc is ignored by hardware.
|
423 |
|
|
// *The cpx-reply will not contain the control information.
|
424 |
|
|
// *TID(Thread id) applies only to pc and defeature.
|
425 |
|
|
// Data bits :
|
426 |
|
|
// PC(48b),Margin(36b),Bist-Ctl(14b),Defeature(4b).
|
427 |
|
|
// The largest field of 48b is mapped to bits 47:0 of the cpx pkt.
|
428 |
|
|
// END (OLD)
|
429 |
|
|
|
430 |
|
|
// Control bits (mapped to data[127:96] of cpx packet):
|
431 |
|
|
// L1I data,L1D data,BIST,MARGIN,DEFEATURE,PC,TID[1:0]
|
432 |
|
|
// These 8b are mapped to bits 103:96 of the cpx pkt.
|
433 |
|
|
// Unused bits are zeros.
|
434 |
|
|
// (TID is the lowest order 2 bits).
|
435 |
|
|
// *Note that a write to pc is ignored by hardware.
|
436 |
|
|
// *The cpx-reply will not contain the control information.
|
437 |
|
|
// *TID(Thread id) applies only to pc and defeature.
|
438 |
|
|
//
|
439 |
|
|
// Address bits (mapped to data[95:64] of cpx packet):
|
440 |
|
|
// This is used to access the L1 cache arrays. This field
|
441 |
|
|
// is a dont-care for the bist/margin/defeature/pc ASIs.
|
442 |
|
|
// Only the lower 32 address bits are specified here.
|
443 |
|
|
// The core (lsu) will pad zeros create a 64-bit address.
|
444 |
|
|
//
|
445 |
|
|
// Data bits (mapped to data[63:0] of cpx packet):
|
446 |
|
|
// PC(48b),Margin(36b),Bist-Ctl(14b),Defeature(4b).
|
447 |
|
|
// The largest field of 48b is mapped to bits 47:0 of the cpx pkt.
|
448 |
|
|
|
449 |
|
|
|
450 |
|
|
// Formatted to contain fwd req which is of largest size.
|
451 |
|
|
// Truncate address !!! 40b should not be required.
|
452 |
|
|
assign cpx_fwd_pkt_din[107:0] =
|
453 |
|
|
{
|
454 |
|
|
cpx_spc_data_cx[`CPX_NC], // r/!w (1b)
|
455 |
|
|
cpx_spc_data_cx[133:131], // src/tar (3b)
|
456 |
|
|
cpx_spc_data_cx[103:0] // 64b data + 40b addr (104b)
|
457 |
|
|
} ;
|
458 |
|
|
|
459 |
|
|
// Contains cpx fwd reply or req
|
460 |
|
|
//dffe #(108) fwdpkt_ff (
|
461 |
|
|
// .din (cpx_fwd_pkt_din[107:0]),
|
462 |
|
|
// .q (lsu_pcx_fwd_pkt[107:0]),
|
463 |
|
|
// .en (cpx_fwd_pkt_en_cx),
|
464 |
|
|
// .clk (clk),
|
465 |
|
|
// .se (1'b0), .si (), .so ()
|
466 |
|
|
// );
|
467 |
|
|
|
468 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
469 |
|
|
`else
|
470 |
|
|
clken_buf fwdpkt_clken(
|
471 |
|
|
.clk(clk_cpx_fwd_pkt_en_cx),
|
472 |
|
|
.rclk(clk),
|
473 |
|
|
.enb_l(~cpx_fwd_pkt_en_cx),
|
474 |
|
|
.tmb_l(~se));
|
475 |
|
|
`endif
|
476 |
|
|
|
477 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
478 |
|
|
dffe_s #(108) fwdpkt_ff (
|
479 |
|
|
.din (cpx_fwd_pkt_din[107:0]),
|
480 |
|
|
.q (lsu_pcx_fwd_pkt[107:0]),
|
481 |
|
|
.en (~(~cpx_fwd_pkt_en_cx)), .clk(clk),
|
482 |
|
|
.se (1'b0), .si (), .so ());
|
483 |
|
|
`else
|
484 |
|
|
dff_s #(108) fwdpkt_ff (
|
485 |
|
|
.din (cpx_fwd_pkt_din[107:0]),
|
486 |
|
|
.q (lsu_pcx_fwd_pkt[107:0]),
|
487 |
|
|
.clk (clk_cpx_fwd_pkt_en_cx),
|
488 |
|
|
.se (1'b0), .si (), .so ());
|
489 |
|
|
`endif
|
490 |
|
|
|
491 |
|
|
|
492 |
|
|
// New mapping for address bits given that tag is gone. (OBSOLETE)
|
493 |
|
|
// pkt[74:73] - Way
|
494 |
|
|
// pkt[72:65] - Set Index
|
495 |
|
|
// pkt[64] - Word
|
496 |
|
|
// New mapping - based on 0-in testing, alignment with PRM.
|
497 |
|
|
// pkt[76:75] - Way
|
498 |
|
|
// pkt[74:68] - Set Index
|
499 |
|
|
// pkt[67] -DWord
|
500 |
|
|
|
501 |
|
|
wire [7:0] dcache_iob_addr_e ;
|
502 |
|
|
assign dcache_iob_addr_e[7:0] = lsu_pcx_fwd_pkt[74:67] ;
|
503 |
|
|
|
504 |
|
|
//wire [3:0] dcache_iob_wy_e ;
|
505 |
|
|
//assign dcache_iob_wy_e[0] = ~lsu_pcx_fwd_pkt[76] & ~lsu_pcx_fwd_pkt[75] ;
|
506 |
|
|
//assign dcache_iob_wy_e[1] = ~lsu_pcx_fwd_pkt[76] & lsu_pcx_fwd_pkt[75] ;
|
507 |
|
|
//assign dcache_iob_wy_e[2] = lsu_pcx_fwd_pkt[76] & ~lsu_pcx_fwd_pkt[75] ;
|
508 |
|
|
//assign dcache_iob_wy_e[3] = lsu_pcx_fwd_pkt[76] & lsu_pcx_fwd_pkt[75] ;
|
509 |
|
|
|
510 |
|
|
assign lsu_dcache_iob_way_e [1:0] = {lsu_pcx_fwd_pkt[76], lsu_pcx_fwd_pkt[75]};
|
511 |
|
|
|
512 |
|
|
wire [63:0] dcache_iob_data_e ;
|
513 |
|
|
assign dcache_iob_data_e[63:0] = lsu_pcx_fwd_pkt[63:0] ;
|
514 |
|
|
|
515 |
|
|
assign lsu_iobrdge_wr_data[43:0] = lsu_pcx_fwd_pkt[43:0] ;
|
516 |
|
|
assign lsu_iobrdge_tap_rq_type[8:0] = {lsu_pcx_fwd_pkt[107],lsu_pcx_fwd_pkt[103:96]} ;
|
517 |
|
|
|
518 |
|
|
//=================================================================================================
|
519 |
|
|
// DFQ PKT SELECTION
|
520 |
|
|
//=================================================================================================
|
521 |
|
|
|
522 |
|
|
// There are two sources :
|
523 |
|
|
// - from the ccx - load,inv
|
524 |
|
|
// - from the stb - ack'ed store update.
|
525 |
|
|
// ** store updates do not have to be inserted into DFQ for ordering purposes. An inv will
|
526 |
|
|
// clear stale data in the stb and bypass flops to ensure TSO.
|
527 |
|
|
|
528 |
|
|
// to be written to dfq if bypass full else wr to byp mx.
|
529 |
|
|
//assign dfq_wdata[`DFQ_WIDTH:0] =
|
530 |
|
|
// {lsu_cpx_spc_inv_vld,lsu_cpxpkt_type_dcd_cx[5:0],cpx_spc_data_cx[`CPX_WIDTH-1:0]};
|
531 |
|
|
// //{{(`DFQ_WIDTH-`CPX_WIDTH)1'b0},cpx_spc_data_cx[`CPX_WIDTH-1:0]},
|
532 |
|
|
|
533 |
|
|
wire [`DFQ_WIDTH:0] dfq_st_data,dfq_cpx_raw_wdata;
|
534 |
|
|
wire [1:0] cpx_st_ack_addr_b54;
|
535 |
|
|
|
536 |
|
|
assign dfq_cpx_raw_wdata[`DFQ_WIDTH:0] =
|
537 |
|
|
{lsu_cpx_spc_inv_vld,lsu_cpxpkt_type_dcd_cx[5:0],cpx_spc_data_cx[`CPX_WIDTH-1:0]};
|
538 |
|
|
|
539 |
|
|
assign dfq_st_data[`DFQ_WIDTH:0] =
|
540 |
|
|
{lsu_cpx_spc_inv_vld,lsu_cpxpkt_type_dcd_cx[5:0],
|
541 |
|
|
cpx_spc_data_cx[`CPX_WIDTH-1:87],
|
542 |
|
|
cpx_st_ack_addr_b54[1:0], // 86:85
|
543 |
|
|
cpx_st_dcfill_wrway[1:0], // 84:83
|
544 |
|
|
stb_dcfill_data_mx[`STB_DFQ_VLD:0]}; // 82:0
|
545 |
|
|
|
546 |
|
|
mux2ds #(`DFQ_WIDTH+1) dfq_st_data_mx (
|
547 |
|
|
.in0 (dfq_st_data[`DFQ_WIDTH:0]),
|
548 |
|
|
.in1 (dfq_cpx_raw_wdata[`DFQ_WIDTH:0]),
|
549 |
|
|
.sel0 (lsu_cpx_stack_dcfill_vld),
|
550 |
|
|
.sel1 (~lsu_cpx_stack_dcfill_vld),
|
551 |
|
|
.dout (dfq_wdata[`DFQ_WIDTH:0])
|
552 |
|
|
);
|
553 |
|
|
|
554 |
|
|
//timing fix: 05/31/03: decouple byp mux from lsu_cpx_stack_dcfill_vld
|
555 |
|
|
// i.e. replace dfq_wdata w/ dfq_cpx_raw_wdata in byp mux
|
556 |
|
|
// select between dfq output and cpx bypass.
|
557 |
|
|
mux2ds #(`DFQ_WIDTH+1) dfq_byp_mx (
|
558 |
|
|
.in0 (dfq_rdata[`DFQ_WIDTH:0]),
|
559 |
|
|
.in1 (dfq_cpx_raw_wdata[`DFQ_WIDTH:0]),
|
560 |
|
|
.sel0 (dfq_rd_vld_d1),
|
561 |
|
|
.sel1 (~dfq_rd_vld_d1),
|
562 |
|
|
.dout (dfq_byp_mx_data[`DFQ_WIDTH:0])
|
563 |
|
|
);
|
564 |
|
|
|
565 |
|
|
assign lsu_dfq_byp_cpx_inv = dfq_byp_mx_data[`DFQ_WIDTH];
|
566 |
|
|
assign lsu_dfq_byp_tid[1:0] = dfq_byp_mx_data[`CPX_TH_HI:`CPX_TH_LO] ;
|
567 |
|
|
//assign lsu_dfq_byp_cpuid[2:0] = dfq_byp_mx_data[`CPX_INV_CID_HI:`CPX_INV_CID_LO] ;
|
568 |
|
|
assign lsu_dfq_byp_flush = dfq_byp_mx_data[`CPX_NC] ;
|
569 |
|
|
assign lsu_dfq_byp_invwy_vld = dfq_byp_mx_data[`CPX_WYVLD] ;
|
570 |
|
|
|
571 |
|
|
//assign lsu_dfq_byp_type[5:0] = dfq_byp_mx_data[`DFQ_WIDTH-1:`DFQ_WIDTH-6] ;
|
572 |
|
|
assign lsu_dfq_byp_type[5:3] = dfq_byp_mx_data[`DFQ_WIDTH-1:`DFQ_WIDTH-3] ;
|
573 |
|
|
assign lsu_dfq_byp_type[2] = dfq_byp_mx_data[`DFQ_WIDTH-4] & dfq_rd_vld_d1;
|
574 |
|
|
assign lsu_dfq_byp_type[1:0] = dfq_byp_mx_data[`DFQ_WIDTH-5:`DFQ_WIDTH-6] ;
|
575 |
|
|
|
576 |
|
|
//assign lsu_dfq_byp_stquad_pkt2 = dfq_byp_mx_data[130] ;
|
577 |
|
|
assign lsu_dfq_byp_binit_st = dfq_byp_mx_data[125] ;
|
578 |
|
|
//assign lsu_dfq_byp_perror_iinv = dfq_byp_mx_data[`CPX_PERR_DINV+1] ;
|
579 |
|
|
//assign lsu_dfq_byp_perror_dinv = dfq_byp_mx_data[`CPX_PERR_DINV] ;
|
580 |
|
|
//assign lsu_dfq_byp_stack_dcfill_vld = dfq_byp_mx_data[87] ;
|
581 |
|
|
assign lsu_dfq_byp_stack_adr_b54[1:0] = dfq_byp_mx_data[86:85] ;
|
582 |
|
|
assign lsu_dfq_byp_stack_wrway[1:0] = dfq_byp_mx_data[84:83] ;
|
583 |
|
|
|
584 |
|
|
assign lsu_ifill_pkt[`CPX_VLD-1:0] = dfq_byp_mx_data[`CPX_VLD-1:0] ;
|
585 |
|
|
//assign lsu_ifill_pkt[`CPX_WIDTH-1:0] = {lsu_ifill_pkt_vld,dfq_byp_mx_data[`CPX_VLD-1:0]} ;
|
586 |
|
|
|
587 |
|
|
assign lsu_dfq_byp_atm = dfq_byp_mx_data[129] ;
|
588 |
|
|
|
589 |
|
|
// Decode in qctl !!!
|
590 |
|
|
//assign dfq_byp_tid[1:0] = dfq_byp_mx_data[`CPX_TH_HI:`CPX_TH_LO] ;
|
591 |
|
|
//assign dfq_byp_tid[1:0] = dfq_byp_mx_data[`DFQ_TH_HI:`DFQ_TH_LO] ;
|
592 |
|
|
|
593 |
|
|
// Stage dfq output
|
594 |
|
|
// In case of multiple inv or other such cases, pkt will be held in
|
595 |
|
|
// byp ff until pkt completely utilized.
|
596 |
|
|
//dffe #(`DFQ_WIDTH) dfq_data_stg (
|
597 |
|
|
// .din (dfq_byp_mx_data[`DFQ_WIDTH-1:0]),
|
598 |
|
|
// .q (dfq_byp_ff_data[`DFQ_WIDTH-1:0]),
|
599 |
|
|
// .en (dfq_byp_ff_en), .clk (clk),
|
600 |
|
|
// .se (1'b0), .si (), .so ()
|
601 |
|
|
//);
|
602 |
|
|
|
603 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
604 |
|
|
`else
|
605 |
|
|
clken_buf dfq_byp_ff_en_clken(
|
606 |
|
|
.clk(clk_dfq_byp_ff_en),
|
607 |
|
|
.rclk(clk),
|
608 |
|
|
.enb_l(~dfq_byp_ff_en),
|
609 |
|
|
.tmb_l(~se));
|
610 |
|
|
`endif
|
611 |
|
|
|
612 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
613 |
|
|
dffe_s #(`DFQ_WIDTH) dfq_data_stg (
|
614 |
|
|
.din (dfq_byp_mx_data[`DFQ_WIDTH-1:0]),
|
615 |
|
|
.q (dfq_byp_ff_data[`DFQ_WIDTH-1:0]),
|
616 |
|
|
.en (~(~dfq_byp_ff_en)), .clk(clk),
|
617 |
|
|
.se (1'b0), .si (), .so ());
|
618 |
|
|
`else
|
619 |
|
|
dff_s #(`DFQ_WIDTH) dfq_data_stg (
|
620 |
|
|
.din (dfq_byp_mx_data[`DFQ_WIDTH-1:0]),
|
621 |
|
|
.q (dfq_byp_ff_data[`DFQ_WIDTH-1:0]),
|
622 |
|
|
.clk (clk_dfq_byp_ff_en),
|
623 |
|
|
.se (1'b0), .si (), .so ());
|
624 |
|
|
`endif
|
625 |
|
|
|
626 |
|
|
|
627 |
|
|
// To be decoded in qctl
|
628 |
|
|
//assign lsu_st_cmplt_type = dfq_byp_ff_data[`DFQ_ST_CMPLT];
|
629 |
|
|
|
630 |
|
|
assign dfq_tid[1:0] = dfq_byp_ff_data[`CPX_TH_HI:`CPX_TH_LO] ;
|
631 |
|
|
|
632 |
|
|
output lsu_cpx_pkt_ifill_type;
|
633 |
|
|
output lsu_cpx_pkt_atomic ;
|
634 |
|
|
|
635 |
|
|
// Should some of these be in-flight ?
|
636 |
|
|
//assign lsu_cpx_pkt_rqtype[3:0] = dfq_byp_ff_data[`CPX_RQ_HI:`CPX_RQ_LO] ;
|
637 |
|
|
assign lsu_cpx_pkt_ifill_type = dfq_byp_ff_data[`DFQ_WIDTH-2];
|
638 |
|
|
assign lsu_cpx_pkt_tid[1:0] = dfq_byp_ff_data[`CPX_TH_HI:`CPX_TH_LO] ;
|
639 |
|
|
assign lsu_cpx_pkt_vld = dfq_byp_ff_data[`CPX_VLD] ;
|
640 |
|
|
assign lsu_cpx_pkt_atm_st_cmplt = dfq_byp_ff_data[129] ;
|
641 |
|
|
assign lsu_cpx_pkt_invwy[1:0] = dfq_byp_ff_data[`CPX_WY_HI:`CPX_WY_LO] ;
|
642 |
|
|
// Upper 6bits are used to store decoded request type information.
|
643 |
|
|
assign lsu_cpx_pkt_strm_ack = dfq_byp_ff_data[`DFQ_WIDTH-5];
|
644 |
|
|
//assign lsu_cpx_pkt_inv_pa[4:0] = dfq_byp_ff_data[`CPX_INV_PA_HI-1:`CPX_INV_PA_LO]; //!!
|
645 |
|
|
assign lsu_cpx_pkt_inv_pa[4:0] = dfq_byp_ff_data[`CPX_INV_PA_HI:`CPX_INV_PA_LO];
|
646 |
|
|
assign lsu_cpx_pkt_atomic = dfq_byp_ff_data[129] | //atomic st ack
|
647 |
|
|
dfq_byp_ff_data[131] ; //stquad pkt1
|
648 |
|
|
//assign lsu_cpx_pkt_stquad_pkt2 = dfq_byp_ff_data[130] ;
|
649 |
|
|
assign lsu_cpx_pkt_binit_st = dfq_byp_ff_data[125] ;
|
650 |
|
|
assign lsu_cpx_pkt_prefetch = dfq_byp_ff_data[128] ; // for qctl2
|
651 |
|
|
assign lsu_cpx_pkt_prefetch2 = dfq_byp_ff_data[128] ; // for dctl
|
652 |
|
|
//assign lsu_spu_strm_st = dfq_byp_ff_data[134] ; // strm store ack (vs. ma)
|
653 |
|
|
|
654 |
|
|
assign lsu_cpx_pkt_perror_iinv = dfq_byp_ff_data[`CPX_PERR_DINV+1] ;
|
655 |
|
|
assign lsu_cpx_pkt_perror_dinv = dfq_byp_ff_data[`CPX_PERR_DINV] ;
|
656 |
|
|
assign lsu_cpx_pkt_perror_set[1:0] =
|
657 |
|
|
dfq_byp_ff_data[`CPX_PERR_DINV_AD5:`CPX_PERR_DINV_AD4] ;
|
658 |
|
|
|
659 |
|
|
assign lsu_cpx_pkt_ld_err[1:0] = dfq_byp_ff_data[138:137] ;
|
660 |
|
|
assign lsu_cpx_pkt_l2miss = dfq_byp_ff_data[139] ;
|
661 |
|
|
|
662 |
|
|
|
663 |
|
|
//=================================================================================================
|
664 |
|
|
// DFQ OUTPUT - LOCAL PROCESSING
|
665 |
|
|
//=================================================================================================
|
666 |
|
|
|
667 |
|
|
|
668 |
|
|
mux4ds #(14) invfld_lo_sel (
|
669 |
|
|
.in0 ({dfq_byp_mx_data[`CPX_A11_C0_HI:`CPX_A11_C0_LO],
|
670 |
|
|
dfq_byp_mx_data[`CPX_A10_C0_HI:`CPX_A10_C0_LO],
|
671 |
|
|
dfq_byp_mx_data[`CPX_A01_C0_HI:`CPX_A01_C0_LO],
|
672 |
|
|
dfq_byp_mx_data[`CPX_A00_C0_HI:`CPX_A00_C0_LO]}),
|
673 |
|
|
.in1 ({dfq_byp_mx_data[`CPX_A11_C1_HI:`CPX_A11_C1_LO],
|
674 |
|
|
dfq_byp_mx_data[`CPX_A10_C1_HI:`CPX_A10_C1_LO],
|
675 |
|
|
dfq_byp_mx_data[`CPX_A01_C1_HI:`CPX_A01_C1_LO],
|
676 |
|
|
dfq_byp_mx_data[`CPX_A00_C1_HI:`CPX_A00_C1_LO]}),
|
677 |
|
|
.in2 ({dfq_byp_mx_data[`CPX_A11_C2_HI:`CPX_A11_C2_LO],
|
678 |
|
|
dfq_byp_mx_data[`CPX_A10_C2_HI:`CPX_A10_C2_LO],
|
679 |
|
|
dfq_byp_mx_data[`CPX_A01_C2_HI:`CPX_A01_C2_LO],
|
680 |
|
|
dfq_byp_mx_data[`CPX_A00_C2_HI:`CPX_A00_C2_LO]}),
|
681 |
|
|
.in3 ({dfq_byp_mx_data[`CPX_A11_C3_HI:`CPX_A11_C3_LO],
|
682 |
|
|
dfq_byp_mx_data[`CPX_A10_C3_HI:`CPX_A10_C3_LO],
|
683 |
|
|
dfq_byp_mx_data[`CPX_A01_C3_HI:`CPX_A01_C3_LO],
|
684 |
|
|
dfq_byp_mx_data[`CPX_A00_C3_HI:`CPX_A00_C3_LO]}),
|
685 |
|
|
.sel0 (lsu_cpu_dcd_sel[0]),
|
686 |
|
|
.sel1 (lsu_cpu_dcd_sel[1]),
|
687 |
|
|
.sel2 (lsu_cpu_dcd_sel[2]),
|
688 |
|
|
.sel3 (lsu_cpu_dcd_sel[3]),
|
689 |
|
|
.dout (cpx_cpulo_inv_data[13:0])
|
690 |
|
|
);
|
691 |
|
|
|
692 |
|
|
mux4ds #(14) invfld_hi_sel (
|
693 |
|
|
.in0 ({dfq_byp_mx_data[`CPX_A11_C4_HI:`CPX_A11_C4_LO],
|
694 |
|
|
dfq_byp_mx_data[`CPX_A10_C4_HI:`CPX_A10_C4_LO],
|
695 |
|
|
dfq_byp_mx_data[`CPX_A01_C4_HI:`CPX_A01_C4_LO],
|
696 |
|
|
dfq_byp_mx_data[`CPX_A00_C4_HI:`CPX_A00_C4_LO]}),
|
697 |
|
|
.in1 ({dfq_byp_mx_data[`CPX_A11_C5_HI:`CPX_A11_C5_LO],
|
698 |
|
|
dfq_byp_mx_data[`CPX_A10_C5_HI:`CPX_A10_C5_LO],
|
699 |
|
|
dfq_byp_mx_data[`CPX_A01_C5_HI:`CPX_A01_C5_LO],
|
700 |
|
|
dfq_byp_mx_data[`CPX_A00_C5_HI:`CPX_A00_C5_LO]}),
|
701 |
|
|
.in2 ({dfq_byp_mx_data[`CPX_A11_C6_HI:`CPX_A11_C6_LO],
|
702 |
|
|
dfq_byp_mx_data[`CPX_A10_C6_HI:`CPX_A10_C6_LO],
|
703 |
|
|
dfq_byp_mx_data[`CPX_A01_C6_HI:`CPX_A01_C6_LO],
|
704 |
|
|
dfq_byp_mx_data[`CPX_A00_C6_HI:`CPX_A00_C6_LO]}),
|
705 |
|
|
.in3 ({dfq_byp_mx_data[`CPX_A11_C7_HI:`CPX_A11_C7_LO],
|
706 |
|
|
dfq_byp_mx_data[`CPX_A10_C7_HI:`CPX_A10_C7_LO],
|
707 |
|
|
dfq_byp_mx_data[`CPX_A01_C7_HI:`CPX_A01_C7_LO],
|
708 |
|
|
dfq_byp_mx_data[`CPX_A00_C7_HI:`CPX_A00_C7_LO]}),
|
709 |
|
|
.sel0 (lsu_cpu_dcd_sel[4]),
|
710 |
|
|
.sel1 (lsu_cpu_dcd_sel[5]),
|
711 |
|
|
.sel2 (lsu_cpu_dcd_sel[6]),
|
712 |
|
|
.sel3 (lsu_cpu_dcd_sel[7]),
|
713 |
|
|
.dout (cpx_cpuhi_inv_data[13:0])
|
714 |
|
|
);
|
715 |
|
|
|
716 |
|
|
|
717 |
|
|
mux2ds #(14) invfld_sel (
|
718 |
|
|
.in0 (cpx_cpulo_inv_data[13:0]),
|
719 |
|
|
.in1 (cpx_cpuhi_inv_data[13:0]),
|
720 |
|
|
.sel0 (~lsu_cpu_uhlf_sel),
|
721 |
|
|
.sel1 (lsu_cpu_uhlf_sel),
|
722 |
|
|
.dout (lsu_cpu_inv_data[13:0])
|
723 |
|
|
);
|
724 |
|
|
|
725 |
|
|
assign lsu_cpu_inv_data_b13to9[13:9] = lsu_cpu_inv_data[13:9] ;
|
726 |
|
|
assign lsu_cpu_inv_data_b7to2[7:2] = lsu_cpu_inv_data[7:2] ;
|
727 |
|
|
assign lsu_cpu_inv_data_b0 = lsu_cpu_inv_data[0] ;
|
728 |
|
|
|
729 |
|
|
// same structure as above for st data write way
|
730 |
|
|
wire [13:0] cpx_cpulo_dcfill_wrway,
|
731 |
|
|
cpx_cpuhi_dcfill_wrway,
|
732 |
|
|
cpx_st_dcfill_wrway_sel;
|
733 |
|
|
|
734 |
|
|
|
735 |
|
|
mux4ds #(14) st_dcfill_wrway_lo (
|
736 |
|
|
.in0 ({cpx_spc_data_cx[`CPX_A11_C0_HI:`CPX_A11_C0_LO],
|
737 |
|
|
cpx_spc_data_cx[`CPX_A10_C0_HI:`CPX_A10_C0_LO],
|
738 |
|
|
cpx_spc_data_cx[`CPX_A01_C0_HI:`CPX_A01_C0_LO],
|
739 |
|
|
cpx_spc_data_cx[`CPX_A00_C0_HI:`CPX_A00_C0_LO]}),
|
740 |
|
|
.in1 ({cpx_spc_data_cx[`CPX_A11_C1_HI:`CPX_A11_C1_LO],
|
741 |
|
|
cpx_spc_data_cx[`CPX_A10_C1_HI:`CPX_A10_C1_LO],
|
742 |
|
|
cpx_spc_data_cx[`CPX_A01_C1_HI:`CPX_A01_C1_LO],
|
743 |
|
|
cpx_spc_data_cx[`CPX_A00_C1_HI:`CPX_A00_C1_LO]}),
|
744 |
|
|
.in2 ({cpx_spc_data_cx[`CPX_A11_C2_HI:`CPX_A11_C2_LO],
|
745 |
|
|
cpx_spc_data_cx[`CPX_A10_C2_HI:`CPX_A10_C2_LO],
|
746 |
|
|
cpx_spc_data_cx[`CPX_A01_C2_HI:`CPX_A01_C2_LO],
|
747 |
|
|
cpx_spc_data_cx[`CPX_A00_C2_HI:`CPX_A00_C2_LO]}),
|
748 |
|
|
.in3 ({cpx_spc_data_cx[`CPX_A11_C3_HI:`CPX_A11_C3_LO],
|
749 |
|
|
cpx_spc_data_cx[`CPX_A10_C3_HI:`CPX_A10_C3_LO],
|
750 |
|
|
cpx_spc_data_cx[`CPX_A01_C3_HI:`CPX_A01_C3_LO],
|
751 |
|
|
cpx_spc_data_cx[`CPX_A00_C3_HI:`CPX_A00_C3_LO]}),
|
752 |
|
|
.sel0 (lsu_cpu_dcd_sel[0]),
|
753 |
|
|
.sel1 (lsu_cpu_dcd_sel[1]),
|
754 |
|
|
.sel2 (lsu_cpu_dcd_sel[2]),
|
755 |
|
|
.sel3 (lsu_cpu_dcd_sel[3]),
|
756 |
|
|
.dout (cpx_cpulo_dcfill_wrway[13:0])
|
757 |
|
|
);
|
758 |
|
|
|
759 |
|
|
mux4ds #(14) st_dcfill_wrway_hi (
|
760 |
|
|
.in0 ({cpx_spc_data_cx[`CPX_A11_C4_HI:`CPX_A11_C4_LO],
|
761 |
|
|
cpx_spc_data_cx[`CPX_A10_C4_HI:`CPX_A10_C4_LO],
|
762 |
|
|
cpx_spc_data_cx[`CPX_A01_C4_HI:`CPX_A01_C4_LO],
|
763 |
|
|
cpx_spc_data_cx[`CPX_A00_C4_HI:`CPX_A00_C4_LO]}),
|
764 |
|
|
.in1 ({cpx_spc_data_cx[`CPX_A11_C5_HI:`CPX_A11_C5_LO],
|
765 |
|
|
cpx_spc_data_cx[`CPX_A10_C5_HI:`CPX_A10_C5_LO],
|
766 |
|
|
cpx_spc_data_cx[`CPX_A01_C5_HI:`CPX_A01_C5_LO],
|
767 |
|
|
cpx_spc_data_cx[`CPX_A00_C5_HI:`CPX_A00_C5_LO]}),
|
768 |
|
|
.in2 ({cpx_spc_data_cx[`CPX_A11_C6_HI:`CPX_A11_C6_LO],
|
769 |
|
|
cpx_spc_data_cx[`CPX_A10_C6_HI:`CPX_A10_C6_LO],
|
770 |
|
|
cpx_spc_data_cx[`CPX_A01_C6_HI:`CPX_A01_C6_LO],
|
771 |
|
|
cpx_spc_data_cx[`CPX_A00_C6_HI:`CPX_A00_C6_LO]}),
|
772 |
|
|
.in3 ({cpx_spc_data_cx[`CPX_A11_C7_HI:`CPX_A11_C7_LO],
|
773 |
|
|
cpx_spc_data_cx[`CPX_A10_C7_HI:`CPX_A10_C7_LO],
|
774 |
|
|
cpx_spc_data_cx[`CPX_A01_C7_HI:`CPX_A01_C7_LO],
|
775 |
|
|
cpx_spc_data_cx[`CPX_A00_C7_HI:`CPX_A00_C7_LO]}),
|
776 |
|
|
.sel0 (lsu_cpu_dcd_sel[4]),
|
777 |
|
|
.sel1 (lsu_cpu_dcd_sel[5]),
|
778 |
|
|
.sel2 (lsu_cpu_dcd_sel[6]),
|
779 |
|
|
.sel3 (lsu_cpu_dcd_sel[7]),
|
780 |
|
|
.dout (cpx_cpuhi_dcfill_wrway[13:0])
|
781 |
|
|
);
|
782 |
|
|
|
783 |
|
|
|
784 |
|
|
|
785 |
|
|
mux2ds #(14) st_dcfill_wrway_sel (
|
786 |
|
|
.in0 (cpx_cpulo_dcfill_wrway[13:0]),
|
787 |
|
|
.in1 (cpx_cpuhi_dcfill_wrway[13:0]),
|
788 |
|
|
.sel0 (~lsu_cpu_uhlf_sel),
|
789 |
|
|
.sel1 (lsu_cpu_uhlf_sel),
|
790 |
|
|
.dout (cpx_st_dcfill_wrway_sel[13:0])
|
791 |
|
|
);
|
792 |
|
|
|
793 |
|
|
// select the appropriate offset
|
794 |
|
|
|
795 |
|
|
//bug3718 - 0in bug - cpx_st_dcfill_wrway_sel can be multi-hot foe non-stack cpx responses
|
796 |
|
|
// hence qual w/ stack req type
|
797 |
|
|
wire [3:0] st_dcfill_wrway_mxsel ;
|
798 |
|
|
|
799 |
|
|
assign st_dcfill_wrway_mxsel[0] = (lsu_cpxpkt_type_dcd_cx[2] & cpx_st_dcfill_wrway_sel[0]) & ~rst_tri_en ;
|
800 |
|
|
assign st_dcfill_wrway_mxsel[1] = (lsu_cpxpkt_type_dcd_cx[2] & cpx_st_dcfill_wrway_sel[4]) & ~rst_tri_en ;
|
801 |
|
|
assign st_dcfill_wrway_mxsel[2] = (lsu_cpxpkt_type_dcd_cx[2] & cpx_st_dcfill_wrway_sel[7]) & ~rst_tri_en ;
|
802 |
|
|
assign st_dcfill_wrway_mxsel[3] = ~|st_dcfill_wrway_mxsel[2:0] | rst_tri_en;
|
803 |
|
|
|
804 |
|
|
mux4ds #(2) st_dcfill_wrway_sel_b54 (
|
805 |
|
|
.in0 (cpx_st_dcfill_wrway_sel[3:2]),
|
806 |
|
|
.in1 (cpx_st_dcfill_wrway_sel[6:5]),
|
807 |
|
|
.in2 (cpx_st_dcfill_wrway_sel[10:9]),
|
808 |
|
|
.in3 (cpx_st_dcfill_wrway_sel[13:12]),
|
809 |
|
|
.sel0 (st_dcfill_wrway_mxsel[0]),
|
810 |
|
|
.sel1 (st_dcfill_wrway_mxsel[1]),
|
811 |
|
|
.sel2 (st_dcfill_wrway_mxsel[2]),
|
812 |
|
|
.sel3 (st_dcfill_wrway_mxsel[3]),
|
813 |
|
|
.dout (cpx_st_dcfill_wrway[1:0])
|
814 |
|
|
);
|
815 |
|
|
|
816 |
|
|
|
817 |
|
|
assign cpx_st_ack_addr_b54[0] = cpx_st_dcfill_wrway_sel[4] | cpx_st_dcfill_wrway_sel[11] ;
|
818 |
|
|
assign cpx_st_ack_addr_b54[1] = cpx_st_dcfill_wrway_sel[7] | cpx_st_dcfill_wrway_sel[11] ;
|
819 |
|
|
|
820 |
|
|
//=================================================================================================
|
821 |
|
|
|
822 |
|
|
|
823 |
|
|
//assign store_dfq_pkt[`STB_DFQ_WIDTH-1:0] = stb_dfq_pkt_data[`STB_DFQ_WIDTH-1:0] ;
|
824 |
|
|
|
825 |
|
|
// Items generated/prior to fill cycle (but after DFQ read).
|
826 |
|
|
// This logic will be put in qctl and then be fwded to dcache.
|
827 |
|
|
// - Parity (16b) - load & store.
|
828 |
|
|
// - Byte Enable (16b) - store (8b), ld (16b) all high.
|
829 |
|
|
// - Cache Tag (30b) - obtained from LMQ.
|
830 |
|
|
// - RD1 (5b) - obtained from LMQ.
|
831 |
|
|
// - RD2 (5b) - obtained from LMQ.
|
832 |
|
|
// ** DFQ will contain either loads or inv.
|
833 |
|
|
|
834 |
|
|
// Need to do alignment. Assume dw for now.
|
835 |
|
|
// For a load, a bypass will always happen, a write is
|
836 |
|
|
|
837 |
|
|
// Mux in diagnostic information. Only data is muxed in because
|
838 |
|
|
// all other info is critical
|
839 |
|
|
|
840 |
|
|
wire [63:0] diagnstc_wr_data;
|
841 |
|
|
|
842 |
|
|
dff_s #(64) diagnstc_wr_data_ff (
|
843 |
|
|
.din (lsu_diagnstc_wr_data_e[63:0]),
|
844 |
|
|
.q (diagnstc_wr_data[63:0]),
|
845 |
|
|
.clk (clk),
|
846 |
|
|
.se (1'b0), .si (), .so ()
|
847 |
|
|
);
|
848 |
|
|
|
849 |
|
|
mux2ds #(64) dcwr_sel (
|
850 |
|
|
//.in0 ({store_dfq_pkt[`STB_DFQ_DA_HI:`STB_DFQ_DA_LO]}),
|
851 |
|
|
.in0 ({dfq_byp_ff_data[`STB_DFQ_DA_HI:`STB_DFQ_DA_LO]}),
|
852 |
|
|
.in1 ({diagnstc_wr_data[63:0]}),
|
853 |
|
|
.sel0 ( lsu_dfq_st_vld),
|
854 |
|
|
.sel1 (~lsu_dfq_st_vld),
|
855 |
|
|
//.sel0 (~lsu_diagnstc_wr_src_sel_e),
|
856 |
|
|
//.sel1 ( lsu_diagnstc_wr_src_sel_e),
|
857 |
|
|
.dout (dcache_wr_data[63:0])
|
858 |
|
|
);
|
859 |
|
|
|
860 |
|
|
|
861 |
|
|
// store currently assumed to be dword.
|
862 |
|
|
// st dword is duplicated across 16B.
|
863 |
|
|
// currently assume st and not atomics supported.
|
864 |
|
|
// The width can be reduced !!!
|
865 |
|
|
assign st_dcfill_data[127:0] =
|
866 |
|
|
{ //dfq_byp_ff_data[`STB_DFQ_VLD],
|
867 |
|
|
//2'b00, // need thread-id
|
868 |
|
|
//2'b00,1'b0,5'b00000,
|
869 |
|
|
// dfq_byp_ff_data[84:83], // 131:130 - wr_way[1:0]
|
870 |
|
|
// dfq_byp_ff_data[`STB_DFQ_SZ_HI:`STB_DFQ_SZ_LO], // 129:128 - size[1:0]
|
871 |
|
|
//29'd0, //!!! reduce
|
872 |
|
|
//{dfq_byp_ff_data[`CPX_INV_PA_HI:`CPX_INV_PA_LO], // addr 10:6
|
873 |
|
|
//dfq_byp_ff_data[86:85], // addr 5:4
|
874 |
|
|
//dfq_byp_ff_data[`STB_DFQ_AD_LO+3:`STB_DFQ_AD_LO]}, // addr 3:0
|
875 |
|
|
dcache_wr_data[63:0], // 127:64
|
876 |
|
|
dcache_wr_data[63:0]}; // 63:0
|
877 |
|
|
|
878 |
|
|
assign st_dcfill_addr[10:0] =
|
879 |
|
|
{dfq_byp_ff_data[`CPX_INV_PA_HI:`CPX_INV_PA_LO], // addr 10:6
|
880 |
|
|
dfq_byp_ff_data[86:85], // addr 5:4
|
881 |
|
|
dfq_byp_ff_data[`STB_DFQ_AD_LO+3:`STB_DFQ_AD_LO]}; // addr 3:0
|
882 |
|
|
|
883 |
|
|
// lmq0_pcx_pkt will have to be brought in. Same for lmq_ld_addr
|
884 |
|
|
// The width can be reduced !!!
|
885 |
|
|
|
886 |
|
|
//potentially we can take one cycle earlier version dfq_st_data
|
887 |
|
|
assign lsu_st_way_e[1:0] = dfq_byp_ff_data[84:83];
|
888 |
|
|
assign lsu_st_dcfill_size_e [1:0] = dfq_byp_ff_data[`STB_DFQ_SZ_HI:`STB_DFQ_SZ_LO];
|
889 |
|
|
|
890 |
|
|
assign ldinv_dcfill_data[127:0] =
|
891 |
|
|
{ //1'b0,
|
892 |
|
|
//dfq_byp_ff_data[`DFQ_TH_HI:`DFQ_TH_LO],
|
893 |
|
|
//dfq_byp_ff_data[`DFQ_LD_TYPE:`DFQ_INV_TYPE],
|
894 |
|
|
//1'b1, //assume ld always writes.
|
895 |
|
|
//5'b00000,
|
896 |
|
|
// lmq_ld_way[1:0], // 131:130 - way[1:0]- dfq_byp_ff_data[`DFQ_WY_HI:`DFQ_WY_LO],
|
897 |
|
|
// 2'b0, // 129:128 - size[1:0]- lmq_pcx_pkt_sz[1:0], //!!! reduce
|
898 |
|
|
//40'b0, //lmq_pcx_pkt_addr[39:0], //!!! reduce
|
899 |
|
|
dfq_byp_ff_data[`DFQ_DA_HI:`DFQ_DA_LO]}; // 127:0
|
900 |
|
|
|
901 |
|
|
|
902 |
|
|
// Select between dfq-bypass (ld-inv) and store.
|
903 |
|
|
// *** cpu-id currently hardwired in pkt
|
904 |
|
|
// This may be further restricted in width !!!
|
905 |
|
|
|
906 |
|
|
mux2ds #(128) dfq_pkt_src (
|
907 |
|
|
.in0 (st_dcfill_data[127:0]),
|
908 |
|
|
.in1 (ldinv_dcfill_data[127:0]),
|
909 |
|
|
.sel0 (~lsu_dfq_ld_vld),
|
910 |
|
|
.sel1 (lsu_dfq_ld_vld),
|
911 |
|
|
.dout (lsu_dcfill_data[127:0])
|
912 |
|
|
);
|
913 |
|
|
|
914 |
|
|
// Parity Generation for write data - from load or store.
|
915 |
|
|
wire [15:0] dcache_wr_parity ;
|
916 |
|
|
lsu_dc_parity_gen parity_gen (
|
917 |
|
|
.data_in (lsu_dcfill_data[`DCFILL_DA_HI:`DCFILL_DA_LO]),
|
918 |
|
|
.parity_out (dcache_wr_parity[15:0])
|
919 |
|
|
);
|
920 |
|
|
|
921 |
|
|
// Bug 4125. Corrupt parity if l2 unc err detected. Corrupt both upper and lower half
|
922 |
|
|
// as subsequent read will pick up one of two halves.
|
923 |
|
|
//wire parity_byte0_flip ;
|
924 |
|
|
//wire parity_byte8_flip ;
|
925 |
|
|
wire ld_unc_error ;
|
926 |
|
|
assign ld_unc_error = (dfq_byp_ff_data[138] & dfq_byp_ff_data[`DFQ_WIDTH-1]); // not critical !
|
927 |
|
|
|
928 |
|
|
//bug7021/ECO7022
|
929 |
|
|
//assign parity_byte0_flip = dcache_wr_parity[0] ^ ld_unc_error ;
|
930 |
|
|
//assign parity_byte8_flip = dcache_wr_parity[8] ^ ld_unc_error ;
|
931 |
|
|
|
932 |
|
|
wire [15:0] parity_byte_flip;
|
933 |
|
|
assign parity_byte_flip[15:0] = dcache_wr_parity[15:0] ^ {16{ld_unc_error }};
|
934 |
|
|
|
935 |
|
|
//assign dcache_wr_parity_mod[15:0] =
|
936 |
|
|
// lsu_diagnstc_wr_src_sel_e ?
|
937 |
|
|
// ({lsu_diagnstc_dc_prty_invrt_e[7:0],lsu_diagnstc_dc_prty_invrt_e[7:0]} ^ dcache_wr_parity[15:0]) :
|
938 |
|
|
// dcache_wr_parity[15:0] ;
|
939 |
|
|
|
940 |
|
|
wire [15:0] diagnstc_wr_parity;
|
941 |
|
|
|
942 |
|
|
assign diagnstc_wr_parity[15:0] = {lsu_diagnstc_dc_prty_invrt_e[7:0],lsu_diagnstc_dc_prty_invrt_e[7:0]} ^ dcache_wr_parity[15:0];
|
943 |
|
|
|
944 |
|
|
mux2ds #(16) dcache_wr_parity_mod_mux (
|
945 |
|
|
.in0(diagnstc_wr_parity[15:0]),
|
946 |
|
|
// .in1({dcache_wr_parity[15:9],parity_byte8_flip,dcache_wr_parity[7:1],parity_byte0_flip}),
|
947 |
|
|
.in1(parity_byte_flip[15:0]), //bug7021/ECO7022
|
948 |
|
|
.sel0(~lsu_dfq_ldst_vld),
|
949 |
|
|
.sel1( lsu_dfq_ldst_vld),
|
950 |
|
|
//.sel0(lsu_diagnstc_wr_src_sel_e),
|
951 |
|
|
//.sel1(~lsu_diagnstc_wr_src_sel_e),
|
952 |
|
|
.dout(dcache_wr_parity_mod[15:0])
|
953 |
|
|
);
|
954 |
|
|
|
955 |
|
|
|
956 |
|
|
// Bist read and write address sent thru fill_addr
|
957 |
|
|
//assign lsu_dcache_fill_addr_e[10:0] =
|
958 |
|
|
//lsu_dc_iob_access_e ? {dcache_iob_addr_e[7:0],2'b00} :
|
959 |
|
|
//(lsu_bist_wvld_e | lsu_bist_rvld_e) ? {1'b0, lsu_bist_addr_e[7:0],2'b00} : //??FIX
|
960 |
|
|
// lsu_diagnstc_wr_src_sel_e ? lsu_diagnstc_wr_addr_e[10:0] :
|
961 |
|
|
// lsu_dcfill_data[`DCFILL_AD_LO+10:`DCFILL_AD_LO];
|
962 |
|
|
|
963 |
|
|
// wire [10:0] lsu_dcache_fill_addr_e;
|
964 |
|
|
|
965 |
|
|
//mux4ds #(11) lsu_dcache_fill_addr_e_mux (
|
966 |
|
|
// .in0 ({dcache_iob_addr_e[8:0],2'b00}),
|
967 |
|
|
// .in1 ({mbist_dcache_index[6:0], mbist_dcache_word, 3'b00}),
|
968 |
|
|
// .in2 (lsu_diagnstc_wr_addr_e[10:0]),
|
969 |
|
|
// .in3 (lsu_dcfill_data[`DCFILL_AD_LO+10:`DCFILL_AD_LO]),
|
970 |
|
|
// .sel0 (lsu_dcfill_mx_sel_e[0]),
|
971 |
|
|
// .sel1 (lsu_dcfill_mx_sel_e[1]),
|
972 |
|
|
// .sel2 (lsu_dcfill_mx_sel_e[2]),
|
973 |
|
|
// .sel3 (lsu_dcfill_mx_sel_e[3]),
|
974 |
|
|
// .dout (lsu_dcache_fill_addr_e[10:0])
|
975 |
|
|
//);
|
976 |
|
|
|
977 |
|
|
wire [63:0] misc_fill_data_e ;
|
978 |
|
|
// Use smaller width mux to save area.
|
979 |
|
|
//assign misc_fill_data_e[63:0] =
|
980 |
|
|
//lsu_dc_iob_access_e ? dcache_iob_data_e[63:0] :
|
981 |
|
|
// {32{lsu_bist_wdata_e[1:0]}} ;
|
982 |
|
|
|
983 |
|
|
wire [7:0] mbist_write_data_d1;
|
984 |
|
|
|
985 |
|
|
dff_s #(8) mbist_write_data_ff (
|
986 |
|
|
.din (mbist_write_data[7:0]),
|
987 |
|
|
.q (mbist_write_data_d1[7:0]),
|
988 |
|
|
.clk (clk),
|
989 |
|
|
.se (1'b0), .si (), .so ()
|
990 |
|
|
);
|
991 |
|
|
|
992 |
|
|
|
993 |
|
|
wire [3:0] misc_fill_parity_e;
|
994 |
|
|
assign misc_fill_parity_e[3:0] = {4{~lsu_dc_iob_access_e}} & mbist_write_data_d1[3:0];
|
995 |
|
|
|
996 |
|
|
mux2ds #(64) misc_fill_data_e_mux (
|
997 |
|
|
.in0(dcache_iob_data_e[63:0]),
|
998 |
|
|
.in1({8{mbist_write_data_d1[7:0]}}),
|
999 |
|
|
.sel0(lsu_dc_iob_access_e),
|
1000 |
|
|
.sel1(~lsu_dc_iob_access_e),
|
1001 |
|
|
.dout(misc_fill_data_e[63:0])
|
1002 |
|
|
);
|
1003 |
|
|
|
1004 |
|
|
mux2ds #(144) lsu_dcache_fill_data_e_mux (
|
1005 |
|
|
.in0({misc_fill_data_e[63:0],misc_fill_data_e[63:0],{4{misc_fill_parity_e[3:0]}}}),
|
1006 |
|
|
.in1({lsu_dcfill_data[`DCFILL_DA_HI:`DCFILL_DA_LO],dcache_wr_parity_mod[15:0]}),
|
1007 |
|
|
.sel0(lsu_dcfill_data_mx_sel_e),
|
1008 |
|
|
.sel1(~lsu_dcfill_data_mx_sel_e),
|
1009 |
|
|
.dout(lsu_dcache_fill_data_e[143:0])
|
1010 |
|
|
);
|
1011 |
|
|
|
1012 |
|
|
//assign lsu_dcache_fill_size_e[1:0] =
|
1013 |
|
|
//(lsu_dc_iob_access_e | lsu_bist_wvld_e | lsu_diagnstc_wr_src_sel_e) ? 2'b11 :
|
1014 |
|
|
// lsu_dcfill_data[`DCFILL_SZ_HI:`DCFILL_SZ_LO] ;
|
1015 |
|
|
|
1016 |
|
|
|
1017 |
|
|
|
1018 |
|
|
// wire [1:0] bist_way_e;
|
1019 |
|
|
|
1020 |
|
|
//assign bist_way_e[1:0] = (lsu_bist_rvld_e | lsu_bist_wvld_e) ?
|
1021 |
|
|
// mbist_dcache_way[1:0] : 2'b00;
|
1022 |
|
|
|
1023 |
|
|
//assign bist_rsel_way_e[0] = ~bist_way_e[1] & ~bist_way_e[0] ;
|
1024 |
|
|
//assign bist_rsel_way_e[1] = ~bist_way_e[1] & bist_way_e[0] ;
|
1025 |
|
|
//assign bist_rsel_way_e[2] = bist_way_e[1] & ~bist_way_e[0] ;
|
1026 |
|
|
//assign bist_rsel_way_e[3] = bist_way_e[1] & bist_way_e[0] ;
|
1027 |
|
|
|
1028 |
|
|
// assign lsu_bist_rsel_way_e[3:0] = bist_rsel_way_e[3:0];
|
1029 |
|
|
|
1030 |
|
|
|
1031 |
|
|
// This staging may have to go elsewhere
|
1032 |
|
|
//always @(posedge clk)
|
1033 |
|
|
// begin
|
1034 |
|
|
// bist_rsel_way_m[3:0] <= bist_rsel_way_e[3:0] ;
|
1035 |
|
|
// end
|
1036 |
|
|
|
1037 |
|
|
//always @(posedge clk)
|
1038 |
|
|
// begin
|
1039 |
|
|
// lsu_bist_rsel_way_wb[3:0] <= bist_rsel_way_m[3:0] ;
|
1040 |
|
|
// end
|
1041 |
|
|
|
1042 |
|
|
//dff #(4) bist_rsel_way_m_ff (
|
1043 |
|
|
// .din (bist_rsel_way_e[3:0]),
|
1044 |
|
|
// .q (bist_rsel_way_m[3:0]),
|
1045 |
|
|
// .clk (clk),
|
1046 |
|
|
// .se (1'b0), .si (), .so ()
|
1047 |
|
|
// );
|
1048 |
|
|
|
1049 |
|
|
//dff #(4) lsu_bist_rsel_way_wb_ff (
|
1050 |
|
|
// .din (bist_rsel_way_m[3:0]),
|
1051 |
|
|
// .q (lsu_bist_rsel_way_wb[3:0]),
|
1052 |
|
|
// .clk (clk),
|
1053 |
|
|
// .se (1'b0), .si (), .so ()
|
1054 |
|
|
// );
|
1055 |
|
|
|
1056 |
|
|
//assign lsu_dcache_fill_way_e[0] =
|
1057 |
|
|
//lsu_dc_iob_access_e ? dcache_iob_wy_e[0] :
|
1058 |
|
|
// (lsu_bist_wvld_e | lsu_bist_rvld_e) ? bist_rsel_way_e[0] :
|
1059 |
|
|
// lsu_diagnstc_wr_src_sel_e ? lsu_diagnstc_wr_way_e[0] :
|
1060 |
|
|
// ~lsu_dcfill_data[`DCFILL_WY_HI] & ~lsu_dcfill_data[`DCFILL_WY_LO] ;
|
1061 |
|
|
//assign lsu_dcache_fill_way_e[1] =
|
1062 |
|
|
//lsu_dc_iob_access_e ? dcache_iob_wy_e[1] :
|
1063 |
|
|
// (lsu_bist_wvld_e | lsu_bist_rvld_e) ? bist_rsel_way_e[1] :
|
1064 |
|
|
// lsu_diagnstc_wr_src_sel_e ? lsu_diagnstc_wr_way_e[1] :
|
1065 |
|
|
// ~lsu_dcfill_data[`DCFILL_WY_HI] & lsu_dcfill_data[`DCFILL_WY_LO] ;
|
1066 |
|
|
//assign lsu_dcache_fill_way_e[2] =
|
1067 |
|
|
//lsu_dc_iob_access_e ? dcache_iob_wy_e[2] :
|
1068 |
|
|
// (lsu_bist_wvld_e | lsu_bist_rvld_e) ? bist_rsel_way_e[2] :
|
1069 |
|
|
// lsu_diagnstc_wr_src_sel_e ? lsu_diagnstc_wr_way_e[2] :
|
1070 |
|
|
// lsu_dcfill_data[`DCFILL_WY_HI] & ~lsu_dcfill_data[`DCFILL_WY_LO] ;
|
1071 |
|
|
//assign lsu_dcache_fill_way_e[3] =
|
1072 |
|
|
//lsu_dc_iob_access_e ? dcache_iob_wy_e[3] :
|
1073 |
|
|
// (lsu_bist_wvld_e | lsu_bist_rvld_e) ? bist_rsel_way_e[3] :
|
1074 |
|
|
// lsu_diagnstc_wr_src_sel_e ? lsu_diagnstc_wr_way_e[3] :
|
1075 |
|
|
// lsu_dcfill_data[`DCFILL_WY_HI] & lsu_dcfill_data[`DCFILL_WY_LO] ;
|
1076 |
|
|
|
1077 |
|
|
/*
|
1078 |
|
|
mux4ds #(1) lsu_dcache_fill_way0_e_mux (
|
1079 |
|
|
.in0 (dcache_iob_wy_e[0]),
|
1080 |
|
|
.in1 (bist_rsel_way_e[0]),
|
1081 |
|
|
.in2 (lsu_diagnstc_wr_way_e[0]),
|
1082 |
|
|
.in3 (~lsu_dcfill_data[131] & ~lsu_dcfill_data[130]),
|
1083 |
|
|
.sel0 (lsu_dcfill_mx_sel_e[0]),
|
1084 |
|
|
.sel1 (lsu_dcfill_mx_sel_e[1]),
|
1085 |
|
|
.sel2 (lsu_dcfill_mx_sel_e[2]),
|
1086 |
|
|
.sel3 (lsu_dcfill_mx_sel_e[3]),
|
1087 |
|
|
.dout (lsu_dcache_fill_way_e[0]));
|
1088 |
|
|
|
1089 |
|
|
mux4ds #(1) lsu_dcache_fill_way1_e_mux (
|
1090 |
|
|
.in0 (dcache_iob_wy_e[1]),
|
1091 |
|
|
.in1 (bist_rsel_way_e[1]),
|
1092 |
|
|
.in2 (lsu_diagnstc_wr_way_e[1]),
|
1093 |
|
|
.in3 (~lsu_dcfill_data[131] & lsu_dcfill_data[130]),
|
1094 |
|
|
.sel0 (lsu_dcfill_mx_sel_e[0]),
|
1095 |
|
|
.sel1 (lsu_dcfill_mx_sel_e[1]),
|
1096 |
|
|
.sel2 (lsu_dcfill_mx_sel_e[2]),
|
1097 |
|
|
.sel3 (lsu_dcfill_mx_sel_e[3]),
|
1098 |
|
|
.dout (lsu_dcache_fill_way_e[1]));
|
1099 |
|
|
|
1100 |
|
|
mux4ds #(1) lsu_dcache_fill_way2_e_mux (
|
1101 |
|
|
.in0 (dcache_iob_wy_e[2]),
|
1102 |
|
|
.in1 (bist_rsel_way_e[2]),
|
1103 |
|
|
.in2 (lsu_diagnstc_wr_way_e[2]),
|
1104 |
|
|
.in3 ( lsu_dcfill_data[131] & ~lsu_dcfill_data[130]),
|
1105 |
|
|
.sel0 (lsu_dcfill_mx_sel_e[0]),
|
1106 |
|
|
.sel1 (lsu_dcfill_mx_sel_e[1]),
|
1107 |
|
|
.sel2 (lsu_dcfill_mx_sel_e[2]),
|
1108 |
|
|
.sel3 (lsu_dcfill_mx_sel_e[3]),
|
1109 |
|
|
.dout (lsu_dcache_fill_way_e[2]));
|
1110 |
|
|
|
1111 |
|
|
|
1112 |
|
|
mux4ds #(1) lsu_dcache_fill_way3_e_mux (
|
1113 |
|
|
.in0 (dcache_iob_wy_e[3]),
|
1114 |
|
|
.in1 (bist_rsel_way_e[3]),
|
1115 |
|
|
.in2 (lsu_diagnstc_wr_way_e[3]),
|
1116 |
|
|
.in3 ( lsu_dcfill_data[131] & lsu_dcfill_data[130]),
|
1117 |
|
|
.sel0 (lsu_dcfill_mx_sel_e[0]),
|
1118 |
|
|
.sel1 (lsu_dcfill_mx_sel_e[1]),
|
1119 |
|
|
.sel2 (lsu_dcfill_mx_sel_e[2]),
|
1120 |
|
|
.sel3 (lsu_dcfill_mx_sel_e[3]),
|
1121 |
|
|
.dout (lsu_dcache_fill_way_e[3]));
|
1122 |
|
|
*/
|
1123 |
|
|
// assign lsu_dcache_fill_way_enc_e[0] = lsu_dcache_fill_way_e[1] | lsu_dcache_fill_way_e[3];
|
1124 |
|
|
// assign lsu_dcache_fill_way_enc_e[1] = lsu_dcache_fill_way_e[2] | lsu_dcache_fill_way_e[3];
|
1125 |
|
|
|
1126 |
|
|
wire [63:0] l2fill_data_e;
|
1127 |
|
|
|
1128 |
|
|
mux2ds #(64) half_sel (
|
1129 |
|
|
.in0 (lsu_dcfill_data[`DCFILL_DA_HI:`DCFILL_DA_LO+64]),
|
1130 |
|
|
.in1 (lsu_dcfill_data[`DCFILL_DA_LO+63:`DCFILL_DA_LO]),
|
1131 |
|
|
.sel0 (lsu_dfill_data_sel_hi), .sel1 (~lsu_dfill_data_sel_hi),
|
1132 |
|
|
.dout (l2fill_data_e[63:0])
|
1133 |
|
|
);
|
1134 |
|
|
|
1135 |
|
|
dff_s #(64) stgm_l2fd (
|
1136 |
|
|
.din (l2fill_data_e[63:0]),
|
1137 |
|
|
.q (lsu_l2fill_data[63:0]),
|
1138 |
|
|
.clk (clk),
|
1139 |
|
|
.se (se), .si (), .so ()
|
1140 |
|
|
);
|
1141 |
|
|
|
1142 |
|
|
endmodule
|