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// ========== Copyright Header Begin ==========================================

// 

// OpenSPARC T1 Processor File: lsu_stb_rwctl.v

// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

// 

// The above named program is free software; you can redistribute it and/or

// modify it under the terms of the GNU General Public

// License version 2 as published by the Free Software Foundation.

// 

// The above named program is distributed in the hope that it will be 

// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

// General Public License for more details.

// 

// You should have received a copy of the GNU General Public

// License along with this work; if not, write to the Free Software

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// 

// ========== Copyright Header End ============================================

///////////////////////////////////////////////////////////////////

/*

//  Description:  Control for Unified STB CAM/DATA of LSU

*/

////////////////////////////////////////////////////////////////////////

// Global header file includes

////////////////////////////////////////////////////////////////////////

`include  "sys.h" // system level definition file which contains the 

          // time scale definition

`include "iop.h"

////////////////////////////////////////////////////////////////////////

// Local header file includes / local defines

////////////////////////////////////////////////////////////////////////

module lsu_stb_rwctl (/*AUTOARG*/

   // Outputs

   so, lsu_stbctl_flush_pipe_w, stb_cam_wr_no_ivld_m,

   ld_rawp_st_ced_w2, stb_data_wr_ptr, stb_data_wptr_vld,

   stb_data_rd_ptr, stb_data_rptr_vld, stb_wdata_ramd_b75_b64,

   stb_cam_cm_tid, stb_ldst_byte_msk, stb_ldst_byte_msk_min,

   stb_cam_rw_ptr, stb_cam_wptr_vld, stb_cam_rptr_vld,

   lsu_st_sz_bhww_m, lsu_st_sz_dw_m, lsu_st_sz_bhw_m,

   lsu_st_sz_wdw_m, lsu_st_sz_b_m, lsu_st_sz_w_m, lsu_st_sz_hw_m,

   lsu_st_sz_hww_m, ld_rawp_st_ackid_w2, stb_flush_st_g,

   stb_cam_wvld_m, lsu_st_rq_type_m, lsu_stb_data_early_sel_e,

   lsu_stb_data_final_sel_m, lsu_ldquad_inst_m, stb_thrd_en_g,

   flsh_inst_m, lsu_stb_va_m, lsu_stb_empty_buf, lsu_spu_stb_empty,

   ifu_tlu_inst_vld_m_bf1, ifu_tlu_inst_vld_m_bf2, lsu_ifu_stbcnt0,

   lsu_ifu_stbcnt1, lsu_ifu_stbcnt2, lsu_ifu_stbcnt3,

   lsu_ffu_stb_full0, lsu_ffu_stb_full1, lsu_ffu_stb_full2,

   lsu_ffu_stb_full3,

   // Inputs

   rclk, rst_tri_en, si, se, ld_inst_vld_e, ldst_sz_e, st_inst_vld_e,

   stb_pcx_rptr0, stb_wrptr0, stb_pcx_rptr1, stb_wrptr1,

   stb_pcx_rptr2, stb_wrptr2, stb_pcx_rptr3, stb_wrptr3,

   stb_cam_hit_ptr, stb_cam_hit, lsu_ldst_va_m, sta_internal_m,

   ifu_tlu_thrid_e, tlu_exu_early_flush_pipe_w, lsu_ttype_vld_m2,

   ifu_lsu_flush_w, lsu_defr_trp_taken_g, ifu_lsu_casa_e,

   ifu_lsu_ldstub_e, ifu_lsu_swap_e, ifu_lsu_ldst_dbl_e,

   stb_state_ced0, stb_state_ced1, stb_state_ced2, stb_state_ced3,

   stb_ld_full_raw, stb_ld_partial_raw, stb_wrptr0_prev,

   stb_wrptr1_prev, stb_wrptr2_prev, stb_wrptr3_prev,

   ifu_lsu_alt_space_e, ifu_lsu_ldst_fp_e, lsu_quad_asi_e,

   lsu_st_rmo_m, lsu_bst_in_pipe_m, ffu_lsu_kill_fst_w,

   ffu_lsu_blk_st_e, ffu_lsu_blk_st_tid_m, ffu_lsu_blk_st_va_e,

   lsu_snap_blk_st_m, tlb_pgnum_b39_g, lsu_stb_empty,

   ifu_tlu_flsh_inst_e, stb_cam_mhit, ifu_tlu_inst_vld_m,

   lsu_st_pcx_rq_pick, lsu_st_pcx_rq_vld, stb_rdata_ramc_b8t0,

   lsu_stbcnt0, lsu_stbcnt1, lsu_stbcnt2, lsu_stbcnt3

   ) ;

input     rclk ;

//input     grst_l ;   

//input     arst_l ;   

   input  rst_tri_en;

   input  si;

   input  se;

   output so;

input     ld_inst_vld_e ;   // load in pipe.

input [1:0]   ldst_sz_e ;   // size of load.

input     st_inst_vld_e ;   // store in pipe.

// Currently bypass flop make request 

//input [3:0]   pcx_rq_for_stb ;  // pcx request rd of dfq - threaded

//input [2:0]   stb_dfq_rptr0 ;   // dfq rptr for stb0

input [2:0]   stb_pcx_rptr0 ;   // pcx rptr for stb0

input [2:0]   stb_wrptr0 ;    // wrt ptr - stb0

//input [2:0]   stb_dfq_rptr1 ;   // dfq rptr for stb1

input [2:0]   stb_pcx_rptr1 ;   // pcx rptr for stb1

input [2:0]   stb_wrptr1 ;    // wrt ptr - stb1

//input [2:0]   stb_dfq_rptr2 ;   // dfq rptr for stb2

input [2:0]   stb_pcx_rptr2 ;   // pcx rptr for stb2

input [2:0]   stb_wrptr2 ;    // wrt ptr - stb2

//input [2:0]   stb_dfq_rptr3 ;   // dfq rptr for stb3

input [2:0]   stb_pcx_rptr3 ;   // pcx rptr for stb3

input [2:0]   stb_wrptr3 ;    // wrt ptr - stb3

input [2:0]     stb_cam_hit_ptr ; // entry which hit

input     stb_cam_hit ;   // hit has occurred

//input [7:0]     stb_state_vld0 ;  // valid bits - stb0

//input [7:0]     stb_state_vld1 ;  // valid bits - stb1

//input [7:0]     stb_state_vld2 ;  // valid bits - stb2

//input [7:0]     stb_state_vld3 ;  // valid bits - stb3

input [9:0]    lsu_ldst_va_m ;

input     sta_internal_m ;   // internal stxa

input [1:0]   ifu_tlu_thrid_e ; // thread-id.

//   output     lsu_stbrwctl_flush_pipe_w ;  // tmp for tso_mon

   input      tlu_exu_early_flush_pipe_w;

   input      lsu_ttype_vld_m2;

   input      ifu_lsu_flush_w;

   input      lsu_defr_trp_taken_g;

   output     lsu_stbctl_flush_pipe_w;

input                   ifu_lsu_casa_e ;        // compare-swap instr

input                   ifu_lsu_ldstub_e ;      // ldstub

input                   ifu_lsu_swap_e ;        // swap

input     ifu_lsu_ldst_dbl_e; // ldst dbl, specifically for stquad.

//input   [63:0]          lsu_stb_st_data_g ;     // data to be written to stb

input [7:0]   stb_state_ced0 ;

input [7:0]   stb_state_ced1 ;

input [7:0]   stb_state_ced2 ;

input [7:0]   stb_state_ced3 ;

input [7:0]   stb_ld_full_raw ;

input [7:0]   stb_ld_partial_raw ;

input   [2:0]   stb_wrptr0_prev ;

input   [2:0]   stb_wrptr1_prev ;

input   [2:0]     stb_wrptr2_prev ;

input   [2:0]   stb_wrptr3_prev ;

input     ifu_lsu_alt_space_e ; // alt_space inst

input     ifu_lsu_ldst_fp_e ;

//input     tlb_cam_hit ;   // tlb cam hit - mstage

input     lsu_quad_asi_e ;  // quad ldst asi

//input  [3:0]      lsu_st_ack_rq_stb ;

//input     lsu_dtlb_bypass_e ;

input   lsu_st_rmo_m ;  // rmo st in m cycle.

input   lsu_bst_in_pipe_m ;     // 1st helper for bst.

input           ffu_lsu_kill_fst_w ;    // ecc error on st.

input           ffu_lsu_blk_st_e ;      // blk st helper signalled by ffu

input   [1:0]    ffu_lsu_blk_st_tid_m ;  // blk st tid - from ffu_lsu_data

input   [5:3]   ffu_lsu_blk_st_va_e ;   // bits 5:3 of va from increment

input           lsu_snap_blk_st_m ;             // snap blk st state

input           tlb_pgnum_b39_g ;

input   [3:0]   lsu_stb_empty ;         // thread's stb is empty

input           ifu_tlu_flsh_inst_e;

input           stb_cam_mhit ;

input           ifu_tlu_inst_vld_m ;

//input   [3:0]   lsu_st_pcx_rq_kill_w2 ;

input [3:0]   lsu_st_pcx_rq_pick ;

input         lsu_st_pcx_rq_vld ;

input   [8:0]    stb_rdata_ramc_b8t0 ;   // scan-only

output          stb_cam_wr_no_ivld_m ;

//output      ld_rawp_st_ced_g ;

output      ld_rawp_st_ced_w2 ;

output  [4:0]   stb_data_wr_ptr ; // write ptr - stb data

output      stb_data_wptr_vld ; // wr vld for stb data

output  [4:0]   stb_data_rd_ptr ; // rd ptr for stb data

output      stb_data_rptr_vld ; // rptr vld for stb data

output  [75:64]    stb_wdata_ramd_b75_b64 ;  // write data for DATA RAM. 

// partial or full raw required

output  [1:0]   stb_cam_cm_tid ;  // cam tid - stb cam

//output  [7:0]   stb_cam_sqsh_msk ;  // squash spurious hits

//output      stb_cam_vld ;

output  [7:0]   stb_ldst_byte_msk ; // byte mask for write/cam

output  [7:0]   stb_ldst_byte_msk_min ; // byte mask for write/cam for min path

//output  [3:0]   stb_rd_for_pcx_sel ;    // stb's st selected for read for pcx

output  [4:0]   stb_cam_rw_ptr ;        // rw ptr for shared stb cam port

output          stb_cam_wptr_vld ;      // wr vld for stb write   

output          stb_cam_rptr_vld ;      // rd vld for stb write   

//output      lsu_stb_pcx_rvld_d1 ; // stb has been read-delayby1cycle

//output      lsu_stb_dfq_rvld ;  // wr to dfq stb bypass ff

output                  lsu_st_sz_bhww_m ;      // byte or hword or word

output                  lsu_st_sz_dw_m ;        // double word

output                  lsu_st_sz_bhw_m ;       // byte or hword

output                  lsu_st_sz_wdw_m ;       // word or dword

output                  lsu_st_sz_b_m ;         // byte

output                  lsu_st_sz_w_m ;         // word

output                  lsu_st_sz_hw_m ;        // hword

output                  lsu_st_sz_hww_m ;       // hword or word

//output     ld_stb_full_raw_g ;

//output     ld_stb_partial_raw_g ;

//output  [3:0]   ld_stb_full_raw_g ;

//output  [3:0]   ld_stb_partial_raw_g ;

output  [2:0]   ld_rawp_st_ackid_w2 ;

//output  [2:0]   stb_dfq_rd_id ;   // stb entry being read for current thread for current thread

output  [3:0]     stb_flush_st_g ;  // st is flushed in cycle g

output  [3:0]     stb_cam_wvld_m ;

output  [2:1]   lsu_st_rq_type_m ;

output  [3:0]   lsu_stb_data_early_sel_e ;// select source of stb data.

output      lsu_stb_data_final_sel_m ;// select source of stb data.

output      lsu_ldquad_inst_m ; // stquad inst

//output      lsu_stdbl_inst_m ;  // stdbl inst

//output  [1:0]   lsu_stb_rd_tid ;  // thread for which stb read occurs

output  [3:0]    stb_thrd_en_g ; // thread id for current stb access

   output     flsh_inst_m;

   output [9:3] lsu_stb_va_m;

output  [3:0]    lsu_stb_empty_buf ;

output  [3:0]    lsu_spu_stb_empty ;

   output     ifu_tlu_inst_vld_m_bf1;

   output     ifu_tlu_inst_vld_m_bf2;

   input [3:0] lsu_stbcnt0;

   input [3:0] lsu_stbcnt1;

   input [3:0] lsu_stbcnt2;

   input [3:0] lsu_stbcnt3;

   output [3:0] lsu_ifu_stbcnt0;

   output [3:0] lsu_ifu_stbcnt1;

   output [3:0] lsu_ifu_stbcnt2;

   output [3:0] lsu_ifu_stbcnt3;

   output       lsu_ffu_stb_full0;

   output       lsu_ffu_stb_full1;

   output       lsu_ffu_stb_full2;

   output       lsu_ffu_stb_full3;

/*AUTOWIRE*/

// Beginning of automatic wires (for undeclared instantiated-module outputs)

// End of automatics

// Beginning of automatic wires (for undeclared instantiated-module outputs)

// End of automatics

//wire  [4:0] stb_dequeue_ptr ;

wire  [2:0] stb_wptr_prev ;

wire  [1:0] st_thrid_m,st_thrid_g ;

wire  [7:0] ld_any_raw_vld ;

wire  [7:0] ld_any_raw_vld_d1 ;

//wire    ld_raw_mhit ;

wire  [2:0] st_rq_type_m,st_rq_type_g ;

wire  [1:0] ldst_sz_m,ldst_sz_g, pipe_ldst_sz_m ;

wire    ldst_byte, ldst_hwrd, ldst_word, ldst_dwrd ;

wire  [7:0] ldst_byte_mask ;

wire  [2:0] stb_wptr ;

wire  [1:0] thrid_m,thrid_g ;

wire    ld_inst_vld_m, st_inst_vld_m ;

wire    ldst_dbl_m;

wire    atomic_m ;

wire    ldstub_m ;

wire    casa_m, casa_g ;

wire    swap_m;

wire    flush_st_g ;

wire    cam_wptr_vld_g ;

wire  [2:0] cam_wptr_d1 ;

wire  [2:0] stb_rdptr0,stb_rdptr1 ;

wire  [2:0] stb_rdptr2,stb_rdptr3 ;

//wire  [3:0] stb_rd_mask ;

wire  [3:0] stb_select_rptr ;

wire  [1:0] stb_rd_thrid ;

//wire    cam_vld_g ;

wire  [9:0]  ldst_va_m, pipe_ldst_va_m ;

wire  [3:0]  ldst_va_g ;

wire  [2:0] cam_wr_ptr ;

wire  thread0_m, thread1_m, thread2_m, thread3_m ;

wire  thread0_g, thread1_g, thread2_g, thread3_g ;

wire  [2:0]   ld_rawp_stb_id ;

//wire  rd_for_dfq_granted ;

wire  [7:0] stb_state_ced,stb_state_ced_d1 ;

//wire    stq_wr_en ;

//wire  [3:0] stq_wr_en_g ;

//wire  [3:0] stquad_vld ;

//wire  [2:0] stquad_ptr0,stquad_ptr1,stquad_ptr2,stquad_ptr3 ;

//wire  [3:0] ld_stq_hit_g ;

//wire  ldq_hit_g ;

//wire  [3:0] ldq_hit_g ;

wire  ldst_fp_m;

wire  ldstub_e,casa_e,ldst_dbl_e;

//wire  stb_data_final_sel_e ;

wire  alt_space_e,alt_space_m ;

wire  quad_asi_m ;

//wire  stquad_e, stquad_m ;

wire  stdbl_e ;

//wire  dfq_any_rq_for_stb ;

//wire  [3:0]   stb_rd_for_dfq ;  // read rq for dfq - threaded

wire    blkst_m,blkst_g ;

wire    stb_not_empty ;

   wire       clk;

   assign     clk = rclk;

//   wire       rst_l;

//   wire       stb_rwctl_rst_l;

//   dffrl_async rstff(.din (grst_l),

//                     .q   (stb_rwctl_rst_l),

//                     .clk (clk), .se(se), .si(), .so(),

//                     .rst_l (arst_l));

//=========================================================================================

//  MISC

//=========================================================================================

// Scan-only flops.

wire    [8:0]    stb_rdata_ramc_b8t0_so ;

dff_s #(9)  scmscan_ff (

        .din    (stb_rdata_ramc_b8t0[8:0]),

        .q      (stb_rdata_ramc_b8t0_so[8:0]),

        .clk    (clk),

        .se   (se),       .si (),          .so ()

        );

//=========================================================================================

//  INST_VLD_W GENERATION

//=========================================================================================

wire    flush_w_inst_vld_m ;

wire    lsu_inst_vld_w ;

wire    lsu_stbrwctl_flush_pipe_w;

//=======================================

//instaniate buffers

//======================================

   wire   ifu_tlu_inst_vld_m_bf0;

bw_u1_buf_10x UZfix_ifu_tlu_inst_vld_m_bf0 ( .a(ifu_tlu_inst_vld_m), .z(ifu_tlu_inst_vld_m_bf0) );

bw_u1_buf_30x UZfix_ifu_tlu_inst_vld_m_bf1 ( .a(ifu_tlu_inst_vld_m_bf0), .z(ifu_tlu_inst_vld_m_bf1) );

bw_u1_buf_20x UZfix_ifu_tlu_inst_vld_m_bf2 ( .a(ifu_tlu_inst_vld_m_bf0), .z(ifu_tlu_inst_vld_m_bf2) );

assign  flush_w_inst_vld_m =

        ifu_tlu_inst_vld_m_bf0 &

        ~(lsu_stbrwctl_flush_pipe_w & (thrid_m[1:0] == thrid_g[1:0])) ; // really lsu_flush_pipe_w

dff_s  stgw_ivld (

        .din    (flush_w_inst_vld_m),

        .q      (lsu_inst_vld_w),

        .clk    (clk),

        .se   (se),       .si (),          .so ()

        );

   wire other_flush_pipe_w;

   wire tlu_early_flush_pipe_w;

   assign tlu_early_flush_pipe_w = tlu_exu_early_flush_pipe_w;

assign  other_flush_pipe_w =

tlu_early_flush_pipe_w | (lsu_ttype_vld_m2 & lsu_inst_vld_w) |

lsu_defr_trp_taken_g ;

   wire lsu_flush_pipe_w;

assign  lsu_flush_pipe_w = other_flush_pipe_w | ifu_lsu_flush_w ;

assign  lsu_stbctl_flush_pipe_w = lsu_flush_pipe_w ;

assign  lsu_stbrwctl_flush_pipe_w = lsu_flush_pipe_w ;

//=========================================================================================

//  STB Array Addr/Ctl Generation

//=========================================================================================

assign  ldstub_e = ifu_lsu_ldstub_e ;

assign  casa_e   = ifu_lsu_casa_e ;

assign  ldst_dbl_e = ifu_lsu_ldst_dbl_e ;

assign  alt_space_e = ifu_lsu_alt_space_e ;

//assign  stdbl_e =  ldst_dbl_e & (~alt_space_e | (alt_space_e & ~lsu_quad_asi_e)) ;

assign  stdbl_e =  ldst_dbl_e ;

//   wire lsu_stdbl_inst_m;

//dff  stq_stgm (

//  .din  (stdbl_e), 

//  .q          (lsu_stdbl_inst_m),  

//  .clk  (clk), 

//  .se (se), .si (), .so ()

//  );

// This path can probably be eased.

assign  lsu_stb_data_early_sel_e[0] = ldstub_e  & ~rst_tri_en;

assign  lsu_stb_data_early_sel_e[1] = casa_e & ~rst_tri_en;

assign  lsu_stb_data_early_sel_e[2] = ~(ldstub_e | casa_e |  stdbl_e) | rst_tri_en;

assign  lsu_stb_data_early_sel_e[3] = stdbl_e & ~rst_tri_en ;

// modify for accepting bst data out of pipe.

//assign  stb_data_final_sel_e = ~(ldst_fp_e | ffu_lsu_blk_st_e) ;

/*dff  lsel_g (

  .din  (stb_data_final_sel_e),

  .q  (lsu_stb_data_final_sel_m),

  .clk  (clk),

  .se (se), .si (), .so ()

  );*/

assign  lsu_stb_data_final_sel_m = ~(ldst_fp_m | blkst_m) ;

wire    real_st_m ;

wire    flsh_inst_m, flsh_inst_g ;

// !!! could qualify st_inst_vld_e with stxa_internal !!!

dff_s #(13) stgm_vld  (

  .din  ({ld_inst_vld_e,st_inst_vld_e,ldst_sz_e[1:0],

    ifu_lsu_swap_e, ifu_lsu_ldstub_e, ifu_lsu_casa_e,ifu_lsu_ldst_dbl_e,

    ifu_tlu_thrid_e[1:0],ifu_lsu_ldst_fp_e,lsu_quad_asi_e,ifu_tlu_flsh_inst_e}),

  .q  ({ld_inst_vld_m,real_st_m,pipe_ldst_sz_m[1:0],

    swap_m,ldstub_m,casa_m,ldst_dbl_m,thrid_m[1:0],ldst_fp_m,quad_asi_m,flsh_inst_m}),

  .clk  (clk),

  .se   (se), .si (), .so ()

  );

assign  st_inst_vld_m = real_st_m | flsh_inst_m ;

// do we need ld/st unflushed ?

   wire sta_internal_g;

dff_s #(7) stgw_vld  (

  .din  ({sta_internal_m,

    casa_m, thrid_m[1:0],ldst_sz_m[1:0], flsh_inst_m}),

  .q    ({sta_internal_g,

    casa_g, thrid_g[1:0],ldst_sz_g[1:0], flsh_inst_g}),

  .clk  (clk),

  .se   (se), .si (), .so ()

  );

// stb-cam will be written by st at rising edge of g-stage.

// However, st can be flushed after write. To keep, the stb state consistent,

// The valid and write ptr will not be updated until the rising edge of w2.

wire    early_flush_cond_g,partial_flush_st_g ;

assign early_flush_cond_g =

(sta_internal_g | ~(lsu_inst_vld_w | blkst_g) | ffu_lsu_kill_fst_w) ;

assign  flush_st_g = (early_flush_cond_g | lsu_stbrwctl_flush_pipe_w) & cam_wptr_vld_g ;

//timing, send to stb_ctl and qualified by stb_cam_wvld_g (thread version of cam_wptr_vld_g)   

//assign        partial_flush_st_g = early_flush_cond_g & cam_wptr_vld_g ;

assign  partial_flush_st_g = early_flush_cond_g ;

assign  atomic_m = (casa_m | ldstub_m | swap_m) & st_inst_vld_m ;

// WRITE PTR VALID GENERATION.

// meant specifically to squash pcx_rq_for_stb.

assign  stb_cam_wr_no_ivld_m

  = (st_inst_vld_m | casa_m | ldstub_m | swap_m | blkst_m) ;

//bug3610 - kill cam write vld(==stb data write vld next cycle) to avoid datat read and write same cycle

//          to the same entry

wire  b2b_st_detect ;

assign  stb_cam_wptr_vld

  = (((st_inst_vld_m | atomic_m) & ifu_tlu_inst_vld_m_bf0) | blkst_m) & ~(flush_st_g & b2b_st_detect) ;

  //= ((st_inst_vld_m | atomic_m) & ifu_tlu_inst_vld_m_bf0) | blkst_m ;  // bug3610

  //= (st_inst_vld_m | atomic_m | (ldst_dbl_m & st_inst_vld_m) | blkst_m) ;

dff_s  wptr_g (

  .din  (stb_cam_wptr_vld), .q  (cam_wptr_vld_g),

  .clk  (clk),

  .se   (se), .si (), .so ()

  );

//flop move into mem cell (roll back)  

assign  stb_data_wptr_vld = cam_wptr_vld_g ;

// WRITE PTR GENERATION

// It is assumed that if there is a store in the pipe, there is a 

// free entry in the corresponding stb. Otherwise, the pipe would've

// stalled for the thread.      

// If a store-like inst has been flushed, then the old ptr has to be restored

// and used.  This is done within thread specific stb control

assign  thread0_m = ~st_thrid_m[1] & ~st_thrid_m[0] ;

assign  thread1_m = ~st_thrid_m[1] &  st_thrid_m[0] ;

assign  thread2_m =  st_thrid_m[1] & ~st_thrid_m[0] ;

assign  thread3_m =  st_thrid_m[1] &  st_thrid_m[0] ;

dff_s #(4) stgg_thrd (

  .din  ({thread0_m,thread1_m,thread2_m,thread3_m}),

  .q  ({thread0_g,thread1_g,thread2_g,thread3_g}),

  .clk  (clk),

  .se (se), .si (), .so ()

  );

assign  stb_thrd_en_g[0] = thread0_g ;

assign  stb_thrd_en_g[1] = thread1_g ;

assign  stb_thrd_en_g[2] = thread2_g ;

assign  stb_thrd_en_g[3] = thread3_g ;

//assign  stb_wptr[2:0] = 

//  thread0_m ? stb_wrptr0[2:0] :

//    thread1_m ? stb_wrptr1[2:0] :

//      thread2_m ? stb_wrptr2[2:0] :

//        thread3_m ? stb_wrptr3[2:0] : 3'bxxx ;

assign  stb_wptr[2:0] =

  (thread0_m ? stb_wrptr0[2:0] :  3'b000) |

  (thread1_m ? stb_wrptr1[2:0] :  3'b000) |

  (thread2_m ? stb_wrptr2[2:0] :  3'b000) |

  (thread3_m ? stb_wrptr3[2:0] :  3'b000) ;

assign  b2b_st_detect =   // detect back-to-back store

  (thread0_m & thread0_g) |

  (thread1_m & thread1_g) |

  (thread2_m & thread2_g) |

  (thread3_m & thread3_g) ;

assign  cam_wr_ptr[2:0] = (flush_st_g & b2b_st_detect) ? cam_wptr_d1[2:0] : stb_wptr[2:0] ;

dff_s #(3)  wptr_d1 (

  .din  (cam_wr_ptr[2:0]),  .q  (cam_wptr_d1[2:0]),

  .clk  (clk),

  .se (se), .si (), .so ()

  );

assign  stb_cam_wvld_m[0] = stb_cam_wptr_vld & thread0_m ;

assign  stb_cam_wvld_m[1] = stb_cam_wptr_vld & thread1_m ;

assign  stb_cam_wvld_m[2] = stb_cam_wptr_vld & thread2_m ;

assign  stb_cam_wvld_m[3] = stb_cam_wptr_vld & thread3_m ;

// contains potential flush conditions.

assign  stb_flush_st_g[0] = partial_flush_st_g ;

assign  stb_flush_st_g[1] = partial_flush_st_g ;

assign  stb_flush_st_g[2] = partial_flush_st_g ;

assign  stb_flush_st_g[3] = partial_flush_st_g ;

// stb-data has a delayed write in w2. Alignment of stb data will be done on write

// of 64b into stb. This allows write of stb cam and data to be done in the

// same cycle, and thus read can occur simultaneously for pcx. 

//mem cell change to bw_r_rf32x80, flop move into mem cell (roll back)

//flop outside mem cell

assign  stb_data_wr_ptr[4:0] =  {st_thrid_g[1:0],cam_wptr_d1[2:0]};

// RD PTR/VLD GENERATION

// stb read for dfq dumps data into a bypass flop. Thus a read for the dfq can occur

// if a thread's stb has an acked entry and the bypass flop is empty.

// stb read for pcx occurs on availability of queue entry. 

// Both dfq and pcx require a read of the cam and data. The reads

// can thus not happen when load that hits in the stb is in the w2 (change to W3)

// stage and a store is in the g-stage of the pipe. Both

// probabilities are low.

// ??Read for pcx takes priority over dfq. No deadlock can occur

// ??as at some point the pcx reads will be exhausted and the stb

// ??will have to drain itself. The stb is self-regulating in this regard.

// priority of stb read: ld_cam_hit (full raw bypass) > dfq > pcx 

//====================================================================================

//raw bypass timing 

//G/WB                          W2     W3                      W4

//cam_hit(from stb_cam output)  flop   stb_data rd_ptr/rd_vld  read STB_DATA/BYP

//====================================================================================

   wire [1:0] thrid_w2;

   wire [2:0] stb_cam_hit_ptr_w2;

   wire       stb_cam_hit_w2;

   wire       stb_cam_hit_w;

   //bug3503

   assign stb_cam_hit_w  =  stb_cam_hit & lsu_inst_vld_w & ~lsu_stbrwctl_flush_pipe_w;

dff_s #(6) stb_cam_hit_stg_w2 (

  .din  ({thrid_g[1:0],  stb_cam_hit_ptr[2:0],    stb_cam_hit_w   }),

  .q    ({thrid_w2[1:0], stb_cam_hit_ptr_w2[2:0], stb_cam_hit_w2}),

  .clk  (clk),

  .se   (se), .si (), .so ()

  );

// logic moved to qctl1

// pcx is making request for data in current cycle. Can be multi-hot.

//assign  pcx_any_rq_for_stb = |pcx_rq_for_stb[3:0] ;

//assign  pcx_any_rq_for_stb = 

//      (pcx_rq_for_stb[0] & ~lsu_st_pcx_rq_kill_w2[0]) | 

//      (pcx_rq_for_stb[1] & ~lsu_st_pcx_rq_kill_w2[1]) | 

//      (pcx_rq_for_stb[2] & ~lsu_st_pcx_rq_kill_w2[2]) | 

//      (pcx_rq_for_stb[3] & ~lsu_st_pcx_rq_kill_w2[3]) ; 

// ??ld-cam hit based read takes precedence

// ??Timing : This could be made pessimistic by using ld_inst_vld_g

//assign  stb_select_rptr[3:0] =  pcx_rq_for_stb[3:0] ;  // timing fix

assign  stb_select_rptr[3:0] =  lsu_st_pcx_rq_pick[3:0] ;

// This could be a critical path. Be careful !

//assign  stb_rdptr0[2:0] = ~dfq_any_rq_for_stb ? stb_pcx_rptr0[2:0] : stb_dfq_rptr0[2:0] ; 

assign  stb_rdptr0[2:0] = stb_pcx_rptr0[2:0] ;

assign  stb_rdptr1[2:0] = stb_pcx_rptr1[2:0] ;

assign  stb_rdptr2[2:0] = stb_pcx_rptr2[2:0] ;

assign  stb_rdptr3[2:0] = stb_pcx_rptr3[2:0] ;

// logic moved to qctl1

//wire  [1:0] stb_rd_tid ;

//

//assign  stb_rd_tid[0] = pcx_rq_for_stb[1] | pcx_rq_for_stb[3] ;

//assign  stb_rd_tid[1] = pcx_rq_for_stb[2] | pcx_rq_for_stb[3] ;

//   

//dff #(2) stbtid_stgd1 (

//  .din    (stb_rd_tid[1:0]),  .q  (lsu_stb_rd_tid[1:0]),

//  .clk    (clk), 

//  .se   (se), .si (), .so ()

//  );

//assign  stb_dfq_rd_id[2:0] = stb_data_rd_ptr[2:0] ; // or cam rd ptr

//timing fix:5/6/03

//bug4988 - change the prirority from 0->3 to 3->0; the reason is when select_rptr=0, the

//          default thread id(rptr[4:3])=thread0 but the default rptr[2:0]=thread3. If

//          thread0 and thread3 rptr are the same and the thread0 write is occuring, the

//          rptr[4:0] is same as wptr[4:0]

wire  [2:0]  stb_rdptr ;

//assign  stb_rdptr[2:0] = 

//  stb_select_rptr[0] ? stb_rdptr0[2:0] :

//    stb_select_rptr[1] ? stb_rdptr1[2:0] :

//      stb_select_rptr[2] ? stb_rdptr2[2:0] :

//                             stb_rdptr3[2:0] ;

//assign  stb_rdptr[2:0] = 

//  stb_select_rptr[3] ? stb_rdptr3[2:0] :

//    stb_select_rptr[2] ? stb_rdptr2[2:0] :

//      stb_select_rptr[1] ? stb_rdptr1[2:0] :

//                             stb_rdptr0[2:0] ;

assign  stb_rdptr[2:0] =

  (stb_select_rptr[3] ? stb_rdptr3[2:0] : 3'b0) |

  (stb_select_rptr[2] ? stb_rdptr2[2:0] : 3'b0) |

  (stb_select_rptr[1] ? stb_rdptr1[2:0] : 3'b0) |

  (stb_select_rptr[0] ? stb_rdptr0[2:0] : 3'b0) ;

//timing fix: 8/29/03 - remove the default select logic for stb_select_rptr since synthesis is forced to replace 

//            4to1 mux w/ and-or mux or 2to1 mux

//wire   stb_select_rptr_b3;

//assign stb_select_rptr_b3 =  ~|stb_select_rptr[2:0];