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// ========== Copyright Header Begin ==========================================

// 

// OpenSPARC T1 Processor File: spu_mactl.v

// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

// 

// The above named program is free software; you can redistribute it and/or

// modify it under the terms of the GNU General Public

// License version 2 as published by the Free Software Foundation.

// 

// The above named program is distributed in the hope that it will be 

// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

// General Public License for more details.

// 

// You should have received a copy of the GNU General Public

// License along with this work; if not, write to the Free Software

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// 

// ========== Copyright Header End ============================================

////////////////////////////////////////////////////////////////////////

/*

//      Description:    control for MA.

*/

////////////////////////////////////////////////////////////////////////

// Global header file includes

////////////////////////////////////////////////////////////////////////

module spu_mactl (

/*outputs*/

spu_mactl_iss_pulse,

spu_mactl_mpa_wen,

spu_mactl_maaddr_wen,

spu_mactl_manp_wen,

spu_mactl_ldop,

spu_mactl_stop,

spu_mactl_mulop,

spu_mactl_redop,

spu_mactl_expop,

spu_mactl_memmxsel_l,

spu_mactl_memeve_wen,

spu_mactl_memodd_wen,

spu_mactl_mamem_ren,

spu_mactl_mamem_wen,

spu_mactl_iss_pulse_dly,

spu_mactl_ldxa_data_w_sel_l,

spu_mactl_ldxa_data_w_select,

spu_mactl_mpa_sel,

spu_mactl_madp_parflop_wen,

spu_lsu_ldxa_data_vld_w2,

spu_lsu_ldxa_tid_w2,

spu_lsu_stxa_ack,

spu_lsu_stxa_ack_tid,

spu_mactl_ldxa_mactl_reg,

spu_mactl_force_perr,

spu_ifu_ttype_w2,

spu_ifu_ttype_vld_w2,

spu_ifu_ttype_tid_w,

spu_tlu_rsrv_illgl_m,

spu_ifu_corr_err_w2,

spu_ifu_unc_err_w,

spu_lsu_unc_error_w,

spu_ifu_mamem_err_w,

spu_ifu_int_w2,

spu_lsu_ldxa_illgl_va_w2,

spu_mactl_streq,

spu_mactl_ctl_reset,

spu_mactl_mem_reset_l,

spu_mactl_ma_kill_op,

spu_mactl_stxa_force_abort,

spu_mactl_mactl_len,

spu_mactl_uncerr_rst,

spu_mactl_iss_pulse_pre,

spu_mactl_pcx_wen,

spu_mactl_pcx_7170_sel,

spu_mactl_perr_set,

/*inputs*/

spu_mast_streq,

lsu_spu_stb_empty,

spu_maaddr_maaddr_0,

spu_maaddr_mpa_3,

spu_mald_memwen,

spu_mamul_memwen,

spu_mamul_memren,

spu_maaeqb_memwen,

spu_maaeqb_memren,

spu_mared_memren,

spu_mared_memwen,

spu_mast_memren,

lsu_spu_early_flush_g,

tlu_spu_flush_w,

ifu_spu_flush_w,

ifu_spu_inst_vld_w,

lsu_spu_asi_state_e,

ifu_lsu_ld_inst_e,

ifu_lsu_st_inst_e,

ifu_lsu_alt_space_e,

ifu_tlu_thrid_e,

exu_lsu_ldst_va_e,

spu_mald_done_set,

spu_mast_done_set,

spu_mared_done_set,

spu_maexp_done_set,

spu_maexp_memren,

spu_maaddr_nooddwr_on_leneq1,

spu_mared_not_idle,

spu_mamul_oprnd2_bypass,

spu_madp_perr,

ma_ctl_reg_data,

ifu_spu_trap_ack,

spu_mactl_rsrv_data_e,

spu_maaddr_len_cntr,

spu_wen_ma_unc_err,

spu_wen_ma_cor_err,

ifu_spu_nceen,

lsu_spu_ldst_ack,

mux_drive_disable,

se,

grst_l,

arst_l,

rclk);

// ---------------------------------------------

input grst_l;

input arst_l;

input rclk;

input se;

input spu_mald_memwen;

input spu_mamul_memwen;

input spu_mamul_memren;

input spu_maaeqb_memwen;

input spu_maaeqb_memren;

input spu_maaddr_maaddr_0;

input  spu_maaddr_mpa_3;

input  spu_mared_memren;

input  spu_mared_memwen;

input  spu_mast_memren;

input lsu_spu_early_flush_g;

input tlu_spu_flush_w;

input ifu_spu_flush_w;

input ifu_spu_inst_vld_w;

input [7:0] lsu_spu_asi_state_e;

input ifu_lsu_ld_inst_e;

input ifu_lsu_st_inst_e;

input ifu_lsu_alt_space_e;

input [1:0] ifu_tlu_thrid_e;

input [7:0] exu_lsu_ldst_va_e;

input spu_mald_done_set;

input spu_mast_done_set;

input spu_mared_done_set;

input spu_maexp_done_set;

input spu_maexp_memren;

input spu_maaddr_nooddwr_on_leneq1;

input spu_mared_not_idle;

input spu_mamul_oprnd2_bypass;

input spu_madp_perr;

input [13:0] ma_ctl_reg_data;

input ifu_spu_trap_ack;

input [2:0] spu_mactl_rsrv_data_e;

input [3:0] lsu_spu_stb_empty;

input spu_mast_streq;

input [5:0] spu_maaddr_len_cntr;

input spu_wen_ma_unc_err;

input spu_wen_ma_cor_err;

input [3:0] ifu_spu_nceen;

input lsu_spu_ldst_ack;

input mux_drive_disable;

// ---------------------------------------------

output spu_mactl_iss_pulse;

output spu_mactl_mpa_wen;

output spu_mactl_maaddr_wen;

output spu_mactl_manp_wen;

output spu_mactl_ldop;

output spu_mactl_stop;

output spu_mactl_mulop;

output spu_mactl_redop;

output spu_mactl_expop;

output [2:0] spu_mactl_memmxsel_l;

output spu_mactl_memeve_wen;

output spu_mactl_memodd_wen;

output spu_mactl_mamem_ren;

output spu_mactl_mamem_wen;

output spu_mactl_iss_pulse_dly;

output [3:0] spu_mactl_ldxa_data_w_sel_l;

output spu_mactl_ldxa_data_w_select;

output spu_mactl_mpa_sel;

output spu_mactl_madp_parflop_wen;

output spu_lsu_ldxa_data_vld_w2;

output [1:0] spu_lsu_ldxa_tid_w2;

output spu_lsu_stxa_ack;

output [1:0] spu_lsu_stxa_ack_tid;

output [13:0] spu_mactl_ldxa_mactl_reg;

output spu_mactl_force_perr;

output spu_ifu_ttype_w2;

output spu_ifu_ttype_vld_w2;

output [1:0] spu_ifu_ttype_tid_w;

output spu_tlu_rsrv_illgl_m;

output spu_ifu_corr_err_w2;

output spu_ifu_unc_err_w;

output spu_lsu_unc_error_w;

output spu_ifu_mamem_err_w;

output spu_ifu_int_w2;

output spu_lsu_ldxa_illgl_va_w2;

output spu_mactl_streq;

output spu_mactl_ctl_reset;

output spu_mactl_mem_reset_l;

output spu_mactl_ma_kill_op;

output spu_mactl_stxa_force_abort;

output [5:0] spu_mactl_mactl_len;

output spu_mactl_uncerr_rst;

output spu_mactl_iss_pulse_pre;

output spu_mactl_pcx_wen;

output spu_mactl_pcx_7170_sel;

output spu_mactl_perr_set;

// -------------------------------------------------------------------------

// -------------------------------------------------------------------------

// -------------------------------------------------------------------------

wire [1:0] spu_mactl_ldxa_tid_g2;

wire [1:0] spu_mactl_ldxa_tid_w;

wire spu_mactl_clr_busy_bit;

wire spu_mactl_busy_bit_wen,spu_mactl_busy_bit_wrdata;

wire clr_busy_bit_when_masync;

wire spu_mactl_mactl_wen;

wire ma_op_done;

wire spu_mactl_rsrv_done_set;

wire spu_mactl_rsrv_wrdetect_m;

wire spu_mactl_perr_set_int;

wire spu_mactl_disable_stxa_ack_g2;

wire wait_4stb_tobecome_empty;

wire waiting_4stb_tobecome_empty;

wire spu_lsu_stxa_ack_q_buf;

wire wait4_trap_ack_set;

wire spu_mactl_nceen_4int;

wire spu_ifu_mamem_unc_w2;

// -------------------------------------------------------------------------

// -------------------------------------------------------------------------

// -------------------------------------------------------------------------

// -------------------------------------------------------------------------

/*

dffrl_async ma_mem_rst (.din (grst_l),

                        .q   (spu_mactl_mem_reset_l),

                        .clk (rclk),

                        .rst_l (arst_l), .se(se), .si(), .so());

*/

wire spu_mactl_ctl_rst_l;

dffrl_async ma_enc_rst (.din (grst_l),

                        .q   (spu_mactl_ctl_rst_l),

                        .clk (rclk),

                        .rst_l (arst_l), .se(se), .si(), .so());

wire spu_mactl_ctl_rst_local = ~spu_mactl_ctl_rst_l;

assign spu_mactl_ctl_reset = ~spu_mactl_ctl_rst_l;

assign spu_mactl_mem_reset_l = ~spu_mactl_ctl_rst_local;

// -------------------------------------------------------------------------

// -------------------------------------------------------------------------

// -------------------------------------------------------------------------

wire spu_mactl_stxa_2ctl_reg;

wire stxa_2ctl_reg = spu_mactl_stxa_2ctl_reg;

wire ma_op_complete, spu_mactl_done;

wire ma_op_complete_mask;

wire [1:0] spu_thrid_m,spu_thrid_g;

wire [1:0] spu_thrid_g2;

// -----------------------------------------------------------------

// -----------------------------------------------------------------

// -----------------------------------------------------------------

wire wait4_trap_ack_stxa2ctl = wait4_trap_ack_set & stxa_2ctl_reg;

// -----------------------------------------------------------------

// -----------------------------------------------------------------

// -----------------------------------------------------------------

// -----------------------------------------------------------------

wire  state_reset = spu_mactl_ctl_rst_local | spu_mactl_done ;

// -------------------------------------------------------------------------

/*************

state

-----

00      idle

01      operation inprogress

10      wait state

11      abort

**************/

dff_s    #(1) state_00_ff (

        .din(nxt_state_00) ,

        .q(cur_state_00),

        .clk (rclk), .se(se), .si(), .so());

dffr_s  #(1) state_01_ff (

        .din(nxt_state_01) ,

        .q(cur_state_01),

        .rst(state_reset), .clk (rclk), .se(se), .si(), .so());

dffr_s  #(1) state_10_ff (

        .din(nxt_state_10) ,

        .q(cur_state_10),

        .rst(state_reset), .clk (rclk), .se(se), .si(), .so());

dffr_s  #(1) state_11_ff (

        .din(nxt_state_11) ,

        .q(cur_state_11),

        .rst(state_reset), .clk (rclk), .se(se), .si(), .so());

// -------------------------------------------------------------------------

// transition to 00 state.

assign spu_mactl_done = cur_state_01 & ~stxa_2ctl_reg & ma_op_complete_mask;

assign  nxt_state_00 = (

                         state_reset | spu_mactl_done |

                         (cur_state_00 & ~stxa_2ctl_reg ));

// -------------------------------------------------------------------------

// transition to 01 state.

wire tr2state01_frm_state00 = cur_state_00 & stxa_2ctl_reg & ~wait_4stb_tobecome_empty &

                                                                ~wait4_trap_ack_stxa2ctl;

wire tr2state01_frm_state10 = cur_state_10 & ~(stxa_2ctl_reg | waiting_4stb_tobecome_empty |

                                                                wait4_trap_ack_set);

assign  nxt_state_01 = (

                         tr2state01_frm_state00 |

                         tr2state01_frm_state10 |

                         (cur_state_01 & ~stxa_2ctl_reg & ~ma_op_complete_mask));

// -------------------------------------------------------------------------

// transition to 10 state.

wire tr2state10_frm_state11 = cur_state_11 & ~stxa_2ctl_reg & ma_op_complete_mask;

wire tr2state10_frm_state10 = cur_state_10 & (stxa_2ctl_reg | waiting_4stb_tobecome_empty |

                                                                wait4_trap_ack_set);

wire tr2state10_frm_state00 = cur_state_00 & (wait_4stb_tobecome_empty | wait4_trap_ack_stxa2ctl);

assign  nxt_state_10 = (

                         tr2state10_frm_state00 | tr2state10_frm_state11 | tr2state10_frm_state10 );

// -------------------------------------------------------------------------

// transition to 11 state.

wire tr2state11_frm_state01 = cur_state_01 & stxa_2ctl_reg;

wire tr2state11_frm_state11 = cur_state_11 & (stxa_2ctl_reg | ~ma_op_complete_mask);

assign  nxt_state_11 = (

                         tr2state11_frm_state11 | tr2state11_frm_state01 );

// -------------------------------------------------------------------------

assign spu_mactl_mactl_wen = tr2state01_frm_state00 | tr2state01_frm_state10;

wire spu_mactl_mactl_iss_mxsel = tr2state01_frm_state00;

wire spu_mactl_mactl_wen_a_reg = stxa_2ctl_reg;

wire tr2state01_frm_state00_q,tr2state01_frm_state00_qq;

dff_s  #(2) tr2state01_frm_state00_dly_ff (

        .din({tr2state01_frm_state00,tr2state01_frm_state00_q}) ,

        .q({tr2state01_frm_state00_q,tr2state01_frm_state00_qq}),

        .clk (rclk), .se(se), .si(), .so());

wire tr2state01_frm_state10_q,tr2state01_frm_state10_qq;

dff_s  #(2) tr2state01_frm_state10_dly_ff (

        .din({tr2state01_frm_state10,tr2state01_frm_state10_q}) ,

        .q({tr2state01_frm_state10_q,tr2state01_frm_state10_qq}),

        .clk (rclk), .se(se), .si(), .so());

// since there is a 2 cycle delay between stxa to ctlreg and issue signal getting

// asserted and clear of all *_done_set signals. Need to mask out the qualification

// with ma_complete for these 2 cycles.

assign ma_op_complete_mask = ma_op_complete & ~(tr2state01_frm_state00_q |

                                tr2state01_frm_state00_qq) & ~(tr2state01_frm_state10_q |

                                tr2state01_frm_state10_qq);

assign spu_mactl_stxa_force_abort = cur_state_11;

// -------------------------------------------------------------------------

// -------------------------------------------------------------------------

// -------------------------------------------------------------------------

//                              CTL REG

// -------------------------------------------------------------------------

wire [13:0] spu_mactl_mactl_reg;

// -------------------------------------------------------------------------

// -------------------------------------------------------------------------

wire [13:0] spu_mactl_young_ctlreg_data;

wire [13:0] spu_mactl_ctlreg_data_mxout;

// wire [1:0] old_ctlreg_issue_tid;

wire [1:0] young_ctlreg_issue_tid;

wire [1:0] ctlreg_tid_4cmp_2ldxa_tid;

wire ldxa_tid_match_ctlreg_tid_g2;

dffre_s  #(16) young_ctl_reg_ff (

        .din({spu_thrid_g2[1:0], ma_ctl_reg_data[13:0]}) ,

        .q({young_ctlreg_issue_tid[1:0],spu_mactl_young_ctlreg_data[13:0]}),

        .en(spu_mactl_mactl_wen_a_reg),

        .rst(spu_mactl_ctl_rst_local), .clk (rclk), .se(se), .si(), .so());

assign spu_mactl_ctlreg_data_mxout[13:0] = spu_mactl_mactl_iss_mxsel ?

                                                 ma_ctl_reg_data[13:0] :

                                                 spu_mactl_young_ctlreg_data[13:0];

assign spu_mactl_ldxa_mactl_reg[13:0] = (cur_state_01 | cur_state_00) ? spu_mactl_mactl_reg[13:0] :

                                                        spu_mactl_young_ctlreg_data[13:0];

assign ctlreg_tid_4cmp_2ldxa_tid[1:0] = (cur_state_01 | cur_state_00) ? spu_mactl_mactl_reg[12:11] :

                                                        spu_mactl_young_ctlreg_data[12:11];

/*

replaced this with following since an ldxatosync followed and stxa2ctl was getting the incoorect timing

for compare of tids

assign ldxa_tid_match_ctlreg_tid_g = (ctlreg_tid_4cmp_2ldxa_tid[1:0] == spu_thrid_g[1:0]);

dff_s #(1) ldxa_tid_match_ctl_reg_tid_ff (

        .din(ldxa_tid_match_ctlreg_tid_g) ,

        .q(ldxa_tid_match_ctlreg_tid_g2),

        .clk (rclk), .se(se), .si(), .so());

*/

assign ldxa_tid_match_ctlreg_tid_g2 = (ctlreg_tid_4cmp_2ldxa_tid[1:0] == spu_thrid_g2[1:0]);

// -------------------------------------------------------------------------

// -------------------------------------------------------------------------

wire spu_mactl_busy_bit;

mux2ds #(1) busy_bit_mx (

        .in0    (spu_mactl_busy_bit_wrdata),

        .in1    (spu_mactl_ctlreg_data_mxout[10]),

        .sel0    (spu_mactl_busy_bit_wen),

        .sel1    (~spu_mactl_busy_bit_wen),

        .dout   (spu_mactl_busy_bit));

dffre_s  #(1) ctl_reg_busybit_ff (

        .din(spu_mactl_busy_bit ) ,

        .q(spu_mactl_mactl_reg[10]),

        .en(spu_mactl_busy_bit_wen),

        .rst(spu_mactl_ctl_rst_local|spu_mactl_clr_busy_bit), .clk (rclk), .se(se), .si(), .so());

///wire ma_is_busy = spu_mactl_mactl_reg[10];

/*

dffre_s  #(9) mactl_reg_ff (

        .din({spu_mactl_ctlreg_data_mxout[15:11],spu_mactl_ctlreg_data_mxout[9:6]}) ,

        .q({old_ctlreg_issue_tid[1:0], spu_mactl_mactl_reg[13:11],spu_mactl_mactl_reg[9:6]}),

        .en(spu_mactl_mactl_wen),

        .rst(spu_mactl_ctl_rst_local), .clk (rclk), .se(se), .si(), .so());

*/

dffre_s  #(7) mactl_reg_ff (

        .din({spu_mactl_ctlreg_data_mxout[13:11],spu_mactl_ctlreg_data_mxout[9:6]}) ,

        .q({spu_mactl_mactl_reg[13:11],spu_mactl_mactl_reg[9:6]}),

        .en(spu_mactl_mactl_wen),

        .rst(spu_mactl_ctl_rst_local), .clk (rclk), .se(se), .si(), .so());

wire spu_mactl_int_set = spu_mactl_mactl_reg[9];

/////////   NEED TO DO LEN UPDATE AT THE END also

wire [5:0] spu_mactl_len_cntr_mx;

dffre_s  #(6) mactl_reg_len_ff (

        .din(spu_mactl_len_cntr_mx[5:0]) ,

        .q(spu_mactl_mactl_reg[5:0]),

        .en(spu_mactl_mactl_wen | spu_mast_streq),

        .rst(spu_mactl_ctl_rst_local), .clk (rclk), .se(se), .si(), .so());

assign spu_mactl_mactl_len = spu_mactl_mactl_reg[5:0];

// -------------------------------------------------------------------------

// -------------------------------------------------------------------------

// -------------------------------------------------------------------------

// LEN field update

assign spu_mactl_len_cntr_mx[5:0] = (spu_maaddr_len_cntr[5:0] & {6{~spu_mactl_mactl_wen}}) |

                                        (spu_mactl_ctlreg_data_mxout[5:0] & {6{spu_mactl_mactl_wen}}) ;

// -------------------------------------------------------------------------

// -------------------------------------------------------------------------

// -------------------------------------------------------------------------

// -------------------------------------------------------------------------

// -------------------------------------------------------------------------

// stb empty logic

wire allow_stxaack_waiting4trapack_pulse;

wire spu_thrid_decode_tid0 = ~spu_thrid_g2[1] & ~spu_thrid_g2[0];

wire spu_thrid_decode_tid1 = ~spu_thrid_g2[1] & spu_thrid_g2[0];

wire spu_thrid_decode_tid2 = spu_thrid_g2[1] & ~spu_thrid_g2[0];

wire spu_thrid_decode_tid3 = spu_thrid_g2[1] & spu_thrid_g2[0];

wire stb_isempty =

                                (lsu_spu_stb_empty[0] & spu_thrid_decode_tid0) |

                                (lsu_spu_stb_empty[1] & spu_thrid_decode_tid1) |

                                (lsu_spu_stb_empty[2] & spu_thrid_decode_tid2) |

                                (lsu_spu_stb_empty[3] & spu_thrid_decode_tid3) ;

wire wait_4stb_empty_wen = stxa_2ctl_reg & ~stb_isempty;

wire wait_4stb_empty_rst = (stxa_2ctl_reg & stb_isempty) |

                                tr2state01_frm_state10 |

                                (allow_stxaack_waiting4trapack_pulse & ~wait_4stb_empty_wen) ;

assign spu_mactl_disable_stxa_ack_g2 = wait_4stb_empty_wen;

assign wait_4stb_tobecome_empty = wait_4stb_empty_wen;

wire waiting_4stb_empty_set;

dffre_s #(1) wait_4stb_empty_ff (

        .din(1'b1) ,

        .q(waiting_4stb_empty_set),

        .en(wait_4stb_empty_wen),

        .rst(spu_mactl_ctl_rst_local | wait_4stb_empty_rst), .clk (rclk), .se(se), .si(), .so());

wire young_thrid_decode_tid0 = ~young_ctlreg_issue_tid[1] & ~young_ctlreg_issue_tid[0];

wire young_thrid_decode_tid1 = ~young_ctlreg_issue_tid[1] & young_ctlreg_issue_tid[0];

wire young_thrid_decode_tid2 = young_ctlreg_issue_tid[1] & ~young_ctlreg_issue_tid[0];

wire young_thrid_decode_tid3 = young_ctlreg_issue_tid[1] & young_ctlreg_issue_tid[0];

wire stb_hasbecome_empty_while_instate10 =

                                (lsu_spu_stb_empty[0] & young_thrid_decode_tid0) |

                                (lsu_spu_stb_empty[1] & young_thrid_decode_tid1) |

                                (lsu_spu_stb_empty[2] & young_thrid_decode_tid2) |

                                (lsu_spu_stb_empty[3] & young_thrid_decode_tid3) ;

assign waiting_4stb_tobecome_empty  = (~stb_hasbecome_empty_while_instate10 & waiting_4stb_empty_set) |

                                                                                wait_4stb_empty_wen;

wire allow_stxa_ack_while_instate10 =

        //(waiting_4stb_empty_set & wait_4stb_empty_wen & cur_state_10) | // when in state10 & waiting 

        //(waiting_4stb_empty_set & wait_4stb_empty_wen ) | // when in state10 & waiting 

        (waiting_4stb_empty_set & stxa_2ctl_reg ) | // when in state10 & waiting 

                                                                        // 4stb_empty & there is stxa_2ctlreg.

        (waiting_4stb_empty_set & tr2state01_frm_state10 & stb_hasbecome_empty_while_instate10) | // when in state10 & 

                                                                        // waiting 4stb_empty and stb becomes empty. 

        allow_stxaack_waiting4trapack_pulse;

wire delayed_allow_stxa_ack;

wire delayed_allow_stxa_ack_pre = (stxa_2ctl_reg & stb_isempty & waiting_4stb_empty_set) |

                                        (spu_lsu_stxa_ack_q_buf & stxa_2ctl_reg & stb_isempty);//this is to resolve

                                                                        //b-b-b stxa's

wire waiting_4stb_empty_set_dly;

dff_s #(1) waiting_4stb_empty_set_dly_ff (

        .din(waiting_4stb_empty_set) ,

        .q(waiting_4stb_empty_set_dly),

        .clk (rclk), .se(se), .si(), .so());

wire waiting_4stb_empty_set_dly2;

dff_s #(1) waiting_4stb_empty_set_dly2_ff (

        .din(waiting_4stb_empty_set_dly) ,

        .q(waiting_4stb_empty_set_dly2),

        .clk (rclk), .se(se), .si(), .so());

wire delayed_allow_stxa_ack_pre_qual = delayed_allow_stxa_ack_pre & (waiting_4stb_empty_set |

                                                waiting_4stb_empty_set_dly | waiting_4stb_empty_set_dly2);

dffr_s #(1) delayed_allow_stxa_ack_pre_ff (

        .din(delayed_allow_stxa_ack_pre_qual) ,

        .q(delayed_allow_stxa_ack),

        .rst(spu_mactl_ctl_rst_local), .clk (rclk), .se(se), .si(), .so());

// ################################################################################ 

// ECO bug5326.

// this is related to stxa not getting acked when in state 10 and stb becomes empty and wait4_trap_ack is

// asserted and becaues of this tr2state01_frm_state10 does not occur and as a result no ack is sent out

// and when stb becomes empty(wait4_trap_ack is still waiting for ack) still no ack and stxa hangs.

wire  allow_stxaack_waiting4trapack = waiting_4stb_empty_set & stb_hasbecome_empty_while_instate10 &

                                                cur_state_10 & wait4_trap_ack_set;

wire allow_stxaack_waiting4trapack_q;

dff_s  #(1) allow_stxaack_waiting4trapack_ff (

        .din(allow_stxaack_waiting4trapack) ,

        .q(allow_stxaack_waiting4trapack_q),

        .clk (rclk), .se(se), .si(), .so());