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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: spu_maexp.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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module spu_maexp (
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/*outputs*/
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spu_maexp_e_rd_oprnd_sel,
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spu_maexp_shift_e,
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spu_maexp_e_data_wen,
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spu_maexp_incr_es_ptr,
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spu_maexp_es_max_init,
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spu_maexp_es_e_ptr_rst,
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spu_maexp_done_set,
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spu_maexp_memren,
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spu_maexp_start_mulred_aequb,
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spu_maexp_start_mulred_anoteqb,
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spu_mactl_stxa_force_abort,
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/*inputs*/
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spu_maaddr_esmax,
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spu_maaddr_esmod64,
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spu_madp_e_eq_one,
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spu_mared_red_done,
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spu_mactl_iss_pulse_dly,
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spu_mactl_expop,
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spu_mactl_kill_op,
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se,
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reset,
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rclk);
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input reset;
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input rclk;
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input se;
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input spu_maaddr_esmax;
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input spu_maaddr_esmod64;
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input spu_madp_e_eq_one;
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input spu_mared_red_done;
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input spu_mactl_iss_pulse_dly;
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input spu_mactl_expop;
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input spu_mactl_kill_op;
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input spu_mactl_stxa_force_abort;
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// --------------------------------------------------------------------------------
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output spu_maexp_e_rd_oprnd_sel;
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output spu_maexp_shift_e;
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output spu_maexp_e_data_wen;
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output spu_maexp_incr_es_ptr;
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output spu_maexp_es_max_init;
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output spu_maexp_es_e_ptr_rst;
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output spu_maexp_done_set;
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output spu_maexp_memren;
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output spu_maexp_start_mulred_aequb;
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output spu_maexp_start_mulred_anoteqb;
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// --------------------------------------------------------------------------------
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// --------------------------------------------------------------------------------
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wire spu_maexp_exp_done,tr2idle_frm_esmax,tr2rde_frm_idle,tr2rde_frm_esmax,
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tr2gotomulred1_frm_rde,tr2gotomulred1_frm_esmax,tr2echk_frm_gotomulred1,
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tr2gotomulred2_frm_echk,tr2esmax_frm_gotomulred2,tr2esmax_frm_echk;
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// --------------------------------------------------------------------------------
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// --------------------------------------------------------------------------------
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wire cur_rde_state;
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wire local_stxa_abort;
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// --------------------------------------------------------------------------------
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// --------------------------------------------------------------------------------
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// -------------------------------------------------------------------------
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// we need a state set to indcate exp is done, and when an
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// masync gets issued later, then the load asi is returned.
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wire spu_maexp_done_wen = (spu_maexp_exp_done | spu_mactl_kill_op |
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local_stxa_abort) & spu_mactl_expop ;
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wire spu_maexp_done_rst = reset | spu_mactl_iss_pulse_dly;
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dffre_s #(1) spu_maexp_done_ff (
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.din(1'b1) ,
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.q(spu_maexp_done_set),
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.en(spu_maexp_done_wen),
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.rst(spu_maexp_done_rst), .clk (rclk), .se(se), .si(), .so());
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// --------------------------------------------------------------------------------
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// this was causing rd and wr contention in idct when running random diags. cur_rde_state
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//cause perr which caused expop to go to idle, but maaeqb state machine was in progress
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//and then a ldop was started which caused a rd of mem for ldop and a write during
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//maaeqb op in progress.
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//assign local_stxa_abort = (cur_rde_state | spu_mared_red_done) & spu_mactl_stxa_force_abort;
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assign local_stxa_abort = spu_mared_red_done & spu_mactl_stxa_force_abort;
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wire state_reset = reset | spu_maexp_exp_done | spu_mactl_kill_op |
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local_stxa_abort;
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// -------------------------------------------------------------------------------
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// -------------------------------------------------------------------------------
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wire expop_start = spu_mactl_iss_pulse_dly & spu_mactl_expop;
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// -------------------------------------------------------------------------------
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// -------------------------------------------------------------------------------
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// -------------------------------------------------------------------------------
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// -------------------------------------------------------------------------------
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dff_s #(1) idle_state_ff (
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.din(nxt_idle_state) ,
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.q(cur_idle_state),
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.clk (rclk), .se(se), .si(), .so());
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dffr_s #(1) rde_state_ff (
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.din(nxt_rde_state) ,
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.q(cur_rde_state),
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.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
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dffr_s #(1) gotomulred1_state_ff (
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.din(nxt_gotomulred1_state) ,
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.q(cur_gotomulred1_state),
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.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
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dffr_s #(1) echk_state_ff (
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.din(nxt_echk_state) ,
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.q(cur_echk_state),
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.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
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dffr_s #(1) gotomulred2_state_ff (
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.din(nxt_gotomulred2_state) ,
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.q(cur_gotomulred2_state),
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.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
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dffr_s #(1) esmax_state_ff (
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.din(nxt_esmax_state) ,
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.q(cur_esmax_state),
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.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
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// -------------------------------------------------------------------------------
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// -------------------------------------------------------------------------------
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// -------------------------------------------------------------------------------
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// -------------------------------------------------------------------------------
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// -------------------------------------------------------------------------------
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// transition to idle state
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assign tr2idle_frm_esmax = spu_maaddr_esmax & cur_esmax_state;
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assign spu_maexp_exp_done = tr2idle_frm_esmax;
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assign nxt_idle_state = (
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state_reset |
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tr2idle_frm_esmax |
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(cur_idle_state & ~expop_start));
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// -------------------------------------------------------------------------------
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// transition to rde state
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assign tr2rde_frm_idle = cur_idle_state & expop_start;
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/*
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wire dly_tr2rde_frm_idle;
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dff_s #(1) dly_tr2rde_frm_idle_ff (
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.din(tr2rde_frm_idle) ,
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.q(dly_tr2rde_frm_idle),
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.clk (rclk),
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.clk (rclk)
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, .se(se), .si(), .so());
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*/
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assign tr2rde_frm_esmax = cur_esmax_state & ~spu_maaddr_esmax & spu_maaddr_esmod64;
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assign nxt_rde_state = (
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tr2rde_frm_idle |
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tr2rde_frm_esmax );
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// -------------------------------------------------------------------------------
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// transition to gotomulred1 state
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assign tr2gotomulred1_frm_rde = cur_rde_state;
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assign tr2gotomulred1_frm_esmax = cur_esmax_state & ~spu_maaddr_esmax &
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~spu_maaddr_esmod64;
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assign nxt_gotomulred1_state = (
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tr2gotomulred1_frm_rde |
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tr2gotomulred1_frm_esmax |
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(cur_gotomulred1_state & ~spu_mared_red_done) );
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// -------------------------------------------------------------------------------
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// transition to echk state
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assign tr2echk_frm_gotomulred1 = cur_gotomulred1_state & spu_mared_red_done;
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assign nxt_echk_state = (
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tr2echk_frm_gotomulred1);
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// -------------------------------------------------------------------------------
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// transition to gotomulred2 state
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assign tr2gotomulred2_frm_echk = cur_echk_state & spu_madp_e_eq_one;
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assign nxt_gotomulred2_state = (
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tr2gotomulred2_frm_echk |
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(cur_gotomulred2_state & ~spu_mared_red_done) );
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// -------------------------------------------------------------------------------
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// transition to esmax state
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assign tr2esmax_frm_gotomulred2 = cur_gotomulred2_state & spu_mared_red_done;
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assign tr2esmax_frm_echk = cur_echk_state & ~spu_madp_e_eq_one;
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assign nxt_esmax_state = (
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tr2esmax_frm_gotomulred2 |
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tr2esmax_frm_echk);
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// -------------------------------------------------------------------------------
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// -------------------------------------------------------------------------------
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// -------------------------------------------------------------------------------
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// -------------------------------------------------------------------------------
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// SEL XXNM OR XANM
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/*
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wire spu_maexp_xxnm_sel_set = tr2rde_frm_idle | tr2esmax_frm_echk |
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tr2esmax_frm_gotomulred2;
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wire spu_maexp_xxnm_sel_rst = state_reset | tr2echk_frm_gotomulred1;
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dffre_s #(1) xxnm_set_ff (
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.din(1'b1) ,
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.q(spu_maexp_xxnm_sel_q),
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.en(spu_maexp_xxnm_sel_set),
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.rst(spu_maexp_xxnm_sel_rst), .clk (rclk),
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.rst(spu_maexp_xxnm_sel_rst), .clk (rclk)
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, .se(se), .si(), .so());
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assign spu_maexp_b_to_x_sel = spu_maexp_xxnm_sel_q;
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assign spu_maexp_b_to_a_sel = ~spu_maexp_xxnm_sel_q;
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*/
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// -------------------------------------------------------------------------------
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assign spu_maexp_e_rd_oprnd_sel = tr2rde_frm_idle | tr2rde_frm_esmax;
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assign spu_maexp_memren = spu_maexp_e_rd_oprnd_sel;
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assign spu_maexp_shift_e = nxt_esmax_state; // muxsel in madp
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// write enable when data is from mamem or a shift write
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assign spu_maexp_e_data_wen = cur_rde_state | nxt_esmax_state;
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//assign spu_maexp_incr_es_ptr = tr2echk_frm_gotomulred1;
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assign spu_maexp_incr_es_ptr = tr2rde_frm_esmax | tr2gotomulred1_frm_esmax;
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assign spu_maexp_es_max_init = tr2rde_frm_idle;
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assign spu_maexp_es_e_ptr_rst = state_reset;
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// -------------------------------------------------------------------------------
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//assign spu_maexp_start_mulred = tr2gotomulred1_frm_rde | tr2gotomulred1_frm_esmax |
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// tr2gotomulred2_frm_echk ;
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assign spu_maexp_start_mulred_aequb = tr2gotomulred1_frm_rde | tr2gotomulred1_frm_esmax;
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assign spu_maexp_start_mulred_anoteqb = tr2gotomulred2_frm_echk;
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// -------------------------------------------------------------------------------
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endmodule
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