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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: spu_mald.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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////////////////////////////////////////////////////////////////////////
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/*
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// Description: state machine for load requests to L2.
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*/
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////////////////////////////////////////////////////////////////////////
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// Global header file includes
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////////////////////////////////////////////////////////////////////////
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module spu_mald (
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/*outputs*/
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spu_mald_rstln,
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spu_mald_maaddr_addrinc,
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spu_mald_memwen,
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spu_mald_mpa_addrinc,
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spu_mald_ldreq,
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spu_mald_done,
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spu_mald_force_mpa_add16,
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spu_mald_done_set,
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/*inputs*/
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ld_inprog,
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ldreq_ack,
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ln_received,
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len_neqz,
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mactl_ldop,
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spu_maaddr_mpa1maddr0,
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spu_mactl_iss_pulse_dly,
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spu_wen_ma_unc_err_pulse,
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spu_mactl_stxa_force_abort,
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se,
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reset,
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rclk);
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// ---------------------------------------------------------
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input reset;
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input rclk;
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input se;
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input ld_inprog;
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input ldreq_ack;
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input ln_received;
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input len_neqz;
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input mactl_ldop;
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input spu_maaddr_mpa1maddr0;
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input spu_mactl_iss_pulse_dly;
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input spu_wen_ma_unc_err_pulse;
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input spu_mactl_stxa_force_abort;
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// ---------------------------------------------------------
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output spu_mald_rstln;
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output spu_mald_maaddr_addrinc;
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output spu_mald_memwen;
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output spu_mald_mpa_addrinc;
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output spu_mald_ldreq;
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output spu_mald_done;
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output spu_mald_force_mpa_add16;
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output spu_mald_done_set;
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// ---------------------------------------------------------
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wire tr2wait4ln_frm_ldreq;
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// ---------------------------------------------------------
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/*******************************
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there are 8 states:
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000001 idle
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000010 ld1_req
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000100 ld2_req
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001000 wait_4ln1
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010000 wait_4ln2
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100000 mamem_wr
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********************************/
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wire local_stxa_abort;
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// ------------------------------------------------------
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// we need a state set to indcate ld is done, and when an
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// masync gets issued later, then the load asi is returned.
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wire spu_mald_done_wen = (spu_mald_done | spu_wen_ma_unc_err_pulse | local_stxa_abort) &
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mactl_ldop;
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wire spu_mald_done_rst = reset | spu_mactl_iss_pulse_dly;
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dffre_s #(1) spu_mald_done_ff (
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.din(1'b1) ,
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.q(spu_mald_done_set),
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.en(spu_mald_done_wen),
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.rst(spu_mald_done_rst), .clk (rclk), .se(se), .si(), .so());
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// ------------------------------------------------------
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// ------------------------------------------------------
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// ------------------------------------------------------
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// ------------------------------------------------------
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// ------------------------------------------------------
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wire state_reset = reset | spu_mald_done | spu_wen_ma_unc_err_pulse |
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local_stxa_abort;
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// ------------------------------------------------------
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dff_s #(1) idle_state_ff (
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.din(nxt_idle_state) ,
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.q(cur_idle_state),
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.clk (rclk), .se(se), .si(), .so());
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dffr_s #(1) ldreq_state_ff (
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.din(nxt_ldreq_state) ,
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.q(cur_ldreq_state),
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.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
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dffr_s #(1) wait4ln_state_ff (
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.din(nxt_wait4ln_state) ,
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.q(cur_wait4ln_state),
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.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
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dffr_s #(1) mamemwr_state_ff (
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.din(nxt_mamemwr_state) ,
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.q(cur_mamemwr_state),
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.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
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dffr_s #(1) chk4mpa1maddr0_state_ff (
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.din(nxt_chk4mpa1maddr0_state) ,
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.q(cur_chk4mpa1maddr0_state),
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.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
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// ------------------------------------------------------
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// ------------------------------------------------------
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wire start_ldop = spu_mactl_iss_pulse_dly & mactl_ldop;
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// --------------------------------------------------------------
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// transition to idle state.
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assign spu_mald_done = cur_chk4mpa1maddr0_state & ~len_neqz;
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assign nxt_idle_state = (
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state_reset |
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(spu_mald_done) |
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(cur_idle_state & ~start_ldop));
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// --------------------------------------------------------------
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// transition to ldreq state.
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assign nxt_ldreq_state = (
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(cur_chk4mpa1maddr0_state & ~spu_maaddr_mpa1maddr0 & len_neqz) |
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(cur_idle_state & start_ldop) |
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(cur_ldreq_state & ~ldreq_ack));
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assign spu_mald_rstln = (cur_mamemwr_state & ld_inprog & len_neqz) | local_stxa_abort |
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spu_wen_ma_unc_err_pulse;
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// --------------------------------------------------------------
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// transition to wait4ln state.
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//assign tr2wait4ln_frm_ldreq = cur_ldreq_state & ldreq_ack & ln_received;
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assign tr2wait4ln_frm_ldreq = cur_ldreq_state & ldreq_ack ;
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assign nxt_wait4ln_state = (
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(tr2wait4ln_frm_ldreq) |
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(cur_wait4ln_state & ~ln_received));
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// --------------------------------------------------------------
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// transition to mamemwr state.
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wire tr2mamemwr_frm_wait4ln = cur_wait4ln_state & ln_received;
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wire tr2mamemwr_frm_chk4mpa1maddr0 = cur_chk4mpa1maddr0_state & spu_maaddr_mpa1maddr0 & len_neqz;
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wire mald_memwen = ( tr2mamemwr_frm_wait4ln |
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tr2mamemwr_frm_chk4mpa1maddr0) & len_neqz;
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// added this delay for the Parity Gen. added extra cycle.
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wire mald_memwen_dly;
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dffr_s #(1) wen_dly_ff (
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.din(mald_memwen) ,
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.q(mald_memwen_dly),
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.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
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assign nxt_mamemwr_state = ( mald_memwen_dly );
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assign local_stxa_abort = mald_memwen_dly & spu_mactl_stxa_force_abort;
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// --------------------------------------------------------------
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// transition to chk4mpa1maddr0 state.
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assign nxt_chk4mpa1maddr0_state = (
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(cur_mamemwr_state) );
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// --------------------------------------------------------------
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// **************************************************************
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// --------------------------------------------------------------
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assign spu_mald_memwen = nxt_mamemwr_state;
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assign spu_mald_maaddr_addrinc = cur_mamemwr_state;
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assign spu_mald_mpa_addrinc = cur_mamemwr_state ;
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assign spu_mald_force_mpa_add16 = 1'b0 ;
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assign spu_mald_ldreq = cur_ldreq_state ;
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endmodule
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