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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: spu_mamul.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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////////////////////////////////////////////////////////////////////////
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/*
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// Description: state machine to do MA mul/acc/shf.
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*/
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////////////////////////////////////////////////////////////////////////
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module spu_mamul (
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/*outputs*/
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spu_mamul_memren,
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spu_mamul_memwen,
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spu_mamul_rst_iptr,
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spu_mamul_rst_jptr,
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spu_mamul_incr_iptr,
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spu_mamul_incr_jptr,
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spu_mamul_a_rd_oprnd_sel,
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spu_mamul_ax_rd_oprnd_sel,
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spu_mamul_b_rd_oprnd_sel,
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spu_mamul_ba_rd_oprnd_sel,
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spu_mamul_m_rd_oprnd_sel,
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spu_mamul_me_rd_oprnd_sel,
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spu_mamul_n_rd_oprnd_sel,
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spu_mamul_m_wr_oprnd_sel,
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spu_mamul_me_wr_oprnd_sel,
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spu_mamul_i_ptr_sel,
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spu_mamul_iminus1_ptr_sel,
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spu_mamul_j_ptr_sel,
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spu_mamul_iminusj_ptr_sel,
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spu_mamul_iminuslenminus1_sel,
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spu_mamul_jjptr_wen,
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spu_mamul_oprnd2_wen,
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spu_mamul_oprnd2_bypass,
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spu_mamul_oprnd1_mxsel_l,
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spu_mamul_oprnd1_wen,
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spu_mul_req_vld,
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spu_mul_areg_shf,
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spu_mul_acc,
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spu_mul_areg_rst,
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spu_mamul_mul_done,
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spu_mamul_jjptr_sel,
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spu_mamul_rst,
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/*inputs*/
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spu_maaeqb_jjptr_sel,
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spu_mactl_mulop,
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spu_maaddr_iequtwolenplus2,
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spu_maaddr_iequtwolenplus1,
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spu_maaddr_jequiminus1,
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spu_maaddr_jequlen,
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spu_maaddr_halfpnt_set,
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spu_mactl_iss_pulse_dly,
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spu_mared_oprnd2_wen,
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mul_spu_ack,
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mul_spu_shf_ack,
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spu_maexp_start_mulred_anoteqb,
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spu_mactl_expop,
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spu_maaddr_aequb,
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spu_maaeqb_rst_iptr,
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spu_maaeqb_rst_jptr,
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spu_maaeqb_incr_iptr,
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spu_maaeqb_incr_jptr,
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spu_maaeqb_a_rd_oprnd_sel,
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spu_maaeqb_ax_rd_oprnd_sel,
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spu_maaeqb_m_rd_oprnd_sel,
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spu_maaeqb_me_rd_oprnd_sel,
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spu_maaeqb_n_rd_oprnd_sel,
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spu_maaeqb_m_wr_oprnd_sel,
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spu_maaeqb_me_wr_oprnd_sel,
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spu_maaeqb_iminus1_ptr_sel,
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spu_maaeqb_j_ptr_sel,
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spu_maaeqb_iminusj_ptr_sel,
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spu_maaeqb_iminuslenminus1_sel,
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spu_maaeqb_jjptr_wen,
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spu_maaeqb_oprnd2_wen,
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spu_maaeqb_oprnd2_bypass,
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spu_maaeqb_mul_req_vld,
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spu_maaeqb_mul_areg_shf,
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spu_maaeqb_mul_acc,
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spu_maaeqb_mul_areg_rst,
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spu_maaeqb_mul_done,
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spu_maaeqb_oprnd1_mxsel,
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spu_maaeqb_oprnd1_wen,
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spu_mactl_kill_op,
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spu_mactl_stxa_force_abort,
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se,
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reset,
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rclk);
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// ---------------------------------------------------------------
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input reset;
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input rclk;
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input se;
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input spu_maaddr_iequtwolenplus2;
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input spu_maaddr_iequtwolenplus1;
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input spu_maaddr_jequiminus1;
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input spu_maaddr_jequlen;
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input spu_maaddr_halfpnt_set;
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input mul_spu_ack;
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input mul_spu_shf_ack;
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input spu_mactl_mulop;
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input spu_mactl_iss_pulse_dly;
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input spu_mared_oprnd2_wen;
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input spu_maexp_start_mulred_anoteqb;
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input spu_mactl_expop;
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input spu_maaddr_aequb;
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input spu_maaeqb_rst_iptr;
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input spu_maaeqb_rst_jptr;
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input spu_maaeqb_incr_iptr;
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input spu_maaeqb_incr_jptr;
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input spu_maaeqb_a_rd_oprnd_sel;
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input spu_maaeqb_ax_rd_oprnd_sel;
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input spu_maaeqb_m_rd_oprnd_sel;
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input spu_maaeqb_me_rd_oprnd_sel;
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input spu_maaeqb_n_rd_oprnd_sel;
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input spu_maaeqb_m_wr_oprnd_sel;
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input spu_maaeqb_me_wr_oprnd_sel;
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input spu_maaeqb_iminus1_ptr_sel;
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input spu_maaeqb_j_ptr_sel;
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input spu_maaeqb_iminusj_ptr_sel;
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input spu_maaeqb_iminuslenminus1_sel;
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input spu_maaeqb_jjptr_wen;
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input spu_maaeqb_oprnd2_wen;
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input spu_maaeqb_oprnd2_bypass;
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input spu_maaeqb_mul_req_vld;
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input spu_maaeqb_mul_areg_shf;
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input spu_maaeqb_mul_acc;
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input spu_maaeqb_mul_areg_rst;
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input spu_maaeqb_mul_done;
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input [1:0] spu_maaeqb_oprnd1_mxsel;
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input spu_maaeqb_oprnd1_wen;
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input spu_maaeqb_jjptr_sel;
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input spu_mactl_kill_op;
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input spu_mactl_stxa_force_abort;
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// ---------------------------------------------------------------
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output spu_mamul_memwen;
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output spu_mamul_memren;
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output spu_mamul_rst_iptr;
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output spu_mamul_rst_jptr;
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output spu_mamul_incr_iptr;
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output spu_mamul_incr_jptr;
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output spu_mamul_a_rd_oprnd_sel;
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output spu_mamul_ax_rd_oprnd_sel;
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output spu_mamul_b_rd_oprnd_sel;
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output spu_mamul_ba_rd_oprnd_sel;
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output spu_mamul_m_rd_oprnd_sel;
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output spu_mamul_me_rd_oprnd_sel;
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output spu_mamul_n_rd_oprnd_sel;
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output spu_mamul_m_wr_oprnd_sel;
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output spu_mamul_me_wr_oprnd_sel;
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output spu_mamul_i_ptr_sel;
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output spu_mamul_iminus1_ptr_sel;
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output spu_mamul_j_ptr_sel;
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output spu_mamul_iminusj_ptr_sel;
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output spu_mamul_iminuslenminus1_sel;
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output spu_mamul_jjptr_wen;
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output spu_mamul_oprnd2_wen;
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output spu_mamul_oprnd2_bypass;
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output [2:0] spu_mamul_oprnd1_mxsel_l;
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output spu_mamul_oprnd1_wen;
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output spu_mul_req_vld;
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output spu_mul_areg_shf;
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output spu_mul_acc;
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output spu_mul_areg_rst;
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output spu_mamul_mul_done;
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output spu_mamul_jjptr_sel;
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output spu_mamul_rst;
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// ---------------------------------------------------------------
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wire tr2mwrite_frm_accumshft_pre;
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wire tr2mwrite_frm_accumshft,tr2iloopa_frm_jloopn;
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wire spu_mamul_rd_aj,spu_mamul_rd_biminusj,spu_mamul_rd_mj,
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spu_mamul_rd_niminusj,spu_mamul_rd_ai,spu_mamul_rd_b0,
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spu_mamul_wr_mi,spu_mamul_wr_miminuslenminus1,
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spu_mamul_rd_n0;
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wire tr2accumshft_frm_mwrite;
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wire tr2accumshft_frm_iloopn;
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wire nxt_mwrite_state;
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// ---------------------------------------------------------------
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// ---------------------------------------------------------------
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// ---------------------------------------------------------------
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// ---------------------------------------------------------------
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// ---------------------------------------------------------------
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//wire local_stxa_abort = cur_mwrite_state & spu_mactl_stxa_force_abort;// this causes x to in perr_set
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wire local_stxa_abort = nxt_mwrite_state & spu_mactl_stxa_force_abort;
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wire state_reset = reset | spu_mactl_kill_op | local_stxa_abort;
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// ---------------------------------------------------------------
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// ---------------------------------------------------------------
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// ---------------------------------------------------------------
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// ---------------------------------------------------------------
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// ---------------------------------------------------------------
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// ---------------------------------------------------------------
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dff_s #(1) idle_state_ff (
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.din(nxt_idle_state) ,
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.q(cur_idle_state),
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.clk (rclk), .se(se), .si(), .so());
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dffr_s #(1) jloopa_state_ff (
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.din(nxt_jloopa_state) ,
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.q(cur_jloopa_state),
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.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
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dffr_s #(1) jloopb_state_ff (
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.din(nxt_jloopb_state) ,
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.q(cur_jloopb_state),
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.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
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dffr_s #(1) jloopn_state_ff (
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.din(nxt_jloopn_state) ,
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.q(cur_jloopn_state),
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.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
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dffr_s #(1) jloopm_state_ff (
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.din(nxt_jloopm_state) ,
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.q(cur_jloopm_state),
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.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
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dffr_s #(1) iloopa_state_ff (
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.din(nxt_iloopa_state) ,
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.q(cur_iloopa_state),
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.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
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dffr_s #(1) iloopb_state_ff (
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.din(nxt_iloopb_state) ,
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.q(cur_iloopb_state),
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.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
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dffr_s #(1) nprime_state_ff (
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.din(nxt_nprime_state) ,
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.q(cur_nprime_state),
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.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
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dffr_s #(1) mwrite_state_ff (
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.din(nxt_mwrite_state) ,
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.q(cur_mwrite_state),
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.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
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dffr_s #(1) iloopn_state_ff (
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.din(nxt_iloopn_state) ,
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.q(cur_iloopn_state),
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.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
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dffr_s #(1) accumshft_state_ff (
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.din(nxt_accumshft_state) ,
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.q(cur_accumshft_state),
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.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
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// ---------------------------------------------------------------
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wire spu_maaddr_aequb_q;
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dff_s #(1) spu_maaddr_aequb_ff (
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.din(spu_maaddr_aequb) ,
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.q(spu_maaddr_aequb_q),
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.clk (rclk), .se(se), .si(), .so());
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|
324 |
|
|
|
325 |
|
|
// ---------------------------------------------------------------
|
326 |
|
|
// ---------------------------------------------------------------
|
327 |
|
|
// ---------------------------------------------------------------
|
328 |
|
|
// 4 cycle delay for mul result coming back.
|
329 |
|
|
// ---------------------------------------------------------------
|
330 |
|
|
|
331 |
|
|
wire tr2mwrite_frm_jloopn = cur_jloopn_state & mul_spu_ack & spu_maaddr_halfpnt_set &
|
332 |
|
|
spu_maaddr_jequlen;
|
333 |
|
|
|
334 |
|
|
wire mul_result_c0,mul_result_c1,mul_result_c2,mul_result_c3,mul_result_c4,mul_result_c5;
|
335 |
|
|
|
336 |
|
|
//assign mul_result_c0 = (cur_nprime_state & mul_spu_ack & ~spu_maaddr_halfpnt_set) |
|
337 |
|
|
assign mul_result_c0 = (cur_nprime_state & mul_spu_ack) |
|
338 |
|
|
( tr2mwrite_frm_jloopn );
|
339 |
|
|
|
340 |
|
|
|
341 |
|
|
dffr_s #(5) mul_res_ff (
|
342 |
|
|
.din({mul_result_c0,mul_result_c1,mul_result_c2,mul_result_c3,mul_result_c4}) ,
|
343 |
|
|
.q({mul_result_c1,mul_result_c2,mul_result_c3,mul_result_c4,mul_result_c5}),
|
344 |
|
|
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
|
345 |
|
|
|
346 |
|
|
// ---------------------------------------------------------------
|
347 |
|
|
// ---------------------------------------------------------------
|
348 |
|
|
// ---------------------------------------------------------------
|
349 |
|
|
// ---------------------------------------------------------------
|
350 |
|
|
// ---------------------------------------------------------------
|
351 |
|
|
wire tr2idle_frm_accumshft = cur_accumshft_state & spu_maaddr_iequtwolenplus2 &
|
352 |
|
|
mul_spu_shf_ack;
|
353 |
|
|
|
354 |
|
|
wire spu_mamul_mul_done_pre = tr2idle_frm_accumshft;
|
355 |
|
|
wire spu_mamul_mul_done_q;
|
356 |
|
|
dff_s #(1) muldone_dly_ff (
|
357 |
|
|
.din(spu_mamul_mul_done_pre) ,
|
358 |
|
|
.q(spu_mamul_mul_done_q),
|
359 |
|
|
.clk (rclk), .se(se), .si(), .so());
|
360 |
|
|
|
361 |
|
|
assign spu_mamul_mul_done = spu_mamul_mul_done_q | spu_maaeqb_mul_done | local_stxa_abort;
|
362 |
|
|
|
363 |
|
|
assign spu_mamul_rst_iptr = tr2idle_frm_accumshft | spu_maaeqb_rst_iptr;
|
364 |
|
|
|
365 |
|
|
|
366 |
|
|
// the following is to reset jptr on the 1st half.
|
367 |
|
|
wire tr2iloopa_frm_jloopn_dly;
|
368 |
|
|
dff_s #(1) tr2iloopa_frm_jloopn_dly_ff (
|
369 |
|
|
.din(tr2iloopa_frm_jloopn) ,
|
370 |
|
|
.q(tr2iloopa_frm_jloopn_dly),
|
371 |
|
|
.clk (rclk), .se(se), .si(), .so());
|
372 |
|
|
|
373 |
|
|
// ---------------------------------------------------------------
|
374 |
|
|
|
375 |
|
|
wire mulop_start = (spu_mactl_iss_pulse_dly & spu_mactl_mulop & ~spu_maaddr_aequb_q) |
|
376 |
|
|
spu_maexp_start_mulred_anoteqb;
|
377 |
|
|
|
378 |
|
|
assign spu_mul_areg_rst = mulop_start | spu_maaeqb_mul_areg_rst;
|
379 |
|
|
assign spu_mamul_rst = spu_mul_areg_rst;
|
380 |
|
|
|
381 |
|
|
assign nxt_idle_state = (
|
382 |
|
|
state_reset |
|
383 |
|
|
tr2idle_frm_accumshft |
|
384 |
|
|
(cur_idle_state & ~mulop_start));
|
385 |
|
|
|
386 |
|
|
// ---------------------------------------------------------------
|
387 |
|
|
wire tr2jloopa_frm_accumshft = cur_accumshft_state & ~spu_maaddr_iequtwolenplus2 &
|
388 |
|
|
~spu_maaddr_iequtwolenplus1 & mul_spu_shf_ack;
|
389 |
|
|
|
390 |
|
|
wire tr2jloopa_frm_accumshft_dly;
|
391 |
|
|
dffr_s #(1) tr2jloopa_frm_accumshft_dly_ff (
|
392 |
|
|
.din(tr2jloopa_frm_accumshft) ,
|
393 |
|
|
.q(tr2jloopa_frm_accumshft_dly),
|
394 |
|
|
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
|
395 |
|
|
|
396 |
|
|
wire tr2jloopa_frm_jloopn = cur_jloopn_state & mul_spu_ack &
|
397 |
|
|
((~spu_maaddr_jequiminus1 & ~spu_maaddr_halfpnt_set) |
|
398 |
|
|
(~spu_maaddr_jequlen & spu_maaddr_halfpnt_set)) ;
|
399 |
|
|
|
400 |
|
|
assign nxt_jloopa_state = (
|
401 |
|
|
tr2jloopa_frm_jloopn |
|
402 |
|
|
tr2jloopa_frm_accumshft_dly );
|
403 |
|
|
|
404 |
|
|
|
405 |
|
|
assign spu_mamul_jjptr_wen = cur_jloopm_state | spu_maaeqb_jjptr_wen;
|
406 |
|
|
|
407 |
|
|
assign spu_mamul_incr_jptr = tr2jloopa_frm_jloopn | spu_maaeqb_incr_jptr;
|
408 |
|
|
|
409 |
|
|
assign spu_mamul_jjptr_sel = cur_jloopn_state | spu_maaeqb_jjptr_sel;
|
410 |
|
|
|
411 |
|
|
//assign spu_mamul_rd_aj = nxt_jloopa_state;
|
412 |
|
|
assign spu_mamul_rd_aj =
|
413 |
|
|
(cur_jloopn_state & ((~spu_maaddr_jequiminus1 & ~spu_maaddr_halfpnt_set) |
|
414 |
|
|
(~spu_maaddr_jequlen & spu_maaddr_halfpnt_set))) |
|
415 |
|
|
tr2jloopa_frm_accumshft_dly;
|
416 |
|
|
|
417 |
|
|
// ---------------------------------------------------------------
|
418 |
|
|
assign nxt_jloopb_state = (
|
419 |
|
|
cur_jloopa_state |
|
420 |
|
|
(cur_jloopb_state & ~mul_spu_ack));
|
421 |
|
|
|
422 |
|
|
//assign spu_mamul_rd_biminusj = nxt_jloopb_state | cur_jloopb_state;
|
423 |
|
|
assign spu_mamul_rd_biminusj = cur_jloopa_state;
|
424 |
|
|
|
425 |
|
|
// ---------------------------------------------------------------
|
426 |
|
|
assign nxt_jloopm_state = (
|
427 |
|
|
(cur_jloopb_state & mul_spu_ack));
|
428 |
|
|
|
429 |
|
|
//assign spu_mamul_rd_mj = nxt_jloopm_state;
|
430 |
|
|
assign spu_mamul_rd_mj = cur_jloopb_state;
|
431 |
|
|
|
432 |
|
|
// ---------------------------------------------------------------
|
433 |
|
|
|
434 |
|
|
assign nxt_jloopn_state = (
|
435 |
|
|
cur_jloopm_state |
|
436 |
|
|
(cur_jloopn_state & ~mul_spu_ack));
|
437 |
|
|
|
438 |
|
|
//assign spu_mamul_rd_niminusj = nxt_jloopn_state;
|
439 |
|
|
assign spu_mamul_rd_niminusj = cur_jloopm_state;
|
440 |
|
|
|
441 |
|
|
// ---------------------------------------------------------------
|
442 |
|
|
assign tr2iloopa_frm_jloopn = cur_jloopn_state & mul_spu_ack &
|
443 |
|
|
spu_maaddr_jequiminus1 & ~spu_maaddr_halfpnt_set;
|
444 |
|
|
|
445 |
|
|
wire tr2iloopa_frm_idle = cur_idle_state & mulop_start;
|
446 |
|
|
|
447 |
|
|
wire tr2iloopa_frm_idle_dly;
|
448 |
|
|
dff_s #(1) tr2iloopa_frm_idle_ff (
|
449 |
|
|
.din(tr2iloopa_frm_idle) ,
|
450 |
|
|
.q(tr2iloopa_frm_idle_dly),
|
451 |
|
|
.clk (rclk), .se(se), .si(), .so());
|
452 |
|
|
|
453 |
|
|
|
454 |
|
|
assign nxt_iloopa_state = (
|
455 |
|
|
(tr2iloopa_frm_idle_dly) |
|
456 |
|
|
(tr2iloopa_frm_jloopn));
|
457 |
|
|
|
458 |
|
|
// iloop reads are done in cur_* state where as the jloop reads
|
459 |
|
|
// are done in nxt_* and cur_* state(this to hold the rd indx during
|
460 |
|
|
// requests. Due to read of the iloop in cur_* state the spu_mul_req_vld
|
461 |
|
|
// is delayed by a cycle.
|
462 |
|
|
//assign spu_mamul_rd_ai = nxt_iloopa_state;
|
463 |
|
|
assign spu_mamul_rd_ai =
|
464 |
|
|
(cur_jloopn_state & (spu_maaddr_jequiminus1 & ~spu_maaddr_halfpnt_set)) | tr2iloopa_frm_idle_dly;
|
465 |
|
|
|
466 |
|
|
// ---------------------------------------------------------------
|
467 |
|
|
assign nxt_iloopb_state = (
|
468 |
|
|
(cur_iloopa_state) |
|
469 |
|
|
(cur_iloopb_state & ~mul_spu_ack));
|
470 |
|
|
|
471 |
|
|
//assign spu_mamul_rd_b0 = nxt_iloopb_state;
|
472 |
|
|
assign spu_mamul_rd_b0 = cur_iloopa_state;
|
473 |
|
|
|
474 |
|
|
// ---------------------------------------------------------------
|
475 |
|
|
assign nxt_nprime_state = (
|
476 |
|
|
(cur_iloopb_state & mul_spu_ack) |
|
477 |
|
|
(cur_nprime_state & ~mul_spu_ack));
|
478 |
|
|
|
479 |
|
|
|
480 |
|
|
// ---------------------------------------------------------------
|
481 |
|
|
// assign tr2mwrite_frm_accumshft = cur_accumshft_state & mul_spu_shf_ack &
|
482 |
|
|
// spu_maaddr_iequtwolenplus1;
|
483 |
|
|
assign tr2mwrite_frm_accumshft_pre = cur_accumshft_state & mul_spu_shf_ack &
|
484 |
|
|
spu_maaddr_iequtwolenplus1;
|
485 |
|
|
// delaying for one cycle to allow time to do i ptr increment
|
486 |
|
|
// and calculate i-len-1(M[i-len-1]).This is due to skipping jloop on last
|
487 |
|
|
// i iteration, not enough time to do both.
|
488 |
|
|
dffr_s #(1) tr2mwrite_frm_accumshft_ff (
|
489 |
|
|
.din(tr2mwrite_frm_accumshft_pre) ,
|
490 |
|
|
.q(tr2mwrite_frm_accumshft),
|
491 |
|
|
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
|
492 |
|
|
|
493 |
|
|
assign nxt_mwrite_state = (
|
494 |
|
|
tr2mwrite_frm_accumshft |
|
495 |
|
|
(mul_result_c5));
|
496 |
|
|
|
497 |
|
|
// assign spu_mamul_memwen = nxt_mwrite_state;
|
498 |
|
|
//need the following to capture mul data into flop.
|
499 |
|
|
wire spu_mamul_wr_mi_oprnd2_wenbyp = nxt_mwrite_state & ~spu_maaddr_halfpnt_set;
|
500 |
|
|
wire spu_mamul_wr_miminuslenminus1_oprnd2_wenbyp = nxt_mwrite_state & spu_maaddr_halfpnt_set;
|
501 |
|
|
|
502 |
|
|
// ---------------------------------------------------------------
|
503 |
|
|
assign nxt_iloopn_state = (
|
504 |
|
|
(cur_mwrite_state & ~spu_maaddr_halfpnt_set) |
|
505 |
|
|
(cur_iloopn_state & ~mul_spu_ack));
|
506 |
|
|
|
507 |
|
|
//assign spu_mamul_rd_n0 = nxt_iloopn_state | cur_iloopn_state;
|
508 |
|
|
assign spu_mamul_rd_n0 = cur_mwrite_state;
|
509 |
|
|
|
510 |
|
|
// ---------------------------------------------------------------
|
511 |
|
|
assign tr2accumshft_frm_mwrite = cur_mwrite_state & spu_maaddr_halfpnt_set;
|
512 |
|
|
assign tr2accumshft_frm_iloopn = cur_iloopn_state & mul_spu_ack;
|
513 |
|
|
|
514 |
|
|
assign nxt_accumshft_state = (
|
515 |
|
|
tr2accumshft_frm_mwrite |
|
516 |
|
|
tr2accumshft_frm_iloopn |
|
517 |
|
|
(cur_accumshft_state & ~mul_spu_shf_ack));
|
518 |
|
|
|
519 |
|
|
wire mamul_incr_iptr = tr2accumshft_frm_mwrite | tr2accumshft_frm_iloopn;
|
520 |
|
|
|
521 |
|
|
assign spu_mamul_incr_iptr = mamul_incr_iptr | spu_maaeqb_incr_iptr;
|
522 |
|
|
|
523 |
|
|
|
524 |
|
|
dff_s #(1) memwen_dly_ff (
|
525 |
|
|
.din(mamul_incr_iptr) ,
|
526 |
|
|
.q(spu_mamul_memwen),
|
527 |
|
|
.clk (rclk), .se(se), .si(), .so());
|
528 |
|
|
|
529 |
|
|
assign spu_mamul_wr_mi = spu_mamul_memwen & ~spu_maaddr_halfpnt_set;
|
530 |
|
|
assign spu_mamul_wr_miminuslenminus1 = spu_mamul_memwen & spu_maaddr_halfpnt_set;
|
531 |
|
|
|
532 |
|
|
// ---------------------------------------------------------------
|
533 |
|
|
|
534 |
|
|
wire cur_accumshft_pulse,cur_accumshft_q;
|
535 |
|
|
|
536 |
|
|
dff_s #(1) cur_accumshft_pulse_ff (
|
537 |
|
|
.din(cur_accumshft_state) ,
|
538 |
|
|
.q(cur_accumshft_q),
|
539 |
|
|
.clk (rclk), .se(se), .si(), .so());
|
540 |
|
|
|
541 |
|
|
assign cur_accumshft_pulse = ~cur_accumshft_q & cur_accumshft_state;
|
542 |
|
|
|
543 |
|
|
wire mamul_rst_jptr = mulop_start | tr2iloopa_frm_jloopn_dly | (cur_accumshft_pulse &
|
544 |
|
|
spu_maaddr_halfpnt_set & ~spu_maaddr_iequtwolenplus2 &
|
545 |
|
|
~spu_maaddr_iequtwolenplus1);
|
546 |
|
|
|
547 |
|
|
assign spu_mamul_rst_jptr = mamul_rst_jptr | spu_maaeqb_rst_jptr;
|
548 |
|
|
// ---------------------------------------------------------------
|
549 |
|
|
// ---------------------------------------------------------------
|
550 |
|
|
// send selects to spu_maaddr.v
|
551 |
|
|
// ---------------------------------------------------------------
|
552 |
|
|
// ---------------------------------------------------------------
|
553 |
|
|
assign spu_mamul_memren = spu_mamul_rd_aj |
|
554 |
|
|
spu_mamul_rd_biminusj |
|
555 |
|
|
spu_mamul_rd_mj |
|
556 |
|
|
spu_mamul_rd_niminusj |
|
557 |
|
|
spu_mamul_rd_ai | spu_mamul_rd_b0 | spu_mamul_rd_n0;
|
558 |
|
|
|
559 |
|
|
// ---------------------------------------------------------------
|
560 |
|
|
// ---------------------------------------------------------------
|
561 |
|
|
// ---------------------------------------------------------------
|
562 |
|
|
wire mamul_a_rd_oprnd_sel = (spu_mamul_rd_aj | spu_mamul_rd_ai) & ~spu_mactl_expop;
|
563 |
|
|
assign spu_mamul_a_rd_oprnd_sel = mamul_a_rd_oprnd_sel | spu_maaeqb_a_rd_oprnd_sel;
|
564 |
|
|
|
565 |
|
|
wire mamul_ax_rd_oprnd_sel = (spu_mamul_rd_aj | spu_mamul_rd_ai) & spu_mactl_expop;
|
566 |
|
|
assign spu_mamul_ax_rd_oprnd_sel = mamul_ax_rd_oprnd_sel | spu_maaeqb_ax_rd_oprnd_sel;
|
567 |
|
|
|
568 |
|
|
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
569 |
|
|
|
570 |
|
|
//assign spu_mamul_b_rd_oprnd_sel = ((spu_mamul_rd_biminusj & ~spu_mamul_rd_aj & ~spu_mamul_rd_mj) |
|
571 |
|
|
assign spu_mamul_b_rd_oprnd_sel = (spu_mamul_rd_biminusj |
|
572 |
|
|
spu_mamul_rd_b0) & ~spu_mactl_expop;
|
573 |
|
|
|
574 |
|
|
// bx should be removed, since xxnm does not start mamul, instead it starts maaeqb.
|
575 |
|
|
// assign spu_mamul_bx_rd_oprnd_sel = ((spu_mamul_rd_biminusj & ~spu_mamul_rd_aj & ~spu_mamul_rd_mj) |
|
576 |
|
|
// spu_mamul_rd_b0) & spu_maexp_b_to_x_sel & spu_mactl_expop;
|
577 |
|
|
|
578 |
|
|
//assign spu_mamul_ba_rd_oprnd_sel = ((spu_mamul_rd_biminusj & ~spu_mamul_rd_aj & ~spu_mamul_rd_mj) |
|
579 |
|
|
assign spu_mamul_ba_rd_oprnd_sel = (spu_mamul_rd_biminusj |
|
580 |
|
|
spu_mamul_rd_b0) & spu_mactl_expop;
|
581 |
|
|
|
582 |
|
|
|
583 |
|
|
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
584 |
|
|
|
585 |
|
|
wire mamul_m_rd_oprnd_sel = spu_mamul_rd_mj & ~spu_mactl_expop ;
|
586 |
|
|
assign spu_mamul_m_rd_oprnd_sel = mamul_m_rd_oprnd_sel | spu_maaeqb_m_rd_oprnd_sel ;
|
587 |
|
|
|
588 |
|
|
wire mamul_me_rd_oprnd_sel = spu_mamul_rd_mj & spu_mactl_expop ;
|
589 |
|
|
assign spu_mamul_me_rd_oprnd_sel = mamul_me_rd_oprnd_sel | spu_maaeqb_me_rd_oprnd_sel ;
|
590 |
|
|
|
591 |
|
|
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
592 |
|
|
//wire mamul_n_rd_oprnd_sel = (spu_mamul_rd_niminusj & ~spu_mamul_rd_aj & ~spu_mamul_rd_mj) | spu_mamul_rd_n0;
|
593 |
|
|
wire mamul_n_rd_oprnd_sel = spu_mamul_rd_niminusj | spu_mamul_rd_n0;
|
594 |
|
|
assign spu_mamul_n_rd_oprnd_sel = mamul_n_rd_oprnd_sel | spu_maaeqb_n_rd_oprnd_sel;
|
595 |
|
|
|
596 |
|
|
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
597 |
|
|
wire mamul_m_wr_oprnd_sel = (spu_mamul_wr_mi | spu_mamul_wr_miminuslenminus1) &
|
598 |
|
|
~spu_mactl_expop;
|
599 |
|
|
assign spu_mamul_m_wr_oprnd_sel = mamul_m_wr_oprnd_sel | spu_maaeqb_m_wr_oprnd_sel;
|
600 |
|
|
|
601 |
|
|
wire mamul_me_wr_oprnd_sel = (spu_mamul_wr_mi | spu_mamul_wr_miminuslenminus1) &
|
602 |
|
|
spu_mactl_expop;
|
603 |
|
|
assign spu_mamul_me_wr_oprnd_sel = mamul_me_wr_oprnd_sel | spu_maaeqb_me_wr_oprnd_sel;
|
604 |
|
|
|
605 |
|
|
|
606 |
|
|
|
607 |
|
|
wire mamul_m_wr_oprnd2_wen = (spu_mamul_wr_mi_oprnd2_wenbyp |
|
608 |
|
|
spu_mamul_wr_miminuslenminus1_oprnd2_wenbyp) &
|
609 |
|
|
~spu_mactl_expop;
|
610 |
|
|
wire mamul_me_wr_oprnd2_wen = (spu_mamul_wr_mi_oprnd2_wenbyp |
|
611 |
|
|
spu_mamul_wr_miminuslenminus1_oprnd2_wenbyp) &
|
612 |
|
|
spu_mactl_expop;
|
613 |
|
|
|
614 |
|
|
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
615 |
|
|
|
616 |
|
|
//assign spu_mamul_i_ptr_sel = (spu_mamul_rd_ai | spu_mamul_wr_mi) | spu_maaeqb_i_ptr_sel;
|
617 |
|
|
assign spu_mamul_i_ptr_sel = spu_mamul_rd_ai ;
|
618 |
|
|
assign spu_mamul_iminus1_ptr_sel = spu_mamul_wr_mi | spu_maaeqb_iminus1_ptr_sel ;
|
619 |
|
|
|
620 |
|
|
assign spu_mamul_j_ptr_sel = (spu_mamul_rd_aj | spu_mamul_rd_mj) | spu_maaeqb_j_ptr_sel;
|
621 |
|
|
|
622 |
|
|
wire mamul_iminusj_ptr_sel =
|
623 |
|
|
//(spu_mamul_rd_biminusj | spu_mamul_rd_niminusj) & ~(spu_mamul_rd_aj | spu_mamul_rd_mj);
|
624 |
|
|
(spu_mamul_rd_biminusj | spu_mamul_rd_niminusj) ;
|
625 |
|
|
assign spu_mamul_iminusj_ptr_sel = mamul_iminusj_ptr_sel | spu_maaeqb_iminusj_ptr_sel;
|
626 |
|
|
|
627 |
|
|
|
628 |
|
|
assign spu_mamul_iminuslenminus1_sel = spu_mamul_wr_miminuslenminus1 | spu_maaeqb_iminuslenminus1_sel;
|
629 |
|
|
|
630 |
|
|
// ---------------------------------------------------------------
|
631 |
|
|
// ---------------------------------------------------------------
|
632 |
|
|
// request to mul unit when asserted
|
633 |
|
|
/*
|
634 |
|
|
wire iloop_or_req_d;
|
635 |
|
|
wire iloop_or_req = (cur_iloopb_state | cur_nprime_state | cur_iloopn_state)&
|
636 |
|
|
~mul_spu_ack;
|
637 |
|
|
dff_s #(1) iloop_dly_req_ff (
|
638 |
|
|
.din(iloop_or_req) ,
|
639 |
|
|
.q(iloop_or_req_d),
|
640 |
|
|
.clk (rclk), .se(se), .si(), .so());
|
641 |
|
|
assign spu_mul_req_vld = (cur_jloopb_state | cur_jloopn_state | iloop_or_req_d) ;
|
642 |
|
|
*/
|
643 |
|
|
|
644 |
|
|
|
645 |
|
|
wire mamul_mul_req_vld_pre = nxt_jloopb_state | nxt_jloopn_state | nxt_iloopb_state |
|
646 |
|
|
nxt_nprime_state | nxt_iloopn_state ;
|
647 |
|
|
|
648 |
|
|
dffr_s #(1) mamul_mul_req_vld_ff (
|
649 |
|
|
.din(mamul_mul_req_vld_pre) ,
|
650 |
|
|
.q(mamul_mul_req_vld),
|
651 |
|
|
.rst(state_reset), .clk (rclk), .se(se), .si(), .so());
|
652 |
|
|
|
653 |
|
|
/*
|
654 |
|
|
wire mamul_mul_req_vld = cur_jloopb_state | cur_jloopn_state | cur_iloopb_state |
|
655 |
|
|
cur_nprime_state | cur_iloopn_state ;
|
656 |
|
|
*/
|
657 |
|
|
|
658 |
|
|
assign spu_mul_req_vld = mamul_mul_req_vld | spu_maaeqb_mul_req_vld;
|
659 |
|
|
|
660 |
|
|
// ---------------------------------------------------------------
|
661 |
|
|
|
662 |
|
|
assign spu_mul_areg_shf = cur_accumshft_state | spu_maaeqb_mul_areg_shf;
|
663 |
|
|
// ---------------------------------------------------------------
|
664 |
|
|
|
665 |
|
|
/*
|
666 |
|
|
wire oprnd2_sel = mamul_a_rd_oprnd_sel | mamul_ax_rd_oprnd_sel |
|
667 |
|
|
mamul_m_rd_oprnd_sel | mamul_me_rd_oprnd_sel) &
|
668 |
|
|
*/
|
669 |
|
|
|
670 |
|
|
wire oprnd2_sel = nxt_jloopa_state | nxt_iloopa_state | nxt_jloopm_state ;
|
671 |
|
|
|
672 |
|
|
wire oprnd2_sel_q;
|
673 |
|
|
dff_s #(1) oprnd2_wen_ff (
|
674 |
|
|
.din(oprnd2_sel) ,
|
675 |
|
|
.q(oprnd2_sel_q),
|
676 |
|
|
.clk (rclk), .se(se), .si(), .so());
|
677 |
|
|
|
678 |
|
|
assign spu_mamul_oprnd2_wen = oprnd2_sel_q | mamul_m_wr_oprnd2_wen | mamul_me_wr_oprnd2_wen |
|
679 |
|
|
spu_mared_oprnd2_wen |
|
680 |
|
|
spu_maaeqb_oprnd2_wen;
|
681 |
|
|
|
682 |
|
|
assign spu_mamul_oprnd2_bypass = mamul_m_wr_oprnd2_wen | mamul_me_wr_oprnd2_wen |
|
683 |
|
|
spu_maaeqb_oprnd2_bypass;
|
684 |
|
|
|
685 |
|
|
|
686 |
|
|
//assign spu_mamul_oprnd1_sel = cur_nprime_state | spu_maaeqb_oprnd1_sel; // only select nprime if set
|
687 |
|
|
|
688 |
|
|
// ---------------------------------------------------------------
|
689 |
|
|
assign spu_mul_acc = (mamul_mul_req_vld & ~cur_nprime_state) | spu_maaeqb_mul_acc;
|
690 |
|
|
|
691 |
|
|
// ---------------------------------------------------------------
|
692 |
|
|
// ---------------------------------------------------------------
|
693 |
|
|
// ---------------------------------------------------------------
|
694 |
|
|
|
695 |
|
|
|
696 |
|
|
wire select_mamul = ~cur_idle_state;
|
697 |
|
|
|
698 |
|
|
|
699 |
|
|
wire spu_mamul_memrd4op1 = spu_mamul_rd_biminusj | spu_mamul_rd_b0 | spu_mamul_rd_n0 |
|
700 |
|
|
spu_mamul_rd_niminusj;
|
701 |
|
|
|
702 |
|
|
wire spu_mamul_memrd4op1_q;
|
703 |
|
|
dff_s #(1) spu_mamul_memrd4op1_ff (
|
704 |
|
|
.din(spu_mamul_memrd4op1) ,
|
705 |
|
|
.q(spu_mamul_memrd4op1_q),
|
706 |
|
|
.clk (rclk), .se(se), .si(), .so());
|
707 |
|
|
|
708 |
|
|
|
709 |
|
|
wire [1:0] spu_mamul_oprnd1_mxsel;
|
710 |
|
|
assign spu_mamul_oprnd1_mxsel[0] = (select_mamul & (~cur_nprime_state & ~spu_mamul_memrd4op1_q)) |
|
711 |
|
|
(~select_mamul & spu_maaeqb_oprnd1_mxsel[0]) ;
|
712 |
|
|
assign spu_mamul_oprnd1_mxsel[1] = (select_mamul & (~cur_nprime_state & spu_mamul_memrd4op1_q)) |
|
713 |
|
|
(~select_mamul & spu_maaeqb_oprnd1_mxsel[1]);
|
714 |
|
|
//assign spu_mamul_oprnd1_mxsel[2] = (select_mamul & cur_nprime_state) | (~select_mamul & spu_maaeqb_oprnd1_mxsel[2]);
|
715 |
|
|
|
716 |
|
|
|
717 |
|
|
wire [2:0] spu_mamul_oprnd1_mxsel_ps;
|
718 |
|
|
assign spu_mamul_oprnd1_mxsel_ps[0] = spu_mamul_oprnd1_mxsel[0];
|
719 |
|
|
assign spu_mamul_oprnd1_mxsel_ps[1] = ~spu_mamul_oprnd1_mxsel[0] & spu_mamul_oprnd1_mxsel[1];
|
720 |
|
|
assign spu_mamul_oprnd1_mxsel_ps[2] = ~spu_mamul_oprnd1_mxsel[0] & ~spu_mamul_oprnd1_mxsel[1];
|
721 |
|
|
|
722 |
|
|
|
723 |
|
|
assign spu_mamul_oprnd1_mxsel_l = ~spu_mamul_oprnd1_mxsel_ps;
|
724 |
|
|
|
725 |
|
|
assign spu_mamul_oprnd1_wen = spu_mamul_memrd4op1_q | spu_maaeqb_oprnd1_wen;
|
726 |
|
|
|
727 |
|
|
endmodule
|