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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: sparc_tlu_intctl.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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////////////////////////////////////////////////////////////////////////
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/*
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// Module Name: sparc_tlu_intctl
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// Description:
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// Contains the code for receiving interrupts from the crossbar,
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// and sending interrupts out to other processors through the corssbar.
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// The interrupt receive register (INRR, asi=0x49/VA=0), incoming
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// vector register (INVR, asi=0x7f/VA=0x40), and interrupt vector
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// dispatch register (INDR, asi=0x77/VA=0) are implemented in this
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// block. This block also initiates thread reset/wake up when a
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// reset packet is received.
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//
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*/
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`include "iop.h"
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// from intdp.v for now
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`define INT_THR_HI 12
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////////////////////////////////////////////////////////////////////////
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// Local header file includes / local defines
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////////////////////////////////////////////////////////////////////////
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`include "tlu.h"
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module sparc_tlu_intctl(/*AUTOARG*/
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// Outputs
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so, int_rst_l, tlu_ifu_hwint_i3, tlu_ifu_rstthr_i2, tlu_ifu_rstint_i2,
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tlu_ifu_nukeint_i2, tlu_ifu_resumint_i2, tlu_ifu_pstate_ie,
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int_tlu_longop_done, inc_ind_ld_int_i1, inc_indr_req_valid,
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inc_ind_rstthr_i1, // inc_ind_asi_thr, inc_ind_asi_wr_inrr,
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// inc_ind_asi_rd_invr, inc_ind_asi_inrr, inc_ind_asi_wr_indr,
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inc_ind_indr_grant, inc_ind_thr_m, tlu_lsu_int_ld_ill_va_w2,
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inc_indr_req_thrid, tlu_asi_data_nf_vld_w2, tlu_asi_rdata_mxsel_g,
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// Inputs
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// modified to abide to the Niagara reset methodology
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// clk, se, si, reset, const_cpuid, lsu_tlu_cpx_vld, lsu_tlu_cpx_req,
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rclk, se, sehold, si, rst_tri_en, arst_l, grst_l, const_cpuid,
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lsu_tlu_cpx_vld, lsu_tlu_cpx_req, lsu_tlu_pcxpkt_ack, tlu_ld_data_vld_g,
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ind_inc_thrid_i1, ind_inc_type_i1, tlu_int_asi_vld, tlu_int_asi_load,
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tlu_int_asi_store, tlu_int_asi_thrid, tlu_int_asi_state, tlu_int_tid_m,
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tlu_int_pstate_ie, int_pending_i2_l, // indr_inc_rst_pkt, tlu_int_redmode,
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tlu_asi_queue_rd_vld_g, tlu_va_ill_g); // tlu_flush_all_w2
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//
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// modified to abide to the Niagara reset methodology
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// input clk, se, si, reset;
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input rclk, se, si;
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input arst_l, grst_l;
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input sehold;
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input rst_tri_en;
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input [3:0] const_cpuid;
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input lsu_tlu_cpx_vld; // cpx from lsu
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input [3:0] lsu_tlu_cpx_req; // cpx req type
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// the flush bit is included in lsu_tlu_cpx_vld
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// input lsu_tlu_cpx_nc;
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input lsu_tlu_pcxpkt_ack;
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// removed unused pins
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// input [`INT_THR_HI:0] lsu_tlu_st_rs3_data_g;
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// input lsu_tlu_pmode;
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// input [3:0] tlu_int_sftint_pend;
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input [4:0] ind_inc_thrid_i1; // connect to lsu_tlu_intpkt[12:8]
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input [1:0] ind_inc_type_i1; // connect to lsu_tlu_intpkt[16]
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input tlu_int_asi_vld;
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input tlu_int_asi_load; // read enable
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input tlu_int_asi_store; // write enable
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input [1:0] tlu_int_asi_thrid; // thread making asi request
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input [7:0] tlu_int_asi_state; // asi to be read/written
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// input tlu_scpd_rd_vld_g; // rdata vld from scratchpad
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// removed no longer necessary
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// input tlu_va_all_zero_g; // va address - all zero
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input tlu_va_ill_g; // illega va range
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input tlu_asi_queue_rd_vld_g; // rdata vld from asi queues
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input tlu_ld_data_vld_g; // rdata vld from asi queues
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// input tlu_flush_all_w2; // flush pipe from tcl
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input [1:0] tlu_int_tid_m;
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input [3:0] tlu_int_pstate_ie;
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// input [3:0] tlu_int_redmode;
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// from int_dp
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input [3:0] int_pending_i2_l; // uncleared interrupt
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// input indr_inc_rst_pkt;
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// added for timing
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// input [1:0] lsu_tlu_rst_pkt;
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output int_rst_l, so;
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// to ifu
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output [3:0] tlu_ifu_hwint_i3; // interrupt
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output [3:0] tlu_ifu_rstthr_i2; // reset, nuke or resume
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output tlu_ifu_rstint_i2; // reset msg
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output tlu_ifu_nukeint_i2; // idle/suspend message
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output tlu_ifu_resumint_i2;// resume message
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output [3:0] tlu_ifu_pstate_ie;
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output [3:0] int_tlu_longop_done;
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//
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// removed - IFU will derive the signal locally
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// output [3:0] tlu_ifu_int_activate_i3;// wake up signal for thread
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// to int_dp
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output [3:0] inc_ind_ld_int_i1; // ld new interrupt
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output [3:0] inc_ind_rstthr_i1; // ld new rst vector
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// convert the signal back to non-inverting version for grape
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// output [3:0] inc_ind_asi_thr_l; // choose asi op thread
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// output [3:0] inc_ind_asi_thr; // choose asi op thread
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// output [3:0] inc_ind_asi_wr_inrr; // write to INRR (per thread)
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// output [3:0] inc_ind_asi_wr_indr; // write to INDR
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// output [3:0] inc_ind_asi_rd_invr; // read INVR and
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// reset corr. bit in INRR
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// obsolete output
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// output inc_ind_asi_inrr; // choose which reg to read
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// convert the signal back to non-inverting version for grape
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// output [3:0] inc_ind_indr_grant_l; // move on to next pcx pkt
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output [3:0] inc_ind_indr_grant; // move on to next pcx pkt
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// convert the signal back to non-inverting version for grape
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// output [3:0] inc_ind_thr_m_l; // M stage thread
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output [3:0] inc_ind_thr_m; // M stage thread
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// pcx pkt fields
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output inc_indr_req_valid; // valid bit for PCX int pkt
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output [1:0] inc_indr_req_thrid; // thread sending pcx int pkt
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// to tlu
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// output tlu_lsu_int_ldxa_vld_w2; // valid asi data from int or scpd
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output tlu_asi_data_nf_vld_w2; // valid asi data from int or scpd
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output tlu_lsu_int_ld_ill_va_w2; // illega va range - load
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// to intdp
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output [3:0] tlu_asi_rdata_mxsel_g; // mux selects to the asi rdata
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// local signals
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// wire indr_inc_rst_pkt;
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wire inc_ind_asi_inrr; // choose which reg to read
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wire int_tlu_asi_data_vld_g, int_tlu_asi_data_vld_w2;
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wire int_ld_ill_va_g, int_ld_ill_va_w2;
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wire hw_int_i1,
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rst_int_i1,
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nuke_int_i1,
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resum_int_i1;
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wire [3:0] int_thr_i1,
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rstthr_i1,
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asi_thr;
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wire [3:0] int_pending_i2;
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// int_activate_i2;
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wire asi_write,
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asi_read,
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asi_invr,
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asi_indr;
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wire [3:0] indr_vld,
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indr_rst,
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indr_vld_next,
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indr_grant;
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// added for bug 3945
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wire [3:0] indr_req_vec;
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wire indr_req_valid_disable;
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// wire [3:0] int_or_redrst;
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wire [3:0] intd_done;
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// wire red_thread, valid_dest;
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wire local_rst; // local reset
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wire local_rst_l; // local reset
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wire clk; // local clk
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//
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// Code Starts Here
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//
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//=========================================================================================
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// reset
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//=========================================================================================
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dffrl_async dffrl_local_rst_l(
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.din (grst_l),
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.clk (clk),
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.rst_l(arst_l),
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.q (local_rst_l),
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.se (se),
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.si (),
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.so ()
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);
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assign local_rst = ~local_rst_l;
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assign int_rst_l = local_rst_l;
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// create local clk
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assign clk = rclk;
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//-------------------------------------
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// Basic Operation
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//-------------------------------------
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sink s1(const_cpuid[3]);
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assign tlu_ifu_pstate_ie = tlu_int_pstate_ie;
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// process cpx interrupt type
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// int = 00
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// the flush bit from cpx packet is now included in the
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// lsu_tlu_cpx_vld qualification
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assign hw_int_i1 = (lsu_tlu_cpx_vld &
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// (lsu_tlu_cpx_req == `INT_RET) & ~lsu_tlu_cpx_nc &
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(lsu_tlu_cpx_req == `INT_RET) &
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(ind_inc_thrid_i1[4:2] == const_cpuid[2:0])) ?
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~ind_inc_type_i1[1] & ~ind_inc_type_i1[0] :
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1'b0;
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//reset = 01
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// the flush bit from cpx packet is now included in the
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// lsu_tlu_cpx_vld qualification
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assign rst_int_i1 = (lsu_tlu_cpx_vld &
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// (lsu_tlu_cpx_req == `INT_RET) && ~lsu_tlu_cpx_nc &
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(lsu_tlu_cpx_req == `INT_RET) &
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(ind_inc_thrid_i1[4:2] == const_cpuid[2:0])) ?
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~ind_inc_type_i1[1] & ind_inc_type_i1[0] :
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1'b0;
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// idle/nuke = 10
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// the flush bit from cpx packet is now included in the
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// lsu_tlu_cpx_vld qualification
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assign nuke_int_i1 = (lsu_tlu_cpx_vld &
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// (lsu_tlu_cpx_req == `INT_RET) & ~lsu_tlu_cpx_nc &
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(lsu_tlu_cpx_req == `INT_RET) &
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(ind_inc_thrid_i1[4:2] == const_cpuid[2:0])) ?
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ind_inc_type_i1[1] & ~ind_inc_type_i1[0] :
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1'b0;
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// resume = 11
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// the flush bit from cpx packet is now included in the
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// lsu_tlu_cpx_vld qualification
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assign resum_int_i1 = (lsu_tlu_cpx_vld &
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// (lsu_tlu_cpx_req == `INT_RET) & ~lsu_tlu_cpx_nc &
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(lsu_tlu_cpx_req == `INT_RET) &
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(ind_inc_thrid_i1[4:2] == const_cpuid[2:0])) ?
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ind_inc_type_i1[1] & ind_inc_type_i1[0] :
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1'b0;
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dffr_s #1 rstint_ff(.din (rst_int_i1),
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.q (tlu_ifu_rstint_i2),
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.clk (clk),
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//
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// modified to abide to the Niagara reset methodology
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// .rst (reset),
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.rst (local_rst),
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.se (se), .si(), .so());
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dffr_s #1 nukint_ff(.din (nuke_int_i1),
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.q (tlu_ifu_nukeint_i2),
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.clk (clk),
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//
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// modified to abide to the Niagara reset methodology
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// .rst (reset),
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.rst (local_rst),
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.se (se), .si(), .so());
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dffr_s #1 resint_ff(.din (resum_int_i1),
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.q (tlu_ifu_resumint_i2),
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.clk (clk),
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//
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// modified to abide to the Niagara reset methodology
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// .rst (reset),
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.rst (local_rst),
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.se (se), .si(), .so());
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// decode int thread id
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assign int_thr_i1[0] = ~ind_inc_thrid_i1[1] & ~ind_inc_thrid_i1[0];
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assign int_thr_i1[1] = ~ind_inc_thrid_i1[1] & ind_inc_thrid_i1[0];
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assign int_thr_i1[2] = ind_inc_thrid_i1[1] & ~ind_inc_thrid_i1[0];
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assign int_thr_i1[3] = ind_inc_thrid_i1[1] & ind_inc_thrid_i1[0];
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assign inc_ind_ld_int_i1 = {4{hw_int_i1}} & int_thr_i1;
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assign inc_ind_rstthr_i1 = {4{rst_int_i1}} & int_thr_i1;
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assign rstthr_i1 = {4{rst_int_i1 | nuke_int_i1 | resum_int_i1}}
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& int_thr_i1;
|
301 |
|
|
|
302 |
|
|
// decode thr_m
|
303 |
|
|
// convert the signal back to non-inverting version for grape
|
304 |
|
|
/*
|
305 |
|
|
assign inc_ind_thr_m_l[0] = ~(~tlu_int_tid_m[1] & ~tlu_int_tid_m[0]);
|
306 |
|
|
assign inc_ind_thr_m_l[1] = ~(~tlu_int_tid_m[1] & tlu_int_tid_m[0]);
|
307 |
|
|
assign inc_ind_thr_m_l[2] = ~( tlu_int_tid_m[1] & ~tlu_int_tid_m[0]);
|
308 |
|
|
assign inc_ind_thr_m_l[3] = ~( tlu_int_tid_m[1] & tlu_int_tid_m[0]);
|
309 |
|
|
*/
|
310 |
|
|
|
311 |
|
|
assign inc_ind_thr_m[0] = ~tlu_int_tid_m[1] & ~tlu_int_tid_m[0];
|
312 |
|
|
assign inc_ind_thr_m[1] = ~tlu_int_tid_m[1] & tlu_int_tid_m[0];
|
313 |
|
|
assign inc_ind_thr_m[2] = tlu_int_tid_m[1] & ~tlu_int_tid_m[0];
|
314 |
|
|
assign inc_ind_thr_m[3] = tlu_int_tid_m[1] & tlu_int_tid_m[0];
|
315 |
|
|
|
316 |
|
|
|
317 |
|
|
// Interrupt continues to be signalled even 1 cycle after read is
|
318 |
|
|
// done. This should not be a problem, since the lsu will probably
|
319 |
|
|
// burn one cycle to complete the read by forwarding it to the reg
|
320 |
|
|
// file. Otherwise, just burn another cycle in the IFU before
|
321 |
|
|
// starting the thread (this is also done right now).
|
322 |
|
|
|
323 |
|
|
assign int_pending_i2 = ~int_pending_i2_l;
|
324 |
|
|
|
325 |
|
|
// removed IFU will derive the siganl locally
|
326 |
|
|
/*
|
327 |
|
|
assign int_activate_i2 = ~int_pending_i2_l | tlu_int_sftint_pend;
|
328 |
|
|
// send message to SWL to wake up thread if it is halted
|
329 |
|
|
dff_s #4 act_signal_reg(.din (int_activate_i2[3:0]),
|
330 |
|
|
.q (tlu_ifu_int_activate_i3[3:0]),
|
331 |
|
|
.clk (clk),
|
332 |
|
|
.se (se), .si(), .so());
|
333 |
|
|
*/
|
334 |
|
|
|
335 |
|
|
// ask IFU to schedule interrupt
|
336 |
|
|
dff_s #4 int_signal_reg(.din (int_pending_i2[3:0]),
|
337 |
|
|
.q (tlu_ifu_hwint_i3[3:0]),
|
338 |
|
|
.clk (clk),
|
339 |
|
|
.se (se), .si(), .so());
|
340 |
|
|
|
341 |
|
|
dff_s #4 rst_signal_reg(.din (rstthr_i1[3:0]),
|
342 |
|
|
.q (tlu_ifu_rstthr_i2[3:0]),
|
343 |
|
|
.clk (clk),
|
344 |
|
|
.se (se), .si(), .so());
|
345 |
|
|
|
346 |
|
|
|
347 |
|
|
//----------------------------------
|
348 |
|
|
// ASI Registers
|
349 |
|
|
//----------------------------------
|
350 |
|
|
//ASI_INTR_RECEIVE: 0x72
|
351 |
|
|
//ASI_UDB_INTR_W: 0x73
|
352 |
|
|
//ASI_UDB_INTR_R: 0x74
|
353 |
|
|
//ASI_MESSAGE_MASK: 0x7D
|
354 |
|
|
|
355 |
|
|
// decode asi thread
|
356 |
|
|
assign asi_thr[0] = ~tlu_int_asi_thrid[1] & ~tlu_int_asi_thrid[0];
|
357 |
|
|
assign asi_thr[1] = ~tlu_int_asi_thrid[1] & tlu_int_asi_thrid[0];
|
358 |
|
|
assign asi_thr[2] = tlu_int_asi_thrid[1] & ~tlu_int_asi_thrid[0];
|
359 |
|
|
assign asi_thr[3] = tlu_int_asi_thrid[1] & tlu_int_asi_thrid[0];
|
360 |
|
|
|
361 |
|
|
// convert the signal back to non-inverting version for grape
|
362 |
|
|
// assign inc_ind_asi_thr_l = ~asi_thr;
|
363 |
|
|
// assign inc_ind_asi_thr = asi_thr;
|
364 |
|
|
|
365 |
|
|
// read or write op
|
366 |
|
|
assign asi_write = tlu_int_asi_vld & tlu_int_asi_store;
|
367 |
|
|
assign asi_read = tlu_int_asi_vld & tlu_int_asi_load;
|
368 |
|
|
|
369 |
|
|
// decode asi target
|
370 |
|
|
// ASI_INTR_RECEIVE
|
371 |
|
|
assign inc_ind_asi_inrr = ~tlu_int_asi_state[7] &
|
372 |
|
|
tlu_int_asi_state[6] &
|
373 |
|
|
tlu_int_asi_state[5] &
|
374 |
|
|
tlu_int_asi_state[4] &
|
375 |
|
|
~tlu_int_asi_state[3] &
|
376 |
|
|
~tlu_int_asi_state[2] &
|
377 |
|
|
tlu_int_asi_state[1] &
|
378 |
|
|
~tlu_int_asi_state[0]; // 0x72
|
379 |
|
|
|
380 |
|
|
// need to also check if VA=0x40
|
381 |
|
|
// what else is mapped to this asi?
|
382 |
|
|
// ASI_UDB_INTR_R
|
383 |
|
|
assign asi_invr = ~tlu_int_asi_state[7] &
|
384 |
|
|
tlu_int_asi_state[6] &
|
385 |
|
|
tlu_int_asi_state[5] &
|
386 |
|
|
tlu_int_asi_state[4] &
|
387 |
|
|
~tlu_int_asi_state[3] &
|
388 |
|
|
tlu_int_asi_state[2] &
|
389 |
|
|
~tlu_int_asi_state[1] &
|
390 |
|
|
~tlu_int_asi_state[0]; // 0x74
|
391 |
|
|
|
392 |
|
|
// VA<63:19>=0 is not checked
|
393 |
|
|
// ASI_UDB_INTR_W
|
394 |
|
|
assign asi_indr = ~tlu_int_asi_state[7] &
|
395 |
|
|
tlu_int_asi_state[6] &
|
396 |
|
|
tlu_int_asi_state[5] &
|
397 |
|
|
tlu_int_asi_state[4] &
|
398 |
|
|
~tlu_int_asi_state[3] &
|
399 |
|
|
~tlu_int_asi_state[2] &
|
400 |
|
|
tlu_int_asi_state[1] &
|
401 |
|
|
tlu_int_asi_state[0]; // 0x73
|
402 |
|
|
/*
|
403 |
|
|
// ASI_MESSAGE_MASK_REG
|
404 |
|
|
// not implemented any more
|
405 |
|
|
assign inc_ind_asi_wr_inrr = asi_thr & {4{inc_ind_asi_inrr & asi_write}};
|
406 |
|
|
assign inc_ind_asi_wr_indr = asi_thr & {4{asi_indr & asi_write}};
|
407 |
|
|
assign inc_ind_asi_rd_invr = asi_thr & {4{asi_invr & asi_read}};
|
408 |
|
|
|
409 |
|
|
assign red_thread = (tlu_int_redmode[0] & asi_thr[0] |
|
410 |
|
|
tlu_int_redmode[1] & asi_thr[1] |
|
411 |
|
|
tlu_int_redmode[2] & asi_thr[2] |
|
412 |
|
|
tlu_int_redmode[3] & asi_thr[3]);
|
413 |
|
|
*/
|
414 |
|
|
// modified for bug 2109
|
415 |
|
|
// modified for one-hot mux problem and support of macro test
|
416 |
|
|
//
|
417 |
|
|
assign tlu_asi_rdata_mxsel_g[0] =
|
418 |
|
|
asi_invr & ~(rst_tri_en | sehold);
|
419 |
|
|
assign tlu_asi_rdata_mxsel_g[1] =
|
420 |
|
|
inc_ind_asi_inrr & ~(rst_tri_en | asi_invr | sehold);
|
421 |
|
|
assign tlu_asi_rdata_mxsel_g[2] =
|
422 |
|
|
~((|tlu_asi_rdata_mxsel_g[1:0]) | tlu_asi_rdata_mxsel_g[3]);
|
423 |
|
|
assign tlu_asi_rdata_mxsel_g[3] =
|
424 |
|
|
tlu_asi_queue_rd_vld_g & ~(rst_tri_en | asi_invr | sehold |
|
425 |
|
|
inc_ind_asi_inrr);
|
426 |
|
|
//
|
427 |
|
|
assign int_tlu_asi_data_vld_g =
|
428 |
|
|
((asi_invr | inc_ind_asi_inrr) & asi_read) | tlu_ld_data_vld_g;
|
429 |
|
|
|
430 |
|
|
|
431 |
|
|
dffr_s dffr_int_tlu_asi_data_vld_w2 (
|
432 |
|
|
.din (int_tlu_asi_data_vld_g),
|
433 |
|
|
.q (int_tlu_asi_data_vld_w2),
|
434 |
|
|
.clk (clk),
|
435 |
|
|
.rst (local_rst),
|
436 |
|
|
.se (1'b0),
|
437 |
|
|
.si (),
|
438 |
|
|
.so ()
|
439 |
|
|
);
|
440 |
|
|
|
441 |
|
|
// modified for timing
|
442 |
|
|
// assign tlu_lsu_int_ldxa_vld_w2 =
|
443 |
|
|
// int_tlu_asi_data_vld_w2 & ~tlu_flush_all_w2;
|
444 |
|
|
|
445 |
|
|
assign tlu_asi_data_nf_vld_w2 =
|
446 |
|
|
int_tlu_asi_data_vld_w2;
|
447 |
|
|
//
|
448 |
|
|
// illegal va range
|
449 |
|
|
//
|
450 |
|
|
/*
|
451 |
|
|
assign int_ld_ill_va_g =
|
452 |
|
|
((asi_invr | inc_ind_asi_inrr) & asi_read &
|
453 |
|
|
~tlu_va_all_zero_g) | tlu_va_ill_g;
|
454 |
|
|
*/
|
455 |
|
|
assign int_ld_ill_va_g = tlu_va_ill_g;
|
456 |
|
|
|
457 |
|
|
dffr_s dffr_tlu_lsu_int_ld_ill_va_w2 (
|
458 |
|
|
.din (int_ld_ill_va_g),
|
459 |
|
|
// .q (tlu_lsu_int_ld_ill_va_w2),
|
460 |
|
|
.q (int_ld_ill_va_w2),
|
461 |
|
|
.clk (clk),
|
462 |
|
|
.rst (local_rst),
|
463 |
|
|
.se (1'b0),
|
464 |
|
|
.si (),
|
465 |
|
|
.so ()
|
466 |
|
|
);
|
467 |
|
|
|
468 |
|
|
assign tlu_lsu_int_ld_ill_va_w2 = int_ld_ill_va_w2;
|
469 |
|
|
// Write to INDR
|
470 |
|
|
// Can send reset pkt's only in red mode
|
471 |
|
|
// modified for timing
|
472 |
|
|
// modified for bug3170
|
473 |
|
|
/*
|
474 |
|
|
assign int_or_redrst[3:0] =
|
475 |
|
|
({4{~indr_inc_rst_pkt}} | tlu_int_redmode[3:0]) &
|
476 |
|
|
asi_thr[3:0];
|
477 |
|
|
|
478 |
|
|
assign indr_vld_next[3:0] =
|
479 |
|
|
inc_ind_asi_wr_indr[3:0] & int_or_redrst[3:0] | // set
|
480 |
|
|
indr_vld[3:0] & ~indr_rst[3:0]; // reset
|
481 |
|
|
//
|
482 |
|
|
// original code
|
483 |
|
|
assign indr_vld_next[3] =
|
484 |
|
|
(asi_indr & asi_write & asi_thr[3] &
|
485 |
|
|
(~(|lsu_tlu_rst_pkt[1:0]) | tlu_int_redmode[3])) |
|
486 |
|
|
(indr_vld[3] & ~indr_rst[3]);
|
487 |
|
|
|
488 |
|
|
assign indr_vld_next[2] =
|
489 |
|
|
(asi_indr & asi_write & asi_thr[2] &
|
490 |
|
|
(~(|lsu_tlu_rst_pkt[1:0]) | tlu_int_redmode[2])) |
|
491 |
|
|
(indr_vld[2] & ~indr_rst[2]);
|
492 |
|
|
|
493 |
|
|
assign indr_vld_next[1] =
|
494 |
|
|
(asi_indr & asi_write & asi_thr[1] &
|
495 |
|
|
(~(|lsu_tlu_rst_pkt[1:0]) | tlu_int_redmode[1])) |
|
496 |
|
|
(indr_vld[1] & ~indr_rst[1]);
|
497 |
|
|
|
498 |
|
|
assign indr_vld_next[0] =
|
499 |
|
|
(asi_indr & asi_write & asi_thr[0] &
|
500 |
|
|
(~(|lsu_tlu_rst_pkt[1:0]) | tlu_int_redmode[0])) |
|
501 |
|
|
(indr_vld[0] & ~indr_rst[0]);
|
502 |
|
|
*/
|
503 |
|
|
assign indr_vld_next[3] =
|
504 |
|
|
(asi_indr & asi_write & asi_thr[3]) |
|
505 |
|
|
(indr_vld[3] & ~indr_rst[3]);
|
506 |
|
|
|
507 |
|
|
assign indr_vld_next[2] =
|
508 |
|
|
(asi_indr & asi_write & asi_thr[2]) |
|
509 |
|
|
(indr_vld[2] & ~indr_rst[2]);
|
510 |
|
|
|
511 |
|
|
assign indr_vld_next[1] =
|
512 |
|
|
(asi_indr & asi_write & asi_thr[1]) |
|
513 |
|
|
(indr_vld[1] & ~indr_rst[1]);
|
514 |
|
|
|
515 |
|
|
assign indr_vld_next[0] =
|
516 |
|
|
(asi_indr & asi_write & asi_thr[0]) |
|
517 |
|
|
(indr_vld[0] & ~indr_rst[0]);
|
518 |
|
|
|
519 |
|
|
dff_s #4 indr_vld_reg(.din (indr_vld_next[3:0]),
|
520 |
|
|
.q (indr_vld[3:0]),
|
521 |
|
|
.clk (clk),
|
522 |
|
|
.se (se), .si(), .so());
|
523 |
|
|
//
|
524 |
|
|
// modified for bug 3945
|
525 |
|
|
dffr_s dffr_indr_req_valid_disable(
|
526 |
|
|
.din (|indr_vld[3:0]),
|
527 |
|
|
.q (indr_req_valid_disable),
|
528 |
|
|
.clk (clk),
|
529 |
|
|
.rst (local_rst | lsu_tlu_pcxpkt_ack),
|
530 |
|
|
.se (se),
|
531 |
|
|
.si(),
|
532 |
|
|
.so());
|
533 |
|
|
|
534 |
|
|
dffe_s #(4) dffe_indr_req_vec(
|
535 |
|
|
.din (indr_vld_next[3:0]),
|
536 |
|
|
.q (indr_req_vec[3:0]),
|
537 |
|
|
.en (~indr_req_valid_disable),
|
538 |
|
|
.clk (clk),
|
539 |
|
|
.se (se),
|
540 |
|
|
.si(),
|
541 |
|
|
.so());
|
542 |
|
|
|
543 |
|
|
// Round robin scheduler for indr request to pcx
|
544 |
|
|
sparc_ifu_rndrob indr_sched(
|
545 |
|
|
// .req_vec (indr_vld[3:0]),
|
546 |
|
|
.req_vec (indr_req_vec[3:0]),
|
547 |
|
|
.advance (lsu_tlu_pcxpkt_ack),
|
548 |
|
|
.rst_tri_enable (rst_tri_en),
|
549 |
|
|
.clk (clk),
|
550 |
|
|
.reset (local_rst),
|
551 |
|
|
.se (se),
|
552 |
|
|
.si (si),
|
553 |
|
|
.grant_vec (indr_grant[3:0]),
|
554 |
|
|
.so ());
|
555 |
|
|
|
556 |
|
|
// convert the signal back to non-inverting version for grape
|
557 |
|
|
// modified to fix one-hot indetermination
|
558 |
|
|
assign inc_ind_indr_grant[0] =
|
559 |
|
|
~(|inc_ind_indr_grant[3:1]);
|
560 |
|
|
assign inc_ind_indr_grant[1] =
|
561 |
|
|
indr_grant[1];
|
562 |
|
|
assign inc_ind_indr_grant[2] =
|
563 |
|
|
indr_grant[2] & ~indr_grant[1];
|
564 |
|
|
assign inc_ind_indr_grant[3] =
|
565 |
|
|
indr_grant[3] & ~(|inc_ind_indr_grant[2:1]);
|
566 |
|
|
//
|
567 |
|
|
assign indr_rst[3:0] =
|
568 |
|
|
{4{local_rst}} | (indr_grant[3:0] & {4{lsu_tlu_pcxpkt_ack}});
|
569 |
|
|
assign intd_done[3:0] =
|
570 |
|
|
(indr_grant[3:0] & indr_vld[3:0] & {4{lsu_tlu_pcxpkt_ack}});
|
571 |
|
|
|
572 |
|
|
dffr_s #(4) intd_reg(
|
573 |
|
|
.din (intd_done[3:0]),
|
574 |
|
|
.q (int_tlu_longop_done[3:0]),
|
575 |
|
|
.clk (clk),
|
576 |
|
|
.rst (local_rst),
|
577 |
|
|
.se (se),
|
578 |
|
|
.si(),
|
579 |
|
|
.so());
|
580 |
|
|
|
581 |
|
|
// INDR pcx request control signals
|
582 |
|
|
// modified for bug 3945
|
583 |
|
|
// assign inc_indr_req_valid = (|indr_vld[3:0]) & ~lsu_tlu_pcxpkt_ack;
|
584 |
|
|
assign inc_indr_req_valid = indr_req_valid_disable;
|
585 |
|
|
assign inc_indr_req_thrid[1] = indr_grant[3] | indr_grant[2];
|
586 |
|
|
assign inc_indr_req_thrid[0] = indr_grant[3] | indr_grant[1];
|
587 |
|
|
|
588 |
|
|
endmodule // sparc_tlu_intctl
|