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[/] [sparc64soc/] [trunk/] [T1-CPU/] [tlu/] [tlu_mmu_ctl.v] - Blame information for rev 2

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1 2 dmitryr
// ========== Copyright Header Begin ==========================================
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// 
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// OpenSPARC T1 Processor File: tlu_mmu_ctl.v
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// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// 
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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// 
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// The above named program is distributed in the hope that it will be 
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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// General Public License for more details.
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// 
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
18
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// 
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// ========== Copyright Header End ============================================
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///////////////////////////////////////////////////////////////////////
22
/*
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//      Description:    MMU Control - I & D.
24
*/
25
////////////////////////////////////////////////////////////////////////
26
// Global header file includes
27
////////////////////////////////////////////////////////////////////////
28
`include        "sys.h" // system level definition file which contains the 
29
                                        // time scale definition
30
 
31
////////////////////////////////////////////////////////////////////////
32
// Local header file includes / local defines
33
////////////////////////////////////////////////////////////////////////
34
 
35
module tlu_mmu_ctl ( /*AUTOARG*/
36
   // Outputs
37
   dmmu_any_sfsr_wr, dmmu_sfsr_wr_en_l, dmmu_sfar_wr_en_l,
38
   immu_any_sfsr_wr, immu_sfsr_wr_en_l, immu_tsb_rd_en, tlu_tte_tag_g,
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   tlu_dtlb_rw_index_vld_g,  tlu_dtlb_rw_index_g,
40
   tlu_dtlb_data_rd_g, tlu_dtlb_tag_rd_g, tlu_itlb_rw_index_vld_g,
41
   tlu_itlb_wr_vld_g, itlb_wr_vld_g, tlu_itlb_rw_index_g,
42
   tlu_itlb_data_rd_g, tlu_itlb_tag_rd_g, tlu_idtsb_8k_ptr,
43
   tlu_dtlb_invalidate_all_g, tlu_itlb_invalidate_all_g, tlu_slxa_thrd_sel,
44
   tlu_lsu_ldxa_tid_w2, tlu_itlb_dmp_vld_g,
45
   tlu_itlb_dmp_all_g, tlu_itlb_dmp_pctxt_g, tlu_itlb_dmp_actxt_g,
46
   tlu_itlb_dmp_nctxt_g, tlu_dtlb_dmp_vld_g, tlu_dtlb_dmp_all_g,
47
   tlu_dtlb_dmp_pctxt_g, tlu_dtlb_dmp_sctxt_g, tlu_dtlb_dmp_nctxt_g,
48
   tlu_dtlb_dmp_actxt_g, tlu_idtlb_dmp_thrid_g, tlu_dmp_key_vld_g,
49
   tlu_int_asi_load, tlu_int_asi_store, tlu_int_asi_thrid,
50
   tlu_int_asi_vld, tlb_access_rst_l,
51
   tlu_lsu_stxa_ack, tlu_lsu_stxa_ack_tid, mra_wr_ptr, mra_rd_ptr,
52
   mra_wr_vld, mra_rd_vld, tag_access_wdata_sel,
53
   tlu_admp_key_sel, mra_byte_wen,
54
   tlu_tte_wr_pid_g, tlu_lsu_ldxa_async_data_vld, tlu_tte_real_g,
55
   tlu_ldxa_l1mx1_sel, tlu_ldxa_l1mx2_sel, tlu_ldxa_l2mx1_sel,
56
   lsu_ifu_inj_ack, tlu_tlb_tag_invrt_parity,  tlu_tlb_data_invrt_parity,
57
   tlu_sun4r_tte_g, so, lsu_exu_ldxa_m, tlu_lng_ltncy_en_l,
58
   tlu_tag_access_ctxt_sel_m, tlu_tsb_rd_ps0_sel, tlu_tlb_access_en_l_d1,
59
   // Inputs
60
   ifu_lsu_ld_inst_e, ifu_lsu_st_inst_e, spu_tlu_rsrv_illgl_m,
61
   lsu_tlu_dmmu_miss_g,
62
   tlu_dtsb_split_w2, tlu_dtsb_size_w2, tlu_dtag_access_w2, tlu_itsb_split_w2,
63
   tlu_itsb_size_w2, tlu_ctxt_cfg_w2, lsu_tlu_st_rs3_data_g,
64
   lsu_tlu_st_rs3_data_b48_g, lsu_tlu_st_rs3_data_b12t0_g,
65
   ifu_tlu_immu_miss_m, ifu_lsu_thrid_s,
66
   ifu_lsu_alt_space_e, lsu_tlu_dtlb_done,
67
   ifu_tlu_itlb_done, lsu_tlu_tlb_asi_state_m, lsu_tlu_tlb_ldst_va_m,
68
   lsu_tlu_tlb_ld_inst_m, lsu_tlu_tlb_st_inst_m,
69
   lsu_tlu_tlb_access_tid_m, dmmu_sfsr_trp_wr,
70
   immu_sfsr_trp_wr, lsu_tlu_daccess_excptn_g,
71
   lsu_tlu_daccess_prot_g,
72
   lsu_pid_state0, lsu_pid_state1, lsu_pid_state2, lsu_pid_state3,
73
   lsu_tlu_nucleus_ctxt_m, lsu_tlu_tte_pg_sz_g, ifu_lsu_error_inj,
74
   ifu_tlu_alt_space_d, ifu_lsu_imm_asi_d,
75
   ifu_lsu_memref_d, lsu_asi_reg0, lsu_asi_reg1, lsu_asi_reg2,
76
   lsu_asi_reg3, exu_mmu_early_va_e, rclk, arst_l, grst_l,
77
   si,se,ifu_tlu_flush_m,tlu_mmu_early_flush_pipe_w,lsu_mmu_early_flush_w,
78
   tlu_tag_access_ctxt_g, tlu_lsu_tl_zero,
79
   exu_tlu_va_oor_jl_ret_m, exu_tlu_va_oor_m, tlu_lsu_pstate_am, tlu_tsb_base_w2_d1,
80
   lsu_mmu_flush_pipe_w, ifu_tlu_inst_vld_m, ifu_mmu_trap_m, ffu_tlu_ill_inst_m,
81
   exu_lsu_priority_trap_m, sehold, rst_tri_en, tlu_itag_acc_sel_g, lsu_mmu_defr_trp_taken_g,
82
   ifu_tlu_priv_violtn_m
83
   ) ;
84
 
85
 
86
/*AUTOINPUT*/
87
// Beginning of automatic inputs (from unused autoinst inputs)
88
// End of automatics
89
 
90
input                   ifu_lsu_ld_inst_e;      // inst_is_load (src-decode)
91
input                   ifu_lsu_st_inst_e;      // inst is store (src-decode)
92
input                   lsu_tlu_dmmu_miss_g ;   // ld/st misses in dtlb.
93
input                   spu_tlu_rsrv_illgl_m ;
94
 
95
input                   tlu_itag_acc_sel_g ;
96
input                   lsu_mmu_defr_trp_taken_g ;
97
 
98
// The timing on these signals can be changed to any earlier stage.
99
// For both SPARC_HPV_EN and non-SPARC_HPV_EN - tsb,tag-access 
100
// dtsb maps to ps0. itsb maps to ps1.
101
input  [47:13]          tlu_tsb_base_w2_d1 ;
102
//input  [47:13]                tlu_dtsb_base_w2 ;
103
input                   tlu_dtsb_split_w2 ;
104
input  [3:0]             tlu_dtsb_size_w2 ;
105
input  [47:13]          tlu_dtag_access_w2 ;    // used to represent both i/d.
106
//input  [47:13]                tlu_itsb_base_w2 ;
107
input                   tlu_itsb_split_w2 ;
108
input  [3:0]             tlu_itsb_size_w2 ;
109
 
110
// For SPARC_HPV_EN - BEGIN
111
input  [5:0]             tlu_ctxt_cfg_w2 ;       // i/d context zero/non-zero config.
112
//input                         tlu_tag_access_nctxt_g ;// tag-access contains nucleus context.
113
// For SPARC_HPV_EN - END
114
 
115
input   [62:61]         lsu_tlu_st_rs3_data_g ;     // Page Size (1,0) bits of TTE
116
input                   lsu_tlu_st_rs3_data_b48_g ; // Page Size (2)   bits of TTE
117
//input   [2:0]           lsu_tlu_st_rs3_data_b10t8_g ; // ps1 of ctxt-cfg
118
input   [12:0]          lsu_tlu_st_rs3_data_b12t0_g ;
119
//input   [2:0]           lsu_tlu_st_rs3_data_b2t0_g ; // sun4v tte size
120
input                   ifu_tlu_immu_miss_m ;
121
input   [1:0]           ifu_lsu_thrid_s ;        // Thread id.
122
input                   ifu_lsu_alt_space_e ;   // alt-space access
123
input                   lsu_tlu_dtlb_done ; // dtlb rd/wr/dmp complete
124
input                   ifu_tlu_itlb_done ; // itlb rd/wr/dmp complete
125
//input                 int_tlu_asi_data_vld ;  // asi return vld for int blk
126
//input                 int_tlu_ldxa_illgl_va ; // int asi has illgl va
127
input  [7:0]             lsu_tlu_tlb_asi_state_m ;
128
input  [10:0]           lsu_tlu_tlb_ldst_va_m ;
129
input                   lsu_tlu_tlb_ld_inst_m ;
130
input                   lsu_tlu_tlb_st_inst_m ;
131
input  [1:0]             lsu_tlu_tlb_access_tid_m ;
132
input                   ifu_tlu_flush_m ;
133
input                   tlu_mmu_early_flush_pipe_w ;
134
input                   lsu_mmu_early_flush_w ;
135
input   [3:0]    dmmu_sfsr_trp_wr ;
136
input   [3:0]    immu_sfsr_trp_wr ;
137
//input                         tlu_inst_vld_m ;        // qualified inst vld
138
input                   lsu_tlu_daccess_excptn_g ; // data access exception 
139
input                   lsu_tlu_daccess_prot_g ;// data access protection
140
                                                // obsolete with SPARC_HPV_EN !!!
141
//input                 lsu_tlu_asi_rd_unc ;    // uncorrectable error for tlb rd
142
input   [2:0]    lsu_pid_state0 ;        // pid thread0 ; global use
143
input   [2:0]    lsu_pid_state1 ;        // pid thread1 ; global use
144
input   [2:0]    lsu_pid_state2 ;        // pid thread2 ; global use
145
input   [2:0]    lsu_pid_state3 ;        // pid thread3 ; global use
146
 
147
input                   lsu_tlu_nucleus_ctxt_m ;// access is nucleus context
148
input   [2:0]            lsu_tlu_tte_pg_sz_g ;   // page-size of tte 
149
 
150
input   [3:0]           ifu_lsu_error_inj ;     // inject parity error into tlb
151
 
152
// BEGIN - MMU_ASI_RD_CHANGE
153
// !! early va required.
154
input                   ifu_tlu_alt_space_d ;   // alt space access - new;_e exists
155
//input                 ifu_lsu_imm_asi_vld_d ; // imm asi is vld - current
156
input   [8:0]            ifu_lsu_imm_asi_d ;     // imm asi - current
157
input                   ifu_lsu_memref_d;       // ld/st - prefer ld_inst_e;
158
input   [7:0]    lsu_asi_reg0 ;          // asi state - thread0
159
input   [7:0]    lsu_asi_reg1 ;          // asi state - thread1
160
input   [7:0]    lsu_asi_reg2 ;          // asi state - thread2
161
input   [7:0]    lsu_asi_reg3 ;          // asi state - thread3
162
//input [1:0]           ifu_tlu_thrid_d ;       // thread id
163
input   [7:0]            exu_mmu_early_va_e;     // early va from exu
164
// END - MMU_ASI_RD_CHANGE
165
 
166
input [12:0]          tlu_tag_access_ctxt_g ;
167
 
168
input [3:0] tlu_lsu_tl_zero;   // trap level is zero.
169
//input           exu_tlu_ttype_vld_m;    // exu src ttype vld
170
input           exu_tlu_va_oor_jl_ret_m;
171
input           exu_tlu_va_oor_m;
172
input [3:0] tlu_lsu_pstate_am;
173
 
174
input           lsu_mmu_flush_pipe_w ;
175
input           ifu_tlu_inst_vld_m ;
176
input           ifu_mmu_trap_m ;
177
input           ffu_tlu_ill_inst_m ;
178
input           exu_lsu_priority_trap_m ; // fill/ue
179
input           ifu_tlu_priv_violtn_m ;
180
 
181
input           rclk ;
182
input           arst_l, grst_l;
183
input           si,se;
184
input           sehold ;
185
input           rst_tri_en ;
186
 
187
/*AUTOOUTPUT*/
188
// Beginning of automatic outputs (from unused autoinst outputs)
189
// End of automatics
190
 
191
output                  dmmu_any_sfsr_wr ;
192
output  [3:0]            dmmu_sfsr_wr_en_l ;
193
output  [3:0]            dmmu_sfar_wr_en_l ;
194
//output        [3:0]           dmmu_tsb_wr_en ;
195
//output        [3:0]           dmmu_tsb_rd_en ;
196
//output        [3:0]           dmmu_tag_access_wr_en ;
197
//output        [3:0]           dmmu_tag_access_rd_en ;
198
//output                        dmmu_tag_read_en ; 
199
 
200
output                  immu_any_sfsr_wr ;
201
output  [3:0]            immu_sfsr_wr_en_l ;
202
//output        [3:0]           immu_tsb_wr_en ;
203
output  [3:0]            immu_tsb_rd_en ;
204
//output        [3:0]           immu_tag_access_wr_en ;
205
//output        [3:0]           immu_tag_access_rd_en ;
206
//output                        immu_tag_read_en ; 
207
 
208
// tlb/itlb related control can potentially be
209
// made g-stage.
210
output  [2:0]            tlu_tte_tag_g ;
211
output                  tlu_dtlb_rw_index_vld_g ;
212
output  [5:0]            tlu_dtlb_rw_index_g ;
213
output                  tlu_dtlb_data_rd_g ;
214
output                  tlu_dtlb_tag_rd_g ;
215
output                  tlu_itlb_rw_index_vld_g ;
216
output                  tlu_itlb_wr_vld_g ;
217
output                  itlb_wr_vld_g ;
218
output  [5:0]            tlu_itlb_rw_index_g ;
219
output                  tlu_itlb_data_rd_g ;
220
output                  tlu_itlb_tag_rd_g ;
221
output  [47:0]           tlu_idtsb_8k_ptr ;      // maps to ps0/ps1 ptr. require only 1.
222
 
223
output                  tlu_dtlb_invalidate_all_g ;
224
output                  tlu_itlb_invalidate_all_g ;
225
 
226
output  [3:0]           tlu_slxa_thrd_sel ;
227
 
228
output  [1:0]            tlu_lsu_ldxa_tid_w2 ;
229
 
230
output                  tlu_itlb_dmp_vld_g ;
231
output                  tlu_itlb_dmp_all_g ;
232
output                  tlu_itlb_dmp_pctxt_g ;
233
output                  tlu_itlb_dmp_actxt_g ;
234
output                  tlu_itlb_dmp_nctxt_g ;
235
output                  tlu_dtlb_dmp_vld_g ;
236
output                  tlu_dtlb_dmp_all_g ;
237
output                  tlu_dtlb_dmp_pctxt_g ;
238
output                  tlu_dtlb_dmp_sctxt_g ;
239
output                  tlu_dtlb_dmp_nctxt_g ;
240
output                  tlu_dtlb_dmp_actxt_g ;
241
output  [1:0]            tlu_idtlb_dmp_thrid_g ;
242
output  [4:0]           tlu_dmp_key_vld_g ;
243
output                  tlu_int_asi_load;
244
output                  tlu_int_asi_store;
245
output  [1:0]            tlu_int_asi_thrid;
246
output                  tlu_int_asi_vld;
247
//output                        tlb_access_en_l ;
248
output                  tlb_access_rst_l ;
249
output                  tlu_lsu_stxa_ack ;         // write to tlb is complete.
250
output   [1:0]           tlu_lsu_stxa_ack_tid ;
251
output   [3:0]          mra_wr_ptr ;    // wr ptr for mra
252
output   [3:0]          mra_rd_ptr ;    // thrd id for rd.
253
output                  mra_wr_vld ;    // write pointer vld
254
output                  mra_rd_vld ;    // read vld
255
output   [19:0]          mra_byte_wen ;
256
output   [2:0]           tag_access_wdata_sel ;
257
output                  tlu_admp_key_sel ;
258
//output                        tlu_mmu_sync_data_excp_g ;      // sync asi related data excp
259
//output                        tlu_lsu_dtlb_rd_unc ;           // unc error for tlb rd
260
 
261
//output   [3:0]          tlu_dldxa_mx2_sel ;           // obsolete for SPARC_HPV_EN
262
//output   [2:0]          tlu_dldxa_mx3_sel ;           // obsolete for SPARC_HPV_EN
263
//output   [2:0]          tlu_dldxa_fmx_sel ;           // obsolete for SPARC_HPV_EN
264
//output   [3:0]          tlu_ildxa_mx1_sel ;           // obsolete for SPARC_HPV_EN
265
//output   [2:0]          tlu_ildxa_fmx_sel ;           // obsolete for SPARC_HPV_EN
266
 
267
output   [2:0]           tlu_tte_wr_pid_g ;      // thread selected pid
268
output                  tlu_lsu_ldxa_async_data_vld ;   // tlu_lsu_ldxa_data_vld is for async op.
269
 
270
output                  tlu_tte_real_g ;                // tte is real
271
 
272
output  [3:0]    tlu_ldxa_l1mx1_sel ;    // mmu ldxa level1 mx1 sel
273
output  [3:0]    tlu_ldxa_l1mx2_sel ;    // mmu ldxa level1 mx2 sel
274
output  [2:0]    tlu_ldxa_l2mx1_sel ;    // mmu ldxa level2 mx1 sel
275
 
276
output  [3:0]           lsu_ifu_inj_ack ;       // ack for tlb error injection.
277
output                  tlu_tlb_tag_invrt_parity ;      // invert parity on write tag.
278
output                  tlu_tlb_data_invrt_parity ;     // invert parity on write data.
279
 
280
output                  tlu_sun4r_tte_g ;       // sun4r vs. sun4v tte.
281
 
282
output                  lsu_exu_ldxa_m ;
283
 
284
output                  tlu_lng_ltncy_en_l ;
285
 
286
output  [2:0]            tlu_tag_access_ctxt_sel_m ;
287
 
288
output                  tlu_tsb_rd_ps0_sel ;
289
 
290
output                  tlu_tlb_access_en_l_d1 ;
291
 
292
output                  so ;
293
 
294
/*AUTOWIRE*/
295
// Beginning of automatic wires (for undeclared instantiated-module outputs)
296
// End of automatics
297
 
298
reg                     dmmu_invalidate_all_en_m ;
299
reg                     immu_invalidate_all_en_m ;
300
reg     dmmu_decode_asi58_e ;
301
reg     immu_decode_asi50_e ;
302
reg     dmmu_8k_ptr_e,dmmu_64k_ptr_e,dmmu_direct_ptr_e ;
303
reg     immu_8k_ptr_e,immu_64k_ptr_e;
304
reg     dmmu_zctxt_ps0_tsb_e, dmmu_zctxt_ps1_tsb_e ;
305
reg     dmmu_nzctxt_ps0_tsb_e, dmmu_nzctxt_ps1_tsb_e ;
306
reg     dmmu_zctxt_cfg_e, dmmu_nzctxt_cfg_e ;
307
reg     immu_zctxt_ps0_tsb_e, immu_zctxt_ps1_tsb_e ;
308
reg     immu_nzctxt_ps0_tsb_e, immu_nzctxt_ps1_tsb_e ;
309
reg     immu_zctxt_cfg_e, immu_nzctxt_cfg_e ;
310
 
311
reg                     dmmu_data_in_en_m,dmmu_data_access_en_m;
312
reg                     dmmu_tag_read_en_m,dmmu_demap_en_m;
313
 
314
wire                    sehold_d1 ;
315
wire                    tlb_access_en_l ;
316
wire                    dmmu_sync_illgl_va_g ;
317
wire                    dmmu_async_supported_asi,dmmu_async_illgl_va_g ;
318
wire                    immu_sync_illgl_va_g ;
319
wire                    immu_async_supported_asi,immu_async_illgl_va_g ;
320
wire                    ld_inst_m,st_inst_m ;
321
wire                    ld_inst_g,st_inst_g ;
322
wire [3:0]               tsb_size ;
323
wire                    tsb_split ;
324
//wire [47:13]          tsb_base ;
325
wire [47:13]            tag_access ;
326
/*wire  tsb_sz_8k_b0_mx1_out,tsb_sz_8k_b1_mx1_out,tsb_sz_8k_b2_mx1_out,tsb_sz_8k_b3_mx1_out;
327
wire    tsb_sz_8k_b4_mx1_out,tsb_sz_8k_b5_mx1_out,tsb_sz_8k_b6_mx1_out,tsb_sz_8k_b7_mx1_out;
328
wire    tsb_sz_8k_b0_mx2_out,tsb_sz_8k_b1_mx2_out,tsb_sz_8k_b2_mx2_out,tsb_sz_8k_b3_mx2_out;
329
wire    tsb_sz_8k_b4_mx2_out,tsb_sz_8k_b5_mx2_out,tsb_sz_8k_b6_mx2_out,tsb_sz_8k_b7_mx2_out;
330
wire    tsb_sz_8k_b0_mx3_out,tsb_sz_8k_b1_mx3_out,tsb_sz_8k_b2_mx3_out,tsb_sz_8k_b3_mx3_out;
331
wire    tsb_sz_8k_b4_mx3_out,tsb_sz_8k_b5_mx3_out,tsb_sz_8k_b6_mx3_out,tsb_sz_8k_b7_mx3_out;
332
wire    tsb_sz_64k_b0_mx1_out,tsb_sz_64k_b1_mx1_out,tsb_sz_64k_b2_mx1_out,tsb_sz_64k_b3_mx1_out;
333
wire    tsb_sz_64k_b4_mx1_out,tsb_sz_64k_b5_mx1_out,tsb_sz_64k_b6_mx1_out,tsb_sz_64k_b7_mx1_out;
334
wire    tsb_sz_64k_b0_mx2_out,tsb_sz_64k_b1_mx2_out,tsb_sz_64k_b2_mx2_out,tsb_sz_64k_b3_mx2_out;
335
wire    tsb_sz_64k_b4_mx2_out,tsb_sz_64k_b5_mx2_out,tsb_sz_64k_b6_mx2_out ;
336
wire    tsb_sz_64k_b0_mx3_out,tsb_sz_64k_b1_mx3_out,tsb_sz_64k_b2_mx3_out,tsb_sz_64k_b3_mx3_out;
337
wire    tsb_sz_64k_b4_mx3_out ;*/
338
wire    dtlb_rw_index_vld_g,dtlb_wr_vld_g ;
339
wire            dmmu_data_in_wr_en, dmmu_data_access_wr_en ;
340
wire            dmmu_tag_read_rd_en, dmmu_data_access_rd_en ;
341
wire            immu_data_in_wr_en, immu_data_access_wr_en ;
342
wire            immu_data_access_rd_en, immu_tag_read_rd_en ;
343
wire            itlb_rw_index_vld_g,itlb_wr_vld_g;
344
wire            tlu_ldxa_data_vld ;
345
wire    tlu_dldxa_data_vld ;
346
wire    [1:0]    thrid_d,thrid_e,thrid_m,thrid_g ;
347
wire            thread0_sel_g, thread1_sel_g ;
348
wire            thread2_sel_g, thread3_sel_g ;
349
wire            alt_space_m, alt_space_g ;
350
wire            immu_miss_g;
351
wire            ddemap_by_page,ddemap_by_ctxt,ddemap_all;
352
wire            idemap_by_page,idemap_by_ctxt,idemap_all;
353
wire            demap_pctxt,demap_sctxt,demap_nctxt ;
354
//wire          lsu_tlu_page_ebit_g ;
355
wire            ddemap_vld, idemap_vld ;
356
wire    [2:0]   tlu_tte_tag_g ;
357
wire            demap_resrv ;
358
wire    itlb_wr_pend,itlb_data_rd_pend,itlb_tag_rd_pend ;
359
wire    dtlb_wr_pend,dtlb_data_rd_pend,dtlb_tag_rd_pend ;
360
wire    tlb_access_en ;
361
wire    tlb_access_rst ;
362
wire    dmra_wr_g, imra_wr_g ;
363
wire                    dmmu_data_in_en, dmmu_data_access_en, dmmu_tag_read_en, dmmu_demap_en ;
364
wire                    immu_data_in_en, immu_data_access_en, immu_tag_read_en, immu_demap_en ;
365
wire    immu_invalidate_all_en,dmmu_invalidate_all_en ;
366
wire    tlb_wr_vld_g ;
367
wire    tlb_admp_en, tlb_admp_rst, tlb_wr_rst ;
368
wire    tlb_admp_mode,tlb_write_mode ;
369
wire    tlb_ldst_inst_m ;
370
wire    tlb_admp_mode_d1 ;
371
wire    itlb_wr_vld_unmsked,dtlb_wr_vld_unmsked;
372
wire    idemap_pend, ddemap_pend ;
373
wire    itlb_tag_rd_en, dtlb_tag_rd_en ;
374
wire    [3:0]    dsfsr_asi_wr_en ;
375
wire    [3:0]    isfsr_asi_wr_en ;
376
wire    [10:3]  tlb_ldst_va_g ;
377
wire            tlb_ld_inst_g,tlb_st_inst_g ;
378
wire            tlb_ld_inst_unflushed,tlb_st_inst_unflushed ;
379
wire    [1:0]    tlb_access_tid_g ;
380
wire            inst_vld_g ;
381
wire    st_inst_unflushed, ld_inst_unflushed ;
382
wire    imra_lng_lat_rd,dmra_lng_lat_rd ;
383
wire    iside_mra_access_rd, iside_mra_access_wr ;
384
wire    [1:0]    mra_raccess_tid ;
385
//wire  dmmu_sync_rd_only_asi_g ;
386
//wire  immu_sync_rd_only_asi_g ;
387
wire    dptr0_pg64k_en,dptr1_pg64k_en,dptr2_pg64k_en,dptr3_pg64k_en;
388
wire    dptr0_pg64k_vld,dptr1_pg64k_vld,dptr2_pg64k_vld,dptr3_pg64k_vld;
389
//wire  dmmu_direct_ptr_rd_en ;
390
wire    tlu_dtlb_rd_done ;
391
wire    dmmu_ctxt_cfg_en, immu_ctxt_cfg_en ;
392
//wire  dmmu_ctxt_cfg_rd_en ;
393
wire    dacc_prot_ps1_match ;
394
wire    tacc_nctxt, itacc_nctxt, dtacc_nctxt ;  // for in-pipe access
395
wire    tacc_anctxt, itacc_anctxt, dtacc_anctxt ;// for async access
396
wire    thread0_async_g,thread1_async_g,thread2_async_g ;
397
wire    sun4r_tte_g ;
398
wire    dmmu_decode_asi58_m, immu_decode_asi50_m ;
399
wire    dmmu_zctxt_ps0_tsb_m, dmmu_zctxt_ps1_tsb_m,
400
        dmmu_nzctxt_ps0_tsb_m, dmmu_nzctxt_ps1_tsb_m,
401
        dmmu_zctxt_cfg_m, dmmu_nzctxt_cfg_m,
402
        immu_zctxt_ps0_tsb_m, immu_zctxt_ps1_tsb_m,
403
        immu_nzctxt_ps0_tsb_m, immu_nzctxt_ps1_tsb_m,
404
        immu_zctxt_cfg_m, immu_nzctxt_cfg_m ;
405
wire    dmmu_sync_fsr_en, dmmu_sync_far_en,
406
        dmmu_zctxt_ps0_tsb_en, dmmu_zctxt_ps1_tsb_en,
407
        dmmu_nzctxt_ps0_tsb_en, dmmu_nzctxt_ps1_tsb_en,
408
        dmmu_zctxt_cfg_en, dmmu_nzctxt_cfg_en,
409
        immu_sync_fsr_en,
410
        immu_zctxt_ps0_tsb_en, immu_zctxt_ps1_tsb_en,
411
        immu_nzctxt_ps0_tsb_en, immu_nzctxt_ps1_tsb_en,
412
        immu_zctxt_cfg_en, immu_nzctxt_cfg_en ;
413
wire    dmmu_tag_target_en_m,dmmu_tag_access_en_m;
414
wire    immu_tag_target_en_m,immu_tag_access_en_m;
415
wire    dmmu_tag_access_en;
416
wire    immu_tag_access_en;
417
wire    dmmu_8k_ptr_en_m,dmmu_64k_ptr_en_m,dmmu_direct_ptr_en_m ;
418
wire    immu_8k_ptr_en_m,immu_64k_ptr_en_m ;
419
wire    dmmu_sync_fsr_en_m, dmmu_sync_far_en_m,
420
        dmmu_zctxt_ps0_tsb_en_m, dmmu_zctxt_ps1_tsb_en_m,
421
        dmmu_nzctxt_ps0_tsb_en_m, dmmu_nzctxt_ps1_tsb_en_m,
422
        dmmu_zctxt_cfg_en_m, dmmu_nzctxt_cfg_en_m,
423
        immu_sync_fsr_en_m,
424
        immu_zctxt_ps0_tsb_en_m, immu_zctxt_ps1_tsb_en_m,
425
        immu_nzctxt_ps0_tsb_en_m, immu_nzctxt_ps1_tsb_en_m,
426
        immu_zctxt_cfg_en_m, immu_nzctxt_cfg_en_m ;
427
wire    thread0_d,thread1_d,thread2_d,thread3_d;
428
wire    thread0_e, thread1_e, thread2_e, thread3_e ;
429
wire [7:0]       asi_state_d, asi_state_e ;
430
wire    memref_e,memref_m ;
431
wire [7:0] early_va_m ;
432
wire    idmra_rd_d ;
433
wire idmra_nzctxt_rd_d ;
434
wire idmra_fault_rd_d ;
435
wire    dmmu_tsb_en_m, dmmu_ctxt_cfg_en_m ;
436
wire    immu_tsb_en_m, immu_ctxt_cfg_en_m ;
437
wire    tlu_ildxa_data_vld ;
438
wire    dmmu_direct_8kptr_sel_g ;       // direct ptr should select 8k ptr
439
 
440
        wire    dmmu_tsb_en ;
441
        wire    immu_tsb_en ;
442
 
443
wire    mra_field1_en, mra_field2_en ;
444
wire    mra_field3_en, mra_field4_en ;
445
 
446
//=========================================================================================
447
//      RESET/CLK
448
//=========================================================================================
449
 
450
    wire       clk;
451
    assign     clk = rclk;
452
 
453
    wire       rst_l;
454
 
455
    dffrl_async rstff(.din (grst_l),
456
                      .q   (rst_l),
457
                      .clk (clk), .se(se), .si(), .so(),
458
                      .rst_l (arst_l));
459
 
460
 
461
//=========================================================================================
462
//      Early Flush Generation
463
//=========================================================================================
464
 
465
 
466
 
467
 
468
wire    ifu_tlu_flush_w ;
469
dff_s  #(1) stg_w (
470
        .din    (ifu_tlu_flush_m),
471
        .q      (ifu_tlu_flush_w),
472
        .clk    (clk),
473
        .se     (1'b0),       .si (),          .so ()
474
) ;
475
 
476
wire    local_flush_w ;
477
 
478
assign  local_flush_w =
479
        ifu_tlu_flush_w                 |       // ifu flush 
480
        lsu_mmu_defr_trp_taken_g        |       // defr trp 
481
        tlu_mmu_early_flush_pipe_w      |       // tlu flush
482
        lsu_mmu_early_flush_w           ;       // lsu early flush
483
 
484
wire    flush_w_inst_vld_m ;
485
assign  flush_w_inst_vld_m =
486
        ifu_tlu_inst_vld_m &
487
        ~(lsu_mmu_flush_pipe_w & (thrid_m[1:0] == thrid_g[1:0])) ; // really lsu_flush_pipe_w
488
 
489
dff_s  stgw_ivld (
490
        .din    (flush_w_inst_vld_m),
491
        .q      (inst_vld_g),
492
        .clk    (clk),
493
        .se     (1'b0),       .si (),          .so ()
494
        );
495
 
496
// Bug 4183
497
wire    priority_squash_m, priority_squash_g ;
498
assign  priority_squash_m =
499
ifu_mmu_trap_m | ffu_tlu_ill_inst_m | exu_lsu_priority_trap_m |  spu_tlu_rsrv_illgl_m ;
500
 
501
wire    trp_vld_m,trp_vld_g ;
502
assign  trp_vld_m = flush_w_inst_vld_m & ~priority_squash_m ;
503
 
504
dff_s  #(2) sqshstgw (
505
        .din    ({priority_squash_m,trp_vld_m}),
506
        .q      ({priority_squash_g,trp_vld_g}),
507
        .clk    (clk),
508
        .se     (1'b0),       .si (),          .so ()
509
) ;
510
 
511
//=========================================================================================
512
//      Staging
513
//=========================================================================================
514
 
515
dff_s  #(2) stg_d (
516
        .din    (ifu_lsu_thrid_s[1:0]),
517
        .q      (thrid_d[1:0]),
518
        .clk    (clk),
519
        .se     (1'b0),       .si (),          .so ()
520
        );
521
 
522
dff_s  #(2) stg_e (
523
        .din    (thrid_d[1:0]),
524
        .q      (thrid_e[1:0]),
525
        .clk    (clk),
526
        .se     (1'b0),       .si (),          .so ()
527
        );
528
 
529
dff_s  #(5) stg_m (
530
        .din    ({ifu_lsu_ld_inst_e,ifu_lsu_st_inst_e,
531
                thrid_e[1:0],ifu_lsu_alt_space_e}),
532
        .q      ({ld_inst_m,st_inst_m,thrid_m[1:0],alt_space_m}),
533
        .clk    (clk),
534
        .se     (1'b0),       .si (),          .so ()
535
        );
536
 
537
dff_s  #(6) stg_g (
538
        .din    ({ld_inst_m,st_inst_m,thrid_m[1:0],alt_space_m,ifu_tlu_immu_miss_m}),
539
        .q      ({ld_inst_unflushed,st_inst_unflushed,thrid_g[1:0],alt_space_g,immu_miss_g}),
540
        .clk    (clk),
541
        .se     (1'b0),       .si (),          .so ()
542
        );
543
 
544
// reads are terminated for illegal va case.
545
assign  ld_inst_g = ld_inst_unflushed & inst_vld_g & ~local_flush_w ;
546
//assign        ld_inst_g = ld_inst_unflushed & inst_vld_g & ~(dmmu_sync_illgl_va_g | immu_sync_illgl_va_g) & ;
547
// writes are terminated for illegal va case.
548
assign  st_inst_g = st_inst_unflushed & inst_vld_g & ~local_flush_w &
549
                        ~(dmmu_sync_illgl_va_g | immu_sync_illgl_va_g) ;
550
//assign        st_inst_g = st_inst_unflushed & inst_vld_g & ~(dmmu_sync_illgl_va_g | immu_sync_illgl_va_g);
551
 
552
assign  thread0_sel_g =  ~thrid_g[1] & ~thrid_g[0] ;
553
assign  thread1_sel_g =  ~thrid_g[1] &  thrid_g[0] ;
554
assign  thread2_sel_g =   thrid_g[1] & ~thrid_g[0] ;
555
assign  thread3_sel_g =   thrid_g[1] &  thrid_g[0] ;
556
 
557
assign tlu_slxa_thrd_sel[0] = ~thrid_m[1] & ~thrid_m[0] ;
558
assign tlu_slxa_thrd_sel[1] = ~thrid_m[1] &  thrid_m[0] ;
559
assign tlu_slxa_thrd_sel[2] =  thrid_m[1] & ~thrid_m[0] ;
560
assign tlu_slxa_thrd_sel[3] =  thrid_m[1] &  thrid_m[0] ;
561
 
562
/*dff stgivld_g (
563
        .din    (tlu_inst_vld_m),
564
        .q      (inst_vld_g),
565
        .clk    (clk),
566
        .se     (1'b0),       .si (),          .so ()
567
        ); */
568
 
569
//=========================================================================================
570
//      ASI RD DP MUX SELECT
571
//=========================================================================================
572
 
573
// qualification with vld not required as this dp is used by synchronous ops only
574
// Need to be made non zero-hot in functional mode
575
 
576
// Decode of bits va[5:4] to distinguish reads.  
577
wire va_54_eq_0,va_54_eq_1,va_54_eq_2,va_54_eq_3 ;
578
wire    [2:0]    ldxa_l1mx1_sel_d1 ;
579
assign va_54_eq_0 = (~early_va_m[5] & ~early_va_m[4]) ;
580
assign va_54_eq_1 = (~early_va_m[5] &  early_va_m[4]) ;
581
assign va_54_eq_2 = ( early_va_m[5] & ~early_va_m[4]) ;
582
assign va_54_eq_3 = ( early_va_m[5] &  early_va_m[4]) ;
583
 
584
// i/d tag-target
585
// Extend for MacroTest Control.
586
assign  tlu_ldxa_l1mx1_sel[0] =
587
((((dmmu_decode_asi58_m | immu_decode_asi50_m) & va_54_eq_0) & ~sehold_d1) | rst_tri_en) |
588
(ldxa_l1mx1_sel_d1[0] & sehold_d1) ;
589
assign  tlu_ldxa_l1mx1_sel[1] =
590
((dmmu_zctxt_ps0_tsb_e | dmmu_nzctxt_ps0_tsb_e |
591
immu_zctxt_ps0_tsb_e | immu_nzctxt_ps0_tsb_e) & ~sehold_d1 & ~rst_tri_en) |
592
(ldxa_l1mx1_sel_d1[1] & sehold_d1) ;
593
assign  tlu_ldxa_l1mx1_sel[2] =
594
((dmmu_zctxt_ps1_tsb_e | dmmu_nzctxt_ps1_tsb_e |
595
immu_zctxt_ps1_tsb_e | immu_nzctxt_ps1_tsb_e) & ~sehold_d1 & ~rst_tri_en) |
596
(ldxa_l1mx1_sel_d1[2] & sehold_d1) ;
597
 
598
 
599
 
600
// Extend flops to hold selects for MacroTest of MRA.
601
wire [2:0] ldxa_l1mx1_sel_out ;
602
dff_s #(3)   l1mx1s_stgd1(
603
        .din    (tlu_ldxa_l1mx1_sel[2:0]),
604
        .q      (ldxa_l1mx1_sel_out[2:0]),
605
        .clk    (clk),
606
        .se     (1'b0),         .si (),          .so ()
607
        );
608
 
609
// scan protection.
610
assign  ldxa_l1mx1_sel_d1[0] = ldxa_l1mx1_sel_out[0] ;
611
assign  ldxa_l1mx1_sel_d1[1] = ldxa_l1mx1_sel_out[1] & ~rst_tri_en ;
612
assign  ldxa_l1mx1_sel_d1[2] = ldxa_l1mx1_sel_out[2] & ~rst_tri_en ;
613
 
614
wire    sehold_out ;
615
dff_s #(1)   seh_d1 (
616
        .din    (sehold),
617
        .q      (sehold_out),
618
        .clk    (clk),
619
        .se     (1'b0),         .si (),          .so ()
620
        );
621
 
622
assign  sehold_d1 = sehold_out & ~rst_tri_en ;
623
 
624
// i/d tag-access
625
assign  tlu_ldxa_l1mx1_sel[3] =  ~|tlu_ldxa_l1mx1_sel[2:1];
626
wire    ldxa_l1mx1_sel3;
627
// * read timing change.
628
assign  ldxa_l1mx1_sel3 =
629
(dmmu_decode_asi58_m | immu_decode_asi50_m) & va_54_eq_3 & ~rst_tri_en ;
630
 
631
// d sync-fsr
632
// * read timing change.
633
wire    dmmu_sync_fsr_m_sel,dmmu_sync_far_m_sel,immu_sync_fsr_m_sel;
634
assign  dmmu_sync_fsr_m_sel     = (dmmu_decode_asi58_m & va_54_eq_1) | rst_tri_en ;
635
assign  dmmu_sync_far_m_sel     = (dmmu_decode_asi58_m & va_54_eq_2) & ~rst_tri_en ;
636
assign  immu_sync_fsr_m_sel     = (immu_decode_asi50_m & va_54_eq_1) & ~rst_tri_en ;
637
assign  tlu_ldxa_l1mx2_sel[0] = dmmu_sync_fsr_m_sel ;
638
// d sync-far
639
// * read timing change.
640
assign  tlu_ldxa_l1mx2_sel[1] = dmmu_sync_far_m_sel ;
641
// i sync-fsr
642
assign  tlu_ldxa_l1mx2_sel[2] = immu_sync_fsr_m_sel ;
643
assign  tlu_ldxa_l1mx2_sel[3] = ~|tlu_ldxa_l1mx2_sel[2:0];
644
wire    ldxa_l1mx2_sel3;
645
assign  ldxa_l1mx2_sel3 = (dmmu_zctxt_cfg_m | dmmu_nzctxt_cfg_m |
646
                          immu_zctxt_cfg_m | immu_nzctxt_cfg_m) & ~rst_tri_en ;
647
 
648
assign  tlu_ldxa_l2mx1_sel[0] =
649
|{ldxa_l1mx1_sel3,ldxa_l1mx1_sel_d1[2:1],(tlu_ldxa_l1mx1_sel[0] & ~rst_tri_en)} ;
650
assign  tlu_ldxa_l2mx1_sel[1] = |{ldxa_l1mx2_sel3,tlu_ldxa_l1mx2_sel[2:0]} ;
651
assign  tlu_ldxa_l2mx1_sel[2] = ~|tlu_ldxa_l2mx1_sel[1:0];
652
 
653
//=========================================================================================
654
//      MRA RD/WRITE
655
//=========================================================================================
656
 
657
wire    [3:0]    isfsr_trp_wr ;
658
wire    flush_mmuasi_wr ;
659
assign  flush_mmuasi_wr = ifu_tlu_flush_w | lsu_mmu_defr_trp_taken_g ; // Bug 5196
660
assign  isfsr_trp_wr[0] = immu_sfsr_trp_wr[0] & ~flush_mmuasi_wr ;
661
assign  isfsr_trp_wr[1] = immu_sfsr_trp_wr[1] & ~flush_mmuasi_wr ;
662
assign  isfsr_trp_wr[2] = immu_sfsr_trp_wr[2] & ~flush_mmuasi_wr ;
663
assign  isfsr_trp_wr[3] = immu_sfsr_trp_wr[3] & ~flush_mmuasi_wr ;
664
 
665
wire  tag_access_nctxt_g ;
666
 
667
wire immu_miss_vld_g ;
668
assign immu_miss_vld_g = immu_miss_g & inst_vld_g ;
669
 
670
// fast-asi read takes precedence over long-latency rd. Can long-latency read get
671
// starved out ?? Assume memref_d is never x.
672
assign  dmra_lng_lat_rd = ((dmmu_data_in_en | dmmu_data_access_en) & tlb_st_inst_g & ~ifu_lsu_memref_d) ;
673
assign  imra_lng_lat_rd = ((immu_data_in_en | immu_data_access_en) & tlb_st_inst_g & ~ifu_lsu_memref_d) ;
674
//assign        dmra_lng_lat_rd = ((dmmu_data_in_en | dmmu_data_access_en) & tlb_st_inst_g) ;
675
//assign        imra_lng_lat_rd = ((immu_data_in_en | immu_data_access_en) & tlb_st_inst_g) ;
676
 
677
wire  dmra_ldst,imra_ldst ;
678
assign        dmra_ldst = dmmu_tag_access_en | dmmu_tsb_en | dmmu_ctxt_cfg_en ;
679
assign        imra_ldst = immu_tag_access_en | immu_tsb_en | immu_ctxt_cfg_en ;
680
 
681
// sync_far_en no longer written/read
682
assign  dmra_wr_g =
683
        (dmra_ldst & st_inst_g) |
684
        (lsu_tlu_dmmu_miss_g | lsu_tlu_daccess_excptn_g | lsu_tlu_daccess_prot_g)
685
        & trp_vld_g & ~flush_mmuasi_wr ;
686
        //(lsu_tlu_dmmu_miss_g | lsu_tlu_daccess_excptn_g | lsu_tlu_daccess_prot_g) & inst_vld_g ;
687
        // Bug 4183
688
wire    isfsr_trap ;
689
assign  isfsr_trap = |isfsr_trp_wr[3:0] ;
690
assign  imra_wr_g =
691
        (imra_ldst & st_inst_g) |
692
        //((immu_tag_access_en | immu_tsb_en | immu_ctxt_cfg_en) & st_inst_g) | 
693
        (immu_miss_vld_g & ~flush_mmuasi_wr) | isfsr_trap ;
694
 
695
wire    dmra_rw_d ;
696
assign  iside_mra_access_rd = ((~dmra_rw_d) & ~(imra_lng_lat_rd | dmra_lng_lat_rd))  | imra_lng_lat_rd ;
697
assign  iside_mra_access_wr = imra_wr_g ;
698
 
699
assign  mra_raccess_tid[1:0] = (dmra_lng_lat_rd | imra_lng_lat_rd) ? tlb_access_tid_g[1:0] : thrid_d[1:0] ;
700
 
701
wire idside_nzctxt_accwr_early_m,idside_nzctxt_accwr_early_g  ;
702
assign  idside_nzctxt_accwr_early_m =
703
        ((dmmu_nzctxt_cfg_en_m   | immu_nzctxt_cfg_en_m     |
704
        dmmu_nzctxt_ps0_tsb_en_m | immu_nzctxt_ps0_tsb_en_m |
705
        dmmu_nzctxt_ps1_tsb_en_m | immu_nzctxt_ps1_tsb_en_m) & st_inst_m) ; // tsb/cfg asi wr
706
 
707
dff_s ctacc_stgg (
708
        .din    (idside_nzctxt_accwr_early_m),
709
        .q      (idside_nzctxt_accwr_early_g),
710
        .clk    (clk),
711
        .se     (1'b0),       .si (),          .so ()
712
        );
713
 
714
//wire  idside_nzctxt_access ;
715
wire    idside_nzctxt_access_rd,idside_nzctxt_access_wr ;
716
wire    st_wr_g ;
717
 
718
assign  idside_nzctxt_access_wr =
719
        ((dmmu_tag_access_en    | immu_tag_access_en)   // tag-access asi write
720
                & st_inst_unflushed & ~tag_access_nctxt_g)       |
721
        ((lsu_tlu_daccess_excptn_g | lsu_tlu_daccess_prot_g | lsu_tlu_dmmu_miss_g |
722
        immu_miss_g | (isfsr_trap))             // tag-access exception write 
723
                & inst_vld_g & ~tag_access_nctxt_g)      |
724
        (idside_nzctxt_accwr_early_g & st_wr_g) ; // Bug 4828
725
        //((dmmu_nzctxt_cfg_en  | immu_nzctxt_cfg_en     |
726
        //dmmu_nzctxt_ps0_tsb_en        | immu_nzctxt_ps0_tsb_en |
727
        //dmmu_nzctxt_ps1_tsb_en        | immu_nzctxt_ps1_tsb_en) & st_inst_unflushed) ; // tsb/cfg asi wr
728
assign  idside_nzctxt_access_rd =
729
        (idmra_nzctxt_rd_d)              |  // => nzctxt rd with decode
730
        (idmra_fault_rd_d & ~tacc_nctxt) |  // => fault-based rd
731
        ((dmra_lng_lat_rd | imra_lng_lat_rd) & ~tacc_anctxt) ;
732
// access non zero context levels
733
 
734
assign  mra_wr_ptr[3:0]  = {thrid_g[1:0],idside_nzctxt_access_wr,iside_mra_access_wr};
735
assign  mra_rd_ptr[3:0]  = {mra_raccess_tid[1:0],idside_nzctxt_access_rd,iside_mra_access_rd};
736
 
737
assign  mra_wr_vld = dmra_wr_g | imra_wr_g ;
738
assign  mra_rd_vld = idmra_rd_d | dmra_lng_lat_rd | imra_lng_lat_rd ;
739
 
740
assign  dmmu_ctxt_cfg_en = dmmu_zctxt_cfg_en | dmmu_nzctxt_cfg_en ;
741
assign  immu_ctxt_cfg_en = immu_zctxt_cfg_en | immu_nzctxt_cfg_en ;
742
//assign        dmmu_ctxt_cfg_rd_en = (dmmu_zctxt_cfg_en | dmmu_nzctxt_cfg_en) & ld_inst_g ;
743
//assign        immu_ctxt_cfg_rd_en = (immu_zctxt_cfg_en | immu_nzctxt_cfg_en) & ld_inst_g ;
744
 
745
// Change - with 8 tsbs per thread, tsb can be in any of the 3 fields
746
// of a line in the mra.
747
wire    mra_itag_acc_en,mra_dtag_acc_en ;
748
// Be careful about loading on trap conditions.
749
assign st_wr_g = st_inst_unflushed & ~local_flush_w ;
750
assign  mra_itag_acc_en =
751
        (immu_tag_access_en & st_wr_g) | immu_miss_g | (isfsr_trap) ;
752
assign  mra_dtag_acc_en =
753
        (dmmu_tag_access_en & st_wr_g) | lsu_tlu_dmmu_miss_g | lsu_tlu_daccess_excptn_g |
754
        lsu_tlu_daccess_prot_g ;
755
assign  mra_field1_en   = (dmmu_zctxt_ps0_tsb_en  | immu_zctxt_ps0_tsb_en |
756
                          dmmu_nzctxt_ps0_tsb_en | immu_nzctxt_ps0_tsb_en) & st_wr_g ;
757
                          // dmmu_nzctxt_ps0_tsb_en | immu_nzctxt_ps0_tsb_en) & st_inst_unflushed ; Bug 3378
758
assign  mra_field2_en   = (dmmu_zctxt_ps1_tsb_en  | immu_zctxt_ps1_tsb_en |
759
                          dmmu_nzctxt_ps1_tsb_en | immu_nzctxt_ps1_tsb_en) & st_wr_g ;
760
assign  mra_field3_en   = mra_itag_acc_en | mra_dtag_acc_en ;
761
assign  mra_field4_en   = (dmmu_ctxt_cfg_en | immu_ctxt_cfg_en) & st_wr_g ;
762
 
763
// for use of rf16x160
764
assign  mra_byte_wen[19:14] = {6{mra_field1_en}} ;
765
assign  mra_byte_wen[13:8]  = {6{mra_field2_en}} ;
766
assign  mra_byte_wen[7:2]  =  {6{mra_field3_en}} ;
767
assign  mra_byte_wen[1:0]  =  {2{mra_field4_en}} ;
768
 
769
// active-low selects
770
// Need to add inst_access_excp to the sel !!!
771
// Prioritized between the two sels.
772
assign        tag_access_wdata_sel[0] =
773
      ~(tag_access_wdata_sel[1] | tag_access_wdata_sel[2]) | rst_tri_en ;
774
//assign        tag_access_wdata_sel[1] = (immu_miss_g | isfsr_trap) & ~rst_tri_en ; // Timing
775
assign        tag_access_wdata_sel[1] = tlu_itag_acc_sel_g & ~rst_tri_en ;
776
assign        tag_access_wdata_sel[2] = (dmra_ldst | imra_ldst) & st_wr_g & ~rst_tri_en ;
777
                                        // Bug 4728
778
 
779
wire  [12:0]  tag_access_wdata_ctxt ;
780
assign        tag_access_wdata_ctxt[12:0] =
781
       tag_access_wdata_sel[2] ? lsu_tlu_st_rs3_data_b12t0_g[12:0] : tlu_tag_access_ctxt_g[12:0] ;
782
 
783
assign  tag_access_nctxt_g = (tag_access_wdata_ctxt[12:0] == 13'd0) ;
784
 
785
//=========================================================================================
786
//      Tag-Access Context Per thread
787
//=========================================================================================
788
 
789
// Mark ctxt field in tag-access register as being nucleus or non-nucleus.
790
// State will not be ~rst_l as use is expected to be preceeded by write.
791
 
792
wire    [3:0]    itacc_ctxt_en, dtacc_ctxt_en ;
793
wire            itacc_nctxt0,itacc_nctxt1,itacc_nctxt2,itacc_nctxt3;
794
wire            dtacc_nctxt0,dtacc_nctxt1,dtacc_nctxt2,dtacc_nctxt3;
795
assign  itacc_ctxt_en[0] = thread0_sel_g & mra_itag_acc_en & mra_wr_vld ;
796
assign  itacc_ctxt_en[1] = thread1_sel_g & mra_itag_acc_en & mra_wr_vld ;
797
assign  itacc_ctxt_en[2] = thread2_sel_g & mra_itag_acc_en & mra_wr_vld ;
798
assign  itacc_ctxt_en[3] = thread3_sel_g & mra_itag_acc_en & mra_wr_vld ;
799
assign  dtacc_ctxt_en[0] = thread0_sel_g & mra_dtag_acc_en & mra_wr_vld ;
800
assign  dtacc_ctxt_en[1] = thread1_sel_g & mra_dtag_acc_en & mra_wr_vld ;
801
assign  dtacc_ctxt_en[2] = thread2_sel_g & mra_dtag_acc_en & mra_wr_vld ;
802
assign  dtacc_ctxt_en[3] = thread3_sel_g & mra_dtag_acc_en & mra_wr_vld ;
803
 
804
// Thread0
805
dffe_s   itacc_ctxt0 (
806
        .din    (tag_access_nctxt_g), .q  (itacc_nctxt0),
807
        .en     (itacc_ctxt_en[0]),      .clk (clk),
808
        .se     (1'b0),         .si (),          .so ()
809
        );
810
 
811
dffe_s   dtacc_ctxt0 (
812
        .din    (tag_access_nctxt_g), .q  (dtacc_nctxt0),
813
        .en     (dtacc_ctxt_en[0]),      .clk (clk),
814
        .se     (1'b0),         .si (),          .so ()
815
        );
816
 
817
// Thread1
818
dffe_s   itacc_ctxt1 (
819
        .din    (tag_access_nctxt_g), .q  (itacc_nctxt1),
820
        .en     (itacc_ctxt_en[1]),     .clk (clk),
821
        .se     (1'b0),         .si (),          .so ()
822
        );
823
 
824
dffe_s   dtacc_ctxt1 (
825
        .din    (tag_access_nctxt_g), .q  (dtacc_nctxt1),
826
        .en     (dtacc_ctxt_en[1]),     .clk (clk),
827
        .se     (1'b0),         .si (),          .so ()
828
        );
829
 
830
// Thread2
831
dffe_s   itacc_ctxt2 (
832
        .din    (tag_access_nctxt_g), .q  (itacc_nctxt2),
833
        .en     (itacc_ctxt_en[2]),     .clk (clk),
834
        .se     (1'b0),         .si (),          .so ()
835
        );
836
 
837
dffe_s   dtacc_ctxt2 (
838
        .din    (tag_access_nctxt_g), .q  (dtacc_nctxt2),
839
        .en     (dtacc_ctxt_en[2]),     .clk (clk),
840
        .se     (1'b0),         .si (),          .so ()
841
        );
842
 
843
// Thread3
844
dffe_s   itacc_ctxt3 (
845
        .din    (tag_access_nctxt_g), .q  (itacc_nctxt3),
846
        .en     (itacc_ctxt_en[3]),     .clk (clk),
847
        .se     (1'b0),         .si (),          .so ()
848
        );
849
 
850
dffe_s   dtacc_ctxt3 (
851
        .din    (tag_access_nctxt_g), .q  (dtacc_nctxt3),
852
        .en     (dtacc_ctxt_en[3]),     .clk (clk),
853
        .se     (1'b0),         .si (),          .so ()
854
        );
855
 
856
// In-pipe Access
857
assign  itacc_nctxt =
858
        thread0_d ? itacc_nctxt0 :
859
                thread1_d ? itacc_nctxt1 :
860
                        thread2_d ? itacc_nctxt2 : itacc_nctxt3 ;
861
assign  dtacc_nctxt =
862
        thread0_d ? dtacc_nctxt0 :
863
                thread1_d ? dtacc_nctxt1 :
864
                        thread2_d ? dtacc_nctxt2 : dtacc_nctxt3 ;
865
assign  tacc_nctxt =
866
        iside_mra_access_rd ? itacc_nctxt : dtacc_nctxt ;
867
 
868
// Asynchronous Access
869
assign  itacc_anctxt =
870
        thread0_async_g ? itacc_nctxt0 :
871
                thread1_async_g ? itacc_nctxt1 :
872
                        thread2_async_g ? itacc_nctxt2 : itacc_nctxt3 ;
873
assign  dtacc_anctxt =
874
        thread0_async_g ? dtacc_nctxt0 :
875
                thread1_async_g ? dtacc_nctxt1 :
876
                        thread2_async_g ? dtacc_nctxt2 : dtacc_nctxt3 ;
877
 
878
assign  tacc_anctxt =
879
        imra_lng_lat_rd ? itacc_anctxt : dtacc_anctxt ;
880
 
881
//=========================================================================================
882
//      Interrupt Control
883
//=========================================================================================
884
 
885
assign  tlu_int_asi_load =  ld_inst_g & alt_space_g ;
886
assign  tlu_int_asi_store =  st_inst_g & alt_space_g ;
887
assign  tlu_int_asi_thrid[1:0] = thrid_g[1:0] ;
888
assign  tlu_int_asi_vld = alt_space_g ;
889
 
890
//=========================================================================================
891
//      ASI Error Condition
892
//=========================================================================================
893
 
894
// Supported asi but illegal_va. ldxa must signal this occurrence when returning data
895
// to LSU.
896
// The decode can be shared with the statement below (grape)
897
// SPARC_HPV_EN - Needs to change once asi assignments are available !!!
898
// Bug 2201 : pid and va_wtchpt decoded in lsu (asi 58)
899
/*wire lsu_asi58_g ;
900
assign lsu_asi58_g =
901
        ((tlu_ldst_va_g[8:0] == 9'h080) |       // pid
902
        (tlu_ldst_va_g[8:0] == 9'h038)) ;       // va-wtchpt
903
assign  dmmu_sync_supported_asi =
904
        (((lsu_asi_state[7:0] == 8'h58) & ~lsu_asi58_g) |
905
        (lsu_asi_state[7:0] == 8'h59) |
906
        (lsu_asi_state[7:0] == 8'h5A) |
907
        (lsu_asi_state[7:0] == 8'h5B)) & alt_space_g  ;*/
908
 
909
 
910
wire    dmmu_inv_all_asi ;
911
assign dmmu_inv_all_asi =
912
({lsu_tlu_tlb_asi_state_m[7:0],lsu_tlu_tlb_ldst_va_m[7:0]} == {8'h60,8'h08}) ;
913
 
914
wire    dmmu_async_supported_asi_m ;
915
assign  dmmu_async_supported_asi_m =
916
        ((lsu_tlu_tlb_asi_state_m[7:0] == 8'h5C) |
917
        //dmmu_inv_all_asi |
918
        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h60) | // Bug 4901
919
        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h5D) |
920
        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h5E) |
921
        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h5F)) & tlb_ldst_inst_m ;
922
 
923
dff_s stgg_dasi (
924
        .din    (dmmu_async_supported_asi_m),
925
        .q      (dmmu_async_supported_asi),
926
        .clk    (clk),
927
        .se     (1'b0),       .si (),          .so ()
928
        );
929
 
930
assign  dmmu_async_illgl_va_g =
931
        dmmu_async_supported_asi &
932
        ~(dmmu_data_in_en |
933
        dmmu_invalidate_all_en | immu_invalidate_all_en | // Bug 4901
934
        dmmu_data_access_en |
935
        dmmu_tag_read_en | dmmu_demap_en) ;
936
 
937
/*assign        immu_sync_supported_asi =
938
        ((lsu_asi_state[7:0] == 8'h50) |
939
        (lsu_asi_state[7:0] == 8'h51) |
940
        (lsu_asi_state[7:0] == 8'h52)) & alt_space_g ;
941
 
942
assign  immu_sync_illgl_va_g =
943
        immu_sync_supported_asi & ~(immu_tag_target_en | immu_sync_fsr_en | immu_tsb_en |
944
        immu_tag_access_en | immu_8k_ptr_en | immu_64k_ptr_en | immu_ctxt_cfg_en) ;*/
945
 
946
wire    immu_inv_all_asi ;
947
assign immu_inv_all_asi =
948
({lsu_tlu_tlb_asi_state_m[7:0],lsu_tlu_tlb_ldst_va_m[7:0]} == {8'h60,8'h00}) ;
949
 
950
wire    immu_async_supported_asi_m ;
951
assign  immu_async_supported_asi_m =
952
        ((lsu_tlu_tlb_asi_state_m[7:0] == 8'h54) |
953
        //immu_inv_all_asi |
954
        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h60) | // Bug 4901
955
        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h55) |
956
        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h56) |
957
        (lsu_tlu_tlb_asi_state_m[7:0] == 8'h57)) & tlb_ldst_inst_m  ;
958
 
959
dff_s stgg_iasi (
960
        .din    (immu_async_supported_asi_m),
961
        .q      (immu_async_supported_asi),
962
        .clk    (clk),
963
        .se     (1'b0),       .si (),          .so ()
964
        );
965
 
966
assign  immu_async_illgl_va_g =
967
        immu_async_supported_asi &
968
        ~(immu_data_in_en |
969
        immu_data_access_en | immu_tag_read_en | immu_demap_en |
970
        immu_invalidate_all_en | dmmu_invalidate_all_en) ; // Bug 4901
971
 
972
//=========================================================================================
973
//      IN-PIPE ASI RD SUPPORT
974
//=========================================================================================
975
 
976
 
977
assign  thread0_d = ~thrid_d[1] & ~thrid_d[0] ;
978
assign  thread1_d = ~thrid_d[1] &  thrid_d[0] ;
979
assign  thread2_d =  thrid_d[1] & ~thrid_d[0] ;
980
assign  thread3_d =  thrid_d[1] &  thrid_d[0] ;
981
 
982
wire    [7:0]   asi_reg0_d1 ;
983
dff_s #(8) stgd1_asi0 (
984
        .din    (lsu_asi_reg0[7:0]),
985
        .q      (asi_reg0_d1[7:0]),
986
        .clk    (clk),
987
        .se     (1'b0),       .si (),          .so ()
988
        );
989
 
990
wire    [7:0]   asi_reg1_d1 ;
991
dff_s #(8) stgd1_asi1 (
992
        .din    (lsu_asi_reg1[7:0]),
993
        .q      (asi_reg1_d1[7:0]),
994
        .clk    (clk),
995
        .se     (1'b0),       .si (),          .so ()
996
        );
997
 
998
wire    [7:0]   asi_reg2_d1 ;
999
dff_s #(8) stgd1_asi2 (
1000
        .din    (lsu_asi_reg2[7:0]),
1001
        .q      (asi_reg2_d1[7:0]),
1002
        .clk    (clk),
1003
        .se     (1'b0),       .si (),          .so ()
1004
        );
1005
 
1006
wire    [7:0]   asi_reg3_d1 ;
1007
dff_s #(8) stgd1_asi3 (
1008
        .din    (lsu_asi_reg3[7:0]),
1009
        .q      (asi_reg3_d1[7:0]),
1010
        .clk    (clk),
1011
        .se     (1'b0),       .si (),          .so ()
1012
        );
1013
 
1014
wire    [7:0]   asi_reg_state ;
1015
assign  asi_reg_state[7:0] =
1016
        (thread0_d ? asi_reg0_d1[7:0] :
1017
          (thread1_d ? asi_reg1_d1[7:0] :
1018
            (thread2_d ? asi_reg2_d1[7:0] :
1019
              asi_reg3_d1[7:0]))) ;
1020
 
1021
wire    imm_asi_vld_d ;
1022
assign  imm_asi_vld_d = ~ifu_lsu_imm_asi_d[8] ;
1023
 
1024
// Use of asi delayed by a cycle.
1025
assign  asi_state_d[7:0] = imm_asi_vld_d ?
1026
      ifu_lsu_imm_asi_d[7:0] : asi_reg_state[7:0] ;
1027
 
1028
dff_s #(8) stgd1_asi (
1029
        .din    (asi_state_d[7:0]),
1030
        .q      (asi_state_e[7:0]),
1031
        .clk    (clk),
1032
        .se     (1'b0),       .si (),          .so ()
1033
        );
1034
 
1035
// bit8 is unused.
1036
dff_s #(8) stgd1_eva (
1037
        .din    (exu_mmu_early_va_e[7:0]),
1038
        .q      (early_va_m[7:0]),
1039
        .clk    (clk),
1040
        .se     (1'b0),       .si (),          .so ()
1041
        );
1042
 
1043
dff_s #(6) stgd1_mref (
1044
        .din    ({ifu_lsu_memref_d,thread0_d,thread1_d,thread2_d,thread3_d,ifu_tlu_alt_space_d}),
1045
        .q      ({memref_e,thread0_e, thread1_e, thread2_e, thread3_e,alt_space_e}),
1046
        .clk    (clk),
1047
        .se     (1'b0),       .si (),          .so ()
1048
        );
1049
 
1050
dff_s #(1) stgm_mref (
1051
        .din    (memref_e),
1052
        .q      (memref_m),
1053
        .clk    (clk),
1054
        .se     (1'b0),       .si (),          .so ()
1055
        );
1056
 
1057
 
1058
// qualification with memref_d to cut down on number of speculative reads
1059
// decode can be shared with corresponding enables
1060
// gates can be shared.
1061
 
1062
// Establish that mra *could* be read by sync events. full decode would
1063
// cause critical path.
1064
assign  idmra_rd_d =
1065
        //((asi_state_d[6:4] == 3'h6)  | // specifically tag-access.
1066
        ((asi_state_d[6:4] == 3'h5)  |
1067
         (asi_state_d[6:4] == 3'h3)) & ifu_tlu_alt_space_d & ifu_lsu_memref_d ;
1068
 
1069
// need to decode 58,59,5a,5B,31,32,39,3A,33,3B
1070
// use lower hex. need to distinguish 1 & 2 between both accesses.
1071
assign  dmra_rw_d =
1072
        (asi_state_d[3:0] == 4'b1000)   | // 8   
1073
        (((asi_state_d[3:0] == 4'b0001)  | // 1  
1074
        (asi_state_d[3:0] == 4'b0010)) & asi_state_d[5])  | // 2 ;1 & 2 need distinction between I&D     
1075
        (asi_state_d[3:0] == 4'b1001)   | // 9   
1076
        (asi_state_d[3:0] == 4'b1010)   | // A   
1077
        (asi_state_d[2:0] == 3'b011)   ; // partial B    
1078
 
1079
 
1080
// Read requires that ctxt of access be chosen.
1081
// ctxt_cfg,ps0_tsb,ps1_tsb require decode for ctxt.
1082
// tag_access,ps0-ptr,ps1-ptr,direct-ptr,tag-target require lookup of logged ctxt. 
1083
// ** Solution here is to exclude zctxt asi rds from equation.
1084
 
1085
assign idmra_nzctxt_rd_d =
1086
        (asi_state_d[7:4] == 4'h3) &    // common
1087
                ((asi_state_d[3:0] == 4'h9) |    // dmmu_nzctxt_ps0_tsb
1088
                (asi_state_d[3:0] == 4'hA) |     // dmmu_nzctxt_ps1_tsb
1089
                (asi_state_d[3:0] == 4'hB) |     // dmmu_nzctxt_cfg
1090
                (asi_state_d[3:0] == 4'hD) |     // immu_nzctxt_ps0_tsb
1091
                (asi_state_d[3:0] == 4'hE) |     // immu_nzctxt_ps1_tsb
1092
                (asi_state_d[3:0] == 4'hF)) &    // immu_nzctxt_cfg
1093
                ifu_tlu_alt_space_d & ifu_lsu_memref_d ;
1094
 
1095
// Fault based reads
1096
assign  idmra_fault_rd_d =
1097
        (asi_state_d[7:4] == 4'h5) &    // common
1098
                ((asi_state_d[3:0] == 4'h8) |    // dmmu_tag_access/target; va ignored
1099
                (asi_state_d[3:0] == 4'h9) |     // dmmu_ps0_ptr
1100
                (asi_state_d[3:0] == 4'hA) |     // dmmu_ps1_ptr
1101
                (asi_state_d[3:0] == 4'hB) |     // direct_ptr
1102
                (asi_state_d[3:0] == 4'h0) |     // immu_tag_access/target ; va ignored
1103
                (asi_state_d[3:0] == 4'h1) |     // immu_ps0_ptr
1104
                (asi_state_d[3:0] == 4'h2)) &    // immu_ps1_ptr
1105
                ifu_tlu_alt_space_d & ifu_lsu_memref_d ;
1106
 
1107
 
1108
// Note - tag_access needs to be included.
1109
always  @ (/*AUTOSENSE*/alt_space_e or asi_state_e or memref_e)
1110
        begin
1111
                // DMMU
1112
                dmmu_decode_asi58_e =
1113
                 ({asi_state_e[7:0]} == {8'h58}) & alt_space_e & memref_e ;
1114
                dmmu_8k_ptr_e =
1115
                 ({asi_state_e[7:0]} == {8'h59}) & alt_space_e & memref_e ;
1116
                dmmu_64k_ptr_e =
1117
                 ({asi_state_e[7:0]} == {8'h5A}) & alt_space_e & memref_e ;
1118
                dmmu_direct_ptr_e =
1119
                 ({asi_state_e[7:0]} == {8'h5B}) & alt_space_e & memref_e ;
1120
                dmmu_zctxt_ps0_tsb_e =
1121
                 ({asi_state_e[7:0]} == {8'h31}) & alt_space_e & memref_e ;
1122
                dmmu_zctxt_ps1_tsb_e =
1123
                 ({asi_state_e[7:0]} == {8'h32}) & alt_space_e & memref_e ;
1124
                dmmu_nzctxt_ps0_tsb_e =
1125
                 ({asi_state_e[7:0]} == {8'h39}) & alt_space_e & memref_e ;
1126
                dmmu_nzctxt_ps1_tsb_e =
1127
                 ({asi_state_e[7:0]} == {8'h3A}) & alt_space_e & memref_e ;
1128
                dmmu_zctxt_cfg_e =
1129
                 ({asi_state_e[7:0]} == {8'h33}) & alt_space_e & memref_e ;
1130
                dmmu_nzctxt_cfg_e =
1131
                 ({asi_state_e[7:0]} == {8'h3B}) & alt_space_e & memref_e ;
1132
                // IMMU
1133
                immu_decode_asi50_e =
1134
                 ({asi_state_e[7:0]} == {8'h50}) & alt_space_e & memref_e ;
1135
                immu_8k_ptr_e =
1136
                 ({asi_state_e[7:0]} == {8'h51}) & alt_space_e & memref_e ;
1137
                immu_64k_ptr_e =
1138
                 ({asi_state_e[7:0]} == {8'h52}) & alt_space_e & memref_e ;
1139
                immu_zctxt_ps0_tsb_e =
1140
                 ({asi_state_e[7:0]} == {8'h35}) & alt_space_e & memref_e ;
1141
                immu_zctxt_ps1_tsb_e =
1142
                 ({asi_state_e[7:0]} == {8'h36}) & alt_space_e & memref_e ;
1143
                immu_nzctxt_ps0_tsb_e =
1144
                 ({asi_state_e[7:0]} == {8'h3D}) & alt_space_e & memref_e ;
1145
                immu_nzctxt_ps1_tsb_e =
1146
                 ({asi_state_e[7:0]} == {8'h3E}) & alt_space_e & memref_e ;
1147
                immu_zctxt_cfg_e =
1148
                 ({asi_state_e[7:0]} == {8'h37}) & alt_space_e & memref_e ;
1149
                immu_nzctxt_cfg_e =
1150
                 ({asi_state_e[7:0]} == {8'h3F}) & alt_space_e & memref_e ;
1151
        end
1152
 
1153
wire immu_64k_ptr_m,immu_8k_ptr_m,dmmu_direct_ptr_m,dmmu_64k_ptr_m,
1154
dmmu_8k_ptr_m ;
1155
dff_s  #(19) fastasi_m (
1156
        .din    ({dmmu_8k_ptr_e,dmmu_64k_ptr_e,dmmu_direct_ptr_e,
1157
                dmmu_decode_asi58_e, immu_decode_asi50_e,
1158
                dmmu_zctxt_ps0_tsb_e, dmmu_zctxt_ps1_tsb_e,
1159
                dmmu_nzctxt_ps0_tsb_e, dmmu_nzctxt_ps1_tsb_e,
1160
                dmmu_zctxt_cfg_e, dmmu_nzctxt_cfg_e,
1161
                immu_zctxt_ps0_tsb_e, immu_zctxt_ps1_tsb_e,
1162
                immu_nzctxt_ps0_tsb_e, immu_nzctxt_ps1_tsb_e,
1163
                immu_zctxt_cfg_e, immu_nzctxt_cfg_e,
1164
                immu_8k_ptr_e,immu_64k_ptr_e}),
1165
        .q      ({dmmu_8k_ptr_m,dmmu_64k_ptr_m,dmmu_direct_ptr_m,
1166
                dmmu_decode_asi58_m, immu_decode_asi50_m,
1167
                dmmu_zctxt_ps0_tsb_m, dmmu_zctxt_ps1_tsb_m,
1168
                dmmu_nzctxt_ps0_tsb_m, dmmu_nzctxt_ps1_tsb_m,
1169
                dmmu_zctxt_cfg_m, dmmu_nzctxt_cfg_m,
1170
                immu_zctxt_ps0_tsb_m, immu_zctxt_ps1_tsb_m,
1171
                immu_nzctxt_ps0_tsb_m, immu_nzctxt_ps1_tsb_m,
1172
                immu_zctxt_cfg_m, immu_nzctxt_cfg_m,
1173
                immu_8k_ptr_m,immu_64k_ptr_m}),
1174
        .clk    (clk),
1175
        .se     (1'b0),       .si (),          .so ()
1176
        );
1177
 
1178
assign  dmmu_tag_target_en_m = dmmu_decode_asi58_m & (early_va_m[7:0] == 8'h00) ;
1179
assign  dmmu_tag_access_en_m = dmmu_decode_asi58_m & (early_va_m[7:0] == 8'h30) ;
1180
assign  dmmu_sync_fsr_en_m = dmmu_decode_asi58_m & (early_va_m[7:0] == 8'h18) ;
1181
assign  dmmu_sync_far_en_m = dmmu_decode_asi58_m & (early_va_m[7:0] == 8'h20) ;
1182
assign  dmmu_zctxt_ps0_tsb_en_m = dmmu_zctxt_ps0_tsb_m & (early_va_m[7:0] == 8'h00) ;
1183
assign  dmmu_zctxt_ps1_tsb_en_m = dmmu_zctxt_ps1_tsb_m & (early_va_m[7:0] == 8'h00) ;
1184
assign  dmmu_nzctxt_ps0_tsb_en_m = dmmu_nzctxt_ps0_tsb_m & (early_va_m[7:0] == 8'h00) ;
1185
assign  dmmu_nzctxt_ps1_tsb_en_m = dmmu_nzctxt_ps1_tsb_m & (early_va_m[7:0] == 8'h00) ;
1186
assign  dmmu_zctxt_cfg_en_m = dmmu_zctxt_cfg_m & (early_va_m[7:0] == 8'h00) ;
1187
assign  dmmu_nzctxt_cfg_en_m = dmmu_nzctxt_cfg_m & (early_va_m[7:0] == 8'h00) ;
1188
assign  dmmu_8k_ptr_en_m = dmmu_8k_ptr_m & (early_va_m[7:0] == 8'h00) ;
1189
assign  dmmu_64k_ptr_en_m = dmmu_64k_ptr_m & (early_va_m[7:0] == 8'h00) ;
1190
assign  dmmu_direct_ptr_en_m = dmmu_direct_ptr_m & (early_va_m[7:0] == 8'h00) ;
1191
 
1192
// Calculation of dmmu illgl-va
1193
 
1194
wire    dmmu_sync_supported_asi_e ;
1195
wire    dmmu_sync_supported_asi_m ;
1196
assign  dmmu_sync_supported_asi_e =
1197
        (dmmu_decode_asi58_e | dmmu_zctxt_ps0_tsb_e | dmmu_zctxt_ps1_tsb_e |
1198
        dmmu_nzctxt_ps0_tsb_e | dmmu_nzctxt_ps1_tsb_e | dmmu_zctxt_cfg_e |
1199
        dmmu_nzctxt_cfg_e | dmmu_8k_ptr_e | dmmu_64k_ptr_e | dmmu_direct_ptr_e);
1200
 
1201
dff_s stgm_dsynca (
1202
        .din    (dmmu_sync_supported_asi_e),
1203
        .q      (dmmu_sync_supported_asi_m),
1204
        .clk    (clk),
1205
        .se     (1'b0),       .si (),          .so ()
1206
        );
1207
 
1208
wire    dmmu_sync_illgl_va_m ;
1209
assign  dmmu_sync_illgl_va_m = dmmu_sync_supported_asi_m & ~(dmmu_tag_target_en_m |
1210
        dmmu_tag_access_en_m | dmmu_sync_fsr_en_m | dmmu_sync_far_en_m | dmmu_tsb_en_m |
1211
        dmmu_ctxt_cfg_en_m | dmmu_8k_ptr_en_m | dmmu_64k_ptr_en_m | dmmu_direct_ptr_en_m);
1212
 
1213
assign  dmmu_tsb_en_m =
1214
        dmmu_zctxt_ps0_tsb_en_m  | dmmu_zctxt_ps1_tsb_en_m |
1215
        dmmu_nzctxt_ps0_tsb_en_m | dmmu_nzctxt_ps1_tsb_en_m ;
1216
assign  dmmu_ctxt_cfg_en_m = dmmu_zctxt_cfg_en_m | dmmu_nzctxt_cfg_en_m ;
1217
 
1218
assign  immu_tag_target_en_m = immu_decode_asi50_m & (early_va_m[7:0] == 8'h00) ;
1219
assign  immu_tag_access_en_m = immu_decode_asi50_m & (early_va_m[7:0] == 8'h30) ;
1220
assign  immu_sync_fsr_en_m = immu_decode_asi50_m & (early_va_m[7:0] == 8'h18) ;
1221
assign  immu_zctxt_ps0_tsb_en_m = immu_zctxt_ps0_tsb_m & (early_va_m[7:0] == 8'h00) ;
1222
assign  immu_zctxt_ps1_tsb_en_m = immu_zctxt_ps1_tsb_m & (early_va_m[7:0] == 8'h00) ;
1223
assign  immu_nzctxt_ps0_tsb_en_m = immu_nzctxt_ps0_tsb_m & (early_va_m[7:0] == 8'h00) ;
1224
assign  immu_nzctxt_ps1_tsb_en_m = immu_nzctxt_ps1_tsb_m & (early_va_m[7:0] == 8'h00) ;
1225
assign  immu_zctxt_cfg_en_m = immu_zctxt_cfg_m & (early_va_m[7:0] == 8'h00) ;
1226
assign  immu_nzctxt_cfg_en_m = immu_nzctxt_cfg_m & (early_va_m[7:0] == 8'h00) ;
1227
assign  immu_8k_ptr_en_m = immu_8k_ptr_m & (early_va_m[7:0] == 8'h00) ;
1228
assign  immu_64k_ptr_en_m = immu_64k_ptr_m & (early_va_m[7:0] == 8'h00) ;
1229
 
1230
assign  immu_tsb_en_m =
1231
        immu_zctxt_ps0_tsb_en_m  | immu_zctxt_ps1_tsb_en_m |
1232
        immu_nzctxt_ps0_tsb_en_m | immu_nzctxt_ps1_tsb_en_m ;
1233
assign  immu_ctxt_cfg_en_m = immu_zctxt_cfg_en_m | immu_nzctxt_cfg_en_m ;
1234
 
1235
 
1236
// Calculation of immu illgl-va
1237
 
1238
wire    immu_sync_supported_asi_e ;
1239
wire    immu_sync_supported_asi_m ;
1240
assign  immu_sync_supported_asi_e =
1241
        (immu_decode_asi50_e | immu_zctxt_ps0_tsb_e | immu_zctxt_ps1_tsb_e |
1242
        immu_nzctxt_ps0_tsb_e | immu_nzctxt_ps1_tsb_e | immu_zctxt_cfg_e |
1243
        immu_nzctxt_cfg_e | immu_8k_ptr_e | immu_64k_ptr_e);
1244
 
1245
dff_s stgm_isynca (
1246
        .din    (immu_sync_supported_asi_e),
1247
        .q      (immu_sync_supported_asi_m),
1248
        .clk    (clk),
1249
        .se     (1'b0),       .si (),          .so ()
1250
        );
1251
 
1252
wire    immu_sync_illgl_va_m ;
1253
assign  immu_sync_illgl_va_m = immu_sync_supported_asi_m & ~(immu_tag_target_en_m |
1254
        immu_tag_access_en_m | immu_sync_fsr_en_m | immu_tsb_en_m | immu_ctxt_cfg_en_m |
1255
        immu_8k_ptr_en_m | immu_64k_ptr_en_m);
1256
 
1257
dff_s #(2) stgg_illgl (
1258
        .din    ({immu_sync_illgl_va_m,dmmu_sync_illgl_va_m}),
1259
        .q      ({immu_sync_illgl_va_g,dmmu_sync_illgl_va_g}),
1260
        .clk    (clk),
1261
        .se     (1'b0),       .si (),          .so ()
1262
        );
1263
 
1264
// Staged to g for writes
1265
dff_s  #(17) fastasi_g (
1266
        .din    ({dmmu_tag_access_en_m,
1267
                dmmu_sync_fsr_en_m, dmmu_sync_far_en_m,
1268
                dmmu_zctxt_ps0_tsb_en_m, dmmu_zctxt_ps1_tsb_en_m,
1269
                dmmu_nzctxt_ps0_tsb_en_m, dmmu_nzctxt_ps1_tsb_en_m,
1270
                dmmu_zctxt_cfg_en_m, dmmu_nzctxt_cfg_en_m,
1271
                immu_tag_access_en_m,
1272
                immu_sync_fsr_en_m,
1273
                immu_zctxt_ps0_tsb_en_m, immu_zctxt_ps1_tsb_en_m,
1274
                immu_nzctxt_ps0_tsb_en_m, immu_nzctxt_ps1_tsb_en_m,
1275
                immu_zctxt_cfg_en_m, immu_nzctxt_cfg_en_m}),
1276
        .q      ({dmmu_tag_access_en,
1277
                dmmu_sync_fsr_en, dmmu_sync_far_en,
1278
                dmmu_zctxt_ps0_tsb_en, dmmu_zctxt_ps1_tsb_en,
1279
                dmmu_nzctxt_ps0_tsb_en, dmmu_nzctxt_ps1_tsb_en,
1280
                dmmu_zctxt_cfg_en, dmmu_nzctxt_cfg_en,
1281
                immu_tag_access_en,
1282
                immu_sync_fsr_en,
1283
                immu_zctxt_ps0_tsb_en, immu_zctxt_ps1_tsb_en,
1284
                immu_nzctxt_ps0_tsb_en, immu_nzctxt_ps1_tsb_en,
1285
                immu_zctxt_cfg_en, immu_nzctxt_cfg_en}),
1286
        .clk    (clk),
1287
        .se     (1'b0),       .si (),          .so ()
1288
        );
1289
 
1290
//=========================================================================================
1291
//      MMU ASI Decode - D-Side
1292
//=========================================================================================
1293
 
1294
 
1295
// Assumption is that only 9 bits of VA are required.
1296
// Comparison for asi-state and va is to be done uniformly in w2.
1297
 
1298
// This will have to change because of tsb mapping to mra.
1299
        assign  dmmu_tsb_en =
1300
                        dmmu_zctxt_ps0_tsb_en  | dmmu_zctxt_ps1_tsb_en |
1301
                        dmmu_nzctxt_ps0_tsb_en | dmmu_nzctxt_ps1_tsb_en ;
1302
 
1303
assign  tlb_ldst_inst_m = lsu_tlu_tlb_ld_inst_m | lsu_tlu_tlb_st_inst_m ;
1304
 
1305
// M-stage decoding for long-latency tlb accesses
1306
always  @ (/*AUTOSENSE*/dmmu_inv_all_asi or lsu_tlu_tlb_asi_state_m
1307
           or lsu_tlu_tlb_ldst_va_m[7:0] or tlb_ldst_inst_m)
1308
        begin
1309
                dmmu_data_in_en_m =
1310
                 ({lsu_tlu_tlb_asi_state_m[7:0],lsu_tlu_tlb_ldst_va_m[7:0]} == {8'h5C,8'h00}) & tlb_ldst_inst_m ;
1311
                dmmu_invalidate_all_en_m =
1312
                 dmmu_inv_all_asi & tlb_ldst_inst_m ;
1313
                 //({lsu_tlu_tlb_asi_state_m[7:0],lsu_tlu_tlb_ldst_va_m[7:0]} == {8'h60,8'h08}) & tlb_ldst_inst_m ;
1314
                // Address specifies tlb entry.
1315
                dmmu_data_access_en_m =
1316
                 ({lsu_tlu_tlb_asi_state_m[7:0]} == {8'h5D}) &   tlb_ldst_inst_m ;
1317
                // Address specifies tlb entry.
1318
                dmmu_tag_read_en_m =
1319
                 ({lsu_tlu_tlb_asi_state_m[7:0]} == {8'h5E}) &   tlb_ldst_inst_m ;
1320
                dmmu_demap_en_m =
1321
                 ({lsu_tlu_tlb_asi_state_m[7:0]} == {8'h5F}) &  tlb_ldst_inst_m ;
1322
        end
1323
 
1324
// Stage to g.
1325
// Make dff->dffre. This required to avoid conflict between fast-asi and lng-latency
1326
// rds of mra. Specifically, data-in/data_access need to be staged, along with
1327
// support information.
1328
 
1329
wire lng_ltncy_en_d1 ;
1330
assign  tlu_lng_ltncy_en_l = ~lng_ltncy_en_d1 | sehold ;
1331
wire    lng_ltncy_en ;
1332
dff_s stgd1_lltncyen (
1333
        .din    (lng_ltncy_en),
1334
        .q      (lng_ltncy_en_d1),
1335
        .clk    (clk),
1336
        .se     (1'b0),       .si (),          .so ()
1337
        );
1338
 
1339
assign  lng_ltncy_en = (lsu_tlu_tlb_st_inst_m | lsu_tlu_tlb_ld_inst_m) ;
1340
wire    lng_ltncy_rst ;
1341
assign  lng_ltncy_rst =
1342
        tlb_ld_inst_unflushed |         // all reads processed immediately
1343
        (tlb_st_inst_unflushed &        // all writes not requiring mra processed immediately
1344
                ~(dmmu_data_in_en | dmmu_data_access_en | immu_data_in_en | immu_data_access_en)) |
1345
        dmra_lng_lat_rd | imra_lng_lat_rd | // lng-ltncy rds - delay until bubble available.
1346
        ((tlb_ld_inst_unflushed | tlb_st_inst_unflushed) &  // rst w/o use if illgl-va
1347
                        (dmmu_async_illgl_va_g | immu_async_illgl_va_g)) |
1348
        ~rst_l ;
1349
 
1350
dffe_s  #(10) dtlbacc_stgg (
1351
        .din    ({lsu_tlu_tlb_ldst_va_m[10:3], lsu_tlu_tlb_access_tid_m[1:0]}),
1352
        .q      ({tlb_ldst_va_g[10:3],tlb_access_tid_g[1:0]}),
1353
        .clk    (clk),
1354
        .en     (lng_ltncy_en),
1355
        .se     (1'b0),       .si (),          .so ()
1356
        );
1357
 
1358
dffre_s  #(7) dtlbaccr_stgg (
1359
        .din    ({dmmu_data_in_en_m,dmmu_data_access_en_m,dmmu_tag_read_en_m,
1360
                dmmu_demap_en_m,dmmu_invalidate_all_en_m,
1361
                lsu_tlu_tlb_ld_inst_m,lsu_tlu_tlb_st_inst_m}),
1362
        .q      ({dmmu_data_in_en,dmmu_data_access_en,dmmu_tag_read_en,
1363
                dmmu_demap_en,dmmu_invalidate_all_en,
1364
                tlb_ld_inst_unflushed,tlb_st_inst_unflushed}),
1365
        .clk    (clk),
1366
        .rst    (lng_ltncy_rst),        .en     (lng_ltncy_en),
1367
        .se     (1'b0),       .si (),          .so ()
1368
        );
1369
 
1370
 
1371
assign  tlb_st_inst_g = tlb_st_inst_unflushed & ~(dmmu_async_illgl_va_g | immu_async_illgl_va_g) ;
1372
assign  tlb_ld_inst_g = tlb_ld_inst_unflushed & ~(dmmu_async_illgl_va_g | immu_async_illgl_va_g) ;
1373
 
1374
assign  dsfsr_asi_wr_en[0] = dmmu_sync_fsr_en & st_inst_g & thread0_sel_g ;
1375
assign  dsfsr_asi_wr_en[1] = dmmu_sync_fsr_en & st_inst_g & thread1_sel_g ;
1376
assign  dsfsr_asi_wr_en[2] = dmmu_sync_fsr_en & st_inst_g & thread2_sel_g ;
1377
assign  dsfsr_asi_wr_en[3] = dmmu_sync_fsr_en & st_inst_g & thread3_sel_g ;
1378
 
1379
assign  dmmu_any_sfsr_wr = dmmu_sync_fsr_en & st_inst_g ; //|(dsfsr_asi_wr_en[3:0]);
1380
 
1381
assign  dmmu_sfsr_wr_en_l[3:0] =
1382
~(dsfsr_asi_wr_en[3:0] | (dmmu_sfsr_trp_wr[3:0] & {4{~priority_squash_g}})) ; // Bug 4183
1383
 
1384
assign  dmmu_sfar_wr_en_l[0] =
1385
~((dmmu_sync_far_en & st_inst_g & thread0_sel_g) |
1386
(dmmu_sfsr_trp_wr[0] & ~priority_squash_g)) ; // Bug 4183
1387
assign  dmmu_sfar_wr_en_l[1] =
1388
~((dmmu_sync_far_en & st_inst_g & thread1_sel_g) |
1389
(dmmu_sfsr_trp_wr[1] & ~priority_squash_g)) ;
1390
assign  dmmu_sfar_wr_en_l[2] =
1391
~((dmmu_sync_far_en & st_inst_g & thread2_sel_g) |
1392
(dmmu_sfsr_trp_wr[2] & ~priority_squash_g)) ;
1393
assign  dmmu_sfar_wr_en_l[3] =
1394
~((dmmu_sync_far_en & st_inst_g & thread3_sel_g) |
1395
(dmmu_sfsr_trp_wr[3] & ~priority_squash_g)) ;
1396
 
1397
 
1398
assign  dmmu_data_in_wr_en = dmmu_data_in_en & tlb_st_inst_g ;  // Write-Only.
1399
assign  dmmu_data_access_wr_en = dmmu_data_access_en & tlb_st_inst_g ;
1400
// non-threaded as shared resource
1401
assign  dmmu_data_access_rd_en = dmmu_data_access_en & tlb_ld_inst_g ;
1402
 
1403
// take exception for write case.
1404
assign  dmmu_tag_read_rd_en = dmmu_tag_read_en & tlb_ld_inst_g ;
1405
 
1406
 
1407
assign  dtlb_rw_index_vld_g = dmmu_data_access_rd_en | dmmu_data_access_wr_en | dmmu_tag_read_rd_en ;
1408
// terminate write if tlb full and signal exception.
1409
assign  dtlb_wr_vld_g = (dmmu_data_in_wr_en | dmmu_data_access_wr_en) & ~ifu_lsu_memref_d ;
1410
 
1411
wire            dtlb_rw_index_vld_pend ;
1412
wire [5:0]       dtlb_rw_index_pend ;
1413
 
1414
dffre_s  #(1) stgw2_dtlbctl (
1415
        .din    (dtlb_rw_index_vld_g),
1416
        .q      (dtlb_rw_index_vld_pend),
1417
        .rst    (tlb_access_rst),       .en     (tlb_access_en),
1418
        .clk    (clk),
1419
        .se     (1'b0),       .si (),          .so ()
1420
        );
1421
 
1422
dffre_s  #(6) stgw2_dtlbidx (
1423
        .din    (tlb_ldst_va_g[8:3]),
1424
        .q      (dtlb_rw_index_pend[5:0]),
1425
        .rst    (tlb_access_rst),       .en     (tlb_access_en),
1426
        .clk    (clk),
1427
        .se     (1'b0),       .si (),          .so ()
1428
        );
1429
 
1430
wire    tlb_rd_mode, tlb_rd_mode_d1 ;
1431
assign  tlb_rd_mode =
1432
                tlu_itlb_tag_rd_g | tlu_itlb_data_rd_g |        // i-side read
1433
                tlu_dtlb_tag_rd_g | tlu_dtlb_data_rd_g ;        // d-side read
1434
 
1435
dff_s stgd1_rmode (
1436
        .din    (tlb_rd_mode),
1437
        .q      (tlb_rd_mode_d1),
1438
        .clk    (clk),
1439
        .se     (1'b0),       .si (),          .so ()
1440
        );
1441
 
1442
wire    dtlb_done_d1 ;
1443
dff_s stgd1_ddone (
1444
        .din    (lsu_tlu_dtlb_done),
1445
        .q      (dtlb_done_d1),
1446
        .clk    (clk),
1447
        .se     (1'b0),       .si (),          .so ()
1448
        );
1449
 
1450
wire    itlb_done_d1 ;
1451
dff_s stgd1_idone (
1452
        .din    (ifu_tlu_itlb_done),
1453
        .q      (itlb_done_d1),
1454
        .clk    (clk),
1455
        .se     (1'b0),       .si (),          .so ()
1456
        );
1457
 
1458
// Advanced by a cycle.
1459
assign  tlu_dtlb_rw_index_vld_g  = dtlb_rw_index_vld_g | dtlb_rw_index_vld_pend ;
1460
//assign        tlu_dtlb_rw_index_vld_g  = dtlb_rw_index_vld_g | (dtlb_rw_index_vld_pend & ~dtlb_done_d1) ; //Bug3974
1461
//assign        tlu_dtlb_rw_index_vld_g  = dtlb_rw_index_vld_g | (dtlb_rw_index_vld_pend & ~lsu_tlu_dtlb_done) ;
1462
assign  tlu_dtlb_rw_index_g[5:0] = (tlb_ldst_va_g[8:3] & {6{~(tlb_admp_mode | tlb_write_mode | tlb_rd_mode_d1)}})  |
1463
                                        dtlb_rw_index_pend[5:0]  ;
1464
 
1465
// Exception on reserved field.
1466
assign  demap_pctxt = ~tlb_ldst_va_g[5] & ~tlb_ldst_va_g[4] ;
1467
assign  demap_sctxt = ~tlb_ldst_va_g[5] &  tlb_ldst_va_g[4] ;
1468
assign  demap_nctxt =  tlb_ldst_va_g[5] & ~tlb_ldst_va_g[4] ;
1469
// reserved ctxt causes demap to be ignored.
1470
// reserved dmp type causes demap to be ignored.
1471
assign  demap_resrv =   (tlb_ldst_va_g[5] &  tlb_ldst_va_g[4])          // ctxt
1472
                        | (tlb_ldst_va_g[7] &  tlb_ldst_va_g[6]) ;      // type
1473
 
1474
assign  ddemap_by_page  = dmmu_demap_en & ~tlb_ldst_va_g[7] & ~tlb_ldst_va_g[6] ;
1475
assign  ddemap_by_ctxt  = dmmu_demap_en & ~tlb_ldst_va_g[7] &  tlb_ldst_va_g[6] ;
1476
assign  ddemap_all      = dmmu_demap_en &  tlb_ldst_va_g[7] & ~tlb_ldst_va_g[6] ;
1477
 
1478
// assumption is that demap_all is unaffected by presence of reserved ctxt as it
1479
// does not use ctxt.
1480
assign  ddemap_vld      = ((ddemap_by_page | ddemap_by_ctxt) & ~demap_resrv) |
1481
                                ddemap_all ;
1482
 
1483
//wire          dtlb_dmp_by_ctxt_pend ;
1484
wire            dtlb_dmp_all_pend ;
1485
wire            dtlb_dmp_pctxt_pend ;
1486
wire            dtlb_dmp_sctxt_pend ;
1487
wire            dtlb_dmp_nctxt_pend ;
1488
wire    [1:0]    idtlb_dmp_thrid_pend ;
1489
wire    [1:0]    ldst_asi_tid ;
1490
wire            dmmu_inv_all_g, dmmu_inv_all_pend ;
1491
 
1492
assign  dmmu_inv_all_g = dmmu_invalidate_all_en & tlb_st_inst_g ;
1493
 
1494
// Demap/Invalidate
1495
dffre_s  #(5) stgw2_dtlbdmp (
1496
        .din    ({ddemap_all,demap_pctxt,demap_sctxt,demap_nctxt,dmmu_inv_all_g}),
1497
        .q      ({dtlb_dmp_all_pend,dtlb_dmp_pctxt_pend,dtlb_dmp_sctxt_pend,
1498
                dtlb_dmp_nctxt_pend,dmmu_inv_all_pend }),
1499
        .rst    (tlb_access_rst),       .en     (tlb_access_en),
1500
        .clk    (clk),
1501
        .se     (1'b0),       .si (),          .so ()
1502
        );
1503
 
1504
// Bug 3905 - rm from above flop.
1505
assign  idtlb_dmp_thrid_pend[1:0] = tlb_access_tid_g[1:0] ;
1506
 
1507
assign  ldst_asi_tid[1:0] =
1508
        (lsu_tlu_dtlb_done | dmmu_async_illgl_va_g | immu_async_illgl_va_g)  ?
1509
        idtlb_dmp_thrid_pend[1:0] : thrid_g[1:0] ;
1510
 
1511
// Thread for tlb
1512
dff_s  #(4) stg_w2 (
1513
        .din    ({ldst_asi_tid[1:0],idtlb_dmp_thrid_pend[1:0]}),
1514
        .q      ({tlu_lsu_ldxa_tid_w2[1:0],tlu_lsu_stxa_ack_tid[1:0]}),
1515
        .clk    (clk),
1516
        .se     (1'b0),       .si (),          .so ()
1517
        );
1518
 
1519
assign  tlu_dtlb_invalidate_all_g = dmmu_inv_all_g | (dmmu_inv_all_pend & ~dtlb_done_d1) ;
1520
//assign        tlu_dtlb_invalidate_all_g = dmmu_inv_all_g | (dmmu_inv_all_pend & ~lsu_tlu_dtlb_done) ;
1521
 
1522
// Timing Change : Delay by a cycle to match vlds.
1523
wire  pre_dtlb_dmp_all, pre_dtlb_dmp_pctxt ;
1524
wire pre_dtlb_dmp_sctxt, pre_dtlb_dmp_nctxt, pre_dtlb_dmp_actxt ;
1525
//assign        pre_dtlb_dmp_by_ctxt = (ddemap_by_ctxt | dtlb_dmp_by_ctxt_pend) & ~tlu_admp_key_sel  ;
1526
assign  pre_dtlb_dmp_all = (ddemap_all | dtlb_dmp_all_pend) & ~tlu_admp_key_sel ;
1527
assign  pre_dtlb_dmp_pctxt = (dtlb_dmp_pctxt_pend) & ~tlu_admp_key_sel ;
1528
assign  pre_dtlb_dmp_sctxt = (dtlb_dmp_sctxt_pend) & ~tlu_admp_key_sel ;
1529
assign  pre_dtlb_dmp_nctxt = (dtlb_dmp_nctxt_pend) & ~tlu_admp_key_sel ;
1530
assign  pre_dtlb_dmp_actxt = tlu_admp_key_sel ;
1531
 
1532
dff_s  #(5) dmp_stgd1 (
1533
        .din    ({pre_dtlb_dmp_all, pre_dtlb_dmp_pctxt,
1534
                pre_dtlb_dmp_sctxt, pre_dtlb_dmp_nctxt, pre_dtlb_dmp_actxt}),
1535
        .q      ({tlu_dtlb_dmp_all_g,tlu_dtlb_dmp_pctxt_g,
1536
                tlu_dtlb_dmp_sctxt_g,tlu_dtlb_dmp_nctxt_g,tlu_dtlb_dmp_actxt_g}),
1537
        .clk    (clk),
1538
        .se     (1'b0),       .si (),          .so ()
1539
        );
1540
 
1541
assign  tlu_idtlb_dmp_thrid_g = tlb_access_tid_g[1:0] | idtlb_dmp_thrid_pend[1:0] ;
1542
 
1543
 
1544
//=========================================================================================
1545
//      MMU ASI Decode - I-Side
1546
//=========================================================================================
1547
 
1548
// Assumption is that only 9 bits of VA are required.
1549
// Comparison for asi-state and va is to be done uniformly in w2.
1550
 
1551
        assign  immu_tsb_en =
1552
                        immu_zctxt_ps0_tsb_en  | immu_zctxt_ps1_tsb_en |
1553
                        immu_nzctxt_ps0_tsb_en | immu_nzctxt_ps1_tsb_en ;
1554
 
1555
reg     immu_data_in_en_m,immu_data_access_en_m,immu_tag_read_en_m,immu_demap_en_m;
1556
 
1557
// M-stage decoding for long-latency tlb accesses
1558
always  @ (/*AUTOSENSE*/immu_inv_all_asi or lsu_tlu_tlb_asi_state_m
1559
           or lsu_tlu_tlb_ldst_va_m[7:0] or tlb_ldst_inst_m)
1560
        begin
1561
                immu_data_in_en_m =
1562
                 ({lsu_tlu_tlb_asi_state_m[7:0],lsu_tlu_tlb_ldst_va_m[7:0]} == {8'h54,8'h00}) & tlb_ldst_inst_m ;
1563
                // Address specifies tlb entry.
1564
                immu_invalidate_all_en_m =
1565
                 immu_inv_all_asi & tlb_ldst_inst_m ;
1566
                 //({lsu_tlu_tlb_asi_state_m[7:0],lsu_tlu_tlb_ldst_va_m[7:0]} == {8'h60,8'h00}) & tlb_ldst_inst_m ;
1567
                immu_data_access_en_m =
1568
                 ({lsu_tlu_tlb_asi_state_m[7:0]} == {8'h55}) & tlb_ldst_inst_m ;
1569
                // Address specifies tlb entry.
1570
                immu_tag_read_en_m =
1571
                 ({lsu_tlu_tlb_asi_state_m[7:0]} == {8'h56}) & tlb_ldst_inst_m ;
1572
                immu_demap_en_m =
1573
                 ({lsu_tlu_tlb_asi_state_m[7:0]} == {8'h57}) & tlb_ldst_inst_m ;
1574
        end
1575
 
1576
// Stage to g.
1577
// Convert to dffre to resolve conflict between fast-asi and lng-ltncy reads.
1578
dffre_s #(5) itlbacc_stgg (
1579
        .din    ({immu_data_in_en_m,immu_data_access_en_m,immu_tag_read_en_m,immu_demap_en_m,immu_invalidate_all_en_m}),
1580
        .q      ({immu_data_in_en,immu_data_access_en,immu_tag_read_en,immu_demap_en,immu_invalidate_all_en}),
1581
        .clk    (clk),
1582
        .rst    (lng_ltncy_rst),        .en     (lng_ltncy_en),
1583
        .se     (1'b0),       .si (),          .so ()
1584
        );
1585
 
1586
 
1587
assign  isfsr_asi_wr_en[0] = immu_sync_fsr_en & st_inst_g & thread0_sel_g ;
1588
assign  isfsr_asi_wr_en[1] = immu_sync_fsr_en & st_inst_g & thread1_sel_g ;
1589
assign  isfsr_asi_wr_en[2] = immu_sync_fsr_en & st_inst_g & thread2_sel_g ;
1590
assign  isfsr_asi_wr_en[3] = immu_sync_fsr_en & st_inst_g & thread3_sel_g ;
1591
 
1592
assign  immu_any_sfsr_wr = immu_sync_fsr_en & st_inst_g ; //|(isfsr_asi_wr_en[3:0]);
1593
 
1594
assign  immu_sfsr_wr_en_l[3:0] = ~(isfsr_trp_wr[3:0] | isfsr_asi_wr_en[3:0]) ;
1595
 
1596
assign  immu_tsb_rd_en[0] = immu_tsb_en & ld_inst_g & thread0_sel_g ;
1597
assign  immu_tsb_rd_en[1] = immu_tsb_en & ld_inst_g & thread1_sel_g ;
1598
assign  immu_tsb_rd_en[2] = immu_tsb_en & ld_inst_g & thread2_sel_g ;
1599
assign  immu_tsb_rd_en[3] = immu_tsb_en & ld_inst_g & thread3_sel_g ;
1600
 
1601
assign  immu_data_in_wr_en = immu_data_in_en & tlb_st_inst_g ;  // Write-Only.
1602
assign  immu_data_access_wr_en = immu_data_access_en & tlb_st_inst_g ;
1603
assign  immu_data_access_rd_en = immu_data_access_en & tlb_ld_inst_g ;
1604
 
1605
assign  immu_tag_read_rd_en = immu_tag_read_en & tlb_ld_inst_g ;
1606
 
1607
assign  itlb_rw_index_vld_g = immu_data_access_rd_en | immu_data_access_wr_en | immu_tag_read_rd_en ;
1608
// terminate write if tlb full and signal exception.
1609
assign  itlb_wr_vld_g = (immu_data_in_wr_en | immu_data_access_wr_en) & ~ifu_lsu_memref_d ;
1610
 
1611
wire    itlb_rw_index_vld_pend ;
1612
 
1613
dffre_s #(1)  stgw2_itlbctl (
1614
        .din    (itlb_rw_index_vld_g),
1615
        .q      (itlb_rw_index_vld_pend),
1616
        .rst    (tlb_access_rst),       .en     (tlb_access_en),
1617
        .clk    (clk),
1618
        .se     (1'b0),       .si (),          .so ()
1619
        );
1620
 
1621
assign  tlu_itlb_rw_index_vld_g  = itlb_rw_index_vld_g | (itlb_rw_index_vld_pend & ~itlb_done_d1) ;
1622
assign  tlu_itlb_rw_index_g[5:0] = tlu_dtlb_rw_index_g[5:0] ;
1623
 
1624
assign  idemap_by_page  = immu_demap_en & ~tlb_ldst_va_g[7] & ~tlb_ldst_va_g[6] ;
1625
assign  idemap_by_ctxt  = immu_demap_en & ~tlb_ldst_va_g[7] &  tlb_ldst_va_g[6] ;
1626
assign  idemap_all      = immu_demap_en &  tlb_ldst_va_g[7] & ~tlb_ldst_va_g[6] ;
1627
 
1628
// assumption is that demap_all is unaffected by presence of reserved ctxt as it
1629
// does not use ctxt.
1630
assign  idemap_vld      = ((idemap_by_page | idemap_by_ctxt) & ~(demap_resrv | demap_sctxt)) |
1631
                                idemap_all ;
1632
 
1633
wire    itlb_dmp_by_ctxt_pend ;
1634
wire    itlb_dmp_all_pend ;
1635
wire    immu_inv_all_g, immu_inv_all_pend ;
1636
 
1637
assign  immu_inv_all_g = immu_invalidate_all_en & tlb_st_inst_g ;
1638
 
1639
// Demap
1640
dffre_s  #(3) stgw2_itlbdmp (
1641
        .din    ({idemap_by_ctxt,idemap_all,immu_inv_all_g}),
1642
        .q      ({itlb_dmp_by_ctxt_pend, itlb_dmp_all_pend,immu_inv_all_pend}),
1643
        .rst    (tlb_access_rst),       .en     (tlb_access_en),
1644
        .clk    (clk),
1645
        .se     (1'b0),       .si (),          .so ()
1646
        );
1647
 
1648
wire    tlu_itlb_dmp_all_g = (idemap_all | itlb_dmp_all_pend) & ~tlu_admp_key_sel ;
1649
 
1650
assign  tlu_itlb_invalidate_all_g = immu_inv_all_g | (immu_inv_all_pend & ~itlb_done_d1) ;
1651
assign  tlu_itlb_dmp_pctxt_g = tlu_dtlb_dmp_pctxt_g ;
1652
 
1653
// Timing Change - delay by 1-cycle to match vld.
1654
wire    pre_itlb_dmp_actxt ;
1655
assign  pre_itlb_dmp_actxt = tlu_admp_key_sel ;
1656
dff_s  #(1) preidmp_d1 (
1657
        .din    (pre_itlb_dmp_actxt),
1658
        .q      (tlu_itlb_dmp_actxt_g),
1659
        .clk    (clk),
1660
        .se     (1'b0),       .si (),          .so ()
1661
        );
1662
 
1663
assign  tlu_itlb_dmp_nctxt_g = tlu_dtlb_dmp_nctxt_g ;
1664
 
1665
 
1666
// Adapt key vlds to autodemap.
1667
// Note that sense of global bit has changed. Otherwise vlds remain same.
1668
assign  tlu_dmp_key_vld_g[4:0] =
1669
        (ddemap_by_ctxt | idemap_by_ctxt) ? 5'b00000 :                  // demap-ctxt - include only ctxt 
1670
                        (ddemap_all | idemap_all) ? 5'b00001 :          // demap-all - do not include va or ctxt
1671
                        // Bug 3129             5'b11110 ;              // else include both va and ctxt
1672
                                tlb_ldst_va_g[9] ? 5'b11111 :           // include va and NO ctxt;dmp-pg-real
1673
                                                       5'b11110 ;       // include both va and ctxt; dmp-pg
1674
 
1675
// real tte for demap and write. both are indicated in bit 9 of va.
1676
// demap_by_ctxt will not effect real translations.
1677
assign  tlu_tte_real_g = tlb_ldst_va_g[9] & ~(ddemap_by_ctxt | idemap_by_ctxt) ;
1678
 
1679
//=========================================================================================
1680
//      EXCEPTIONS
1681
//=========================================================================================
1682
 
1683
// Now generated in LSU.
1684
 
1685
// These are all related to asi use.
1686
/*assign        tlu_mmu_sync_data_excp_g =
1687
        (immu_sync_rd_only_asi_g | dmmu_sync_rd_only_asi_g) & st_inst_unflushed & inst_vld_g  ;*/
1688
 
1689
//=========================================================================================
1690
//      TAG/DATA RD/WR/DMP HANDSHAKE
1691
//=========================================================================================
1692
 
1693
// RD/WR HANDSHAKE
1694
// Need to add autodemap capability.
1695
 
1696
// Assume mutually exclusive by construction.
1697
assign  tlb_access_en = itlb_wr_vld_g | immu_data_access_rd_en | immu_tag_read_rd_en |
1698
                        dtlb_wr_vld_g | dmmu_data_access_rd_en | dmmu_tag_read_rd_en |
1699
                        idemap_vld    | ddemap_vld | immu_inv_all_g | dmmu_inv_all_g ;
1700
assign  tlb_access_en_l = ~tlb_access_en ;
1701
assign  tlb_access_rst = ~rst_l | ((lsu_tlu_dtlb_done | ifu_tlu_itlb_done) & ~(tlb_admp_mode | tlb_admp_mode_d1)) ;
1702
assign  tlb_access_rst_l = ~tlb_access_rst ;
1703
 
1704
wire    tlb_access_en_l_d1 ;
1705
dff_s  #(1) stgd1_tlbacc (
1706
        .din    (tlb_access_en_l),
1707
        .q      (tlb_access_en_l_d1),
1708
        .clk    (clk),
1709
        .se     (1'b0),       .si (),          .so ()
1710
        );
1711
 
1712
assign  tlu_tlb_access_en_l_d1 = tlb_access_en_l_d1 | sehold ;
1713
 
1714
assign  itlb_tag_rd_en = immu_tag_read_rd_en | immu_data_access_rd_en ;
1715
assign  dtlb_tag_rd_en = dmmu_tag_read_rd_en | dmmu_data_access_rd_en ;
1716
 
1717
dffre_s #(8)  tlb_access (
1718
        .din    ({itlb_wr_vld_g,immu_data_access_rd_en,itlb_tag_rd_en,
1719
                dtlb_wr_vld_g,dmmu_data_access_rd_en,dtlb_tag_rd_en,
1720
                idemap_vld, ddemap_vld}),
1721
        .q      ({itlb_wr_pend,itlb_data_rd_pend,itlb_tag_rd_pend,
1722
                dtlb_wr_pend,dtlb_data_rd_pend,dtlb_tag_rd_pend,
1723
                idemap_pend, ddemap_pend}),
1724
        .rst    (tlb_access_rst),       .en     (tlb_access_en),
1725
        .clk    (clk),
1726
        .se     (1'b0),       .si (),          .so ()
1727
        );
1728
assign  tlu_dtlb_rd_done  = lsu_tlu_dtlb_done & (dtlb_data_rd_pend | dtlb_tag_rd_pend) ;
1729
//assign  itlb_rd_done  = ifu_tlu_itlb_done & (itlb_data_rd_pend | itlb_tag_rd_pend) ;
1730
 
1731
 
1732
// w2 should be renamed to g at some time !!!
1733
// Write may take one extra cycle to get initiated !!!
1734
assign  itlb_wr_vld_unmsked = (itlb_wr_vld_g | (itlb_wr_pend & ~itlb_done_d1)) ;
1735
wire    pre_itlb_wr_vld_g ;
1736
assign pre_itlb_wr_vld_g = (itlb_wr_pend & ~itlb_done_d1) & tlb_write_mode ;
1737
//assign pre_itlb_wr_vld_g = itlb_wr_vld_unmsked & tlb_write_mode ;
1738
// name kept as _g for now to avoid interface change.
1739
 
1740
assign  tlu_itlb_wr_vld_g = pre_itlb_wr_vld_g ;
1741
/*dff  #(1) iwvld_d1 (
1742
        .din    (pre_itlb_wr_vld_g),
1743
        .q      (tlu_itlb_wr_vld_g),
1744
        .clk    (clk),
1745
        .se     (1'b0),       .si (),          .so ()
1746
        ); */
1747
assign  tlu_itlb_data_rd_g = immu_data_access_rd_en | (itlb_data_rd_pend & ~itlb_done_d1) ;
1748
assign  tlu_itlb_tag_rd_g = (immu_tag_read_rd_en | immu_data_access_rd_en) | (itlb_tag_rd_pend & ~itlb_done_d1) ;
1749
 
1750
assign  dtlb_wr_vld_unmsked = (dtlb_wr_vld_g | (dtlb_wr_pend & ~dtlb_done_d1)) ;
1751
wire    pre_dtlb_wr_vld_g ;
1752
assign pre_dtlb_wr_vld_g = (dtlb_wr_pend & ~dtlb_done_d1) & tlb_write_mode ;
1753
// name kept as _g for now to avoid interface change.
1754
 
1755
//assign        tlu_dtlb_wr_vld_g = pre_dtlb_wr_vld_g ;
1756
assign  tlu_dtlb_data_rd_g = dmmu_data_access_rd_en | (dtlb_data_rd_pend & ~dtlb_done_d1) ;
1757
assign  tlu_dtlb_tag_rd_g = (dmmu_tag_read_rd_en | dmmu_data_access_rd_en) | (dtlb_tag_rd_pend & ~dtlb_done_d1) ;
1758
 
1759
// Delay by a cycle - rd for long-latency matches fast-asi.
1760
// Both occur on a posedge.
1761
 
1762
wire    dtlb_dmp_vld_g,itlb_dmp_vld_g;
1763
assign  dtlb_dmp_vld_g =
1764
                // qual with dtlb-done may not be needed. Taken into account in ddemap_pend.
1765
                (ddemap_pend & ~dtlb_done_d1) |
1766
                (dtlb_wr_vld_unmsked & tlb_admp_mode) ;
1767
assign  itlb_dmp_vld_g =
1768
                (idemap_pend & ~itlb_done_d1) |
1769
                (itlb_wr_vld_unmsked & tlb_admp_mode) ;
1770
// dmp_vld should be w2. kept as _g for now to avoid
1771
// interface change.
1772
wire    dtlb_dmp_vld_d1,itlb_dmp_vld_d1 ;
1773
dff_s  #(2) dmpvld_d1 (
1774
        .din    ({dtlb_dmp_vld_g,itlb_dmp_vld_g}),
1775
        .q      ({dtlb_dmp_vld_d1,itlb_dmp_vld_d1}),
1776
        .clk    (clk),
1777
        .se     (1'b0),       .si (),          .so ()
1778
        );
1779
assign  tlu_dtlb_dmp_vld_g = dtlb_dmp_vld_d1 & ~dtlb_done_d1 ;
1780
assign  tlu_itlb_dmp_vld_g = itlb_dmp_vld_d1 & ~itlb_done_d1 ;
1781
 
1782
wire    stxa_ack ;
1783
 
1784
// Assume mutually exclusive.
1785
// Third term is meant to complete demap with reserved ctxt.
1786
assign  stxa_ack =
1787
        (((itlb_wr_pend | dtlb_wr_pend) & ~(tlb_admp_mode | tlb_admp_mode_d1))  |
1788
        idemap_pend | ddemap_pend | immu_inv_all_pend | dmmu_inv_all_pend) & (lsu_tlu_dtlb_done | ifu_tlu_itlb_done)    |
1789
        (demap_resrv & tlb_st_inst_g &
1790
                ((immu_demap_en & ~idemap_all)  | (dmmu_demap_en & ~ddemap_all))) | //5053
1791
        (demap_sctxt & tlb_st_inst_g & (immu_demap_en & ~idemap_all)) | // Bug5053                                
1792
                                                // iside should not use sctxt
1793
        // lng-latency store needs to signal cmplt to lsu even with illegal va
1794
        (tlb_st_inst_unflushed & (dmmu_async_illgl_va_g | immu_async_illgl_va_g)) ;
1795
 
1796
dff_s  #(1) stack_d1 (
1797
        .din    (stxa_ack),
1798
        .q      (tlu_lsu_stxa_ack),
1799
        .clk    (clk),
1800
        .se     (1'b0),       .si (),          .so ()
1801
        );
1802
 
1803
//=========================================================================================
1804
//      AUTODEMAP
1805
//=========================================================================================
1806
 
1807
 
1808
assign  tlb_wr_vld_g = itlb_wr_vld_unmsked | dtlb_wr_vld_unmsked ;
1809
 
1810
assign  tlb_admp_en   = tlb_wr_vld_g & ~tlb_admp_mode & ~tlb_write_mode ;
1811
assign  tlb_admp_rst  = ~rst_l |
1812
        (((itlb_wr_pend | dtlb_wr_pend) & (lsu_tlu_dtlb_done | ifu_tlu_itlb_done)) & tlb_admp_mode) ;
1813
assign  tlb_wr_rst  = ~rst_l |
1814
        (((itlb_wr_pend | dtlb_wr_pend) & (lsu_tlu_dtlb_done | ifu_tlu_itlb_done))
1815
                        & tlb_write_mode & ~tlb_admp_mode_d1) ;
1816
 
1817
assign  tlu_admp_key_sel = (dtlb_wr_vld_g | itlb_wr_vld_g) | tlb_admp_mode ;
1818
 
1819
// 1st Phase - Autodemap
1820
dffre_s  #(1) dmp1_ff (
1821
        .din    (tlb_wr_vld_g),
1822
        .q      (tlb_admp_mode),
1823
        .rst    (tlb_admp_rst), .en     (tlb_admp_en),
1824
        .clk    (clk),
1825
        .se     (1'b0),       .si (),          .so ()
1826
        );
1827
 
1828
 
1829
// this is temporary - IFU is spuriously sourcing extra done signal.
1830
dff_s  #(1) admp_d1 (
1831
        .din    (tlb_admp_mode),
1832
        .q      (tlb_admp_mode_d1),
1833
        .clk    (clk),
1834
        .se     (1'b0),       .si (),          .so ()
1835
        );
1836
 
1837
// 2nd Phase - Follow-up with Write
1838
dffre_s  #(1) dmp2_ff (
1839
        .din    (tlb_admp_rst),
1840
        .q      (tlb_write_mode),
1841
        .rst    (tlb_wr_rst),   .en     (tlb_admp_rst),
1842
        .clk    (clk),
1843
        .se     (1'b0),       .si (),          .so ()
1844
        );
1845
 
1846
//=========================================================================================
1847
 
1848
wire    tlu_ldxa_async_data_vld ;
1849
assign  tlu_ldxa_async_data_vld =
1850
        tlu_dtlb_rd_done                |
1851
        (tlb_ld_inst_unflushed & (dmmu_async_illgl_va_g | immu_async_illgl_va_g)) ;
1852
 
1853
assign  tlu_dldxa_data_vld =
1854
// ** need to qualify with inst_vld in LSU
1855
        ((dmmu_tag_target_en_m  |
1856
         dmmu_8k_ptr_en_m       |
1857
         dmmu_64k_ptr_en_m      |
1858
         dmmu_direct_ptr_en_m   |
1859
         dmmu_tsb_en_m          |
1860
         dmmu_tag_access_en_m   |
1861
         dmmu_sync_fsr_en_m     |
1862
         dmmu_sync_far_en_m     |
1863
         dmmu_ctxt_cfg_en_m) & ld_inst_m) ;
1864
        //tlu_dtlb_rd_done              | // complete thru lsu
1865
        // for sync/async lng-latency ldxa with illegal va
1866
        // MMU_ASI
1867
        //(ld_inst_g & dmmu_sync_illgl_va_g) |
1868
        //(tlb_ld_inst_unflushed & dmmu_async_illgl_va_g) ;
1869
 
1870
assign  tlu_ildxa_data_vld =
1871
// ** need to qualify with inst_vld in LSU
1872
        ((immu_tag_target_en_m          |
1873
         immu_8k_ptr_en_m               |
1874
         immu_64k_ptr_en_m              |
1875
         immu_tsb_en_m                  |
1876
         immu_tag_access_en_m           |
1877
         immu_sync_fsr_en_m             |
1878
         immu_ctxt_cfg_en_m) & ld_inst_m)  ;
1879
        // for sync/async lng-latency ldxa with illegal va
1880
        // MMU_ASI
1881
        //(ld_inst_g & immu_sync_illgl_va_g) |
1882
        //(tlb_ld_inst_unflushed & immu_async_illgl_va_g) ;
1883
 
1884
assign  tlu_ldxa_data_vld = tlu_ildxa_data_vld | tlu_dldxa_data_vld ;
1885
 
1886
        // Flush needs to be removed.
1887
        assign  lsu_exu_ldxa_m = tlu_ldxa_data_vld & ~(dmmu_sync_illgl_va_m | immu_sync_illgl_va_m);
1888
 
1889
dff_s #(1) stg_asyncdvld (
1890
        .din    (tlu_ldxa_async_data_vld),
1891
        .q      (tlu_lsu_ldxa_async_data_vld),
1892
        .clk    (clk),
1893
        .se     (1'b0),       .si (),          .so ()
1894
        );
1895
 
1896
//=========================================================================================
1897
//      SFSR/SFAR Control
1898
//=========================================================================================
1899
 
1900
// In tcl
1901
 
1902
//=========================================================================================
1903
//      PS0 and PS1 Ptr Registers (NEW !!!!)
1904
//=========================================================================================
1905
 
1906
// If N=TSB_Size, P=Page_Size, then
1907
// Ptr = TSB_Base<63:13+N> | VA<21+N+3xP:13+3xP> | 0000 if TSB not split
1908
// Ptr = TSB_Base<63:14+N> | 0 | VA<21+N+3xP:13+3xP> | 0000 if TSB split
1909
// Assume P=0(8K),1(64K),3(4M),5(256M).
1910
// Note that Nmax=11 even though N=0..15, for 256M page. This is because VA cannot exceed 47 for ms bit.
1911
// Otherwise entire range of N can be covered by all 3 remaining page-size.
1912
 
1913
// Timing :
1914
//
1915
//      |   D-stage  |  E-stage | M-stage | W-stage    |        
1916
//      | Read setup | Read +   | Logic + | Latched in |
1917
//      | to mra     | Logic    | xmit    | LSU. Select|        
1918
//      |            |          |         | for wr-back|        
1919
//
1920
 
1921
// TSB Size Logic - Form 8 bits for 8k and 64k Ptr regs respectively.
1922
 
1923
// Macrotest support for logic in shadow of mra scan collar.
1924
// Scan only. Scan value valid in 2nd cycle of macrotest.
1925
wire    mtest_rdps0_sel ;
1926
dff_s  #(1) rps0d_d1 (
1927
        .din    (1'b0),
1928
        .q      (mtest_rdps0_sel),
1929
        .clk    (clk),
1930
        .se     (1'b0),       .si (),          .so ()
1931
) ;
1932
 
1933
wire    tsb_rd_ps0_sel ;
1934
assign  tlu_tsb_rd_ps0_sel = tsb_rd_ps0_sel ;
1935
assign  tsb_rd_ps0_sel =
1936
                        ((dmmu_8k_ptr_e | immu_8k_ptr_e |
1937
                        // really _m stage.
1938
                        dmmu_direct_8kptr_sel_g) & ~sehold_d1) | // direct-ptr selects ps0
1939
                        (mtest_rdps0_sel & sehold_d1) ;
1940
 
1941
// Choose between zero and non-zero context
1942
assign  tsb_size[3:0]    =
1943
        tsb_rd_ps0_sel ? tlu_dtsb_size_w2[3:0] : tlu_itsb_size_w2[3:0] ;
1944
assign  tsb_split       =
1945
        tsb_rd_ps0_sel ? tlu_dtsb_split_w2 : tlu_itsb_split_w2 ;
1946
// Mux'ed and staged in mmu_dp.
1947
assign  tag_access[47:13] = tlu_dtag_access_w2[47:13] ;
1948
wire    [2:0]    page_size,tsb_page_size_g ;
1949
assign  page_size[2:0] = tsb_page_size_g[2:0] ;
1950
 
1951
// Currently, all the logic is done in one stage. This will have to
1952
// be rearranged once the read of the mra is advanced. 
1953
 
1954
wire    pg8k,pg64k,pg4M;
1955
assign  pg8k    = ~page_size[2] & ~page_size[1] & ~page_size[0] ; // 000
1956
assign  pg64k   = ~page_size[2] & ~page_size[1] &  page_size[0] ; // 001
1957
assign  pg4M    = ~page_size[2] &  page_size[1] &  page_size[0] ; // 011
1958
//assign        pg256M  =  page_size[2] & ~page_size[1] &  page_size[0] ; // 101
1959
 
1960
// Mux tag-access <36:13>,<39:13>,<45:22>,<51:28> based on page-size.
1961
// Notebook contains greater detail of mapping of base,tag-access to ptr.
1962
wire    [23:0]   va ;
1963
assign  va[23:0] = pg8k ? tag_access[36:13] :
1964
                        pg64k ? tag_access[39:16] :
1965
                                pg4M ? tag_access[45:22] :
1966
                                                {{5{tag_access[47]}},tag_access[46:28]} ;// 256M        
1967
                                                //{4'b0000,tag_access[47:28]} ; // 256M // Bug3727
1968
 
1969
// The ptr address is broken up into 3 regions :
1970
// ptr<3:0>=4'b0000,                 : constant
1971
// ptr<12:4>=va<8:0>                 : va from tag-access only  
1972
// ptr<27:13>=va<23:9>/base<27:13>/0/1 : va from tag-access OR tsb base address OR '0/1' (split).
1973
// ptr<28>=base<28>/0/1              : tsb base address OR '0' (split).
1974
// ptr<47:29>=base<47:29>            : tsb base address. 
1975
 
1976
// Assuming N=0..15. Could be reduced to N=11.
1977
// Need to take exception for unused page size and value of N not compatible with selected page-size.
1978
 
1979
wire [28:13] ptr ;
1980
wire    ps1;
1981
assign ps1 = ~tsb_rd_ps0_sel ;
1982
 
1983
// This is an obvious flop boundary break. 
1984
 
1985
wire    [3:0] tsb_size_d1 ;
1986
wire    tsb_split_d1 ;
1987
wire    [47:13] tsb_base_d1 ;
1988
wire    ps1_d1 ;
1989
wire    [23:0]   va_d1 ;
1990
 
1991
dff_s  #(4) tsbsize_stgd1 (
1992
        .din    (tsb_size[3:0]),
1993
        .q      (tsb_size_d1[3:0]),
1994
        .clk    (clk),
1995
        .se     (1'b0),       .si (),          .so ()
1996
) ;
1997
 
1998
dff_s  #(1) tsbsplit_stgd1 (
1999
        .din    (tsb_split),
2000
        .q      (tsb_split_d1),
2001
        .clk    (clk),
2002
        .se     (1'b0),       .si (),          .so ()
2003
) ;
2004
 
2005
assign  tsb_base_d1[47:13] = tlu_tsb_base_w2_d1[47:13] ;
2006
 
2007
dff_s  #(1) ps1_stgd1 (
2008
        .din    (ps1),
2009
        .q      (ps1_d1),
2010
        .clk    (clk),
2011
        .se     (1'b0),       .si (),          .so ()
2012
) ;
2013
 
2014
dff_s  #(24) va_stgd1 (
2015
        .din    (va[23:0]),
2016
        .q      (va_d1[23:0]),
2017
        .clk    (clk),
2018
        .se     (1'b0),       .si (),          .so ()
2019
) ;
2020
 
2021
// These equations have to be optimized.
2022
assign  ptr[28] = ((tsb_size_d1==4'd15) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[28] ;
2023
assign  ptr[27] = (tsb_size_d1==4'd15) ? va_d1[23] : ((tsb_size_d1==4'd14) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[27] ;
2024
assign  ptr[26] = (tsb_size_d1>=4'd14) ? va_d1[22] : ((tsb_size_d1==4'd13) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[26] ;
2025
assign  ptr[25] = (tsb_size_d1>=4'd13) ? va_d1[21] : ((tsb_size_d1==4'd12) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[25] ;
2026
assign  ptr[24] = (tsb_size_d1>=4'd12) ? va_d1[20] : ((tsb_size_d1==4'd11) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[24] ;
2027
assign  ptr[23] = (tsb_size_d1>=4'd11) ? va_d1[19] : ((tsb_size_d1==4'd10) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[23] ;
2028
assign  ptr[22] = (tsb_size_d1>=4'd10) ? va_d1[18] : ((tsb_size_d1==4'd9) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[22] ;
2029
assign  ptr[21] = (tsb_size_d1>=4'd9) ? va_d1[17] : ((tsb_size_d1==4'd8) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[21] ;
2030
assign  ptr[20] = (tsb_size_d1>=4'd8) ? va_d1[16] : ((tsb_size_d1==4'd7) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[20] ;
2031
assign  ptr[19] = (tsb_size_d1>=4'd7) ? va_d1[15] : ((tsb_size_d1==4'd6) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[19] ;
2032
assign  ptr[18] = (tsb_size_d1>=4'd6) ? va_d1[14] : ((tsb_size_d1==4'd5) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[18] ;
2033
assign  ptr[17] = (tsb_size_d1>=4'd5) ? va_d1[13] : ((tsb_size_d1==4'd4) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[17] ;
2034
assign  ptr[16] = (tsb_size_d1>=4'd4) ? va_d1[12] : ((tsb_size_d1==4'd3) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[16] ;
2035
assign  ptr[15] = (tsb_size_d1>=4'd3) ? va_d1[11] : ((tsb_size_d1==4'd2) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[15] ;
2036
assign  ptr[14] = (tsb_size_d1>=4'd2) ? va_d1[10] : ((tsb_size_d1==4'd1) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[14] ;
2037
assign  ptr[13] = (tsb_size_d1>=4'd1) ? va_d1[9] :  tsb_split_d1 ? ps1_d1 : tsb_base_d1[13] ;
2038
 
2039
// TSB 8K Ptr. This maps to tsb ps0 ptr !!!
2040
// This is mapped to either PS0 or PS1 ptr. Do not need to send
2041
// 8k and 64K ptrs to mmu_dp.
2042
// Direct ptr needs to be accounted for.
2043
assign  tlu_idtsb_8k_ptr[47:0] =
2044
        {tsb_base_d1[47:29],
2045
        ptr[28:13],
2046
        va_d1[8:0],
2047
        4'b0000};
2048
 
2049
//=========================================================================================
2050
//      Establishing Context for Ptr Read
2051
//=========================================================================================
2052
 
2053
// Context of Ptr Read determined by context within d/i tag-access register. 
2054
// Markers per thread will be maintained to determine whether any subsequent 
2055
// ptr access is made in nucleus or non-nucleus context.
2056
// Note i and d tag-access can be merged within tlu_mmu_dp.v
2057
 
2058
// write of tag-access ctxt needs to be setup in M for subsequent read of MRA in M.
2059
 
2060
assign  tsb_page_size_g[2:0] = tsb_rd_ps0_sel ? tlu_ctxt_cfg_w2[2:0] : tlu_ctxt_cfg_w2[5:3] ;
2061
 
2062
// Listening Flops for Macrotest of mra.
2063
dff_s #(6) ctxtcfg_listen (
2064
        .din    (tlu_ctxt_cfg_w2[5:0]),
2065
        .q      (),
2066
        .clk    (clk),
2067
        .se     (1'b0),       .si (),          .so ()
2068
        );
2069
 
2070
 
2071
 
2072
//=========================================================================================
2073
//      Direct Ptr State
2074
//=========================================================================================
2075
 
2076
// For new ptr support, if page-size of tte matches that of ps1 then
2077
// direct-ptr maps to ps1-ptr else ps0-ptr.
2078
 
2079
wire    daccess_prot_qual ;
2080
assign  daccess_prot_qual =
2081
lsu_tlu_daccess_prot_g & ~lsu_tlu_daccess_excptn_g &
2082
inst_vld_g & ~(priority_squash_g | flush_mmuasi_wr) ;
2083
 
2084
// For SPARC_HPV_EN, 64k represents ps1 ptr.
2085
assign  dptr0_pg64k_en = daccess_prot_qual & thread0_sel_g ;
2086
assign  dptr1_pg64k_en = daccess_prot_qual & thread1_sel_g ;
2087
assign  dptr2_pg64k_en = daccess_prot_qual & thread2_sel_g ;
2088
assign  dptr3_pg64k_en = daccess_prot_qual & thread3_sel_g ;
2089
 
2090
// For SPARC_HPV_EN this means ps0 sel. This should be an internal
2091
// wire with SPARC_HPV_EN
2092
assign  dmmu_direct_8kptr_sel_g  =
2093
        dmmu_direct_ptr_e & ((thread0_e & ~dptr0_pg64k_vld) |
2094
                                (thread1_e & ~dptr1_pg64k_vld) |
2095
                                (thread2_e & ~dptr2_pg64k_vld) |
2096
                                (thread3_e & ~dptr3_pg64k_vld));
2097
wire    dptr_state_din ;
2098
        assign dptr_state_din = dacc_prot_ps1_match ;
2099
 
2100
dffre_s  #(1) dptrstate_0 (
2101
        .din    (dptr_state_din),
2102
        .q      (dptr0_pg64k_vld),
2103
        .rst    (~rst_l),       .en     (dptr0_pg64k_en),
2104
        .clk    (clk),
2105
        .se     (1'b0),       .si (),          .so ()
2106
        );
2107
 
2108
dffre_s  #(1) dptrstate_1 (
2109
        .din    (dptr_state_din),
2110
        .q      (dptr1_pg64k_vld),
2111
        .rst    (~rst_l),       .en     (dptr1_pg64k_en),
2112
        .clk    (clk),
2113
        .se     (1'b0),       .si (),          .so ()
2114
        );
2115
 
2116
dffre_s  #(1) dptrstate_2 (
2117
        .din    (dptr_state_din),
2118
        .q      (dptr2_pg64k_vld),
2119
        .rst    (~rst_l),       .en     (dptr2_pg64k_en),
2120
        .clk    (clk),
2121
        .se     (1'b0),       .si (),          .so ()
2122
        );
2123
 
2124
dffre_s  #(1) dptrstate_3 (
2125
        .din    (dptr_state_din),
2126
        .q      (dptr3_pg64k_vld),
2127
        .rst    (~rst_l),       .en     (dptr3_pg64k_en),
2128
        .clk    (clk),
2129
        .se     (1'b0),       .si (),          .so ()
2130
        );
2131
 
2132
//=========================================================================================
2133
//      PS1 PAGE SIZE FOR DMMU
2134
//=========================================================================================
2135
 
2136
// Maintain ps1 page-size for dmmu zero/non-zero ctxt. This is required to compare
2137
// against the page-size of the tte on a data-access-protection to set-up the
2138
// direct-pointer. Note that the real copy is in the mra.
2139
 
2140
wire [2:0] zctxt_cfg0_ps1,zctxt_cfg1_ps1,zctxt_cfg2_ps1,zctxt_cfg3_ps1;
2141
wire [2:0] nzctxt_cfg0_ps1,nzctxt_cfg1_ps1,nzctxt_cfg2_ps1,nzctxt_cfg3_ps1;
2142
wire [3:0] dzctxt_cfg_wr_en ;
2143
wire [3:0] dnzctxt_cfg_wr_en ;
2144
 
2145
assign  dzctxt_cfg_wr_en[3] = dmmu_zctxt_cfg_en & st_inst_g & thread3_sel_g ;
2146
assign  dzctxt_cfg_wr_en[2] = dmmu_zctxt_cfg_en & st_inst_g & thread2_sel_g ;
2147
assign  dzctxt_cfg_wr_en[1] = dmmu_zctxt_cfg_en & st_inst_g & thread1_sel_g ;
2148
assign  dzctxt_cfg_wr_en[0] = dmmu_zctxt_cfg_en & st_inst_g & thread0_sel_g ;
2149
 
2150
assign  dnzctxt_cfg_wr_en[3] = dmmu_nzctxt_cfg_en & st_inst_g & thread3_sel_g ;
2151
assign  dnzctxt_cfg_wr_en[2] = dmmu_nzctxt_cfg_en & st_inst_g & thread2_sel_g ;
2152
assign  dnzctxt_cfg_wr_en[1] = dmmu_nzctxt_cfg_en & st_inst_g & thread1_sel_g ;
2153
assign  dnzctxt_cfg_wr_en[0] = dmmu_nzctxt_cfg_en & st_inst_g & thread0_sel_g ;
2154
 
2155
// Thread0
2156
// Zero-Ctxt Cfg PS1
2157
dffe_s #(3)   zctxtps1_0 (
2158
        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),
2159
        .q      (zctxt_cfg0_ps1[2:0]),
2160
        .en     (dzctxt_cfg_wr_en[0]),   .clk (clk),
2161
        .se     (1'b0),         .si (),          .so ()
2162
        );
2163
 
2164
// Non-Zero-Ctxt Cfg PS1
2165
dffe_s #(3)   nzctxtps1_0 (
2166
        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),
2167
        .q      (nzctxt_cfg0_ps1[2:0]),
2168
        .en     (dnzctxt_cfg_wr_en[0]),  .clk (clk),
2169
        .se     (1'b0),         .si (),          .so ()
2170
        );
2171
 
2172
// Thread1
2173
// Zero-Ctxt Cfg PS1
2174
dffe_s #(3)   zctxtps1_1 (
2175
        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),
2176
        .q      (zctxt_cfg1_ps1[2:0]),
2177
        .en     (dzctxt_cfg_wr_en[1]),  .clk (clk),
2178
        .se     (1'b0),         .si (),          .so ()
2179
        );
2180
 
2181
// Non-Zero-Ctxt Cfg PS1
2182
dffe_s #(3)   nzctxtps1_1 (
2183
        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),
2184
        .q      (nzctxt_cfg1_ps1[2:0]),
2185
        .en     (dnzctxt_cfg_wr_en[1]),         .clk (clk),
2186
        .se     (1'b0),         .si (),          .so ()
2187
        );
2188
 
2189
// Thread2
2190
// Zero-Ctxt Cfg PS1
2191
dffe_s #(3)   zctxtps1_2 (
2192
        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),
2193
        .q      (zctxt_cfg2_ps1[2:0]),
2194
        .en     (dzctxt_cfg_wr_en[2]),  .clk (clk),
2195
        .se     (1'b0),         .si (),          .so ()
2196
        );
2197
 
2198
// Non-Zero-Ctxt Cfg PS1
2199
dffe_s #(3)   nzctxtps1_2 (
2200
        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),
2201
        .q      (nzctxt_cfg2_ps1[2:0]),
2202
        .en     (dnzctxt_cfg_wr_en[2]),         .clk (clk),
2203
        .se     (1'b0),         .si (),          .so ()
2204
        );
2205
 
2206
// Thread3
2207
// Zero-Ctxt Cfg PS1
2208
dffe_s #(3)   zctxtps1_3 (
2209
        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),
2210
        .q      (zctxt_cfg3_ps1[2:0]),
2211
        .en     (dzctxt_cfg_wr_en[3]),  .clk (clk),
2212
        .se     (1'b0),         .si (),          .so ()
2213
        );
2214
 
2215
// Non-Zero-Ctxt Cfg PS1
2216
dffe_s #(3)   nzctxtps1_3 (
2217
        .din    (lsu_tlu_st_rs3_data_b12t0_g[10:8]),
2218
        .q      (nzctxt_cfg3_ps1[2:0]),
2219
        .en     (dnzctxt_cfg_wr_en[3]),         .clk (clk),
2220
        .se     (1'b0),         .si (),          .so ()
2221
        );
2222
 
2223
 
2224
wire [2:0] zctxt_cfg_ps1,nzctxt_cfg_ps1 ;
2225
 
2226
assign  zctxt_cfg_ps1[2:0] =
2227
        thread0_sel_g ? zctxt_cfg0_ps1[2:0] :
2228
                thread1_sel_g ? zctxt_cfg1_ps1[2:0] :
2229
                        thread2_sel_g ? zctxt_cfg2_ps1[2:0] :
2230
                                                zctxt_cfg3_ps1[2:0] ;
2231
 
2232
assign  nzctxt_cfg_ps1[2:0] =
2233
        thread0_sel_g ? nzctxt_cfg0_ps1[2:0] :
2234
                thread1_sel_g ? nzctxt_cfg1_ps1[2:0] :
2235
                        thread2_sel_g ? nzctxt_cfg2_ps1[2:0] :
2236
                                                nzctxt_cfg3_ps1[2:0] ;
2237
wire    nucleus_ctxt_g ;
2238
dff_s nctxt_stgg(
2239
        .din    (lsu_tlu_nucleus_ctxt_m),
2240
        .q      (nucleus_ctxt_g),
2241
        .clk    (clk),
2242
        .se     (1'b0),       .si (),          .so ()
2243
        );
2244
 
2245
wire    [2:0]    ctxt_cfg_ps1 ;
2246
assign  ctxt_cfg_ps1[2:0] =
2247
        nucleus_ctxt_g ? zctxt_cfg_ps1[2:0] : nzctxt_cfg_ps1[2:0] ;
2248
 
2249
assign  dacc_prot_ps1_match
2250
        = (lsu_tlu_tte_pg_sz_g[2:0] == ctxt_cfg_ps1[2:0]) ;
2251
 
2252
//=========================================================================================
2253
//      CTXT SEL
2254
//=========================================================================================
2255
 
2256
wire    thread_tl_zero_e,thread_tl_zero_m ;
2257
assign thread_tl_zero_e =
2258
        thread0_e ? tlu_lsu_tl_zero[0] :
2259
                thread1_e ? tlu_lsu_tl_zero[1] :
2260
                        thread2_e ? tlu_lsu_tl_zero[2] : tlu_lsu_tl_zero[3];
2261
 
2262
dff_s tlz_stgm(
2263
        .din    (thread_tl_zero_e),
2264
        .q      (thread_tl_zero_m),
2265
        .clk    (clk),
2266
        .se     (1'b0),       .si (),          .so ()
2267
        );
2268
 
2269
// Generate selects for ctxt to be written to tag_access
2270
// iside trap meant to cover immu_miss and inst_access_excp
2271
// modified for hypervisor support
2272
// assign       iside_trap = exu_tlu_ttype_vld_m | immu_va_oor_brnchetc_m | exu_tlu_va_oor_jl_ret_m;
2273
 
2274
wire    pstate_am_e,pstate_am_m;
2275
assign  pstate_am_e =
2276
        (thread0_e & tlu_lsu_pstate_am[0]) |
2277
        (thread1_e & tlu_lsu_pstate_am[1]) |
2278
        (thread2_e & tlu_lsu_pstate_am[2]) |
2279
        (thread3_e & tlu_lsu_pstate_am[3]);
2280
 
2281
dff_s pam_stgm(
2282
        .din    (pstate_am_e),
2283
        .q      (pstate_am_m),
2284
        .clk    (clk),
2285
        .se     (1'b0),       .si (),          .so ()
2286
        );
2287
 
2288
wire    immu_va_oor_brnchetc_m ;
2289
assign  immu_va_oor_brnchetc_m
2290
        = exu_tlu_va_oor_m & ~pstate_am_m & ~memref_m;
2291
 
2292
wire iside_trap ;
2293
assign  iside_trap =
2294
            ifu_tlu_immu_miss_m | // exu_tlu_ttype_vld_m : Rm along with Bug 5346
2295
            immu_va_oor_brnchetc_m | exu_tlu_va_oor_jl_ret_m |
2296
            ifu_tlu_priv_violtn_m ; // Bug 5346.
2297
assign  tlu_tag_access_ctxt_sel_m[0] = iside_trap &  thread_tl_zero_m;
2298
assign  tlu_tag_access_ctxt_sel_m[1] = iside_trap & ~thread_tl_zero_m;
2299
assign  tlu_tag_access_ctxt_sel_m[2] = ~iside_trap;
2300
 
2301
 
2302
//=========================================================================================
2303
//      TLB Write Data
2304
//=========================================================================================
2305
 
2306
wire    [2:0]    pg_size ;
2307
wire            page_8k, page_64k, page_4m ;
2308
wire            va_15_13_vld, va_21_16_vld, va_27_22_vld ;
2309
 
2310
assign sun4r_tte_g = ~tlb_ldst_va_g[10] ;
2311
 
2312
assign tlu_sun4r_tte_g = sun4r_tte_g ;
2313
 
2314
assign  pg_size[2:0]     =
2315
        sun4r_tte_g ? {lsu_tlu_st_rs3_data_b48_g,lsu_tlu_st_rs3_data_g[62:61]} :
2316
                        {lsu_tlu_st_rs3_data_b12t0_g[2:0]} ;
2317
 
2318
assign  page_8k         = ~pg_size[2] & ~pg_size[1] & ~pg_size[0] ;
2319
assign  page_64k        = ~pg_size[2] & ~pg_size[1] &  pg_size[0] ;
2320
assign  page_4m         = ~pg_size[2] &  pg_size[1] &  pg_size[0] ;
2321
//assign        page_256m       =  pg_size[2] & ~pg_size[1] &  pg_size[0] ;     
2322
 
2323
assign  va_15_13_vld    = page_8k ;
2324
assign  va_21_16_vld    = page_8k | page_64k  ;
2325
assign  va_27_22_vld    = page_8k | page_64k | page_4m ;
2326
 
2327
assign  tlu_tte_tag_g[2:0] = {va_27_22_vld,va_21_16_vld,va_15_13_vld} ;
2328
 
2329
assign  thread0_async_g = ~tlb_access_tid_g[1] & ~tlb_access_tid_g[0] ;
2330
assign  thread1_async_g = ~tlb_access_tid_g[1] &  tlb_access_tid_g[0] ;
2331
assign  thread2_async_g =  tlb_access_tid_g[1] & ~tlb_access_tid_g[0] ;
2332
//assign        thread3_async_g =  tlb_access_tid_g[1] &  tlb_access_tid_g[0] ; // to be used in instanced mux
2333
 
2334
assign  tlu_tte_wr_pid_g[2:0] =
2335
        thread0_async_g ? lsu_pid_state0[2:0] :
2336
                thread1_async_g ? lsu_pid_state1[2:0] :
2337
                        thread2_async_g ? lsu_pid_state2[2:0] : lsu_pid_state3[2:0] ;
2338
 
2339
// Error Injection :
2340
// Error injection is one-shot. It will occur for either dmmu or immu. The ifu
2341
// is informed once the error injection is accomplished.
2342
 
2343
wire    i_tag_invrt_par,d_tag_invrt_par ;
2344
wire    i_data_invrt_par,d_data_invrt_par ;
2345
assign tlu_tlb_tag_invrt_parity = i_tag_invrt_par | d_tag_invrt_par ;
2346
assign i_tag_invrt_par = (ifu_lsu_error_inj[2] & (immu_data_in_en | immu_data_access_en)) ;
2347
assign d_tag_invrt_par = (ifu_lsu_error_inj[0] & (dmmu_data_in_en | dmmu_data_access_en)) ;
2348
assign tlu_tlb_data_invrt_parity = i_data_invrt_par | d_data_invrt_par ;
2349
assign i_data_invrt_par = (ifu_lsu_error_inj[3] & (immu_data_in_en | immu_data_access_en)) ;
2350
assign d_data_invrt_par = (ifu_lsu_error_inj[1] & (dmmu_data_in_en | dmmu_data_access_en)) ;
2351
 
2352
wire tlb_wr_vld ;
2353
assign tlb_wr_vld = dtlb_wr_vld_g | itlb_wr_vld_g ;
2354
wire [3:0] err_inj_ack ;
2355
assign  err_inj_ack[0] = tlb_wr_vld & d_tag_invrt_par ;
2356
assign  err_inj_ack[1] = tlb_wr_vld & d_data_invrt_par ;
2357
assign  err_inj_ack[2] = tlb_wr_vld & i_tag_invrt_par ;
2358
assign  err_inj_ack[3] = tlb_wr_vld & i_data_invrt_par ;
2359
 
2360
dff_s #(4) err_inj (
2361
        .din    (err_inj_ack[3:0]),
2362
        .q      (lsu_ifu_inj_ack[3:0]),
2363
        .clk    (clk),
2364
        .se     (1'b0),       .si (),          .so ()
2365
        );
2366
 
2367
endmodule

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