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// ========== Copyright Header Begin ==========================================

// 

// OpenSPARC T1 Processor File: tlu_mmu_dp.v

// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.

// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.

// 

// The above named program is free software; you can redistribute it and/or

// modify it under the terms of the GNU General Public

// License version 2 as published by the Free Software Foundation.

// 

// The above named program is distributed in the hope that it will be 

// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

// General Public License for more details.

// 

// You should have received a copy of the GNU General Public

// License along with this work; if not, write to the Free Software

// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.

// 

// ========== Copyright Header End ============================================

///////////////////////////////////////////////////////////////////////

/*

//      Description:    MMU Datapath - I & D.

*/

////////////////////////////////////////////////////////////////////////

// Global header file includes

////////////////////////////////////////////////////////////////////////

`include        "sys.h" // system level definition file which contains the 

                                        // time scale definition

////////////////////////////////////////////////////////////////////////

// Local header file includes / local defines

////////////////////////////////////////////////////////////////////////

`include "tlu.h"

//FPGA_SYN enables all FPGA related modifications

`ifdef FPGA_SYN

`define FPGA_SYN_CLK_EN

`define FPGA_SYN_CLK_DFF

`endif

module tlu_mmu_dp ( /*AUTOARG*/

   // Outputs

   tlu_dtsb_split_w2, tlu_dtsb_size_w2, tlu_dtag_access_w2,

   tlu_itsb_split_w2, tlu_itsb_size_w2,

   tlu_itlb_tte_tag_w2, tlu_itlb_tte_data_w2, tlu_dtlb_tte_tag_w2,

   tlu_dtlb_tte_data_w2, tlu_idtlb_dmp_key_g, tlu_dsfsr_flt_vld,

   tlu_isfsr_flt_vld, mra_wdata, tlu_ctxt_cfg_w2, tlu_tag_access_ctxt_g,

   lsu_exu_ldxa_data_g, so, tlu_tsb_base_w2_d1,

   // Inputs

   tlu_addr_msk_g, dmmu_any_sfsr_wr, dmmu_sfsr_wr_en_l, dmmu_sfar_wr_en_l,

   immu_any_sfsr_wr, immu_sfsr_wr_en_l, tlu_lng_ltncy_en_l,

   lsu_tlu_dside_ctxt_m, lsu_tlu_pctxt_m, tlu_tag_access_ctxt_sel_m,

   lsu_tlu_st_rs3_data_b63t59_g, lsu_tlu_st_rs3_data_b47t0_g,

   exu_lsu_ldst_va_e, tlu_idtsb_8k_ptr,lsu_tlu_tlb_dmp_va_m, ifu_tlu_pc_m,

   tlu_slxa_thrd_sel,

   tlu_tte_tag_g, tlu_dmp_key_vld_g, tlb_access_rst_l,

   tag_access_wdata_sel, mra_rdata, tlu_admp_key_sel,

   tlu_isfsr_din_g, tlu_dsfsr_din_g,

   tlu_tte_wr_pid_g, tlu_tte_real_g, tlu_ldxa_l1mx1_sel,

   tlu_ldxa_l1mx2_sel, tlu_ldxa_l2mx1_sel, rclk, grst_l, arst_l,

   tlu_tlb_tag_invrt_parity, tlu_tlb_data_invrt_parity, tlu_sun4r_tte_g,

   tlu_tsb_rd_ps0_sel, si, se, tlu_tlb_access_en_l_d1

   ) ;

/*AUTOINPUT*/

// Beginning of automatic inputs (from unused autoinst inputs)

// End of automatics

input                   tlu_addr_msk_g ;        // address masking active for thread in pipe.

input                   dmmu_any_sfsr_wr ;

input   [3:0]            dmmu_sfsr_wr_en_l ;

input   [3:0]            dmmu_sfar_wr_en_l ;

input                   immu_any_sfsr_wr ;

input   [3:0]           immu_sfsr_wr_en_l ;

input   [12:0]          lsu_tlu_dside_ctxt_m ;

input   [12:0]          lsu_tlu_pctxt_m ;

input   [2:0]            tlu_tag_access_ctxt_sel_m ;

// rs3_data split for vlint purposes.

input   [63:59]         lsu_tlu_st_rs3_data_b63t59_g ;

input   [47:0]           lsu_tlu_st_rs3_data_b47t0_g ;

input   [47:0]           exu_lsu_ldst_va_e ;

input   [47:0]          tlu_idtsb_8k_ptr ;

input   [47:13]         lsu_tlu_tlb_dmp_va_m ;

input   [47:13]         ifu_tlu_pc_m ;

input   [3:0]            tlu_slxa_thrd_sel ;

//input         [63:0]          int_tlu_asi_data;

//input                 int_tlu_asi_data_vld;

input   [2:0]            tlu_tte_tag_g ;

input   [4:0]            tlu_dmp_key_vld_g ;

//input                 tlb_access_en_l ;

input                   tlu_tlb_access_en_l_d1 ;

input                   tlb_access_rst_l ;

input   [2:0]            tag_access_wdata_sel ;

input   [155:6]         mra_rdata ;

input                   tlu_admp_key_sel ;

input   [23:0]           tlu_isfsr_din_g ;

input   [23:0]           tlu_dsfsr_din_g ;

input   [2:0]            tlu_tte_wr_pid_g ;      // thread selected pid

input                   tlu_tte_real_g ;        // tte is real          

input   [3:0]            tlu_ldxa_l1mx1_sel ;    // mmu ldxa level1 mx1 sel

input   [3:0]            tlu_ldxa_l1mx2_sel ;    // mmu ldxa level1 mx2 sel

input   [2:0]            tlu_ldxa_l2mx1_sel ;    // mmu ldxa level2 mx1 sel

input                   tlu_tlb_tag_invrt_parity ;      // invert parity for tag write

input                   tlu_tlb_data_invrt_parity ;     // invert parity for data write

input                   tlu_sun4r_tte_g ;       // sun4r vs. sun4v tte.

input                  tlu_lng_ltncy_en_l ;

input                  tlu_tsb_rd_ps0_sel ;

input                 rclk ;

input                 arst_l ;

input                 grst_l ;

input                 si ;

input                 se ;

output                        so ;

//output  [47:13]         tlu_dtsb_base_w2 ;    // represents ps0

output                  tlu_dtsb_split_w2 ;

output  [3:0]           tlu_dtsb_size_w2 ;

output  [47:13]         tlu_dtag_access_w2 ;    // used to represent both i/d.

//output  [47:13]         tlu_itsb_base_w2 ;    // represents ps1

output                  tlu_itsb_split_w2 ;

output  [3:0]           tlu_itsb_size_w2 ;

//output  [32:13]               tlu_itag_access_w2 ;    // to be obsoleted.

output  [58:0]           tlu_itlb_tte_tag_w2 ;

output  [42:0]           tlu_itlb_tte_data_w2 ;

output  [58:0]           tlu_dtlb_tte_tag_w2 ;

output  [42:0]           tlu_dtlb_tte_data_w2 ;

//output        [63:0]          tlu_lsu_ldxa_data_w2 ;

output  [5:0]           tlu_ctxt_cfg_w2 ;       // i/d context zero/non-zero config.

output  [40:0]           tlu_idtlb_dmp_key_g ;

output  [3:0]            tlu_dsfsr_flt_vld ;

output  [3:0]            tlu_isfsr_flt_vld ;

output  [12:0]           tlu_tag_access_ctxt_g ;

output  [63:0]           lsu_exu_ldxa_data_g ;

output  [47:13]         tlu_tsb_base_w2_d1 ;

///output       tlu_tag_access_nctxt_g ;                // tag-access contains nucleus context.

output  [155:0]          mra_wdata ;

wire    [47:0]           ldst_va_m,ldst_va_g ;

// st_rs3_data partitioned for vlint.

//wire  [63:0]          st_rs3_data_g ;

wire    [63:59]         st_rs3_data_b63t59_g ;

wire    [39:8]          st_rs3_data_b39t8_g ;

wire    [6:1]           st_rs3_data_b6t1_g ;

wire    [63:0]           tag_target ;

wire    [47:13]         dtag_access_w2 ;

wire    [23:0]           dsfsr,isfsr ;

wire    [23:0]           dsfsr0,isfsr0 ;

wire    [23:0]           dsfsr1,isfsr1 ;

wire    [23:0]           dsfsr2,isfsr2 ;

wire    [23:0]           dsfsr3,isfsr3 ;

wire    [47:0]           dsfar ;

wire    [47:0]           dsfar0,dsfar1 ;

wire    [47:0]           dsfar2,dsfar3 ;

wire    [23:0]           dsfsr_din ;

wire    [23:0]           isfsr_din ;

//wire  [39:22]         tte_relocated_pa ;

wire    [40:0]           dmp_key ;

wire    [47:0]           tag_access_w2 ;

wire    [41:0]           idtte_data_w2 ;

wire                    tlb_access0_clk, tlb_access1_clk ;

wire    [40:0]           idtlb_dmp_key_pend ;

wire    [47:0]           tag_access_wdata ;

wire    [12:0]           tag_access_ctxt_m,tag_access_ctxt_g ;

// buses split for vlint purposes.

wire    [58:55]         idtte_tag_b58t55_g ;

wire    [53:0]           idtte_tag_b53t0_g ;

wire    [58:55]         idtte_tag_b58t55_w2 ;

wire    [53:0]           idtte_tag_b53t0_w2 ;

wire    [41:0]           idtte_data_g ;

wire    [47:13]         tlb_dmp_va_g ;

wire    [47:0]   ldxa_l1mx1_dout_e ;

wire    [47:0]   ldxa_l1mx1_dout_m ;

 //=========================================================================================

 //    RESET/CLK

 //=========================================================================================

    wire       clk;

    assign     clk = rclk;

    wire       rst_l;

    dffrl_async rstff(.din (grst_l),

                      .q   (rst_l),

                      .clk (clk), .se(se), .si(), .so(),

                      .rst_l (arst_l));

//=========================================================================================

//      Staging

//=========================================================================================

// Stage

wire [47:13] pc_g ;

dff_s  #(35) stg_w (

        .din    (ifu_tlu_pc_m[47:13]),

        .q      (pc_g[47:13]),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        );

//assign        pc_g[47:13] = ifu_tlu_pc_w[47:13] ;

// Stage va

dff_s  #(48) stg_m (

        .din    (exu_lsu_ldst_va_e[47:0]),

        .q      (ldst_va_m[47:0]),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        );

dff_s  #(48) stg_g (

        .din    (ldst_va_m[47:0]),

        .q      (ldst_va_g[47:0]),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        );

dff_s  #(35) dstg_g (

        .din    (lsu_tlu_tlb_dmp_va_m[47:13]),

        .q      (tlb_dmp_va_g[47:13]),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        );

//=========================================================================================

wire [4:0] tlu_dmp_key_vld_d1 ;

wire [47:13] tlb_dmp_va_d1 ;

dff_s  #(40) dstg_d1 (

        .din    ({tlb_dmp_va_g[47:13],tlu_dmp_key_vld_g[4:0]}),

        .q      ({tlb_dmp_va_d1[47:13],tlu_dmp_key_vld_d1[4:0]}),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        );

wire    [2:0]    tlu_tte_tag_d1,tlu_tte_wr_pid_d1 ;

wire            tlu_tte_real_d1,tlu_tlb_tag_invrt_parity_d1 ;

wire    [47:13] dmp_va_d1 ;

wire    [5:0]    dmp_key_vld_d1 ;

dp_mux2es #(41) dmp_key_sel (

                .in0    ({tlb_dmp_va_d1[47:13],tlu_dmp_key_vld_d1[4:0],tlu_tte_real_d1}),

                .in1    ({tag_access_w2[47:13],1'b1,tlu_tte_tag_d1[2:0],tlu_tte_real_d1,tlu_tte_real_d1}),

                //.in1  ({tag_access_w2[47:13],1'b1,tlu_tte_tag_d1[2:0],1'b0,tlu_tte_real_d1}), // Bug 3754

                .sel    (tlu_admp_key_sel),

                .dout   ({dmp_va_d1[47:13],dmp_key_vld_d1[5:0]})

        );

assign  dmp_key[40:0] =

        {

        dmp_va_d1[47:28],        // (20b)

        dmp_key_vld_d1[5],       // (1b)

        dmp_va_d1[27:22],        // (6b)

        dmp_key_vld_d1[4],       // (1b)

        dmp_va_d1[21:16],        // (6b)

        dmp_key_vld_d1[3],       // (1b)

        dmp_va_d1[15:13],        // (3b)

        dmp_key_vld_d1[2],       // (1b)

        dmp_key_vld_d1[1],       // (1b)

        dmp_key_vld_d1[0]        // (1b)

        } ;

//wire  tlb_access_en_l_d1 ;

wire    tlb_access2_clk ;

`ifdef FPGA_SYN_CLK_EN

`else

`ifdef FPGA_SYN_CLK_EN

`else

clken_buf clkbf_dmpky (

                .rclk   (clk),

                .enb_l  (tlu_tlb_access_en_l_d1),

                .tmb_l  (~se),

                .clk    (tlb_access2_clk)

                ) ;

`endif

`endif

// Advance by a cycle. Do not have to reset state.

`ifdef FPGA_SYN_CLK_DFF

dffrle_s  #(41) stg_w2 (

        .din    (dmp_key[40:0]),

        .q      (idtlb_dmp_key_pend[40:0]),

        .rst_l  (tlb_access_rst_l),

        .en (~(tlu_tlb_access_en_l_d1)), .clk(clk),

        .se     (1'b0),       .si (),          .so ()

        );

`else

`ifdef FPGA_SYN_CLK_DFF

dffrle_s  #(41) stg_w2 (

        .din    (dmp_key[40:0]),

        .q      (idtlb_dmp_key_pend[40:0]),

        .rst_l  (tlb_access_rst_l),

        .en (~(tlu_tlb_access_en_l_d1)), .clk(clk),

        .se     (1'b0),       .si (),          .so ()

        );

`else

dffrl_s  #(41) stg_w2 (

        .din    (dmp_key[40:0]),

        .q      (idtlb_dmp_key_pend[40:0]),

        .rst_l  (tlb_access_rst_l),

        .clk    (tlb_access2_clk),

        .se     (1'b0),       .si (),          .so ()

        );

`endif

`endif

assign  tlu_idtlb_dmp_key_g[40:0] = idtlb_dmp_key_pend[40:0] ;

//=========================================================================================

//      WR DATA FOR MRA

//=========================================================================================

// Format for each entry of MRA on a per thread basis.

// Current :

//      |       dtsb(48b)       |       dtag_access(48b)        |       dsfar(48b)      |       

//      |       itsb(48b)       |       itag_access(48b)        |                       |       

// New(Hyp,Legacy) : 8 tsb per thread instead of 2. dsfar removed.

// -This allows tag-access to be lined up with simultaneous reads of tsb

// -zero-ctxt and non-zero-ctxt tag-access will have to be distinguished either

// by doing a zero-detect on the lower 13b of the write-data or using a disinct asi.

//      |       zcps0_dtsb(48b) |       zcps1_dtsb(48b) |       zctxt_dtag_acc(48b) | dzctxt_cfg(6b) |

//      |       zcps0_itsb(48b) |       zcps1_itsb(48b) |       zctxt_itag_acc(48b) | izctxt_cfg(6b) |

//      |       nzcps0_dtsb(48b)|       nzcps1_dtsb(48b)|       nzctxt_dtag_acc(48b)| dnzctxt_cfg(6b)|

//      |       nzcps0_itsb(48b)|       nzcps1_itsb(48b)|       nzctxt_itag_acc(48b)| inzctxt_cfg(6b)|

mux3ds #(13)    tag_acc_ctxtmx(

                .in0    (lsu_tlu_pctxt_m[12:0]), // iside selects primary ctxt

                .in1    (13'd0),                 // iside selects nucleus ctxt

                .in2    (lsu_tlu_dside_ctxt_m[12:0]), // otherwise select dside ctxt

                .sel0   (tlu_tag_access_ctxt_sel_m[0]),

                .sel1   (tlu_tag_access_ctxt_sel_m[1]),

                .sel2   (tlu_tag_access_ctxt_sel_m[2]),

                .dout   (tag_access_ctxt_m[12:0])

        );

/*assign        tag_access_ctxt_m[12:0] =

        tlu_tag_access_ctxt_sel_m[0] ?  lsu_tlu_pctxt_m[12:0] :         // iside selects primary ctxt

                tlu_tag_access_ctxt_sel_m[1] ?  13'd0  :                // iside selects nucleus ctxt

                        tlu_tag_access_ctxt_sel_m[2] ? lsu_tlu_dside_ctxt_m[12:0] : 13'bx_xxxx_xxxx_xxxx ;                      // otherwise select dside ctxt

*/

dff_s  #(13) ctxt_stgg (

        .din    (tag_access_ctxt_m[12:0]),

        .q      (tag_access_ctxt_g[12:0]),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        );

// pstate.am masking

wire    [15:0]   ldst_va_masked_g ;

assign  ldst_va_masked_g[15:0] = ldst_va_g[47:32] & {16{~tlu_addr_msk_g}} ;

mux3ds #(48)    dtag_access_dsel(

                .in0    ({ldst_va_masked_g[15:0],ldst_va_g[31:13],tag_access_ctxt_g[12:0]}), // dside hardware

                .in1    ({pc_g[47:13],tag_access_ctxt_g[12:0]}), // iside hardware

                .in2    (lsu_tlu_st_rs3_data_b47t0_g[47:0]),     // stxa,tsb write as an example.

                .sel0   (tag_access_wdata_sel[0]),

                .sel1   (tag_access_wdata_sel[1]),

                .sel2   (tag_access_wdata_sel[2]),

                .dout   (tag_access_wdata[47:0])

        );

// Determine whether context is nucleus or not.

//assign tlu_tag_access_nctxt_g = (tag_access_wdata[12:0] == 13'd0) ;

assign        tlu_tag_access_ctxt_g[12:0] = tag_access_ctxt_g[12:0] ;

wire    [47:0]   dsfar_wdata ;

dp_mux2es #(48) dsfar_dsel(

                .in0    ({ldst_va_masked_g[15:0],ldst_va_g[31:0]}), // dsfar;trap

                .in1    (lsu_tlu_st_rs3_data_b47t0_g[47:0]), // asi write

                .sel    (dmmu_any_sfsr_wr),

                .dout   (dsfar_wdata[47:0])

        );

// Warning for Grape Mapper - the number of bits may have to be changed to

// map implementation.

assign  mra_wdata[155:0] =

        // Bug 4676 - tsb rsrved field

        {lsu_tlu_st_rs3_data_b47t0_g[47:12],8'd0,

                lsu_tlu_st_rs3_data_b47t0_g[3:0],        //ps0 zctxt,nzctxt tsb

         lsu_tlu_st_rs3_data_b47t0_g[47:12],8'd0,

                lsu_tlu_st_rs3_data_b47t0_g[3:0],        //ps1 zctxt,nzctxt tsb

         tag_access_wdata[47:0],         //i/d tag-access

         lsu_tlu_st_rs3_data_b47t0_g[10:8],     //ps1 page size

         lsu_tlu_st_rs3_data_b47t0_g[2:0],       //ps0 page size

         6'd0};

//=========================================================================================

//      D-TAG ACCESS

//=========================================================================================

// 4 registers for the 4 threads.

// 35b of VA || 13b Ctxt.

// ** Ctxt is to be read as zero if there is no context associated with the access **

// VA will be sing-extended based on bit 47. 

// Update in w2.

assign  dtag_access_w2[47:13] = mra_rdata[`MRA_TACCESS_HI:`MRA_TACCESS_LO+13] ;

// Can this be shared with the i-side ?

assign  tlu_dtag_access_w2[47:13] = dtag_access_w2[47:13] ;

//=========================================================================================

//      I-TAG ACCESS

//=========================================================================================

// 4 registers for the 4 threads.

// 35b of VA || 13b Ctxt.

// ** Ctxt is to be read as zero if there is no context associated with the access **

// VA will be sing-extended based on bit 47. 

// Update in w2.

// SPARC_HPV_EN - This needs to be obsoleted. Common tag-access will be superimposed

// on dta_access bus.

//assign        itag_access_w2[32:13] = mra_rdata[`MRA_TACCESS_HI-15:`MRA_TACCESS_LO+13] ;

//assign        itag_access_w2[47:0] = mra_rdata[`MRA_TACCESS_HI:`MRA_TACCESS_LO] ;

//assign        tlu_itag_access_w2[32:13] = itag_access_w2[32:13] ;

//=========================================================================================

//      D-TAG TARGET

//=========================================================================================

// Tag Target is based on currently selected thread.

// Thread0,1,2,3

assign tag_target[63:0] =

        {3'b000,

        ldxa_l1mx1_dout_m[12:0], // Context

        //tag_access_w2[12:0],          // Context

        6'b000000,

        {16{ldxa_l1mx1_dout_m[47]}},    // Sign-extend VA[47]

        //{16{tag_access_w2[47]}},      // Sign-extend VA[47]

        ldxa_l1mx1_dout_m[47:22]};      // VA // Bug 3975.

        //tag_access_w2[47:22]};        // VA

//=========================================================================================

//      D-TSB

//=========================================================================================

// Note : on interface, dtsb represents ps0 tsbs, itsb represents ps1 tsbs. 

wire    [47:0]   tsb_ps0, tsb_ps1 ;

assign  tsb_ps0[47:0] = mra_rdata[`MRA_TSB_PS0_HI:`MRA_TSB_PS0_LO] ;

assign  tsb_ps1[47:0] = mra_rdata[`MRA_TSB_PS1_HI:`MRA_TSB_PS1_LO] ;

assign  tlu_dtsb_split_w2 = tsb_ps0[12] ;

// SPARC_HPV_EN - extend tsb_size by 1b.

assign  tlu_dtsb_size_w2[3:0] = tsb_ps0[3:0] ;

//=========================================================================================

//      CTXT CONFIG

//=========================================================================================

wire    [5:0]    ptr_ctxt_cfg ;

assign  tlu_ctxt_cfg_w2[5:0] =   mra_rdata[`MRA_CTXTCFG_HI:`MRA_CTXTCFG_LO] ;

dff_s  #(6) pctxt_stgm (

        .din    (mra_rdata[`MRA_CTXTCFG_HI:`MRA_CTXTCFG_LO]),

        .q      (ptr_ctxt_cfg[5:0]),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        );

//=========================================================================================

//      I-TSB

//=========================================================================================

assign  tlu_itsb_split_w2 = tsb_ps1[12] ;

assign  tlu_itsb_size_w2[3:0] = tsb_ps1[3:0] ;

//=========================================================================================

//      STAGE TSB BASE FOR USE IN PTR CALCULATION

//=========================================================================================

wire    [47:13] tsb_base ;

assign  tsb_base[47:13] =

        tlu_tsb_rd_ps0_sel ? tsb_ps0[47:13] : tsb_ps1[47:13] ;

        //tlu_tsb_rd_ps0_sel ? dtsb[47:13] : itsb[47:13] ;

dff_s  #(35) tsbbase_stgm (

        .din    (tsb_base[47:13]),

        .q      (tlu_tsb_base_w2_d1[47:13]),

        .clk    (clk),

        .se     (1'b0),       .si (),          .so ()

        );

//=========================================================================================

//      8K and 64K Ptr

//=========================================================================================

// In MMU Control.

//=========================================================================================

//      Direct Ptr

//=========================================================================================

//=========================================================================================

//      I-/D TLB Fill : TTE Tag and Data.

//=========================================================================================

// TTE Tag is formed from Tag Access.

// TTE Data is formed from rs3_data for store.

// Timing needs to be fixed !!! Partition mode will add one more cycle

// to path. tlb write will occur in w3.

// partitioned for vlint purposes.

//assign        st_rs3_data_g[63:0] = lsu_tlu_st_rs3_data_g[63:0] ; 

assign  st_rs3_data_b63t59_g[63:59] = lsu_tlu_st_rs3_data_b63t59_g[63:59] ;

assign  st_rs3_data_b39t8_g[39:8] = lsu_tlu_st_rs3_data_b47t0_g[39:8] ;

assign  st_rs3_data_b6t1_g[6:1] = lsu_tlu_st_rs3_data_b47t0_g[6:1] ;

assign  tag_access_w2[47:0] = mra_rdata[`MRA_TACCESS_HI:`MRA_TACCESS_LO] ;

wire idtte_tag_vld_g,idtte_tag_vld_d1 ;

assign  idtte_tag_vld_g =

        st_rs3_data_b63t59_g[63] ;

wire idtte_tag_lock_g,idtte_tag_lock_d1 ;

assign  idtte_tag_lock_g =

        tlu_sun4r_tte_g ? st_rs3_data_b6t1_g[6] : st_rs3_data_b63t59_g[61] ;

`ifdef FPGA_SYN_CLK_EN

`else

`ifdef FPGA_SYN_CLK_EN

`else

clken_buf clkbf_idttetg (

                .rclk   (clk),

                .enb_l  (tlu_lng_ltncy_en_l),

                .tmb_l  (~se),

                .clk    (tlb_access3_clk)

                ) ;

`endif

`endif

// Stage some bits to match posedge rd for lng-lat reads of mra.

`ifdef FPGA_SYN_CLK_DFF

dffe_s  #(10) stgd1_idttetg (

        .din    ({idtte_tag_vld_g,idtte_tag_lock_g,tlu_tte_tag_g[2:0],

                tlu_tte_wr_pid_g[2:0],tlu_tte_real_g,tlu_tlb_tag_invrt_parity}),

        .q      ({idtte_tag_vld_d1,idtte_tag_lock_d1,tlu_tte_tag_d1[2:0],

                tlu_tte_wr_pid_d1[2:0],tlu_tte_real_d1,tlu_tlb_tag_invrt_parity_d1}),

        .en (~(tlu_lng_ltncy_en_l)), .clk(clk),

        .se     (1'b0),       .si (),          .so ()

        );

`else

`ifdef FPGA_SYN_CLK_DFF

dffe_s  #(10) stgd1_idttetg (

        .din    ({idtte_tag_vld_g,idtte_tag_lock_g,tlu_tte_tag_g[2:0],

                tlu_tte_wr_pid_g[2:0],tlu_tte_real_g,tlu_tlb_tag_invrt_parity}),

        .q      ({idtte_tag_vld_d1,idtte_tag_lock_d1,tlu_tte_tag_d1[2:0],

                tlu_tte_wr_pid_d1[2:0],tlu_tte_real_d1,tlu_tlb_tag_invrt_parity_d1}),

        .en (~(tlu_lng_ltncy_en_l)), .clk(clk),

        .se     (1'b0),       .si (),          .so ()

        );

`else

dff_s  #(10) stgd1_idttetg (

        .din    ({idtte_tag_vld_g,idtte_tag_lock_g,tlu_tte_tag_g[2:0],

                tlu_tte_wr_pid_g[2:0],tlu_tte_real_g,tlu_tlb_tag_invrt_parity}),

        .q      ({idtte_tag_vld_d1,idtte_tag_lock_d1,tlu_tte_tag_d1[2:0],

                tlu_tte_wr_pid_d1[2:0],tlu_tte_real_d1,tlu_tlb_tag_invrt_parity_d1}),

        .clk    (tlb_access3_clk),

        .se     (1'b0),       .si (),          .so ()

        );

`endif

`endif

// assumption is that tag_access_w2 gets delayed by a cycle because

// the rd is now posedge.

assign idtte_tag_b53t0_g[53:0] =

        {tag_access_w2[47:22],          // VA_tag       (26b)

        tlu_tte_tag_d1[2],              // 27:22 are valid (1b)

        idtte_tag_vld_d1,               // V            (1b) can be 0 or 1

        idtte_tag_lock_d1,              // L            (1b) 

        1'b1,                           // U            (1b) : must be set on write

        tag_access_w2[21:16],           // VA_tag       (6b)

        tlu_tte_tag_d1[1],              // 21:16 are valid (1b)

        tag_access_w2[15:13],           // VA_tag       (3b)

        tlu_tte_tag_d1[0],               // 15:13 are valid (1b)

        tag_access_w2[12:0]              // Ctxt b12:0   (13b)

                        };

assign  idtte_tag_b58t55_g[58:55] = {tlu_tte_wr_pid_d1[2:0],tlu_tte_real_d1};

// V and U bit omitted from tag as it can change once in tlb

// assign       idtte_tag_g[54] = 

// tlu_tlb_tag_invrt_parity_d1^(^{idtte_tag_g[58:55],idtte_tag_g[53:27],idtte_tag_g[25],idtte_tag_g[23:0]}) ;

// Additional page size bit does not have to be included. EP ? 

// SUN4R TTE

wire    [41:0]   idtte_data_sun4r_g ;