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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: tlu_tdp.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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///////////////////////////////////////////////////////////////////////
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/*
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// Description: Trap Datapath
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*/
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////////////////////////////////////////////////////////////////////////
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// Global header file includes
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////////////////////////////////////////////////////////////////////////
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`include "sys.h" // system level definition file which contains the
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// time scale definition
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////////////////////////////////////////////////////////////////////////
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// Local header file includes / local defines
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////////////////////////////////////////////////////////////////////////
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`include "tlu.h"
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//FPGA_SYN enables all FPGA related modifications
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`ifdef FPGA_SYN
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`define FPGA_SYN_CLK_EN
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`define FPGA_SYN_CLK_DFF
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`endif
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module tlu_tdp (/*AUTOARG*/
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// Outputs
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tlu_pib_rsr_data_e, tlu_restore_pc_w1, tlu_restore_npc_w1, tlu_partial_trap_pc_w1,
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tsa_wdata, tlu_int_pstate_ie, local_pstate_ie, tlu_ifu_pstate_pef,
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tlu_lsu_pstate_cle, tlu_lsu_pstate_priv, tlu_int_redmode, tlu_lsu_redmode,
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tlu_sscan_test_data,
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// modified for bug 1767
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tlu_pstate_am, tlu_sftint_id,
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// added for timing
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// modfied for hypervisor support
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tlu_dnrtry_global_g, tlu_tick_incr_din, tlu_exu_rsr_data_m,
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tlu_hpstate_priv, local_hpstate_priv, local_hpstate_enb, local_pstate_priv,
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tlu_hpstate_enb, tlu_hintp, tlu_por_rstint_g, tcl_hpstate_priv, tcl_hpstate_enb,
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tlu_trap_hpstate_enb, tlu_hpstate_tlz, tlu_asi_state_e, tlu_hpstate_ibe,
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so,
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// Inputs
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tsa_rdata, tlu_wsr_data_w, lsu_tlu_rsr_data_e, tlu_ibrkpt_trap_w2,
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// reset was modified to abide to the Niagara reset methodology
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rclk, tlu_rst, tlu_thrd_wsel_w2, ifu_lsu_imm_asi_d, // tm_l,
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tlu_final_ttype_w2, tlu_pstate_din_sel0, tlu_pstate_din_sel1,
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tlu_pstate_din_sel2, tlu_pstate_din_sel3, ifu_lsu_imm_asi_vld_d,
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lsu_asi_reg0, lsu_asi_reg1, lsu_asi_reg2, lsu_asi_reg3,
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exu_tlu_ccr0_w, exu_tlu_ccr1_w, exu_tlu_ccr2_w, exu_tlu_ccr3_w,
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exu_tlu_cwp0, exu_tlu_cwp1, exu_tlu_cwp2, exu_tlu_cwp3, tlu_trap_cwp_en,
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tlu_pc_new_w, tlu_npc_new_w, tlu_sftint_en_l_g, tlu_sftint_mx_sel,
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tlu_set_sftint_l_g, tlu_wr_tsa_inst_w2, tlu_clr_sftint_l_g,
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tlu_wr_sftint_l_g, tlu_sftint_penc_sel, tlu_tba_en_l, tlu_tick_en_l,
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tlu_tickcmp_sel, tlu_tickcmp_en_l, // tlu_retry_inst_m, tlu_done_inst_m,
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tlu_update_pc_l_w, tlu_tl_gt_0_w2, pib_pich_wrap, // tlu_dnrtry_inst_m_l,
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tlu_select_tba_w2, tlu_select_redmode, tlu_update_pstate_l_w2, tlu_pil,
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tlu_trp_lvl, tlu_tick_npt, tlu_thrd_rsel_e, tlu_tick_incr_dout,
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tlu_rdpr_mx1_sel, tlu_rdpr_mx2_sel, tlu_rdpr_mx3_sel, tlu_rdpr_mx4_sel,
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tlu_hpstate_din_sel0, tlu_hpstate_din_sel1, tlu_pc_mxsel_w2,
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tlu_hpstate_din_sel2, tlu_hpstate_din_sel3, tlu_update_hpstate_l_w2,
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tlu_htba_en_l, tlu_rdpr_mx5_sel, tlu_rdpr_mx6_sel, pib_picl_wrap,
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tlu_rdpr_mx7_sel, tlu_htickcmp_intdis, tlu_stickcmp_en_l, tlu_htickcmp_en_l,
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tlu_gl_lvl0, tlu_gl_lvl1, tlu_gl_lvl2, tlu_gl_lvl3, tlu_wr_hintp_g,
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tlu_set_hintp_sel_g, ctu_sscan_tid, si, se
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);
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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// End of automatics
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input [`TLU_TDP_TSA_WIDTH-1:0] tsa_rdata; // rd data for tsa.
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input [`TLU_THRD_NUM-1:0] tlu_por_rstint_g;
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//
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// modified for timing
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input [`TLU_ASR_DATA_WIDTH-1:0] tlu_wsr_data_w; // pr/st data from irf.
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input [7:0] lsu_tlu_rsr_data_e; // lsu sr/pr read data
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input rclk; // clock
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//
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// reset was removed to abide to the Niagara reset methodology
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input tlu_rst; // unit-reset
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input [`TLU_THRD_NUM-1:0] tlu_thrd_wsel_w2;// thread requiring tsa write.
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input [`TSA_TTYPE_WIDTH-1:0] tlu_final_ttype_w2; // selected ttype - g
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input tlu_ibrkpt_trap_w2; // instruction brkpt trap
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input tlu_trap_hpstate_enb; // mode indicator for the trapped thrd
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input tlu_wr_tsa_inst_w2; // write state inst
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input [1:0] tlu_pstate_din_sel0; // sel source of tsa wdata
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input [1:0] tlu_pstate_din_sel1; // sel source of tsa wdata
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input [1:0] tlu_pstate_din_sel2; // sel source of tsa wdata
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input [1:0] tlu_pstate_din_sel3; // sel source of tsa wdata
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input [`TLU_ASI_STATE_WIDTH-1:0] lsu_asi_reg0; // asi state - thread0
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input [`TLU_ASI_STATE_WIDTH-1:0] lsu_asi_reg1; // asi state - thread1
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input [`TLU_ASI_STATE_WIDTH-1:0] lsu_asi_reg2; // asi state - thread2
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input [`TLU_ASI_STATE_WIDTH-1:0] lsu_asi_reg3; // asi state - thread3
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input [`TLU_ASI_STATE_WIDTH-1:0] ifu_lsu_imm_asi_d; // asi state value from imm
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input ifu_lsu_imm_asi_vld_d; // valid asi state value from imm
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input [3:0] tlu_tickcmp_sel; // select src for tickcmp
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input [3:0] tlu_tickcmp_en_l; // tick cmp reg write enable
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input tlu_tick_en_l; // tick reg write enable
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// overflow for the pic registers - lvl15 int
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// input [`TLU_THRD_NUM-1:0] pib_pic_wrap;
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input [`TLU_THRD_NUM-1:0] pib_pich_wrap;
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input [`TLU_THRD_NUM-1:0] pib_picl_wrap;
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input [7:0] exu_tlu_ccr0_w; // ccr - thread0
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input [7:0] exu_tlu_ccr1_w; // ccr - thread1
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input [7:0] exu_tlu_ccr2_w; // ccr - thread2
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input [7:0] exu_tlu_ccr3_w; // ccr - thread3
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// input [2:0] exu_tlu_cwp0_w; // cwp - thread0
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// input [2:0] exu_tlu_cwp1_w; // cwp - thread1
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// input [2:0] exu_tlu_cwp2_w; // cwp - thread2
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// input [2:0] exu_tlu_cwp3_w; // cwp - thread3
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input [2:0] exu_tlu_cwp0; // cwp - thread0
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input [2:0] exu_tlu_cwp1; // cwp - thread1
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input [2:0] exu_tlu_cwp2; // cwp - thread2
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input [2:0] exu_tlu_cwp3; // cwp - thread3
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// added for bug3499
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input [`TLU_THRD_NUM-1:0] tlu_trap_cwp_en;
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// modified due to bug 3017
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// input [47:0] ifu_tlu_pc_m; // pc
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// input [47:0] ifu_tlu_npc_m; // npc
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// modified due to redistribution of logic
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// input [48:0] ifu_tlu_pc_m; // pc
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// input [48:0] ifu_tlu_npc_m; // npc
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input [48:0] tlu_pc_new_w; // pc
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input [48:0] tlu_npc_new_w; // npc
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input [3:0] tlu_sftint_en_l_g; // wr enable for sftint regs.
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input [3:0] tlu_sftint_mx_sel; // mux select for sftint regs
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input tlu_set_sftint_l_g; // set sftint
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input tlu_clr_sftint_l_g; // clr sftint
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input tlu_wr_sftint_l_g; // wr to sftin (asr 16)
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//
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// removed due to sftint recode
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// input [3:0] tlu_sftint_lvl14_int; // sftint lvl 14 plus tick int
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input [3:0] tlu_sftint_penc_sel;
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input [3:0] tlu_tba_en_l; // tba reg write enable
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// logic moved to tlu_misctl
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// input tlu_retry_inst_m; // valid retry inst
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// input tlu_done_inst_m; // valid done inst
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// input tlu_dnrtry_inst_m; // valid done/retry inst - g
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// input tlu_dnrtry_inst_m_l; // valid done/retry inst - g
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// input [3:0] tlu_update_pc_l_m; // update pc or npc for a thread
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input [3:0] tlu_update_pc_l_w; // update pc or npc for a thread
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// modified due to timing
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// input tlu_self_boot_rst_g;
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// input tlu_tl_gt_0_g; // trp lvl gt then 0
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// input tlu_select_tba_g;
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// input tlu_select_htba_g; // choosing htba for forming trappc/trapnpc
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// input tlu_self_boot_rst_w2;
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// added for one-hot mux problem
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input [2:0] tlu_pc_mxsel_w2;
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input tlu_tl_gt_0_w2; // trp lvl gt then 0
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input tlu_select_tba_w2;
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input [`TLU_THRD_NUM-1:0] tlu_update_pstate_l_w2; // pstate write enable
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input [`TLU_THRD_NUM-1:0] tlu_thrd_rsel_e; // read select for threaded regs
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input [3:0] tlu_pil; // mx'ed pil
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input [2:0] tlu_trp_lvl; // mx'ed trp lvl
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input tlu_select_redmode;
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input tlu_tick_npt; // npt bit of tick
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input [`TLU_ASR_DATA_WIDTH-4:0] tlu_tick_incr_dout;
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//
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// added and/or modified for hypervisor support
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input [1:0] tlu_hpstate_din_sel0; // sel source of tsa wdata
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input [1:0] tlu_hpstate_din_sel1; // sel source of tsa wdata
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input [1:0] tlu_hpstate_din_sel2; // sel source of tsa wdata
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input [1:0] tlu_hpstate_din_sel3; // sel source of tsa wdata
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input [`TLU_THRD_NUM-1:0] tlu_stickcmp_en_l; // stick cmp reg write enable
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input [`TLU_THRD_NUM-1:0] tlu_htickcmp_en_l; // htick cmp reg write enable
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input [`TLU_THRD_NUM-1:0] tlu_wr_hintp_g; // wr control for hintp regs.
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input [`TLU_THRD_NUM-1:0] tlu_set_hintp_sel_g; // set control for hintp regs.
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input [`TLU_THRD_NUM-1:0] tlu_htba_en_l; // htba reg write enable
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input [`TLU_THRD_NUM-1:0] tlu_update_hpstate_l_w2; // hpstate write enable
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input tlu_htickcmp_intdis; // int. disable bit of htick-cmp
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input [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl0; // global register value t0
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input [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl1; // global register value t1
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input [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl2; // global register value t2
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input [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl3; // global register value t3
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// mux select to read the new ASR registers
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input [3:1] tlu_rdpr_mx1_sel;
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input [3:1] tlu_rdpr_mx2_sel;
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input [2:1] tlu_rdpr_mx3_sel;
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input [2:1] tlu_rdpr_mx4_sel;
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input [3:1] tlu_rdpr_mx5_sel;
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input [2:0] tlu_rdpr_mx6_sel;
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input [3:0] tlu_rdpr_mx7_sel;
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//
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input [`TLU_THRD_NUM-1:0] ctu_sscan_tid;
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input [`TLU_ASR_DATA_WIDTH-1:0] tlu_pib_rsr_data_e; // rsr data from pib
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input si; // scan-in
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input se; // scan-en
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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// End of automatics
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//
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// modified due to bug 3017
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output [48:0] tlu_restore_pc_w1; // trap pc or pc on retry.
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output [48:0] tlu_restore_npc_w1; // trap pc or pc on retry.
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output [33:0] tlu_partial_trap_pc_w1;
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// the tlu_exu_rsr_data_e will become obsolete, to be removed
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// added for timing
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// output [`TLU_ASR_DATA_WIDTH-1:0] tlu_exu_rsr_data_e; // rsr data to exu
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output [`TLU_ASR_DATA_WIDTH-1:0] tlu_exu_rsr_data_m; // rsr data to exu
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// modified due to timing violations
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// output [`TLU_ASR_DATA_WIDTH-1:0] tlu_pib_rsr_data_e; // trap pc or pc on retry.
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//
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// modified for hypervisor support
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output [`TLU_TSA_WIDTH-1:0] tsa_wdata; // wr data for tsa.
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//
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output [`TLU_THRD_NUM-1:0] tlu_int_pstate_ie; // interrupt enable
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output [`TLU_THRD_NUM-1:0] local_pstate_ie; // interrupt enable
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output [`TLU_THRD_NUM-1:0] tlu_ifu_pstate_pef; // fp enable
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output [`TLU_THRD_NUM-1:0] tlu_lsu_pstate_cle; // current little endian
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output [`TLU_THRD_NUM-1:0] tlu_lsu_pstate_priv; // privilege mode
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output [`TLU_THRD_NUM-1:0] tlu_int_redmode; // redmode
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output [`TLU_THRD_NUM-1:0] tlu_lsu_redmode; // redmode
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// modified for bug 1767
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// output [1:0] tlu_pstate0_mmodel; // mem. model - thread0
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// output [1:0] tlu_pstate1_mmodel; // mem. model - thread1
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// output [1:0] tlu_pstate2_mmodel; // mem. model - thread2
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// output [1:0] tlu_pstate3_mmodel; // mem. model - thread3
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// output [3:0] tlu_pstate_tle; // trap little endian
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// output [`TLU_THRD_NUM-1:0] tlu_pstate_cle; // current little endian
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245 |
|
|
// output [`TLU_THRD_NUM-1:0] tlu_pstate_priv; // privilege mode
|
246 |
|
|
output [`TLU_THRD_NUM-1:0] tlu_pstate_am; // address mask
|
247 |
|
|
//
|
248 |
|
|
// removed for bug 2187
|
249 |
|
|
// output [`TLU_THRD_NUM-1:0] tlu_sftint_lvl14;
|
250 |
|
|
output [`TLU_THRD_NUM-1:0] tlu_hpstate_priv; // hypervisor privilege
|
251 |
|
|
output [`TLU_THRD_NUM-1:0] tlu_hpstate_enb; // hypervisor lite enb
|
252 |
|
|
output [`TLU_THRD_NUM-1:0] tlu_hpstate_tlz; // hypervisor tlz
|
253 |
|
|
output [`TLU_THRD_NUM-1:0] tlu_hpstate_ibe; // hypervisor instruction brkpt
|
254 |
|
|
output [`TLU_THRD_NUM-1:0] local_hpstate_priv; // hypervisor privilege
|
255 |
|
|
output [`TLU_THRD_NUM-1:0] tcl_hpstate_priv; // hypervisor privilege
|
256 |
|
|
output [`TLU_THRD_NUM-1:0] local_pstate_priv; // pstate privilege
|
257 |
|
|
output [`TLU_THRD_NUM-1:0] local_hpstate_enb; // hypervisor lite enb
|
258 |
|
|
output [`TLU_THRD_NUM-1:0] tcl_hpstate_enb; // hypervisor lite enb
|
259 |
|
|
output [3:0] tlu_sftint_id;
|
260 |
|
|
// output tlu_tick_match; // tick to tick cmp match
|
261 |
|
|
// output tlu_stick_match; // stick to tick cmp match
|
262 |
|
|
// output tlu_htick_match; // htick to tick cmp match
|
263 |
|
|
// output [`TLU_ASR_DATA_WIDTH-1:0] tlu_tick_incr_din;
|
264 |
|
|
output [`TLU_ASR_DATA_WIDTH-3:0] tlu_tick_incr_din;
|
265 |
|
|
//
|
266 |
|
|
// modified for hypervisor support
|
267 |
|
|
// output [2:0] tlu_restore_globals; // restored global regs
|
268 |
|
|
//
|
269 |
|
|
output [`TSA_GLOBAL_WIDTH-1:0] tlu_dnrtry_global_g; // restored globals
|
270 |
|
|
output [`TLU_THRD_NUM-1:0] tlu_hintp;
|
271 |
|
|
//
|
272 |
|
|
// current asi state
|
273 |
|
|
output [`TLU_ASI_STATE_WIDTH-1:0] tlu_asi_state_e;
|
274 |
|
|
//
|
275 |
|
|
// modified due to race key word limitation
|
276 |
|
|
// output [62:0] tlu_sscan_test_data;
|
277 |
|
|
output [`TDP_SSCAN_WIDTH-1:0] tlu_sscan_test_data;
|
278 |
|
|
output so; // scan-out;
|
279 |
|
|
|
280 |
|
|
/*AUTOWIRE*/
|
281 |
|
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
282 |
|
|
// End of automatics
|
283 |
|
|
//
|
284 |
|
|
// local reset was added to abide to the Niagara reset methodology
|
285 |
|
|
wire local_rst; // local reset
|
286 |
|
|
wire se_l; // testmode_l replacement
|
287 |
|
|
//
|
288 |
|
|
// rdpr muxe outputs
|
289 |
|
|
wire [`TLU_ASR_DATA_WIDTH-1:0] tlu_rdpr_mx1_out;
|
290 |
|
|
wire [3:0] tlu_rdpr_mx2_out;
|
291 |
|
|
wire [`SFTINT_WIDTH-1:0] tlu_rdpr_mx3_out;
|
292 |
|
|
wire [`RDSR_TSTATE_WIDTH-1:0] tlu_rdpr_mx4_out;
|
293 |
|
|
//
|
294 |
|
|
// constructing one-hot selects
|
295 |
|
|
wire rdpr_mx1_onehot_sel, rdpr_mx2_onehot_sel;
|
296 |
|
|
wire rdpr_mx3_onehot_sel, rdpr_mx4_onehot_sel;
|
297 |
|
|
wire rdpr_mx5_onehot_sel, rdpr_mx6_onehot_sel;
|
298 |
|
|
//
|
299 |
|
|
wire [32:0] true_tba0,true_tba1,true_tba2,true_tba3;
|
300 |
|
|
wire [60:0] true_tick;
|
301 |
|
|
// modified due to bug 3017
|
302 |
|
|
wire [48:0] true_pc0,true_pc1,true_pc2,true_pc3;
|
303 |
|
|
// wire [47:0] sscan_pc;
|
304 |
|
|
wire [`TDP_SSCAN_WIDTH-1:0] sscan_data_test0;
|
305 |
|
|
wire [`TDP_SSCAN_WIDTH-1:0] sscan_data_test1;
|
306 |
|
|
wire [`TDP_SSCAN_WIDTH-1:0] sscan_data_test2;
|
307 |
|
|
wire [`TDP_SSCAN_WIDTH-1:0] sscan_data_test3;
|
308 |
|
|
wire [`TDP_SSCAN_WIDTH-1:0] tdp_sscan_test_data;
|
309 |
|
|
wire [`TLU_THRD_NUM-1:0] sscan_tid_sel;
|
310 |
|
|
wire [48:0] true_npc0,true_npc1,true_npc2,true_npc3;
|
311 |
|
|
// wire [47:0] true_npc0,true_npc1,true_npc2,true_npc3;
|
312 |
|
|
// wire [47:0] true_pc0,true_pc1,true_pc2,true_pc3;
|
313 |
|
|
// wire [47:0] sscan_pc;
|
314 |
|
|
// wire [47:0] normal_trap_pc, normal_trap_npc;
|
315 |
|
|
//
|
316 |
|
|
// modified for hypervisor support
|
317 |
|
|
wire [`TLU_TSA_WIDTH-1:0] trap_tsa_wdata;
|
318 |
|
|
wire [`TLU_TSA_WIDTH-1:0] trap0_tsa_wdata,trap1_tsa_wdata;
|
319 |
|
|
wire [`TLU_TSA_WIDTH-1:0] trap2_tsa_wdata,trap3_tsa_wdata;
|
320 |
|
|
wire [`TLU_TSA_WIDTH-1:0] wrpr_tsa_wdata;
|
321 |
|
|
wire [`TLU_TSA_WIDTH-1:0] tsa_wdata;
|
322 |
|
|
wire [`RDSR_TSTATE_WIDTH-1:0] tstate_rdata;
|
323 |
|
|
wire [1:0] tstate_dummy_zero;
|
324 |
|
|
wire [`WSR_TSTATE_WIDTH-1:0] compose_tstate;
|
325 |
|
|
wire [`TSA_HTSTATE_WIDTH-1:0] compose_htstate;
|
326 |
|
|
wire [`TSA_GLOBAL_WIDTH-1:0] global_rdata;
|
327 |
|
|
// wire [`TLU_ASR_DATA_WIDTH-1:0] wsr_data_w;
|
328 |
|
|
wire [`SFTINT_WIDTH-1:0] wsr_data_w;
|
329 |
|
|
// reduced width to 48 due to lint violations
|
330 |
|
|
wire [47:0] wsr_data_w2;
|
331 |
|
|
//
|
332 |
|
|
// modified for bug 3017
|
333 |
|
|
// wire [47:2] trap_pc0,trap_pc1,trap_pc2,trap_pc3;
|
334 |
|
|
// wire [47:2] trap_npc0,trap_npc1,trap_npc2,trap_npc3;
|
335 |
|
|
wire [48:2] trap_pc0,trap_pc1,trap_pc2,trap_pc3;
|
336 |
|
|
wire [48:2] trap_npc0,trap_npc1,trap_npc2,trap_npc3;
|
337 |
|
|
wire [7:0] trap_ccr0,trap_ccr1,trap_ccr2,trap_ccr3;
|
338 |
|
|
wire [7:0] trap_asi0,trap_asi1,trap_asi2,trap_asi3;
|
339 |
|
|
wire [2:0] trap_cwp0,trap_cwp1,trap_cwp2,trap_cwp3;
|
340 |
|
|
wire [2:0] tlu_cwp0,tlu_cwp1,tlu_cwp2,tlu_cwp3;
|
341 |
|
|
wire [`TLU_ASI_STATE_WIDTH-1:0] imm_asi_e;
|
342 |
|
|
wire [`TLU_ASI_STATE_WIDTH-1:0] asi_state_reg_e;
|
343 |
|
|
wire [`TLU_ASI_STATE_WIDTH-1:0] asi_state_final_e;
|
344 |
|
|
wire imm_asi_vld_e;
|
345 |
|
|
//
|
346 |
|
|
// modified due to tickcmp, stickcmp and sftint cleanup
|
347 |
|
|
// wire [15:0] sftint0, sftint1, sftint2, sftint3;
|
348 |
|
|
// wire [15:1] sftint_set_din, sftint_clr_din, sftint_wr_din;
|
349 |
|
|
wire [`SFTINT_WIDTH-1:0] sftint0, sftint1, sftint2, sftint3;
|
350 |
|
|
wire [`SFTINT_WIDTH-1:0] sftint_set_din, sftint_clr_din, sftint_wr_din;
|
351 |
|
|
wire [`SFTINT_WIDTH-1:0] sftint_din;
|
352 |
|
|
wire [`SFTINT_WIDTH-1:0] sftint;
|
353 |
|
|
wire [`TLU_THRD_NUM-1:0] sftint_b0_din;
|
354 |
|
|
wire [`TLU_THRD_NUM-1:0] sftint_b0_en;
|
355 |
|
|
wire [`TLU_THRD_NUM-1:0] sftint_b15_din;
|
356 |
|
|
wire [`TLU_THRD_NUM-1:0] sftint_b15_en;
|
357 |
|
|
wire [`TLU_THRD_NUM-1:0] sftint_b16_din;
|
358 |
|
|
wire [`TLU_THRD_NUM-1:0] sftint_b16_en;
|
359 |
|
|
wire [`TLU_THRD_NUM-1:0] sftint_lvl14;
|
360 |
|
|
wire [3:0] sftin_din_mxsel;
|
361 |
|
|
// recoded for one-hot problem during reset
|
362 |
|
|
// wire sftint_sel_onehot_g;
|
363 |
|
|
//
|
364 |
|
|
// added for PIB support
|
365 |
|
|
wire tcmp0_clk, tcmp1_clk;
|
366 |
|
|
wire tcmp2_clk, tcmp3_clk;
|
367 |
|
|
wire [14:0] sftint_penc_din;
|
368 |
|
|
wire sftint0_clk,sftint1_clk;
|
369 |
|
|
wire sftint2_clk,sftint3_clk;
|
370 |
|
|
//
|
371 |
|
|
wire [32:0] tba_data;
|
372 |
|
|
wire [32:0] tba_rdata;
|
373 |
|
|
wire [33:0] tlu_rstvaddr_base;
|
374 |
|
|
wire [`TLU_HTBA_WIDTH-1:0] htba_data;
|
375 |
|
|
wire tba0_clk,tba1_clk,tba2_clk,tba3_clk;
|
376 |
|
|
// modified for bug 3017
|
377 |
|
|
// wire [46:0] tsa_pc_m,tsa_npc_m;
|
378 |
|
|
// wire [48:0] dnrtry_pc,dnrtry_npc;
|
379 |
|
|
wire [48:0] restore_pc_w2;
|
380 |
|
|
wire [48:0] restore_npc_w2;
|
381 |
|
|
// wire [48:0] pc_new, npc_new;
|
382 |
|
|
// wire [48:0] pc_new_w, npc_new_w;
|
383 |
|
|
wire [33:0] partial_trap_pc_w2;
|
384 |
|
|
wire pc0_clk,pc1_clk,pc2_clk,pc3_clk;
|
385 |
|
|
// wire [`TLU_TSA_WIDTH-1:0] tsa_data_m;
|
386 |
|
|
wire [`TLU_ASR_DATA_WIDTH-1:0] true_tickcmp0, true_tickcmp1;
|
387 |
|
|
wire [`TLU_ASR_DATA_WIDTH-1:0] true_tickcmp2, true_tickcmp3;
|
388 |
|
|
wire [`TLU_ASR_DATA_WIDTH-1:0] tickcmp_rdata;
|
389 |
|
|
wire [`TLU_THRD_NUM-1:0] tickcmp_intdis_din;
|
390 |
|
|
wire [`TLU_THRD_NUM-1:0] tickcmp_intdis_en;
|
391 |
|
|
wire [`TLU_THRD_NUM-1:0] tickcmp_int;
|
392 |
|
|
wire [`TLU_THRD_NUM-1:0] tlu_set_hintp_g;
|
393 |
|
|
wire [`TLU_THRD_NUM-1:0] tlu_hintp_en_l_g;
|
394 |
|
|
wire tlu_htick_match; // htick to tick cmp match
|
395 |
|
|
wire tick_match;
|
396 |
|
|
wire [`TLU_ASR_DATA_WIDTH-4:0] tickcmp_data;
|
397 |
|
|
wire [`TLU_ASR_DATA_WIDTH-2:2] tick_din;
|
398 |
|
|
// reg [`TLU_ASR_DATA_WIDTH-1:0] tlu_rsr_data_e;
|
399 |
|
|
wire [`PSTATE_TRUE_WIDTH-1:0] true_pstate0,true_pstate1;
|
400 |
|
|
wire [`PSTATE_TRUE_WIDTH-1:0] true_pstate2,true_pstate3;
|
401 |
|
|
// wire [`TLU_THRD_NUM-1:0] tlu_pstate_priv; // privilege mode
|
402 |
|
|
// added for hypervisor support
|
403 |
|
|
wire [`TSA_PSTATE_WIDTH-1:0] trap_pstate0,trap_pstate1;
|
404 |
|
|
wire [`TSA_PSTATE_WIDTH-1:0] trap_pstate2,trap_pstate3;
|
405 |
|
|
//
|
406 |
|
|
// wire [`PSTATE_TRUE_WIDTH-1:0] dnrtry_pstate;
|
407 |
|
|
// wire [`PSTATE_TRUE_WIDTH-1:0] dnrtry_pstate_m;
|
408 |
|
|
// wire [`PSTATE_TRUE_WIDTH-1:0] wsr_data_pstate_g;
|
409 |
|
|
wire [`WSR_PSTATE_VR_WIDTH-1:0] dnrtry_pstate_m;
|
410 |
|
|
wire [`WSR_PSTATE_VR_WIDTH-1:0] dnrtry_pstate_g;
|
411 |
|
|
wire [`WSR_PSTATE_VR_WIDTH-1:0] dnrtry_pstate_w2;
|
412 |
|
|
// removed for timing
|
413 |
|
|
// wire [`WSR_PSTATE_VR_WIDTH-1:0] wsr_data_pstate_g;
|
414 |
|
|
wire [`WSR_PSTATE_VR_WIDTH-1:0] wsr_data_pstate_w2;
|
415 |
|
|
//
|
416 |
|
|
// modified for bug 1767
|
417 |
|
|
//wire [`PSTATE_TRUE_WIDTH-1:0] ntrap_pstate;
|
418 |
|
|
// wire [`PSTATE_TRUE_WIDTH-1:0] ntrap_pstate0;
|
419 |
|
|
// wire [`PSTATE_TRUE_WIDTH-1:0] ntrap_pstate1;
|
420 |
|
|
// wire [`PSTATE_TRUE_WIDTH-1:0] ntrap_pstate2;
|
421 |
|
|
// wire [`PSTATE_TRUE_WIDTH-1:0] ntrap_pstate3;
|
422 |
|
|
wire [`WSR_PSTATE_VR_WIDTH-1:0] ntrap_pstate0;
|
423 |
|
|
wire [`WSR_PSTATE_VR_WIDTH-1:0] ntrap_pstate1;
|
424 |
|
|
wire [`WSR_PSTATE_VR_WIDTH-1:0] ntrap_pstate2;
|
425 |
|
|
wire [`WSR_PSTATE_VR_WIDTH-1:0] ntrap_pstate3;
|
426 |
|
|
// modified for bug 2161 and 2584
|
427 |
|
|
wire pstate_priv_set, hpstate_priv_set;
|
428 |
|
|
wire [`TLU_THRD_NUM-1:0] pstate_priv_thrd_set;
|
429 |
|
|
// wire [`TLU_THRD_NUM-1:0] pstate_priv_update_g;
|
430 |
|
|
wire [`TLU_THRD_NUM-1:0] pstate_priv_update_w2;
|
431 |
|
|
// wire [`TLU_THRD_NUM-1:0] hpstate_dnrtry_priv_g;
|
432 |
|
|
wire [`TLU_THRD_NUM-1:0] hpstate_dnrtry_priv_w2;
|
433 |
|
|
wire [`TLU_THRD_NUM-1:0] hpstate_enb_set;
|
434 |
|
|
wire [`TLU_THRD_NUM-1:0] hpstate_ibe_set;
|
435 |
|
|
wire [`TLU_THRD_NUM-1:0] hpstate_tlz_set;
|
436 |
|
|
// wire [`TLU_THRD_NUM-1:0] hpstate_priv_update_g;
|
437 |
|
|
wire [`TLU_THRD_NUM-1:0] hpstate_priv_update_w2;
|
438 |
|
|
//
|
439 |
|
|
// removed for bug 2588
|
440 |
|
|
// wire [1:0] tlu_select_mmodel0;
|
441 |
|
|
// wire [1:0] tlu_select_mmodel1;
|
442 |
|
|
// wire [1:0] tlu_select_mmodel2;
|
443 |
|
|
// wire [1:0] tlu_select_mmodel3;
|
444 |
|
|
wire [`TLU_THRD_NUM-1:0] tlu_select_tle;
|
445 |
|
|
wire [`TLU_THRD_NUM-1:0] tlu_select_cle;
|
446 |
|
|
// wire [1:0] tlu_pstate0_mmodel; // mem. model - thread0
|
447 |
|
|
// wire [1:0] tlu_pstate1_mmodel; // mem. model - thread1
|
448 |
|
|
// wire [1:0] tlu_pstate2_mmodel; // mem. model - thread2
|
449 |
|
|
// wire [1:0] tlu_pstate3_mmodel; // mem. model - thread3
|
450 |
|
|
wire [`TLU_THRD_NUM-1:0] tlu_pstate_tle; // trap little endian
|
451 |
|
|
//
|
452 |
|
|
// modified for bug 1575
|
453 |
|
|
// wire [`PSTATE_TRUE_WIDTH-1:0] restore_pstate;
|
454 |
|
|
// wire [`PSTATE_TRUE_WIDTH-1:0] restore_pstate0;
|
455 |
|
|
// wire [`PSTATE_TRUE_WIDTH-1:0] restore_pstate1;
|
456 |
|
|
// wire [`PSTATE_TRUE_WIDTH-1:0] restore_pstate2;
|
457 |
|
|
// wire [`PSTATE_TRUE_WIDTH-1:0] restore_pstate3;
|
458 |
|
|
wire [`WSR_PSTATE_VR_WIDTH-1:0] restore_pstate0;
|
459 |
|
|
wire [`WSR_PSTATE_VR_WIDTH-1:0] restore_pstate1;
|
460 |
|
|
wire [`WSR_PSTATE_VR_WIDTH-1:0] restore_pstate2;
|
461 |
|
|
wire [`WSR_PSTATE_VR_WIDTH-1:0] restore_pstate3;
|
462 |
|
|
wire [`WSR_PSTATE_VR_WIDTH-1:0] restore_pstate0_w3;
|
463 |
|
|
wire [`WSR_PSTATE_VR_WIDTH-1:0] restore_pstate1_w3;
|
464 |
|
|
wire [`WSR_PSTATE_VR_WIDTH-1:0] restore_pstate2_w3;
|
465 |
|
|
wire [`WSR_PSTATE_VR_WIDTH-1:0] restore_pstate3_w3;
|
466 |
|
|
wire tlu_pstate_nt_sel0, tlu_pstate_nt_sel1;
|
467 |
|
|
wire tlu_pstate_nt_sel2, tlu_pstate_nt_sel3;
|
468 |
|
|
wire tlu_pstate_wsr_sel0, tlu_pstate_wsr_sel1;
|
469 |
|
|
wire tlu_pstate_wsr_sel2, tlu_pstate_wsr_sel3;
|
470 |
|
|
wire hpstate_redmode;
|
471 |
|
|
wire pstate0_clk,pstate1_clk,pstate2_clk,pstate3_clk;
|
472 |
|
|
|
473 |
|
|
//
|
474 |
|
|
// added or modified for hypervisor support
|
475 |
|
|
// wire [2:0] global_sel;
|
476 |
|
|
wire stcmp0_clk, stcmp1_clk, stcmp2_clk, stcmp3_clk;
|
477 |
|
|
wire htcmp0_clk, htcmp1_clk, htcmp2_clk, htcmp3_clk;
|
478 |
|
|
wire tlu_hpstate_hnt_sel0, tlu_hpstate_hnt_sel1;
|
479 |
|
|
wire tlu_hpstate_hnt_sel2, tlu_hpstate_hnt_sel3;
|
480 |
|
|
wire tlu_hpstate_wsr_sel0, tlu_hpstate_wsr_sel1;
|
481 |
|
|
wire tlu_hpstate_wsr_sel2, tlu_hpstate_wsr_sel3;
|
482 |
|
|
wire pc_bit15_sel;
|
483 |
|
|
wire htba0_clk,htba1_clk,htba2_clk,htba3_clk;
|
484 |
|
|
wire hpstate0_clk,hpstate1_clk,hpstate2_clk,hpstate3_clk;
|
485 |
|
|
wire hintp0_clk,hintp1_clk,hintp2_clk,hintp3_clk;
|
486 |
|
|
wire hintp_rdata;
|
487 |
|
|
wire [`TLU_THRD_NUM-1:0] hintp_din;
|
488 |
|
|
// added or modified due to stickcmp clean-up
|
489 |
|
|
// wire [`TLU_ASR_DATA_WIDTH-2:0] stickcmp_rdata;
|
490 |
|
|
// wire [`TLU_ASR_DATA_WIDTH-2:0] true_stickcmp0, true_stickcmp1;
|
491 |
|
|
// wire [`TLU_ASR_DATA_WIDTH-2:0] true_stickcmp2, true_stickcmp3;
|
492 |
|
|
wire [`TLU_ASR_DATA_WIDTH-1:0] stickcmp_rdata;
|
493 |
|
|
wire [`TLU_ASR_DATA_WIDTH-1:0] true_stickcmp0, true_stickcmp1;
|
494 |
|
|
wire [`TLU_ASR_DATA_WIDTH-1:0] true_stickcmp2, true_stickcmp3;
|
495 |
|
|
wire [`TLU_THRD_NUM-1:0] stickcmp_intdis_din;
|
496 |
|
|
wire [`TLU_THRD_NUM-1:0] stickcmp_intdis_en;
|
497 |
|
|
wire [`TLU_THRD_NUM-1:0] stickcmp_int;
|
498 |
|
|
wire stick_match;
|
499 |
|
|
wire [`TLU_ASR_DATA_WIDTH-4:0] stickcmp_data;
|
500 |
|
|
//
|
501 |
|
|
wire [`TLU_ASR_DATA_WIDTH-2:0] htickcmp_rdata;
|
502 |
|
|
wire [`TLU_ASR_DATA_WIDTH-4:0] htickcmp_data;
|
503 |
|
|
wire [`TLU_ASR_DATA_WIDTH-2:0] true_htickcmp0, true_htickcmp1;
|
504 |
|
|
wire [`TLU_ASR_DATA_WIDTH-2:0] true_htickcmp2, true_htickcmp3;
|
505 |
|
|
wire [`TLU_HPSTATE_WIDTH-1:0] true_hpstate0,true_hpstate1;
|
506 |
|
|
wire [`TLU_HPSTATE_WIDTH-1:0] true_hpstate2,true_hpstate3;
|
507 |
|
|
wire [`TLU_HPSTATE_WIDTH-1:0] true_hpstate;
|
508 |
|
|
wire [`TSA_HTSTATE_WIDTH-1:0] tsa_dnrtry_hpstate_m;
|
509 |
|
|
wire [`TSA_HTSTATE_WIDTH-1:0] tsa_dnrtry_hpstate_g;
|
510 |
|
|
wire [`TSA_HTSTATE_WIDTH-1:0] tsa_dnrtry_hpstate_w2;
|
511 |
|
|
// wire [`TLU_HPSTATE_WIDTH-1:0] dnrtry_hpstate0_g, dnrtry_hpstate1_g;
|
512 |
|
|
wire [`TLU_HPSTATE_WIDTH-1:0] dnrtry_hpstate0_w2, dnrtry_hpstate1_w2;
|
513 |
|
|
// wire [`TLU_HPSTATE_WIDTH-1:0] dnrtry_hpstate2_g, dnrtry_hpstate3_g;
|
514 |
|
|
wire [`TLU_HPSTATE_WIDTH-1:0] dnrtry_hpstate2_w2, dnrtry_hpstate3_w2;
|
515 |
|
|
// wire [`TLU_HPSTATE_WIDTH-1:0] hntrap_hpstate0_g, hntrap_hpstate1_g;
|
516 |
|
|
wire [`TLU_HPSTATE_WIDTH-1:0] hntrap_hpstate0_w2, hntrap_hpstate1_w2;
|
517 |
|
|
// wire [`TLU_HPSTATE_WIDTH-1:0] hntrap_hpstate2_g, hntrap_hpstate3_g;
|
518 |
|
|
wire [`TLU_HPSTATE_WIDTH-1:0] hntrap_hpstate2_w2, hntrap_hpstate3_w2;
|
519 |
|
|
wire [`TLU_HPSTATE_WIDTH-1:0] wsr_data_hpstate_w2;
|
520 |
|
|
wire [`TLU_HPSTATE_WIDTH-1:0] restore_hpstate0, restore_hpstate1;
|
521 |
|
|
wire [`TLU_HPSTATE_WIDTH-1:0] restore_hpstate2, restore_hpstate3;
|
522 |
|
|
wire [`TLU_HTBA_WIDTH-1:0] true_htba0, true_htba1;
|
523 |
|
|
wire [`TLU_HTBA_WIDTH-1:0] true_htba2, true_htba3;
|
524 |
|
|
wire [`TSA_GLOBAL_WIDTH-1:0] dnrtry_global_m;
|
525 |
|
|
wire [`TLU_ASR_DATA_WIDTH-1:0] tlu_rdpr_mx5_out;
|
526 |
|
|
wire [`SFTINT_WIDTH-1:0] tlu_rdpr_mx6_out;
|
527 |
|
|
wire [`TLU_ASR_DATA_WIDTH-1:0] tlu_rdpr_mx7_out;
|
528 |
|
|
wire [`TLU_ASR_DATA_WIDTH-1:0] tlu_exu_rsr_data_e;
|
529 |
|
|
wire clk;
|
530 |
|
|
//
|
531 |
|
|
//=========================================================================================
|
532 |
|
|
// create local reset
|
533 |
|
|
|
534 |
|
|
assign local_rst = tlu_rst;
|
535 |
|
|
assign se_l = ~se;
|
536 |
|
|
|
537 |
|
|
// clock rename
|
538 |
|
|
assign clk = rclk;
|
539 |
|
|
|
540 |
|
|
//=========================================================================================
|
541 |
|
|
// Design Notes :
|
542 |
|
|
// HTSTATE- 4 (ENB from HPSTATE is not saved)
|
543 |
|
|
// TPC- 47 (48-2)VA+(1)VA_HOLE
|
544 |
|
|
// TNPC- 47 (48-2)VA+(1)VA_HOLE
|
545 |
|
|
// TSTATE.GL- 2 (Only two significant bits are saved)
|
546 |
|
|
// TSTATE.CCR- 8
|
547 |
|
|
// TSTATE.ASI- 8
|
548 |
|
|
// TSTATE.PSTATE- 8 (RED, IG, MG and AG bits are not used)
|
549 |
|
|
// TSTATE.CWP- 3
|
550 |
|
|
// TRAPTYPE- 9
|
551 |
|
|
//========================================================
|
552 |
|
|
// Total 136
|
553 |
|
|
|
554 |
|
|
//=========================================================================================
|
555 |
|
|
// Timing Diagram
|
556 |
|
|
//=========================================================================================
|
557 |
|
|
|
558 |
|
|
|
559 |
|
|
// WRITE TO TSA and other trap related registers.
|
560 |
|
|
// | | | | |
|
561 |
|
|
// |E |M | W | W2 | Integer
|
562 |
|
|
// | | | exceptions | push tsa |
|
563 |
|
|
// | | | reported | xmit pc |
|
564 |
|
|
// | | | | |
|
565 |
|
|
// |E |M | G | W2 | Long-Latency
|
566 |
|
|
// | | | exceptions | |
|
567 |
|
|
// | | | reported | push tsa |
|
568 |
|
|
// | | | | xmit pc |
|
569 |
|
|
|
570 |
|
|
//=========================================================================================
|
571 |
|
|
// Generate TSA Control and Data
|
572 |
|
|
//=========================================================================================
|
573 |
|
|
|
574 |
|
|
// modified for bug 3017
|
575 |
|
|
assign trap_pc0[48:2] = true_pc0[48:2];
|
576 |
|
|
assign trap_pc1[48:2] = true_pc1[48:2];
|
577 |
|
|
assign trap_pc2[48:2] = true_pc2[48:2];
|
578 |
|
|
assign trap_pc3[48:2] = true_pc3[48:2];
|
579 |
|
|
|
580 |
|
|
assign trap_npc0[48:2] = true_npc0[48:2];
|
581 |
|
|
assign trap_npc1[48:2] = true_npc1[48:2];
|
582 |
|
|
assign trap_npc2[48:2] = true_npc2[48:2];
|
583 |
|
|
assign trap_npc3[48:2] = true_npc3[48:2];
|
584 |
|
|
|
585 |
|
|
assign trap_ccr0[7:0] = exu_tlu_ccr0_w[7:0];
|
586 |
|
|
assign trap_ccr1[7:0] = exu_tlu_ccr1_w[7:0];
|
587 |
|
|
assign trap_ccr2[7:0] = exu_tlu_ccr2_w[7:0];
|
588 |
|
|
assign trap_ccr3[7:0] = exu_tlu_ccr3_w[7:0];
|
589 |
|
|
|
590 |
|
|
// assign trap_cwp0[2:0] = exu_tlu_cwp0_w[2:0];
|
591 |
|
|
// assign trap_cwp1[2:0] = exu_tlu_cwp1_w[2:0];
|
592 |
|
|
// assign trap_cwp2[2:0] = exu_tlu_cwp2_w[2:0];
|
593 |
|
|
// assign trap_cwp3[2:0] = exu_tlu_cwp3_w[2:0];
|
594 |
|
|
//
|
595 |
|
|
// added for bug 3695
|
596 |
|
|
dff_s #(3) dff_tlu_cwp0 (
|
597 |
|
|
.din (exu_tlu_cwp0[2:0]),
|
598 |
|
|
.q (tlu_cwp0[2:0]),
|
599 |
|
|
.clk (clk),
|
600 |
|
|
.se (se),
|
601 |
|
|
.si (),
|
602 |
|
|
.so ()
|
603 |
|
|
);
|
604 |
|
|
|
605 |
|
|
dff_s #(3) dff_tlu_cwp1 (
|
606 |
|
|
.din (exu_tlu_cwp1[2:0]),
|
607 |
|
|
.q (tlu_cwp1[2:0]),
|
608 |
|
|
.clk (clk),
|
609 |
|
|
.se (se),
|
610 |
|
|
.si (),
|
611 |
|
|
.so ()
|
612 |
|
|
);
|
613 |
|
|
|
614 |
|
|
dff_s #(3) dff_tlu_cwp2 (
|
615 |
|
|
.din (exu_tlu_cwp2[2:0]),
|
616 |
|
|
.q (tlu_cwp2[2:0]),
|
617 |
|
|
.clk (clk),
|
618 |
|
|
.se (se),
|
619 |
|
|
.si (),
|
620 |
|
|
.so ()
|
621 |
|
|
);
|
622 |
|
|
|
623 |
|
|
dff_s #(3) dff_tlu_cwp3 (
|
624 |
|
|
.din (exu_tlu_cwp3[2:0]),
|
625 |
|
|
.q (tlu_cwp3[2:0]),
|
626 |
|
|
.clk (clk),
|
627 |
|
|
.se (se),
|
628 |
|
|
.si (),
|
629 |
|
|
.so ()
|
630 |
|
|
);
|
631 |
|
|
//
|
632 |
|
|
// modified for bug 3499 and 3695
|
633 |
|
|
dffe_s #(3) dffe_trap_cwp0 (
|
634 |
|
|
// .din (exu_tlu_cwp0[2:0]),
|
635 |
|
|
.din (tlu_cwp0[2:0]),
|
636 |
|
|
.q (trap_cwp0[2:0]),
|
637 |
|
|
.en (tlu_trap_cwp_en[0]),
|
638 |
|
|
.clk (clk),
|
639 |
|
|
.se (se),
|
640 |
|
|
.si (),
|
641 |
|
|
.so ()
|
642 |
|
|
);
|
643 |
|
|
|
644 |
|
|
dffe_s #(3) dffe_trap_cwp1 (
|
645 |
|
|
// .din (exu_tlu_cwp1[2:0]),
|
646 |
|
|
.din (tlu_cwp1[2:0]),
|
647 |
|
|
.q (trap_cwp1[2:0]),
|
648 |
|
|
.en (tlu_trap_cwp_en[1]),
|
649 |
|
|
.clk (clk),
|
650 |
|
|
.se (se),
|
651 |
|
|
.si (),
|
652 |
|
|
.so ()
|
653 |
|
|
);
|
654 |
|
|
|
655 |
|
|
dffe_s #(3) dffe_trap_cwp2 (
|
656 |
|
|
// .din (exu_tlu_cwp2[2:0]),
|
657 |
|
|
.din (tlu_cwp2[2:0]),
|
658 |
|
|
.q (trap_cwp2[2:0]),
|
659 |
|
|
.en (tlu_trap_cwp_en[2]),
|
660 |
|
|
.clk (clk),
|
661 |
|
|
.se (se),
|
662 |
|
|
.si (),
|
663 |
|
|
.so ()
|
664 |
|
|
);
|
665 |
|
|
|
666 |
|
|
dffe_s #(3) dffe_trap_cwp3 (
|
667 |
|
|
// .din (exu_tlu_cwp3[2:0]),
|
668 |
|
|
.din (tlu_cwp3[2:0]),
|
669 |
|
|
.q (trap_cwp3[2:0]),
|
670 |
|
|
.en (tlu_trap_cwp_en[3]),
|
671 |
|
|
.clk (clk),
|
672 |
|
|
.se (se),
|
673 |
|
|
.si (),
|
674 |
|
|
.so ()
|
675 |
|
|
);
|
676 |
|
|
|
677 |
|
|
assign trap_asi0[7:0] = lsu_asi_reg0[7:0];
|
678 |
|
|
assign trap_asi1[7:0] = lsu_asi_reg1[7:0];
|
679 |
|
|
assign trap_asi2[7:0] = lsu_asi_reg2[7:0];
|
680 |
|
|
assign trap_asi3[7:0] = lsu_asi_reg3[7:0];
|
681 |
|
|
//
|
682 |
|
|
// staging the immediate asi
|
683 |
|
|
|
684 |
|
|
dff_s #(`TLU_ASI_STATE_WIDTH) dff_imm_asi_e (
|
685 |
|
|
.din (ifu_lsu_imm_asi_d[`TLU_ASI_STATE_WIDTH-1:0]),
|
686 |
|
|
.q (imm_asi_e[`TLU_ASI_STATE_WIDTH-1:0]),
|
687 |
|
|
.clk (clk),
|
688 |
|
|
.se (se),
|
689 |
|
|
.si (),
|
690 |
|
|
.so ()
|
691 |
|
|
);
|
692 |
|
|
|
693 |
|
|
dffr_s dffr_imm_asi_vld_e (
|
694 |
|
|
.din (ifu_lsu_imm_asi_vld_d),
|
695 |
|
|
.q (imm_asi_vld_e),
|
696 |
|
|
.clk (clk),
|
697 |
|
|
.rst (local_rst),
|
698 |
|
|
.se (se),
|
699 |
|
|
.si (),
|
700 |
|
|
.so ()
|
701 |
|
|
);
|
702 |
|
|
//
|
703 |
|
|
// generating the current asi state
|
704 |
|
|
mux4ds #(`TLU_ASI_STATE_WIDTH) mx_tlu_asi_state_e (
|
705 |
|
|
.in0 (lsu_asi_reg0[`TLU_ASI_STATE_WIDTH-1:0]),
|
706 |
|
|
.in1 (lsu_asi_reg1[`TLU_ASI_STATE_WIDTH-1:0]),
|
707 |
|
|
.in2 (lsu_asi_reg2[`TLU_ASI_STATE_WIDTH-1:0]),
|
708 |
|
|
.in3 (lsu_asi_reg3[`TLU_ASI_STATE_WIDTH-1:0]),
|
709 |
|
|
.sel0 (tlu_thrd_rsel_e[0]),
|
710 |
|
|
.sel1 (tlu_thrd_rsel_e[1]),
|
711 |
|
|
.sel2 (tlu_thrd_rsel_e[2]),
|
712 |
|
|
.sel3 (tlu_thrd_rsel_e[3]),
|
713 |
|
|
// modified due to bug 2442
|
714 |
|
|
// .dout (tlu_asi_state_e[`TLU_ASI_STATE_WIDTH-1:0])
|
715 |
|
|
.dout (asi_state_reg_e[`TLU_ASI_STATE_WIDTH-1:0])
|
716 |
|
|
);
|
717 |
|
|
//
|
718 |
|
|
// added for bug 2442
|
719 |
|
|
// generating the current asi state
|
720 |
|
|
mux2ds #(`TLU_ASI_STATE_WIDTH) mx_asi_state_final_e (
|
721 |
|
|
.in0 (imm_asi_e[`TLU_ASI_STATE_WIDTH-1:0]),
|
722 |
|
|
.in1 (asi_state_reg_e[`TLU_ASI_STATE_WIDTH-1:0]),
|
723 |
|
|
.sel0 (imm_asi_vld_e),
|
724 |
|
|
.sel1 (~imm_asi_vld_e),
|
725 |
|
|
.dout (asi_state_final_e[`TLU_ASI_STATE_WIDTH-1:0])
|
726 |
|
|
);
|
727 |
|
|
|
728 |
|
|
assign tlu_asi_state_e[`TLU_ASI_STATE_WIDTH-1:0] =
|
729 |
|
|
asi_state_final_e[`TLU_ASI_STATE_WIDTH-1:0];
|
730 |
|
|
//
|
731 |
|
|
// thread 0
|
732 |
|
|
assign trap_pstate0 = {
|
733 |
|
|
true_pstate0[`PSTATE_VRANGE2_HI:`PSTATE_VRANGE2_LO],
|
734 |
|
|
2'b0, true_pstate0[`PSTATE_VRANGE1_HI:`PSTATE_VRANGE1_LO]};
|
735 |
|
|
//
|
736 |
|
|
// modified due to hpstate.ibe addition
|
737 |
|
|
assign trap0_tsa_wdata[`TLU_HTSTATE_HI:`TLU_HTSTATE_LO] =
|
738 |
|
|
{true_hpstate0[`TLU_HPSTATE_WIDTH-1],
|
739 |
|
|
true_hpstate0[`TSA_HTSTATE_WIDTH-2:0]};
|
740 |
|
|
//
|
741 |
|
|
// modified for bug 3017
|
742 |
|
|
//
|
743 |
|
|
assign trap0_tsa_wdata[`TLU_PC_HI:`TLU_PC_LO] =
|
744 |
|
|
trap_pc0[48:2];
|
745 |
|
|
//
|
746 |
|
|
assign trap0_tsa_wdata[`TLU_NPC_HI:`TLU_NPC_LO] =
|
747 |
|
|
trap_npc0[48:2];
|
748 |
|
|
//
|
749 |
|
|
assign trap0_tsa_wdata[`TLU_GL_HI:`TLU_GL_LO] =
|
750 |
|
|
tlu_gl_lvl0[`TSA_GLOBAL_WIDTH-1:0];
|
751 |
|
|
//
|
752 |
|
|
assign trap0_tsa_wdata[`TLU_CCR_HI:`TLU_CCR_LO] =
|
753 |
|
|
trap_ccr0[`TSA_CCR_WIDTH-1:0];
|
754 |
|
|
//
|
755 |
|
|
assign trap0_tsa_wdata[`TLU_ASI_HI:`TLU_ASI_LO] =
|
756 |
|
|
trap_asi0[`TSA_ASI_WIDTH-1:0];
|
757 |
|
|
//
|
758 |
|
|
assign trap0_tsa_wdata[`TLU_PSTATE_HI:`TLU_PSTATE_LO] =
|
759 |
|
|
trap_pstate0[`TSA_PSTATE_WIDTH-1:0];
|
760 |
|
|
//
|
761 |
|
|
assign trap0_tsa_wdata[`TLU_CWP_HI:`TLU_CWP_LO] =
|
762 |
|
|
trap_cwp0[`TSA_CWP_WIDTH-1:0];
|
763 |
|
|
//
|
764 |
|
|
assign trap0_tsa_wdata[`TLU_TT_HI:`TLU_TT_LO] =
|
765 |
|
|
tlu_final_ttype_w2[`TSA_TTYPE_WIDTH-1:0];
|
766 |
|
|
//
|
767 |
|
|
// thread 1
|
768 |
|
|
assign trap_pstate1 = {
|
769 |
|
|
true_pstate1[`PSTATE_VRANGE2_HI:`PSTATE_VRANGE2_LO],
|
770 |
|
|
2'b0, true_pstate1[`PSTATE_VRANGE1_HI:`PSTATE_VRANGE1_LO]};
|
771 |
|
|
//
|
772 |
|
|
// modified due to hpstate.ibe addition
|
773 |
|
|
assign trap1_tsa_wdata[`TLU_HTSTATE_HI:`TLU_HTSTATE_LO] =
|
774 |
|
|
{true_hpstate1[`TLU_HPSTATE_WIDTH-1],
|
775 |
|
|
true_hpstate1[`TSA_HTSTATE_WIDTH-2:0]};
|
776 |
|
|
//
|
777 |
|
|
assign trap1_tsa_wdata[`TLU_PC_HI:`TLU_PC_LO] =
|
778 |
|
|
trap_pc1[48:2];
|
779 |
|
|
//
|
780 |
|
|
assign trap1_tsa_wdata[`TLU_NPC_HI:`TLU_NPC_LO] =
|
781 |
|
|
trap_npc1[48:2];
|
782 |
|
|
//
|
783 |
|
|
assign trap1_tsa_wdata[`TLU_GL_HI:`TLU_GL_LO] =
|
784 |
|
|
tlu_gl_lvl1[`TSA_GLOBAL_WIDTH-1:0];
|
785 |
|
|
//
|
786 |
|
|
assign trap1_tsa_wdata[`TLU_CCR_HI:`TLU_CCR_LO] =
|
787 |
|
|
trap_ccr1[`TSA_CCR_WIDTH-1:0];
|
788 |
|
|
//
|
789 |
|
|
assign trap1_tsa_wdata[`TLU_ASI_HI:`TLU_ASI_LO] =
|
790 |
|
|
trap_asi1[`TSA_ASI_WIDTH-1:0];
|
791 |
|
|
//
|
792 |
|
|
assign trap1_tsa_wdata[`TLU_PSTATE_HI:`TLU_PSTATE_LO] =
|
793 |
|
|
trap_pstate1[`TSA_PSTATE_WIDTH-1:0];
|
794 |
|
|
//
|
795 |
|
|
assign trap1_tsa_wdata[`TLU_CWP_HI:`TLU_CWP_LO] =
|
796 |
|
|
trap_cwp1[`TSA_CWP_WIDTH-1:0];
|
797 |
|
|
//
|
798 |
|
|
assign trap1_tsa_wdata[`TLU_TT_HI:`TLU_TT_LO] =
|
799 |
|
|
tlu_final_ttype_w2[`TSA_TTYPE_WIDTH-1:0];
|
800 |
|
|
//
|
801 |
|
|
// thread 2
|
802 |
|
|
assign trap_pstate2 = {
|
803 |
|
|
true_pstate2[`PSTATE_VRANGE2_HI:`PSTATE_VRANGE2_LO],
|
804 |
|
|
2'b0, true_pstate2[`PSTATE_VRANGE1_HI:`PSTATE_VRANGE1_LO]};
|
805 |
|
|
//
|
806 |
|
|
// modified due to hpstate.ibe addition
|
807 |
|
|
assign trap2_tsa_wdata[`TLU_HTSTATE_HI:`TLU_HTSTATE_LO] =
|
808 |
|
|
{true_hpstate2[`TLU_HPSTATE_WIDTH-1],
|
809 |
|
|
true_hpstate2[`TSA_HTSTATE_WIDTH-2:0]};
|
810 |
|
|
//
|
811 |
|
|
assign trap2_tsa_wdata[`TLU_PC_HI:`TLU_PC_LO] =
|
812 |
|
|
trap_pc2[48:2];
|
813 |
|
|
//
|
814 |
|
|
assign trap2_tsa_wdata[`TLU_NPC_HI:`TLU_NPC_LO] =
|
815 |
|
|
trap_npc2[48:2];
|
816 |
|
|
//
|
817 |
|
|
assign trap2_tsa_wdata[`TLU_GL_HI:`TLU_GL_LO] =
|
818 |
|
|
tlu_gl_lvl2[`TSA_GLOBAL_WIDTH-1:0];
|
819 |
|
|
//
|
820 |
|
|
assign trap2_tsa_wdata[`TLU_CCR_HI:`TLU_CCR_LO] =
|
821 |
|
|
trap_ccr2[`TSA_CCR_WIDTH-1:0];
|
822 |
|
|
//
|
823 |
|
|
assign trap2_tsa_wdata[`TLU_ASI_HI:`TLU_ASI_LO] =
|
824 |
|
|
trap_asi2[`TSA_ASI_WIDTH-1:0];
|
825 |
|
|
//
|
826 |
|
|
assign trap2_tsa_wdata[`TLU_PSTATE_HI:`TLU_PSTATE_LO] =
|
827 |
|
|
trap_pstate2[`TSA_PSTATE_WIDTH-1:0];
|
828 |
|
|
//
|
829 |
|
|
assign trap2_tsa_wdata[`TLU_CWP_HI:`TLU_CWP_LO] =
|
830 |
|
|
trap_cwp2[`TSA_CWP_WIDTH-1:0];
|
831 |
|
|
//
|
832 |
|
|
assign trap2_tsa_wdata[`TLU_TT_HI:`TLU_TT_LO] =
|
833 |
|
|
tlu_final_ttype_w2[`TSA_TTYPE_WIDTH-1:0];
|
834 |
|
|
//
|
835 |
|
|
// thread 3
|
836 |
|
|
assign trap_pstate3 = {
|
837 |
|
|
true_pstate3[`PSTATE_VRANGE2_HI:`PSTATE_VRANGE2_LO],
|
838 |
|
|
2'b0, true_pstate3[`PSTATE_VRANGE1_HI:`PSTATE_VRANGE1_LO]};
|
839 |
|
|
//
|
840 |
|
|
// modified due to hpstate.ibe addition
|
841 |
|
|
assign trap3_tsa_wdata[`TLU_HTSTATE_HI:`TLU_HTSTATE_LO] =
|
842 |
|
|
{true_hpstate3[`TLU_HPSTATE_WIDTH-1],
|
843 |
|
|
true_hpstate3[`TSA_HTSTATE_WIDTH-2:0]};
|
844 |
|
|
//
|
845 |
|
|
assign trap3_tsa_wdata[`TLU_PC_HI:`TLU_PC_LO] =
|
846 |
|
|
trap_pc3[48:2];
|
847 |
|
|
//
|
848 |
|
|
assign trap3_tsa_wdata[`TLU_NPC_HI:`TLU_NPC_LO] =
|
849 |
|
|
trap_npc3[48:2];
|
850 |
|
|
//
|
851 |
|
|
assign trap3_tsa_wdata[`TLU_GL_HI:`TLU_GL_LO] =
|
852 |
|
|
tlu_gl_lvl3[`TSA_GLOBAL_WIDTH-1:0];
|
853 |
|
|
//
|
854 |
|
|
assign trap3_tsa_wdata[`TLU_CCR_HI:`TLU_CCR_LO] =
|
855 |
|
|
trap_ccr3[`TSA_CCR_WIDTH-1:0];
|
856 |
|
|
//
|
857 |
|
|
assign trap3_tsa_wdata[`TLU_ASI_HI:`TLU_ASI_LO] =
|
858 |
|
|
trap_asi3[`TSA_ASI_WIDTH-1:0];
|
859 |
|
|
//
|
860 |
|
|
assign trap3_tsa_wdata[`TLU_PSTATE_HI:`TLU_PSTATE_LO] =
|
861 |
|
|
trap_pstate3[`TSA_PSTATE_WIDTH-1:0];
|
862 |
|
|
//
|
863 |
|
|
assign trap3_tsa_wdata[`TLU_CWP_HI:`TLU_CWP_LO] =
|
864 |
|
|
trap_cwp3[`TSA_CWP_WIDTH-1:0];
|
865 |
|
|
//
|
866 |
|
|
assign trap3_tsa_wdata[`TLU_TT_HI:`TLU_TT_LO] =
|
867 |
|
|
tlu_final_ttype_w2[`TSA_TTYPE_WIDTH-1:0];
|
868 |
|
|
//
|
869 |
|
|
// modified for timing: tlu_thrd_wsel_g -> tlu_thrd_wsel_w2
|
870 |
|
|
`ifdef FPGA_SYN_1THREAD
|
871 |
|
|
assign trap_tsa_wdata[`TLU_TSA_WIDTH-1:0] = trap0_tsa_wdata[`TLU_TSA_WIDTH-1:0];
|
872 |
|
|
`else
|
873 |
|
|
|
874 |
|
|
mux4ds #(`TLU_TSA_WIDTH) tsawdsel (
|
875 |
|
|
.in0 (trap0_tsa_wdata[`TLU_TSA_WIDTH-1:0]),
|
876 |
|
|
.in1 (trap1_tsa_wdata[`TLU_TSA_WIDTH-1:0]),
|
877 |
|
|
.in2 (trap2_tsa_wdata[`TLU_TSA_WIDTH-1:0]),
|
878 |
|
|
.in3 (trap3_tsa_wdata[`TLU_TSA_WIDTH-1:0]),
|
879 |
|
|
.sel0 (tlu_thrd_wsel_w2[0]),
|
880 |
|
|
.sel1 (tlu_thrd_wsel_w2[1]),
|
881 |
|
|
.sel2 (tlu_thrd_wsel_w2[2]),
|
882 |
|
|
.sel3 (tlu_thrd_wsel_w2[3]),
|
883 |
|
|
.dout (trap_tsa_wdata[`TLU_TSA_WIDTH-1:0])
|
884 |
|
|
);
|
885 |
|
|
`endif // !`ifdef FPGA_SYN_1THREAD
|
886 |
|
|
|
887 |
|
|
//
|
888 |
|
|
// modified for timing and lint violations
|
889 |
|
|
// assign wsr_data_w[`TLU_ASR_DATA_WIDTH-1:0] =
|
890 |
|
|
// tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-1:0];
|
891 |
|
|
assign wsr_data_w[`SFTINT_WIDTH-1:0] =
|
892 |
|
|
tlu_wsr_data_w[`SFTINT_WIDTH-1:0];
|
893 |
|
|
//
|
894 |
|
|
// added for timing
|
895 |
|
|
// reduced width to 48 due to lint violations
|
896 |
|
|
dff_s #(48) dff_wsr_data_w2 (
|
897 |
|
|
.din (tlu_wsr_data_w[47:0]),
|
898 |
|
|
.q (wsr_data_w2[47:0]),
|
899 |
|
|
.clk (clk),
|
900 |
|
|
.se (se),
|
901 |
|
|
.si (),
|
902 |
|
|
.so ()
|
903 |
|
|
);
|
904 |
|
|
//
|
905 |
|
|
// extracting the relevant data for tstate from the WSR to be written
|
906 |
|
|
// modified due to timing changes
|
907 |
|
|
assign compose_tstate[`WSR_TSTATE_WIDTH-1:0] =
|
908 |
|
|
{wsr_data_w2[`WSR_TSTATE_GL_HI:`WSR_TSTATE_GL_LO],
|
909 |
|
|
wsr_data_w2[`WSR_TSTATE_CCR_HI:`WSR_TSTATE_CCR_LO],
|
910 |
|
|
wsr_data_w2[`WSR_TSTATE_ASI_HI:`WSR_TSTATE_ASI_LO],
|
911 |
|
|
wsr_data_w2[`WSR_TSTATE_PS2_HI:`WSR_TSTATE_PS2_LO],
|
912 |
|
|
2'b0,
|
913 |
|
|
wsr_data_w2[`WSR_TSTATE_PS1_HI:`WSR_TSTATE_PS1_LO],
|
914 |
|
|
wsr_data_w2[`WSR_TSTATE_CWP_HI:`WSR_TSTATE_CWP_LO]};
|
915 |
|
|
//
|
916 |
|
|
// extracting the relevant data from hstate from the WSR to be written
|
917 |
|
|
assign compose_htstate[`TSA_HTSTATE_WIDTH-1:0] =
|
918 |
|
|
{wsr_data_w2[`WSR_HPSTATE_IBE],
|
919 |
|
|
wsr_data_w2[`WSR_HPSTATE_RED],
|
920 |
|
|
wsr_data_w2[`WSR_HPSTATE_PRIV],
|
921 |
|
|
wsr_data_w2[`WSR_HPSTATE_TLZ]};
|
922 |
|
|
|
923 |
|
|
// htstate
|
924 |
|
|
assign wrpr_tsa_wdata[`TLU_HTSTATE_HI:`TLU_HTSTATE_LO]=
|
925 |
|
|
compose_htstate[`TSA_HTSTATE_WIDTH-1:0];
|
926 |
|
|
//
|
927 |
|
|
// modified for bug 3017
|
928 |
|
|
// pc
|
929 |
|
|
assign wrpr_tsa_wdata[`TLU_PC_HI:`TLU_PC_LO]=
|
930 |
|
|
{1'b0, wsr_data_w2[47:2]};
|
931 |
|
|
// npc
|
932 |
|
|
assign wrpr_tsa_wdata[`TLU_NPC_HI:`TLU_NPC_LO]=
|
933 |
|
|
{1'b0, wsr_data_w2[47:2]};
|
934 |
|
|
// tstate data
|
935 |
|
|
assign wrpr_tsa_wdata[`TLU_GL_HI:`TLU_CWP_LO]=
|
936 |
|
|
compose_tstate[`WSR_TSTATE_WIDTH-1:0];
|
937 |
|
|
// ttype data
|
938 |
|
|
assign wrpr_tsa_wdata[`TLU_TT_HI:`TLU_TT_LO]=
|
939 |
|
|
wsr_data_w2[`TSA_TTYPE_WIDTH-1:0];
|
940 |
|
|
|
941 |
|
|
mux2ds #(`TLU_TSA_WIDTH) tsawdata_sel (
|
942 |
|
|
.in0 ({trap_tsa_wdata[`TLU_TSA_WIDTH-1:0]}),
|
943 |
|
|
.in1 ({wrpr_tsa_wdata[`TLU_TSA_WIDTH-1:0]}),
|
944 |
|
|
.sel0 (~tlu_wr_tsa_inst_w2),
|
945 |
|
|
.sel1 (tlu_wr_tsa_inst_w2),
|
946 |
|
|
.dout ({tsa_wdata[`TLU_TSA_WIDTH-1:0]})
|
947 |
|
|
);
|
948 |
|
|
|
949 |
|
|
//=========================================================================================
|
950 |
|
|
// SOFT INTERRUPT for Threads
|
951 |
|
|
//=========================================================================================
|
952 |
|
|
|
953 |
|
|
// Assumption is that softint state is unknown after reset.
|
954 |
|
|
// TICK_INT will be maintained separately. What is the relative order of
|
955 |
|
|
// setting and clearing this bit ? What takes precedence ?
|
956 |
|
|
//
|
957 |
|
|
// modified for bug 2204
|
958 |
|
|
// recoded due to one-hot problem during reset
|
959 |
|
|
|
960 |
|
|
`ifdef FPGA_SYN_1THREAD
|
961 |
|
|
assign sftint[`SFTINT_WIDTH-1:0] = sftint0[`SFTINT_WIDTH-1:0];
|
962 |
|
|
`else
|
963 |
|
|
|
964 |
|
|
mux4ds #(`SFTINT_WIDTH) mx_sftint (
|
965 |
|
|
.in0 (sftint0[`SFTINT_WIDTH-1:0]),
|
966 |
|
|
.in1 (sftint1[`SFTINT_WIDTH-1:0]),
|
967 |
|
|
.in2 (sftint2[`SFTINT_WIDTH-1:0]),
|
968 |
|
|
.in3 (sftint3[`SFTINT_WIDTH-1:0]),
|
969 |
|
|
.sel0 (tlu_sftint_mx_sel[0]),
|
970 |
|
|
.sel1 (tlu_sftint_mx_sel[1]),
|
971 |
|
|
.sel2 (tlu_sftint_mx_sel[2]),
|
972 |
|
|
.sel3 (tlu_sftint_mx_sel[3]),
|
973 |
|
|
.dout (sftint[`SFTINT_WIDTH-1:0])
|
974 |
|
|
);
|
975 |
|
|
`endif // !`ifdef FPGA_SYN_1THREAD
|
976 |
|
|
|
977 |
|
|
/*
|
978 |
|
|
assign sftint_sel_onehot_g =
|
979 |
|
|
~tlu_sftint_en_l_g[0] | (&tlu_sftint_en_l_g[3:1]);
|
980 |
|
|
|
981 |
|
|
mux4ds #(`SFTINT_WIDTH) mx_sftint (
|
982 |
|
|
.in0 (sftint0[`SFTINT_WIDTH-1:0]),
|
983 |
|
|
.in1 (sftint1[`SFTINT_WIDTH-1:0]),
|
984 |
|
|
.in2 (sftint2[`SFTINT_WIDTH-1:0]),
|
985 |
|
|
.in3 (sftint3[`SFTINT_WIDTH-1:0]),
|
986 |
|
|
.sel0 (sftint_sel_onehot_g),
|
987 |
|
|
.sel1 (~tlu_sftint_en_l_g[1]),
|
988 |
|
|
.sel2 (~tlu_sftint_en_l_g[2]),
|
989 |
|
|
.sel3 (~tlu_sftint_en_l_g[3]),
|
990 |
|
|
.dout (sftint[`SFTINT_WIDTH-1:0])
|
991 |
|
|
);
|
992 |
|
|
*/
|
993 |
|
|
|
994 |
|
|
assign sftint_set_din[`SFTINT_WIDTH-1:0] =
|
995 |
|
|
(wsr_data_w[`SFTINT_WIDTH-1:0] | sftint[`SFTINT_WIDTH-1:0]);
|
996 |
|
|
assign sftint_clr_din[`SFTINT_WIDTH-1:0] =
|
997 |
|
|
(~wsr_data_w[`SFTINT_WIDTH-1:0] & sftint[`SFTINT_WIDTH-1:0]);
|
998 |
|
|
assign sftint_wr_din[`SFTINT_WIDTH-1:0] =
|
999 |
|
|
wsr_data_w[`SFTINT_WIDTH-1:0];
|
1000 |
|
|
|
1001 |
|
|
// consturcting the mux select for the sftin_din mux
|
1002 |
|
|
|
1003 |
|
|
assign sftin_din_mxsel[0] = ~tlu_set_sftint_l_g;
|
1004 |
|
|
assign sftin_din_mxsel[1] = ~tlu_clr_sftint_l_g;
|
1005 |
|
|
assign sftin_din_mxsel[2] = ~tlu_wr_sftint_l_g;
|
1006 |
|
|
assign sftin_din_mxsel[3] =
|
1007 |
|
|
tlu_set_sftint_l_g & tlu_clr_sftint_l_g & tlu_wr_sftint_l_g;
|
1008 |
|
|
|
1009 |
|
|
mux4ds #(`SFTINT_WIDTH) mx_sftint_din (
|
1010 |
|
|
.in0 (sftint_set_din[`SFTINT_WIDTH-1:0]),
|
1011 |
|
|
.in1 (sftint_clr_din[`SFTINT_WIDTH-1:0]),
|
1012 |
|
|
.in2 (sftint_wr_din[`SFTINT_WIDTH-1:0]),
|
1013 |
|
|
.in3 (sftint[`SFTINT_WIDTH-1:0]),
|
1014 |
|
|
.sel0 (sftin_din_mxsel[0]),
|
1015 |
|
|
.sel1 (sftin_din_mxsel[1]),
|
1016 |
|
|
.sel2 (sftin_din_mxsel[2]),
|
1017 |
|
|
.sel3 (sftin_din_mxsel[3]),
|
1018 |
|
|
.dout (sftint_din[`SFTINT_WIDTH-1:0])
|
1019 |
|
|
);
|
1020 |
|
|
|
1021 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
1022 |
|
|
`else
|
1023 |
|
|
clken_buf clkbf_st0 (
|
1024 |
|
|
.rclk (clk),
|
1025 |
|
|
.enb_l (tlu_sftint_en_l_g[0]),
|
1026 |
|
|
.tmb_l (se_l),
|
1027 |
|
|
.clk (sftint0_clk)
|
1028 |
|
|
);
|
1029 |
|
|
`endif
|
1030 |
|
|
|
1031 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
1032 |
|
|
`else
|
1033 |
|
|
clken_buf clkbf_st1 (
|
1034 |
|
|
.rclk (clk),
|
1035 |
|
|
.enb_l (tlu_sftint_en_l_g[1]),
|
1036 |
|
|
.tmb_l (se_l),
|
1037 |
|
|
.clk (sftint1_clk)
|
1038 |
|
|
);
|
1039 |
|
|
`endif
|
1040 |
|
|
|
1041 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
1042 |
|
|
`else
|
1043 |
|
|
clken_buf clkbf_st2 (
|
1044 |
|
|
.rclk (clk),
|
1045 |
|
|
.enb_l (tlu_sftint_en_l_g[2]),
|
1046 |
|
|
.tmb_l (se_l),
|
1047 |
|
|
.clk (sftint2_clk)
|
1048 |
|
|
);
|
1049 |
|
|
`endif
|
1050 |
|
|
|
1051 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
1052 |
|
|
`else
|
1053 |
|
|
clken_buf clkbf_st3 (
|
1054 |
|
|
.rclk (clk),
|
1055 |
|
|
.enb_l (tlu_sftint_en_l_g[3]),
|
1056 |
|
|
.tmb_l (se_l),
|
1057 |
|
|
.clk (sftint3_clk)
|
1058 |
|
|
);
|
1059 |
|
|
`endif
|
1060 |
|
|
//
|
1061 |
|
|
// added for PIB support - modified to make inst count precise
|
1062 |
|
|
assign sftint_b15_din[0] =
|
1063 |
|
|
(pib_picl_wrap[0] | pib_pich_wrap[0] | sftint_din[15]);
|
1064 |
|
|
assign sftint_b15_din[1] =
|
1065 |
|
|
(pib_picl_wrap[1] | pib_pich_wrap[1] | sftint_din[15]);
|
1066 |
|
|
assign sftint_b15_din[2] =
|
1067 |
|
|
(pib_picl_wrap[2] | pib_pich_wrap[2] | sftint_din[15]);
|
1068 |
|
|
assign sftint_b15_din[3] =
|
1069 |
|
|
(pib_picl_wrap[3] | pib_pich_wrap[3] | sftint_din[15]);
|
1070 |
|
|
|
1071 |
|
|
assign sftint_b15_en[0] =
|
1072 |
|
|
(pib_picl_wrap[0] | pib_pich_wrap[0] | ~tlu_sftint_en_l_g[0]);
|
1073 |
|
|
assign sftint_b15_en[1] =
|
1074 |
|
|
(pib_picl_wrap[1] | pib_pich_wrap[1] | ~tlu_sftint_en_l_g[1]);
|
1075 |
|
|
assign sftint_b15_en[2] =
|
1076 |
|
|
(pib_picl_wrap[2] | pib_pich_wrap[2] | ~tlu_sftint_en_l_g[2]);
|
1077 |
|
|
assign sftint_b15_en[3] =
|
1078 |
|
|
(pib_picl_wrap[3] | pib_pich_wrap[3] | ~tlu_sftint_en_l_g[3]);
|
1079 |
|
|
//
|
1080 |
|
|
// added due to sftint spec change
|
1081 |
|
|
// tickcmp interrupts
|
1082 |
|
|
assign sftint_b0_din[0] = (tickcmp_int[0] | sftint_din[0]);
|
1083 |
|
|
assign sftint_b0_din[1] = (tickcmp_int[1] | sftint_din[0]);
|
1084 |
|
|
assign sftint_b0_din[2] = (tickcmp_int[2] | sftint_din[0]);
|
1085 |
|
|
assign sftint_b0_din[3] = (tickcmp_int[3] | sftint_din[0]);
|
1086 |
|
|
|
1087 |
|
|
assign sftint_b0_en[0] = (tickcmp_int[0] | ~tlu_sftint_en_l_g[0]);
|
1088 |
|
|
assign sftint_b0_en[1] = (tickcmp_int[1] | ~tlu_sftint_en_l_g[1]);
|
1089 |
|
|
assign sftint_b0_en[2] = (tickcmp_int[2] | ~tlu_sftint_en_l_g[2]);
|
1090 |
|
|
assign sftint_b0_en[3] = (tickcmp_int[3] | ~tlu_sftint_en_l_g[3]);
|
1091 |
|
|
//
|
1092 |
|
|
// stickcmp interrupts
|
1093 |
|
|
assign sftint_b16_din[0] = (stickcmp_int[0] | sftint_din[16]);
|
1094 |
|
|
assign sftint_b16_din[1] = (stickcmp_int[1] | sftint_din[16]);
|
1095 |
|
|
assign sftint_b16_din[2] = (stickcmp_int[2] | sftint_din[16]);
|
1096 |
|
|
assign sftint_b16_din[3] = (stickcmp_int[3] | sftint_din[16]);
|
1097 |
|
|
|
1098 |
|
|
assign sftint_b16_en[0] = (stickcmp_int[0] | ~tlu_sftint_en_l_g[0]);
|
1099 |
|
|
assign sftint_b16_en[1] = (stickcmp_int[1] | ~tlu_sftint_en_l_g[1]);
|
1100 |
|
|
assign sftint_b16_en[2] = (stickcmp_int[2] | ~tlu_sftint_en_l_g[2]);
|
1101 |
|
|
assign sftint_b16_en[3] = (stickcmp_int[3] | ~tlu_sftint_en_l_g[3]);
|
1102 |
|
|
|
1103 |
|
|
// modified for sftint spec change - special treatments for bit 0, 15 and 16
|
1104 |
|
|
//
|
1105 |
|
|
// thread 0
|
1106 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
1107 |
|
|
dffre_s #(14) dffr_sftint0 (
|
1108 |
|
|
.din (sftint_din[14:1]),
|
1109 |
|
|
.q (sftint0[14:1]),
|
1110 |
|
|
.en (~(tlu_sftint_en_l_g[0])), .clk(clk),
|
1111 |
|
|
.rst (local_rst),
|
1112 |
|
|
.se (se),
|
1113 |
|
|
.si (),
|
1114 |
|
|
.so ()
|
1115 |
|
|
);
|
1116 |
|
|
`else
|
1117 |
|
|
dffr_s #(14) dffr_sftint0 (
|
1118 |
|
|
.din (sftint_din[14:1]),
|
1119 |
|
|
.q (sftint0[14:1]),
|
1120 |
|
|
.clk (sftint0_clk),
|
1121 |
|
|
.rst (local_rst),
|
1122 |
|
|
.se (se),
|
1123 |
|
|
.si (),
|
1124 |
|
|
.so ()
|
1125 |
|
|
);
|
1126 |
|
|
`endif
|
1127 |
|
|
dffre_s dffre_sftint0_b0 (
|
1128 |
|
|
.din (sftint_b0_din[0]),
|
1129 |
|
|
.q (sftint0[`SFTINT_TICK_CMP]),
|
1130 |
|
|
.clk (clk),
|
1131 |
|
|
.rst (local_rst),
|
1132 |
|
|
.en (sftint_b0_en[0]),
|
1133 |
|
|
.se (se),
|
1134 |
|
|
.si (),
|
1135 |
|
|
.so ()
|
1136 |
|
|
);
|
1137 |
|
|
|
1138 |
|
|
dffre_s dffre_sftint0_b15 (
|
1139 |
|
|
.din (sftint_b15_din[0]),
|
1140 |
|
|
.q (sftint0[`SFTINT_PIB_WRAP]),
|
1141 |
|
|
.clk (clk),
|
1142 |
|
|
.rst (local_rst),
|
1143 |
|
|
.en (sftint_b15_en[0]),
|
1144 |
|
|
.se (se),
|
1145 |
|
|
.si (),
|
1146 |
|
|
.so ()
|
1147 |
|
|
);
|
1148 |
|
|
|
1149 |
|
|
dffre_s dffre_sftint0_b16 (
|
1150 |
|
|
.din (sftint_b16_din[0]),
|
1151 |
|
|
.q (sftint0[`SFTINT_STICK_CMP]),
|
1152 |
|
|
.clk (clk),
|
1153 |
|
|
.rst (local_rst),
|
1154 |
|
|
.en (sftint_b16_en[0]),
|
1155 |
|
|
.se (se),
|
1156 |
|
|
.si (),
|
1157 |
|
|
.so ()
|
1158 |
|
|
);
|
1159 |
|
|
//
|
1160 |
|
|
// thread 1
|
1161 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
1162 |
|
|
dffre_s #(14) sftint1ff (
|
1163 |
|
|
.din (sftint_din[14:1]),
|
1164 |
|
|
.q (sftint1[14:1]),
|
1165 |
|
|
.en (~(tlu_sftint_en_l_g[1])), .clk(clk),
|
1166 |
|
|
.rst (local_rst),
|
1167 |
|
|
.se (se),
|
1168 |
|
|
.si (),
|
1169 |
|
|
.so ()
|
1170 |
|
|
);
|
1171 |
|
|
`else
|
1172 |
|
|
dffr_s #(14) sftint1ff (
|
1173 |
|
|
.din (sftint_din[14:1]),
|
1174 |
|
|
.q (sftint1[14:1]),
|
1175 |
|
|
.clk (sftint1_clk),
|
1176 |
|
|
.rst (local_rst),
|
1177 |
|
|
.se (se),
|
1178 |
|
|
.si (),
|
1179 |
|
|
.so ()
|
1180 |
|
|
);
|
1181 |
|
|
`endif
|
1182 |
|
|
|
1183 |
|
|
dffre_s dffre_sftint1_b0 (
|
1184 |
|
|
.din (sftint_b0_din[1]),
|
1185 |
|
|
.q (sftint1[`SFTINT_TICK_CMP]),
|
1186 |
|
|
.clk (clk),
|
1187 |
|
|
.rst (local_rst),
|
1188 |
|
|
.en (sftint_b0_en[1]),
|
1189 |
|
|
.se (se),
|
1190 |
|
|
.si (),
|
1191 |
|
|
.so ()
|
1192 |
|
|
);
|
1193 |
|
|
|
1194 |
|
|
dffre_s dffre_sftint1_b15 (
|
1195 |
|
|
.din (sftint_b15_din[1]),
|
1196 |
|
|
.q (sftint1[`SFTINT_PIB_WRAP]),
|
1197 |
|
|
.clk (clk),
|
1198 |
|
|
.rst (local_rst),
|
1199 |
|
|
.en (sftint_b15_en[1]),
|
1200 |
|
|
.se (se),
|
1201 |
|
|
.si (),
|
1202 |
|
|
.so ()
|
1203 |
|
|
);
|
1204 |
|
|
|
1205 |
|
|
dffre_s dffre_sftint1_b16 (
|
1206 |
|
|
.din (sftint_b16_din[1]),
|
1207 |
|
|
.q (sftint1[`SFTINT_STICK_CMP]),
|
1208 |
|
|
.clk (clk),
|
1209 |
|
|
.rst (local_rst),
|
1210 |
|
|
.en (sftint_b16_en[1]),
|
1211 |
|
|
.se (se),
|
1212 |
|
|
.si (),
|
1213 |
|
|
.so ()
|
1214 |
|
|
);
|
1215 |
|
|
//
|
1216 |
|
|
// thread 2
|
1217 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
1218 |
|
|
dffre_s #(14) sftint2ff (
|
1219 |
|
|
.din (sftint_din[14:1]),
|
1220 |
|
|
.q (sftint2[14:1]),
|
1221 |
|
|
.en (~(tlu_sftint_en_l_g[2])), .clk(clk),
|
1222 |
|
|
.rst (local_rst),
|
1223 |
|
|
.se (se),
|
1224 |
|
|
.si (),
|
1225 |
|
|
.so ()
|
1226 |
|
|
);
|
1227 |
|
|
`else
|
1228 |
|
|
dffr_s #(14) sftint2ff (
|
1229 |
|
|
.din (sftint_din[14:1]),
|
1230 |
|
|
.q (sftint2[14:1]),
|
1231 |
|
|
.clk (sftint2_clk),
|
1232 |
|
|
.rst (local_rst),
|
1233 |
|
|
.se (se),
|
1234 |
|
|
.si (),
|
1235 |
|
|
.so ()
|
1236 |
|
|
);
|
1237 |
|
|
`endif
|
1238 |
|
|
|
1239 |
|
|
dffre_s dffre_sftint2_b0 (
|
1240 |
|
|
.din (sftint_b0_din[2]),
|
1241 |
|
|
.q (sftint2[`SFTINT_TICK_CMP]),
|
1242 |
|
|
.clk (clk),
|
1243 |
|
|
.rst (local_rst),
|
1244 |
|
|
.en (sftint_b0_en[2]),
|
1245 |
|
|
.se (se),
|
1246 |
|
|
.si (),
|
1247 |
|
|
.so ()
|
1248 |
|
|
);
|
1249 |
|
|
|
1250 |
|
|
dffre_s dffre_sftint2_b15 (
|
1251 |
|
|
.din (sftint_b15_din[2]),
|
1252 |
|
|
.q (sftint2[`SFTINT_PIB_WRAP]),
|
1253 |
|
|
.clk (clk),
|
1254 |
|
|
.rst (local_rst),
|
1255 |
|
|
.en (sftint_b15_en[2]),
|
1256 |
|
|
.se (se),
|
1257 |
|
|
.si (),
|
1258 |
|
|
.so ()
|
1259 |
|
|
);
|
1260 |
|
|
|
1261 |
|
|
dffre_s dffre_sftint2_b16 (
|
1262 |
|
|
.din (sftint_b16_din[2]),
|
1263 |
|
|
.q (sftint2[`SFTINT_STICK_CMP]),
|
1264 |
|
|
.clk (clk),
|
1265 |
|
|
.rst (local_rst),
|
1266 |
|
|
.en (sftint_b16_en[2]),
|
1267 |
|
|
.se (se),
|
1268 |
|
|
.si (),
|
1269 |
|
|
.so ()
|
1270 |
|
|
);
|
1271 |
|
|
//
|
1272 |
|
|
// thread 3
|
1273 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
1274 |
|
|
dffre_s #(14) sftint3ff (
|
1275 |
|
|
.din (sftint_din[14:1]),
|
1276 |
|
|
.q (sftint3[14:1]),
|
1277 |
|
|
.en (~(tlu_sftint_en_l_g[3])), .clk(clk),
|
1278 |
|
|
.rst (local_rst),
|
1279 |
|
|
.se (se),
|
1280 |
|
|
.si (),
|
1281 |
|
|
.so ()
|
1282 |
|
|
);
|
1283 |
|
|
`else
|
1284 |
|
|
dffr_s #(14) sftint3ff (
|
1285 |
|
|
.din (sftint_din[14:1]),
|
1286 |
|
|
.q (sftint3[14:1]),
|
1287 |
|
|
.clk (sftint3_clk),
|
1288 |
|
|
.rst (local_rst),
|
1289 |
|
|
.se (se),
|
1290 |
|
|
.si (),
|
1291 |
|
|
.so ()
|
1292 |
|
|
);
|
1293 |
|
|
`endif
|
1294 |
|
|
|
1295 |
|
|
dffre_s dffre_sftint3_b0 (
|
1296 |
|
|
.din (sftint_b0_din[3]),
|
1297 |
|
|
.q (sftint3[`SFTINT_TICK_CMP]),
|
1298 |
|
|
.clk (clk),
|
1299 |
|
|
.rst (local_rst),
|
1300 |
|
|
.en (sftint_b0_en[3]),
|
1301 |
|
|
.se (se),
|
1302 |
|
|
.si (),
|
1303 |
|
|
.so ()
|
1304 |
|
|
);
|
1305 |
|
|
|
1306 |
|
|
dffre_s dffre_sftint3_b15 (
|
1307 |
|
|
.din (sftint_b15_din[3]),
|
1308 |
|
|
.q (sftint3[`SFTINT_PIB_WRAP]),
|
1309 |
|
|
.clk (clk),
|
1310 |
|
|
.rst (local_rst),
|
1311 |
|
|
.en (sftint_b15_en[3]),
|
1312 |
|
|
.se (se),
|
1313 |
|
|
.si (),
|
1314 |
|
|
.so ()
|
1315 |
|
|
);
|
1316 |
|
|
|
1317 |
|
|
dffre_s dffre_sftint3_b16 (
|
1318 |
|
|
.din (sftint_b16_din[3]),
|
1319 |
|
|
.q (sftint3[`SFTINT_STICK_CMP]),
|
1320 |
|
|
.clk (clk),
|
1321 |
|
|
.rst (local_rst),
|
1322 |
|
|
.en (sftint_b16_en[3]),
|
1323 |
|
|
.se (se),
|
1324 |
|
|
.si (),
|
1325 |
|
|
.so ()
|
1326 |
|
|
);
|
1327 |
|
|
//
|
1328 |
|
|
// Datapath priority encoder.
|
1329 |
|
|
assign sftint_lvl14[0] =
|
1330 |
|
|
sftint0[`SFTINT_TICK_CMP] | sftint0[`SFTINT_STICK_CMP] |
|
1331 |
|
|
sftint0[14];
|
1332 |
|
|
assign sftint_lvl14[1] =
|
1333 |
|
|
sftint1[`SFTINT_TICK_CMP] | sftint1[`SFTINT_STICK_CMP] |
|
1334 |
|
|
sftint1[14];
|
1335 |
|
|
assign sftint_lvl14[2] =
|
1336 |
|
|
sftint2[`SFTINT_TICK_CMP] | sftint2[`SFTINT_STICK_CMP] |
|
1337 |
|
|
sftint2[14];
|
1338 |
|
|
assign sftint_lvl14[3] =
|
1339 |
|
|
sftint3[`SFTINT_TICK_CMP] | sftint3[`SFTINT_STICK_CMP] |
|
1340 |
|
|
sftint3[14];
|
1341 |
|
|
//
|
1342 |
|
|
// modified to ensure one-hot mux check
|
1343 |
|
|
|
1344 |
|
|
`ifdef FPGA_SYN_1THREAD
|
1345 |
|
|
assign sftint_penc_din[14:0] = ({sftint0[15],sftint_lvl14[0],sftint0[13:1]});
|
1346 |
|
|
`else
|
1347 |
|
|
|
1348 |
|
|
mux4ds #(`SFTINT_WIDTH-2) mx_sftint_penc_din (
|
1349 |
|
|
.in0 ({sftint0[15],sftint_lvl14[0],sftint0[13:1]}),
|
1350 |
|
|
.in1 ({sftint1[15],sftint_lvl14[1],sftint1[13:1]}),
|
1351 |
|
|
.in2 ({sftint2[15],sftint_lvl14[2],sftint2[13:1]}),
|
1352 |
|
|
.in3 ({sftint3[15],sftint_lvl14[3],sftint3[13:1]}),
|
1353 |
|
|
.sel0 (tlu_sftint_penc_sel[0]),
|
1354 |
|
|
.sel1 (tlu_sftint_penc_sel[1]),
|
1355 |
|
|
.sel2 (tlu_sftint_penc_sel[2]),
|
1356 |
|
|
.sel3 (tlu_sftint_penc_sel[3]),
|
1357 |
|
|
.dout (sftint_penc_din[14:0])
|
1358 |
|
|
);
|
1359 |
|
|
`endif // !`ifdef FPGA_SYN_1THREAD
|
1360 |
|
|
|
1361 |
|
|
tlu_prencoder16 prencoder16 (
|
1362 |
|
|
.din (sftint_penc_din[14:0]),
|
1363 |
|
|
.dout (tlu_sftint_id[3:0])
|
1364 |
|
|
);
|
1365 |
|
|
|
1366 |
|
|
//wire [15:0] sftint_rdata;
|
1367 |
|
|
//
|
1368 |
|
|
// modified for hypervisor support
|
1369 |
|
|
// adding the SM bit
|
1370 |
|
|
wire [`SFTINT_WIDTH-1:0] sftint_rdata;
|
1371 |
|
|
// modified due to spec change
|
1372 |
|
|
/*
|
1373 |
|
|
mux4ds #(`SFTINT_WIDTH) sftint_mx_rsel (
|
1374 |
|
|
.in0 ({tlu_stick_int[0],sftint0[15:1],tlu_tick_int[0]}),
|
1375 |
|
|
.in1 ({tlu_stick_int[1],sftint1[15:1],tlu_tick_int[1]}),
|
1376 |
|
|
.in2 ({tlu_stick_int[2],sftint2[15:1],tlu_tick_int[2]}),
|
1377 |
|
|
.in3 ({tlu_stick_int[3],sftint3[15:1],tlu_tick_int[3]}),
|
1378 |
|
|
.sel0 (tlu_thrd_rsel_e[0]),
|
1379 |
|
|
.sel1 (tlu_thrd_rsel_e[1]),
|
1380 |
|
|
.sel2 (tlu_thrd_rsel_e[2]),
|
1381 |
|
|
.sel3 (tlu_thrd_rsel_e[3]),
|
1382 |
|
|
.dout (sftint_rdata[16:0])
|
1383 |
|
|
);
|
1384 |
|
|
*/
|
1385 |
|
|
`ifdef FPGA_SYN_1THREAD
|
1386 |
|
|
assign sftint_rdata[16:0] = sftint0[`SFTINT_WIDTH-1:0];
|
1387 |
|
|
`else
|
1388 |
|
|
|
1389 |
|
|
mux4ds #(`SFTINT_WIDTH) sftint_mx_rsel (
|
1390 |
|
|
.in0 (sftint0[`SFTINT_WIDTH-1:0]),
|
1391 |
|
|
.in1 (sftint1[`SFTINT_WIDTH-1:0]),
|
1392 |
|
|
.in2 (sftint2[`SFTINT_WIDTH-1:0]),
|
1393 |
|
|
.in3 (sftint3[`SFTINT_WIDTH-1:0]),
|
1394 |
|
|
.sel0 (tlu_thrd_rsel_e[0]),
|
1395 |
|
|
.sel1 (tlu_thrd_rsel_e[1]),
|
1396 |
|
|
.sel2 (tlu_thrd_rsel_e[2]),
|
1397 |
|
|
.sel3 (tlu_thrd_rsel_e[3]),
|
1398 |
|
|
.dout (sftint_rdata[16:0])
|
1399 |
|
|
);
|
1400 |
|
|
`endif // !`ifdef FPGA_SYN_1THREAD
|
1401 |
|
|
|
1402 |
|
|
//=========================================================================================
|
1403 |
|
|
// TBA for Threads
|
1404 |
|
|
//=========================================================================================
|
1405 |
|
|
|
1406 |
|
|
// Lower 15 bits are read as zero and ignored when written.
|
1407 |
|
|
|
1408 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
1409 |
|
|
`else
|
1410 |
|
|
clken_buf clkbf_tba0 (
|
1411 |
|
|
.rclk (clk),
|
1412 |
|
|
.enb_l (tlu_tba_en_l[0]),
|
1413 |
|
|
.tmb_l (se_l),
|
1414 |
|
|
.clk (tba0_clk)
|
1415 |
|
|
);
|
1416 |
|
|
`endif
|
1417 |
|
|
|
1418 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
1419 |
|
|
`else
|
1420 |
|
|
clken_buf clkbf_tba1 (
|
1421 |
|
|
.rclk (clk),
|
1422 |
|
|
.enb_l (tlu_tba_en_l[1]),
|
1423 |
|
|
.tmb_l (se_l),
|
1424 |
|
|
.clk (tba1_clk)
|
1425 |
|
|
);
|
1426 |
|
|
`endif
|
1427 |
|
|
|
1428 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
1429 |
|
|
`else
|
1430 |
|
|
clken_buf clkbf_tba2 (
|
1431 |
|
|
.rclk (clk),
|
1432 |
|
|
.enb_l (tlu_tba_en_l[2]),
|
1433 |
|
|
.tmb_l (se_l),
|
1434 |
|
|
.clk (tba2_clk)
|
1435 |
|
|
);
|
1436 |
|
|
`endif
|
1437 |
|
|
|
1438 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
1439 |
|
|
`else
|
1440 |
|
|
clken_buf clkbf_tba3 (
|
1441 |
|
|
.rclk (clk),
|
1442 |
|
|
.enb_l (tlu_tba_en_l[3]),
|
1443 |
|
|
.tmb_l (se_l),
|
1444 |
|
|
.clk (tba3_clk)
|
1445 |
|
|
);
|
1446 |
|
|
`endif
|
1447 |
|
|
|
1448 |
|
|
// THREAD0
|
1449 |
|
|
|
1450 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
1451 |
|
|
dffe_s #(33) tba0 (
|
1452 |
|
|
.din (tlu_wsr_data_w[47:15]),
|
1453 |
|
|
.q (true_tba0[32:0]),
|
1454 |
|
|
.en (~(tlu_tba_en_l[0])), .clk(clk),
|
1455 |
|
|
.se (se),
|
1456 |
|
|
.si (),
|
1457 |
|
|
.so ()
|
1458 |
|
|
);
|
1459 |
|
|
`else
|
1460 |
|
|
dff_s #(33) tba0 (
|
1461 |
|
|
.din (tlu_wsr_data_w[47:15]),
|
1462 |
|
|
.q (true_tba0[32:0]),
|
1463 |
|
|
.clk (tba0_clk),
|
1464 |
|
|
.se (se),
|
1465 |
|
|
.si (),
|
1466 |
|
|
.so ()
|
1467 |
|
|
);
|
1468 |
|
|
`endif
|
1469 |
|
|
|
1470 |
|
|
// THREAD1
|
1471 |
|
|
|
1472 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
1473 |
|
|
dffe_s #(33) tba1 (
|
1474 |
|
|
.din (tlu_wsr_data_w[47:15]),
|
1475 |
|
|
.q (true_tba1[32:0]),
|
1476 |
|
|
.en (~(tlu_tba_en_l[1])), .clk(clk),
|
1477 |
|
|
.se (se),
|
1478 |
|
|
.si (),
|
1479 |
|
|
.so ()
|
1480 |
|
|
);
|
1481 |
|
|
`else
|
1482 |
|
|
dff_s #(33) tba1 (
|
1483 |
|
|
.din (tlu_wsr_data_w[47:15]),
|
1484 |
|
|
.q (true_tba1[32:0]),
|
1485 |
|
|
.clk (tba1_clk),
|
1486 |
|
|
.se (se),
|
1487 |
|
|
.si (),
|
1488 |
|
|
.so ()
|
1489 |
|
|
);
|
1490 |
|
|
`endif
|
1491 |
|
|
|
1492 |
|
|
// THREAD2
|
1493 |
|
|
|
1494 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
1495 |
|
|
dffe_s #(33) tba2 (
|
1496 |
|
|
.din (tlu_wsr_data_w[47:15]),
|
1497 |
|
|
.q (true_tba2[32:0]),
|
1498 |
|
|
.en (~(tlu_tba_en_l[2])), .clk(clk),
|
1499 |
|
|
.se (se),
|
1500 |
|
|
.si (),
|
1501 |
|
|
.so ()
|
1502 |
|
|
);
|
1503 |
|
|
`else
|
1504 |
|
|
dff_s #(33) tba2 (
|
1505 |
|
|
.din (tlu_wsr_data_w[47:15]),
|
1506 |
|
|
.q (true_tba2[32:0]),
|
1507 |
|
|
.clk (tba2_clk),
|
1508 |
|
|
.se (se),
|
1509 |
|
|
.si (),
|
1510 |
|
|
.so ()
|
1511 |
|
|
);
|
1512 |
|
|
`endif
|
1513 |
|
|
|
1514 |
|
|
// THREAD3
|
1515 |
|
|
|
1516 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
1517 |
|
|
dffe_s #(33) tba3 (
|
1518 |
|
|
.din (tlu_wsr_data_w[47:15]),
|
1519 |
|
|
.q (true_tba3[32:0]),
|
1520 |
|
|
.en (~(tlu_tba_en_l[3])), .clk(clk),
|
1521 |
|
|
.se (se),
|
1522 |
|
|
.si (),
|
1523 |
|
|
.so ()
|
1524 |
|
|
);
|
1525 |
|
|
`else
|
1526 |
|
|
dff_s #(33) tba3 (
|
1527 |
|
|
.din (tlu_wsr_data_w[47:15]),
|
1528 |
|
|
.q (true_tba3[32:0]),
|
1529 |
|
|
.clk (tba3_clk),
|
1530 |
|
|
.se (se),
|
1531 |
|
|
.si (),
|
1532 |
|
|
.so ()
|
1533 |
|
|
);
|
1534 |
|
|
`endif
|
1535 |
|
|
|
1536 |
|
|
// tba_data is for traps specifically
|
1537 |
|
|
// modified for timing
|
1538 |
|
|
|
1539 |
|
|
`ifdef FPGA_SYN_1THREAD
|
1540 |
|
|
assign tba_data[32:0] = true_tba0[32:0];
|
1541 |
|
|
assign tba_rdata[32:0] = true_tba0[32:0];
|
1542 |
|
|
|
1543 |
|
|
`else
|
1544 |
|
|
|
1545 |
|
|
mux4ds #(33) mux_tba_data (
|
1546 |
|
|
.in0 (true_tba0[32:0]),
|
1547 |
|
|
.in1 (true_tba1[32:0]),
|
1548 |
|
|
.in2 (true_tba2[32:0]),
|
1549 |
|
|
.in3 (true_tba3[32:0]),
|
1550 |
|
|
.sel0 (tlu_thrd_wsel_w2[0]),
|
1551 |
|
|
.sel1 (tlu_thrd_wsel_w2[1]),
|
1552 |
|
|
.sel2 (tlu_thrd_wsel_w2[2]),
|
1553 |
|
|
.sel3 (tlu_thrd_wsel_w2[3]),
|
1554 |
|
|
.dout (tba_data[32:0])
|
1555 |
|
|
);
|
1556 |
|
|
|
1557 |
|
|
/*
|
1558 |
|
|
mux4ds #(33) tba_mx (
|
1559 |
|
|
.in0 (true_tba0[32:0]),
|
1560 |
|
|
.in1 (true_tba1[32:0]),
|
1561 |
|
|
.in2 (true_tba2[32:0]),
|
1562 |
|
|
.in3 (true_tba3[32:0]),
|
1563 |
|
|
.sel0 (tlu_thrd_rsel_g[0]),
|
1564 |
|
|
.sel1 (tlu_thrd_rsel_g[1]),
|
1565 |
|
|
.sel2 (tlu_thrd_rsel_g[2]),
|
1566 |
|
|
.sel3 (tlu_thrd_rsel_g[3]),
|
1567 |
|
|
.dout (tba_data[32:0])
|
1568 |
|
|
);
|
1569 |
|
|
*/
|
1570 |
|
|
// tba_rdata is for read of tba regs specifically.
|
1571 |
|
|
mux4ds #(33) tba_mx_rsel (
|
1572 |
|
|
.in0 (true_tba0[32:0]),
|
1573 |
|
|
.in1 (true_tba1[32:0]),
|
1574 |
|
|
.in2 (true_tba2[32:0]),
|
1575 |
|
|
.in3 (true_tba3[32:0]),
|
1576 |
|
|
.sel0 (tlu_thrd_rsel_e[0]),
|
1577 |
|
|
.sel1 (tlu_thrd_rsel_e[1]),
|
1578 |
|
|
.sel2 (tlu_thrd_rsel_e[2]),
|
1579 |
|
|
.sel3 (tlu_thrd_rsel_e[3]),
|
1580 |
|
|
.dout (tba_rdata[32:0])
|
1581 |
|
|
);
|
1582 |
|
|
`endif // !`ifdef FPGA_SYN_1THREAD
|
1583 |
|
|
|
1584 |
|
|
// added for hypervisor support
|
1585 |
|
|
//
|
1586 |
|
|
// HTBA write - constructing clocks
|
1587 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
1588 |
|
|
`else
|
1589 |
|
|
clken_buf clkbf_htba0 (
|
1590 |
|
|
.rclk (clk),
|
1591 |
|
|
.enb_l (tlu_htba_en_l[0]),
|
1592 |
|
|
.tmb_l (se_l),
|
1593 |
|
|
.clk (htba0_clk)
|
1594 |
|
|
);
|
1595 |
|
|
`endif
|
1596 |
|
|
|
1597 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
1598 |
|
|
`else
|
1599 |
|
|
clken_buf clkbf_htba1 (
|
1600 |
|
|
.rclk (clk),
|
1601 |
|
|
.enb_l (tlu_htba_en_l[1]),
|
1602 |
|
|
.tmb_l (se_l),
|
1603 |
|
|
.clk (htba1_clk)
|
1604 |
|
|
);
|
1605 |
|
|
`endif
|
1606 |
|
|
|
1607 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
1608 |
|
|
`else
|
1609 |
|
|
clken_buf clkbf_htba2 (
|
1610 |
|
|
.rclk (clk),
|
1611 |
|
|
.enb_l (tlu_htba_en_l[2]),
|
1612 |
|
|
.tmb_l (se_l),
|
1613 |
|
|
.clk (htba2_clk)
|
1614 |
|
|
);
|
1615 |
|
|
`endif
|
1616 |
|
|
|
1617 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
1618 |
|
|
`else
|
1619 |
|
|
clken_buf clkbf_htba3 (
|
1620 |
|
|
.rclk (clk),
|
1621 |
|
|
.enb_l (tlu_htba_en_l[3]),
|
1622 |
|
|
.tmb_l (se_l),
|
1623 |
|
|
.clk (htba3_clk)
|
1624 |
|
|
);
|
1625 |
|
|
`endif
|
1626 |
|
|
//
|
1627 |
|
|
// HTBA write - writing the registers
|
1628 |
|
|
// lower 14 bits of HTBA are reserved, therefore, not stored
|
1629 |
|
|
//
|
1630 |
|
|
// Thread 0
|
1631 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
1632 |
|
|
dffe_s #(`TLU_HTBA_WIDTH) dff_true_htba0 (
|
1633 |
|
|
.din (tlu_wsr_data_w[`TLU_HTBA_HI:`TLU_HTBA_LO]),
|
1634 |
|
|
.q (true_htba0[`TLU_HTBA_WIDTH-1:0]),
|
1635 |
|
|
.en (~(tlu_htba_en_l[0])), .clk(clk),
|
1636 |
|
|
.se (se),
|
1637 |
|
|
.si (),
|
1638 |
|
|
.so ()
|
1639 |
|
|
);
|
1640 |
|
|
`else
|
1641 |
|
|
dff_s #(`TLU_HTBA_WIDTH) dff_true_htba0 (
|
1642 |
|
|
.din (tlu_wsr_data_w[`TLU_HTBA_HI:`TLU_HTBA_LO]),
|
1643 |
|
|
.q (true_htba0[`TLU_HTBA_WIDTH-1:0]),
|
1644 |
|
|
.clk (htba0_clk),
|
1645 |
|
|
.se (se),
|
1646 |
|
|
.si (),
|
1647 |
|
|
.so ()
|
1648 |
|
|
);
|
1649 |
|
|
`endif
|
1650 |
|
|
//
|
1651 |
|
|
// Thread 1
|
1652 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
1653 |
|
|
dffe_s #(`TLU_HTBA_WIDTH) dff_true_htba1 (
|
1654 |
|
|
.din (tlu_wsr_data_w[`TLU_HTBA_HI:`TLU_HTBA_LO]),
|
1655 |
|
|
.q (true_htba1[`TLU_HTBA_WIDTH-1:0]),
|
1656 |
|
|
.en (~(tlu_htba_en_l[1])), .clk(clk),
|
1657 |
|
|
.se (se),
|
1658 |
|
|
.si (),
|
1659 |
|
|
.so ()
|
1660 |
|
|
);
|
1661 |
|
|
`else
|
1662 |
|
|
dff_s #(`TLU_HTBA_WIDTH) dff_true_htba1 (
|
1663 |
|
|
.din (tlu_wsr_data_w[`TLU_HTBA_HI:`TLU_HTBA_LO]),
|
1664 |
|
|
.q (true_htba1[`TLU_HTBA_WIDTH-1:0]),
|
1665 |
|
|
.clk (htba1_clk),
|
1666 |
|
|
.se (se),
|
1667 |
|
|
.si (),
|
1668 |
|
|
.so ()
|
1669 |
|
|
);
|
1670 |
|
|
`endif
|
1671 |
|
|
//
|
1672 |
|
|
// Thread 2
|
1673 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
1674 |
|
|
dffe_s #(`TLU_HTBA_WIDTH) dff_true_htba2 (
|
1675 |
|
|
.din (tlu_wsr_data_w[`TLU_HTBA_HI:`TLU_HTBA_LO]),
|
1676 |
|
|
.q (true_htba2[`TLU_HTBA_WIDTH-1:0]),
|
1677 |
|
|
.en (~(tlu_htba_en_l[2])), .clk(clk),
|
1678 |
|
|
.se (se),
|
1679 |
|
|
.si (),
|
1680 |
|
|
.so ()
|
1681 |
|
|
);
|
1682 |
|
|
`else
|
1683 |
|
|
dff_s #(`TLU_HTBA_WIDTH) dff_true_htba2 (
|
1684 |
|
|
.din (tlu_wsr_data_w[`TLU_HTBA_HI:`TLU_HTBA_LO]),
|
1685 |
|
|
.q (true_htba2[`TLU_HTBA_WIDTH-1:0]),
|
1686 |
|
|
.clk (htba2_clk),
|
1687 |
|
|
.se (se),
|
1688 |
|
|
.si (),
|
1689 |
|
|
.so ()
|
1690 |
|
|
);
|
1691 |
|
|
`endif
|
1692 |
|
|
//
|
1693 |
|
|
// Thread 3
|
1694 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
1695 |
|
|
dffe_s #(`TLU_HTBA_WIDTH) dff_true_htba3 (
|
1696 |
|
|
.din (tlu_wsr_data_w[`TLU_HTBA_HI:`TLU_HTBA_LO]),
|
1697 |
|
|
.q (true_htba3[`TLU_HTBA_WIDTH-1:0]),
|
1698 |
|
|
.en (~(tlu_htba_en_l[3])), .clk(clk),
|
1699 |
|
|
.se (se),
|
1700 |
|
|
.si (),
|
1701 |
|
|
.so ()
|
1702 |
|
|
);
|
1703 |
|
|
`else
|
1704 |
|
|
dff_s #(`TLU_HTBA_WIDTH) dff_true_htba3 (
|
1705 |
|
|
.din (tlu_wsr_data_w[`TLU_HTBA_HI:`TLU_HTBA_LO]),
|
1706 |
|
|
.q (true_htba3[`TLU_HTBA_WIDTH-1:0]),
|
1707 |
|
|
.clk (htba3_clk),
|
1708 |
|
|
.se (se),
|
1709 |
|
|
.si (),
|
1710 |
|
|
.so ()
|
1711 |
|
|
);
|
1712 |
|
|
`endif
|
1713 |
|
|
//
|
1714 |
|
|
// constructing the rdata for HTBA
|
1715 |
|
|
wire [`TLU_HTBA_WIDTH-1:0] htba_rdata;
|
1716 |
|
|
|
1717 |
|
|
`ifdef FPGA_SYN_1THREAD
|
1718 |
|
|
assign htba_rdata[`TLU_HTBA_WIDTH-1:0] = true_htba0[`TLU_HTBA_WIDTH-1:0];
|
1719 |
|
|
assign htba_data[`TLU_HTBA_WIDTH-1:0] = true_htba0[`TLU_HTBA_WIDTH-1:0];
|
1720 |
|
|
`else
|
1721 |
|
|
|
1722 |
|
|
mux4ds #(`TLU_HTBA_WIDTH) mux_htba_rdata (
|
1723 |
|
|
.in0 (true_htba0[`TLU_HTBA_WIDTH-1:0]),
|
1724 |
|
|
.in1 (true_htba1[`TLU_HTBA_WIDTH-1:0]),
|
1725 |
|
|
.in2 (true_htba2[`TLU_HTBA_WIDTH-1:0]),
|
1726 |
|
|
.in3 (true_htba3[`TLU_HTBA_WIDTH-1:0]),
|
1727 |
|
|
.sel0 (tlu_thrd_rsel_e[0]),
|
1728 |
|
|
.sel1 (tlu_thrd_rsel_e[1]),
|
1729 |
|
|
.sel2 (tlu_thrd_rsel_e[2]),
|
1730 |
|
|
.sel3 (tlu_thrd_rsel_e[3]),
|
1731 |
|
|
.dout (htba_rdata[`TLU_HTBA_WIDTH-1:0])
|
1732 |
|
|
);
|
1733 |
|
|
//
|
1734 |
|
|
// selecting the htba base address to use
|
1735 |
|
|
// modified for timing
|
1736 |
|
|
mux4ds #(`TLU_HTBA_WIDTH) mux_htba_data (
|
1737 |
|
|
.in0 (true_htba0[`TLU_HTBA_WIDTH-1:0]),
|
1738 |
|
|
.in1 (true_htba1[`TLU_HTBA_WIDTH-1:0]),
|
1739 |
|
|
.in2 (true_htba2[`TLU_HTBA_WIDTH-1:0]),
|
1740 |
|
|
.in3 (true_htba3[`TLU_HTBA_WIDTH-1:0]),
|
1741 |
|
|
.sel0 (tlu_thrd_wsel_w2[0]),
|
1742 |
|
|
.sel1 (tlu_thrd_wsel_w2[1]),
|
1743 |
|
|
.sel2 (tlu_thrd_wsel_w2[2]),
|
1744 |
|
|
.sel3 (tlu_thrd_wsel_w2[3]),
|
1745 |
|
|
.dout (htba_data[`TLU_HTBA_WIDTH-1:0])
|
1746 |
|
|
);
|
1747 |
|
|
`endif // !`ifdef FPGA_SYN_1THREAD
|
1748 |
|
|
|
1749 |
|
|
/*
|
1750 |
|
|
mux4ds #(`TLU_HTBA_WIDTH) mux_htba_data (
|
1751 |
|
|
.in0 (true_htba0[`TLU_HTBA_WIDTH-1:0]),
|
1752 |
|
|
.in1 (true_htba1[`TLU_HTBA_WIDTH-1:0]),
|
1753 |
|
|
.in2 (true_htba2[`TLU_HTBA_WIDTH-1:0]),
|
1754 |
|
|
.in3 (true_htba3[`TLU_HTBA_WIDTH-1:0]),
|
1755 |
|
|
.sel0 (tlu_thrd_rsel_g[0]),
|
1756 |
|
|
.sel1 (tlu_thrd_rsel_g[1]),
|
1757 |
|
|
.sel2 (tlu_thrd_rsel_g[2]),
|
1758 |
|
|
.sel3 (tlu_thrd_rsel_g[3]),
|
1759 |
|
|
.dout (htba_data[`TLU_HTBA_WIDTH-1:0])
|
1760 |
|
|
);
|
1761 |
|
|
*/
|
1762 |
|
|
//=========================================================================================
|
1763 |
|
|
// TICKS for Threads
|
1764 |
|
|
//=========================================================================================
|
1765 |
|
|
|
1766 |
|
|
// npt needs to be muxed into read !!!
|
1767 |
|
|
|
1768 |
|
|
|
1769 |
|
|
// THREAD0,1,2,3
|
1770 |
|
|
|
1771 |
|
|
mux2ds #(61) tick_sel (
|
1772 |
|
|
.in0 (tlu_wsr_data_w[62:2]),
|
1773 |
|
|
.in1 (tlu_tick_incr_dout[60:0]),
|
1774 |
|
|
.sel0 (~tlu_tick_en_l),
|
1775 |
|
|
.sel1 ( tlu_tick_en_l),
|
1776 |
|
|
.dout (tick_din[62:2])
|
1777 |
|
|
);
|
1778 |
|
|
//
|
1779 |
|
|
// modified due to the switch to the soft macro
|
1780 |
|
|
// assign tlu_tick_incr_din[`TLU_ASR_DATA_WIDTH-1:0] =
|
1781 |
|
|
// {3'b000,true_tick[60:0]};
|
1782 |
|
|
assign tlu_tick_incr_din[`TLU_ASR_DATA_WIDTH-3:0] =
|
1783 |
|
|
{1'b0,true_tick[60:0]};
|
1784 |
|
|
|
1785 |
|
|
// Does not need enable as either in increment or update state
|
1786 |
|
|
dff_s #(61) tick0123 (
|
1787 |
|
|
.din (tick_din[62:2]),
|
1788 |
|
|
.q (true_tick[60:0]),
|
1789 |
|
|
.clk (clk),
|
1790 |
|
|
.se (se),
|
1791 |
|
|
.si (),
|
1792 |
|
|
.so ()
|
1793 |
|
|
);
|
1794 |
|
|
|
1795 |
|
|
//=========================================================================================
|
1796 |
|
|
// TICK COMPARE for Threads
|
1797 |
|
|
//=========================================================================================
|
1798 |
|
|
|
1799 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
1800 |
|
|
`else
|
1801 |
|
|
clken_buf clkbf_tcmp0 (
|
1802 |
|
|
.rclk (clk),
|
1803 |
|
|
.enb_l (tlu_tickcmp_en_l[0]),
|
1804 |
|
|
.tmb_l (se_l),
|
1805 |
|
|
.clk (tcmp0_clk)
|
1806 |
|
|
);
|
1807 |
|
|
`endif
|
1808 |
|
|
|
1809 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
1810 |
|
|
`else
|
1811 |
|
|
clken_buf clkbf_tcmp1 (
|
1812 |
|
|
.rclk (clk),
|
1813 |
|
|
.enb_l (tlu_tickcmp_en_l[1]),
|
1814 |
|
|
.tmb_l (se_l),
|
1815 |
|
|
.clk (tcmp1_clk)
|
1816 |
|
|
);
|
1817 |
|
|
`endif
|
1818 |
|
|
|
1819 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
1820 |
|
|
`else
|
1821 |
|
|
clken_buf clkbf_tcmp2 (
|
1822 |
|
|
.rclk (clk),
|
1823 |
|
|
.enb_l (tlu_tickcmp_en_l[2]),
|
1824 |
|
|
.tmb_l (se_l),
|
1825 |
|
|
.clk (tcmp2_clk)
|
1826 |
|
|
);
|
1827 |
|
|
`endif
|
1828 |
|
|
|
1829 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
1830 |
|
|
`else
|
1831 |
|
|
clken_buf clkbf_tcmp3 (
|
1832 |
|
|
.rclk (clk),
|
1833 |
|
|
.enb_l (tlu_tickcmp_en_l[3]),
|
1834 |
|
|
.tmb_l (se_l),
|
1835 |
|
|
.clk (tcmp3_clk)
|
1836 |
|
|
);
|
1837 |
|
|
`endif
|
1838 |
|
|
|
1839 |
|
|
// thread 0
|
1840 |
|
|
// added or modified due to tickcmp clean-up
|
1841 |
|
|
assign tickcmp_intdis_din[0] =
|
1842 |
|
|
tlu_wsr_data_w[`TICKCMP_INTDIS] | local_rst |
|
1843 |
|
|
tlu_por_rstint_g[0];
|
1844 |
|
|
// added and modified for bug 4763
|
1845 |
|
|
assign tickcmp_intdis_en[0] =
|
1846 |
|
|
~tlu_tickcmp_en_l[0] | local_rst | tlu_por_rstint_g[0];
|
1847 |
|
|
|
1848 |
|
|
dffe_s dffe_tickcmp_intdis0 (
|
1849 |
|
|
.din (tickcmp_intdis_din[0]),
|
1850 |
|
|
.q (true_tickcmp0[`TICKCMP_INTDIS]),
|
1851 |
|
|
.en (tickcmp_intdis_en[0]),
|
1852 |
|
|
.clk (clk),
|
1853 |
|
|
.se (se),
|
1854 |
|
|
.si (),
|
1855 |
|
|
.so ()
|
1856 |
|
|
);
|
1857 |
|
|
|
1858 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
1859 |
|
|
dffe_s #(`TLU_ASR_DATA_WIDTH-1) tickcmp0 (
|
1860 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
1861 |
|
|
.q (true_tickcmp0[`TLU_ASR_DATA_WIDTH-2:0]),
|
1862 |
|
|
.en (~(tlu_tickcmp_en_l[0])), .clk(clk),
|
1863 |
|
|
.se (se),
|
1864 |
|
|
.si (),
|
1865 |
|
|
.so ()
|
1866 |
|
|
);
|
1867 |
|
|
`else
|
1868 |
|
|
dff_s #(`TLU_ASR_DATA_WIDTH-1) tickcmp0 (
|
1869 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
1870 |
|
|
.q (true_tickcmp0[`TLU_ASR_DATA_WIDTH-2:0]),
|
1871 |
|
|
.clk (tcmp0_clk),
|
1872 |
|
|
.se (se),
|
1873 |
|
|
.si (),
|
1874 |
|
|
.so ()
|
1875 |
|
|
);
|
1876 |
|
|
`endif
|
1877 |
|
|
|
1878 |
|
|
// thread 1
|
1879 |
|
|
// added or modified due to tickcmp clean-up
|
1880 |
|
|
assign tickcmp_intdis_din[1] =
|
1881 |
|
|
tlu_wsr_data_w[`TICKCMP_INTDIS] | local_rst |
|
1882 |
|
|
tlu_por_rstint_g[1];
|
1883 |
|
|
// added and modified for bug 4763
|
1884 |
|
|
assign tickcmp_intdis_en[1] =
|
1885 |
|
|
~tlu_tickcmp_en_l[1] | local_rst | tlu_por_rstint_g[1];
|
1886 |
|
|
|
1887 |
|
|
dffe_s dffe_tickcmp_intdis1 (
|
1888 |
|
|
.din (tickcmp_intdis_din[1]),
|
1889 |
|
|
.q (true_tickcmp1[`TICKCMP_INTDIS]),
|
1890 |
|
|
.en (tickcmp_intdis_en[1]),
|
1891 |
|
|
.clk (clk),
|
1892 |
|
|
.se (se),
|
1893 |
|
|
.si (),
|
1894 |
|
|
.so ()
|
1895 |
|
|
);
|
1896 |
|
|
|
1897 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
1898 |
|
|
dffe_s #(`TLU_ASR_DATA_WIDTH-1) tickcmp1 (
|
1899 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
1900 |
|
|
.q (true_tickcmp1[`TLU_ASR_DATA_WIDTH-2:0]),
|
1901 |
|
|
.en (~(tlu_tickcmp_en_l[1])), .clk(clk),
|
1902 |
|
|
.se (se),
|
1903 |
|
|
.si (),
|
1904 |
|
|
.so ()
|
1905 |
|
|
);
|
1906 |
|
|
`else
|
1907 |
|
|
dff_s #(`TLU_ASR_DATA_WIDTH-1) tickcmp1 (
|
1908 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
1909 |
|
|
.q (true_tickcmp1[`TLU_ASR_DATA_WIDTH-2:0]),
|
1910 |
|
|
.clk (tcmp1_clk),
|
1911 |
|
|
.se (se),
|
1912 |
|
|
.si (),
|
1913 |
|
|
.so ()
|
1914 |
|
|
);
|
1915 |
|
|
`endif
|
1916 |
|
|
|
1917 |
|
|
// thread 2
|
1918 |
|
|
// added or modified due to tickcmp clean-up
|
1919 |
|
|
assign tickcmp_intdis_din[2] =
|
1920 |
|
|
tlu_wsr_data_w[`TICKCMP_INTDIS] | local_rst |
|
1921 |
|
|
tlu_por_rstint_g[2];
|
1922 |
|
|
// added and modified for bug 4763
|
1923 |
|
|
assign tickcmp_intdis_en[2] =
|
1924 |
|
|
~tlu_tickcmp_en_l[2] | local_rst | tlu_por_rstint_g[2];
|
1925 |
|
|
|
1926 |
|
|
dffe_s dffe_tickcmp_intdis2 (
|
1927 |
|
|
.din (tickcmp_intdis_din[2]),
|
1928 |
|
|
.q (true_tickcmp2[`TICKCMP_INTDIS]),
|
1929 |
|
|
.en (tickcmp_intdis_en[2]),
|
1930 |
|
|
.clk (clk),
|
1931 |
|
|
.se (se),
|
1932 |
|
|
.si (),
|
1933 |
|
|
.so ()
|
1934 |
|
|
);
|
1935 |
|
|
|
1936 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
1937 |
|
|
dffe_s #(`TLU_ASR_DATA_WIDTH-1) tickcmp2 (
|
1938 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
1939 |
|
|
.q (true_tickcmp2[`TLU_ASR_DATA_WIDTH-2:0]),
|
1940 |
|
|
.en (~(tlu_tickcmp_en_l[2])), .clk(clk),
|
1941 |
|
|
.se (se),
|
1942 |
|
|
.si (),
|
1943 |
|
|
.so ()
|
1944 |
|
|
);
|
1945 |
|
|
`else
|
1946 |
|
|
dff_s #(`TLU_ASR_DATA_WIDTH-1) tickcmp2 (
|
1947 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
1948 |
|
|
.q (true_tickcmp2[`TLU_ASR_DATA_WIDTH-2:0]),
|
1949 |
|
|
.clk (tcmp2_clk),
|
1950 |
|
|
.se (se),
|
1951 |
|
|
.si (),
|
1952 |
|
|
.so ()
|
1953 |
|
|
);
|
1954 |
|
|
`endif
|
1955 |
|
|
|
1956 |
|
|
// thread 3
|
1957 |
|
|
// added or modified due to tickcmp clean-up
|
1958 |
|
|
assign tickcmp_intdis_din[3] =
|
1959 |
|
|
tlu_wsr_data_w[`TICKCMP_INTDIS] | local_rst |
|
1960 |
|
|
tlu_por_rstint_g[3];
|
1961 |
|
|
// added and modified for bug 4763
|
1962 |
|
|
assign tickcmp_intdis_en[3] =
|
1963 |
|
|
~tlu_tickcmp_en_l[3] | local_rst | tlu_por_rstint_g[3];
|
1964 |
|
|
|
1965 |
|
|
dffe_s dffe_tickcmp_intdis3 (
|
1966 |
|
|
.din (tickcmp_intdis_din[3]),
|
1967 |
|
|
.q (true_tickcmp3[`TICKCMP_INTDIS]),
|
1968 |
|
|
.en (tickcmp_intdis_en[3]),
|
1969 |
|
|
.clk (clk),
|
1970 |
|
|
.se (se),
|
1971 |
|
|
.si (),
|
1972 |
|
|
.so ()
|
1973 |
|
|
);
|
1974 |
|
|
|
1975 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
1976 |
|
|
dffe_s #(`TLU_ASR_DATA_WIDTH-1) tickcmp3 (
|
1977 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
1978 |
|
|
.q (true_tickcmp3[`TLU_ASR_DATA_WIDTH-2:0]),
|
1979 |
|
|
.en (~(tlu_tickcmp_en_l[3])), .clk(clk),
|
1980 |
|
|
.se (se),
|
1981 |
|
|
.si (),
|
1982 |
|
|
.so ()
|
1983 |
|
|
);
|
1984 |
|
|
`else
|
1985 |
|
|
dff_s #(`TLU_ASR_DATA_WIDTH-1) tickcmp3 (
|
1986 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
1987 |
|
|
.q (true_tickcmp3[`TLU_ASR_DATA_WIDTH-2:0]),
|
1988 |
|
|
.clk (tcmp3_clk),
|
1989 |
|
|
.se (se),
|
1990 |
|
|
.si (),
|
1991 |
|
|
.so ()
|
1992 |
|
|
);
|
1993 |
|
|
`endif
|
1994 |
|
|
|
1995 |
|
|
// Select 1/4 sources. Assume compare is independent of read
|
1996 |
|
|
// and thus needs separate mux
|
1997 |
|
|
`ifdef FPGA_SYN_1THREAD
|
1998 |
|
|
assign tickcmp_data[`TLU_ASR_DATA_WIDTH-4:0] = true_tickcmp0[`TLU_ASR_DATA_WIDTH-2:2];
|
1999 |
|
|
assign tickcmp_rdata[`TLU_ASR_DATA_WIDTH-1:0] = true_tickcmp0[`TLU_ASR_DATA_WIDTH-1:0];
|
2000 |
|
|
`else
|
2001 |
|
|
|
2002 |
|
|
mux4ds #(`TLU_ASR_DATA_WIDTH-3) tcmp_mx_sel (
|
2003 |
|
|
.in0 (true_tickcmp0[`TLU_ASR_DATA_WIDTH-2:2]),
|
2004 |
|
|
.in1 (true_tickcmp1[`TLU_ASR_DATA_WIDTH-2:2]),
|
2005 |
|
|
.in2 (true_tickcmp2[`TLU_ASR_DATA_WIDTH-2:2]),
|
2006 |
|
|
.in3 (true_tickcmp3[`TLU_ASR_DATA_WIDTH-2:2]),
|
2007 |
|
|
.sel0 (tlu_tickcmp_sel[0]),
|
2008 |
|
|
.sel1 (tlu_tickcmp_sel[1]),
|
2009 |
|
|
.sel2 (tlu_tickcmp_sel[2]),
|
2010 |
|
|
.sel3 (tlu_tickcmp_sel[3]),
|
2011 |
|
|
.dout (tickcmp_data[`TLU_ASR_DATA_WIDTH-4:0])
|
2012 |
|
|
);
|
2013 |
|
|
|
2014 |
|
|
// mux for read
|
2015 |
|
|
mux4ds #(`TLU_ASR_DATA_WIDTH) tcmp_mx_rsel (
|
2016 |
|
|
.in0 (true_tickcmp0[`TLU_ASR_DATA_WIDTH-1:0]),
|
2017 |
|
|
.in1 (true_tickcmp1[`TLU_ASR_DATA_WIDTH-1:0]),
|
2018 |
|
|
.in2 (true_tickcmp2[`TLU_ASR_DATA_WIDTH-1:0]),
|
2019 |
|
|
.in3 (true_tickcmp3[`TLU_ASR_DATA_WIDTH-1:0]),
|
2020 |
|
|
.sel0 (tlu_thrd_rsel_e[0]),
|
2021 |
|
|
.sel1 (tlu_thrd_rsel_e[1]),
|
2022 |
|
|
.sel2 (tlu_thrd_rsel_e[2]),
|
2023 |
|
|
.sel3 (tlu_thrd_rsel_e[3]),
|
2024 |
|
|
.dout (tickcmp_rdata[`TLU_ASR_DATA_WIDTH-1:0])
|
2025 |
|
|
);
|
2026 |
|
|
`endif // !`ifdef FPGA_SYN_1THREAD
|
2027 |
|
|
|
2028 |
|
|
//
|
2029 |
|
|
// evaluate for tickcmp match
|
2030 |
|
|
assign tick_match =
|
2031 |
|
|
(tickcmp_data[`TICKCMP_RANGE_HI:`TICKCMP_RANGE_LO] ==
|
2032 |
|
|
true_tick[60:0]);
|
2033 |
|
|
//
|
2034 |
|
|
// moved from tlu_tcl
|
2035 |
|
|
assign tickcmp_int[0] =
|
2036 |
|
|
tick_match & ~true_tickcmp0[`TICKCMP_INTDIS] & tlu_tickcmp_sel[0];
|
2037 |
|
|
assign tickcmp_int[1] =
|
2038 |
|
|
tick_match & ~true_tickcmp1[`TICKCMP_INTDIS] & tlu_tickcmp_sel[1];
|
2039 |
|
|
assign tickcmp_int[2] =
|
2040 |
|
|
tick_match & ~true_tickcmp2[`TICKCMP_INTDIS] & tlu_tickcmp_sel[2];
|
2041 |
|
|
assign tickcmp_int[3] =
|
2042 |
|
|
tick_match & ~true_tickcmp3[`TICKCMP_INTDIS] & tlu_tickcmp_sel[3];
|
2043 |
|
|
|
2044 |
|
|
//=========================================================================================
|
2045 |
|
|
// STICK COMPARE for Threads
|
2046 |
|
|
//=========================================================================================
|
2047 |
|
|
// added for hypervisor support
|
2048 |
|
|
|
2049 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
2050 |
|
|
`else
|
2051 |
|
|
clken_buf clkbf_stcmp0 (
|
2052 |
|
|
.rclk (clk),
|
2053 |
|
|
.enb_l (tlu_stickcmp_en_l[0]),
|
2054 |
|
|
.tmb_l (se_l),
|
2055 |
|
|
.clk (stcmp0_clk)
|
2056 |
|
|
);
|
2057 |
|
|
`endif
|
2058 |
|
|
|
2059 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
2060 |
|
|
`else
|
2061 |
|
|
clken_buf clkbf_stcmp1 (
|
2062 |
|
|
.rclk (clk),
|
2063 |
|
|
.enb_l (tlu_stickcmp_en_l[1]),
|
2064 |
|
|
.tmb_l (se_l),
|
2065 |
|
|
.clk (stcmp1_clk)
|
2066 |
|
|
);
|
2067 |
|
|
`endif
|
2068 |
|
|
|
2069 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
2070 |
|
|
`else
|
2071 |
|
|
clken_buf clkbf_stcmp2 (
|
2072 |
|
|
.rclk (clk),
|
2073 |
|
|
.enb_l (tlu_stickcmp_en_l[2]),
|
2074 |
|
|
.tmb_l (se_l),
|
2075 |
|
|
.clk (stcmp2_clk)
|
2076 |
|
|
);
|
2077 |
|
|
`endif
|
2078 |
|
|
|
2079 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
2080 |
|
|
`else
|
2081 |
|
|
clken_buf clkbf_stcmp3 (
|
2082 |
|
|
.rclk (clk),
|
2083 |
|
|
.enb_l (tlu_stickcmp_en_l[3]),
|
2084 |
|
|
.tmb_l (se_l),
|
2085 |
|
|
.clk (stcmp3_clk)
|
2086 |
|
|
);
|
2087 |
|
|
`endif
|
2088 |
|
|
|
2089 |
|
|
// thread 0
|
2090 |
|
|
// added or modified due to stickcmp clean-up
|
2091 |
|
|
assign stickcmp_intdis_din[0] = tickcmp_intdis_din[0];
|
2092 |
|
|
// added and modified for bug 4763
|
2093 |
|
|
assign stickcmp_intdis_en[0] =
|
2094 |
|
|
~tlu_stickcmp_en_l[0] | local_rst | tlu_por_rstint_g[0];
|
2095 |
|
|
|
2096 |
|
|
dffe_s dffe_stickcmp_intdis0 (
|
2097 |
|
|
.din (stickcmp_intdis_din[0]),
|
2098 |
|
|
.q (true_stickcmp0[`TICKCMP_INTDIS]),
|
2099 |
|
|
.en (stickcmp_intdis_en[0]),
|
2100 |
|
|
.clk (clk),
|
2101 |
|
|
.se (se),
|
2102 |
|
|
.si (),
|
2103 |
|
|
.so ()
|
2104 |
|
|
);
|
2105 |
|
|
|
2106 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
2107 |
|
|
dffe_s #(`TLU_ASR_DATA_WIDTH-1) stickcmp0 (
|
2108 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
2109 |
|
|
.q (true_stickcmp0[`TLU_ASR_DATA_WIDTH-2:0]),
|
2110 |
|
|
.en (~(tlu_stickcmp_en_l[0])), .clk(clk),
|
2111 |
|
|
.se (se),
|
2112 |
|
|
.si (),
|
2113 |
|
|
.so ()
|
2114 |
|
|
);
|
2115 |
|
|
`else
|
2116 |
|
|
dff_s #(`TLU_ASR_DATA_WIDTH-1) stickcmp0 (
|
2117 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
2118 |
|
|
.q (true_stickcmp0[`TLU_ASR_DATA_WIDTH-2:0]),
|
2119 |
|
|
.clk (stcmp0_clk),
|
2120 |
|
|
.se (se),
|
2121 |
|
|
.si (),
|
2122 |
|
|
.so ()
|
2123 |
|
|
);
|
2124 |
|
|
`endif
|
2125 |
|
|
|
2126 |
|
|
// thread 1
|
2127 |
|
|
// added or modified due to stickcmp clean-up
|
2128 |
|
|
assign stickcmp_intdis_din[1] = tickcmp_intdis_din[1];
|
2129 |
|
|
// added and modified for bug 4763
|
2130 |
|
|
assign stickcmp_intdis_en[1] =
|
2131 |
|
|
~tlu_stickcmp_en_l[1] | local_rst | tlu_por_rstint_g[1];
|
2132 |
|
|
|
2133 |
|
|
dffe_s dffe_stickcmp_intdis1 (
|
2134 |
|
|
.din (stickcmp_intdis_din[1]),
|
2135 |
|
|
.q (true_stickcmp1[`TICKCMP_INTDIS]),
|
2136 |
|
|
.en (stickcmp_intdis_en[1]),
|
2137 |
|
|
.clk (clk),
|
2138 |
|
|
.se (se),
|
2139 |
|
|
.si (),
|
2140 |
|
|
.so ()
|
2141 |
|
|
);
|
2142 |
|
|
|
2143 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
2144 |
|
|
dffe_s #(`TLU_ASR_DATA_WIDTH-1) stickcmp1 (
|
2145 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
2146 |
|
|
.q (true_stickcmp1[`TLU_ASR_DATA_WIDTH-2:0]),
|
2147 |
|
|
.en (~(tlu_stickcmp_en_l[1])), .clk(clk),
|
2148 |
|
|
.se (se),
|
2149 |
|
|
.si (),
|
2150 |
|
|
.so ()
|
2151 |
|
|
);
|
2152 |
|
|
`else
|
2153 |
|
|
dff_s #(`TLU_ASR_DATA_WIDTH-1) stickcmp1 (
|
2154 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
2155 |
|
|
.q (true_stickcmp1[`TLU_ASR_DATA_WIDTH-2:0]),
|
2156 |
|
|
.clk (stcmp1_clk),
|
2157 |
|
|
.se (se),
|
2158 |
|
|
.si (),
|
2159 |
|
|
.so ()
|
2160 |
|
|
);
|
2161 |
|
|
`endif
|
2162 |
|
|
|
2163 |
|
|
// thread 2
|
2164 |
|
|
// added or modified due to stickcmp clean-up
|
2165 |
|
|
assign stickcmp_intdis_din[2] = tickcmp_intdis_din[2];
|
2166 |
|
|
// added for bug 4763
|
2167 |
|
|
assign stickcmp_intdis_en[2] =
|
2168 |
|
|
~tlu_stickcmp_en_l[2] | local_rst | tlu_por_rstint_g[2];
|
2169 |
|
|
|
2170 |
|
|
dffe_s dffe_stickcmp_intdis2 (
|
2171 |
|
|
.din (stickcmp_intdis_din[2]),
|
2172 |
|
|
.q (true_stickcmp2[`TICKCMP_INTDIS]),
|
2173 |
|
|
.en (stickcmp_intdis_en[2]),
|
2174 |
|
|
.clk (clk),
|
2175 |
|
|
.se (se),
|
2176 |
|
|
.si (),
|
2177 |
|
|
.so ()
|
2178 |
|
|
);
|
2179 |
|
|
|
2180 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
2181 |
|
|
dffe_s #(`TLU_ASR_DATA_WIDTH-1) stickcmp2 (
|
2182 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
2183 |
|
|
.q (true_stickcmp2[`TLU_ASR_DATA_WIDTH-2:0]),
|
2184 |
|
|
.en (~(tlu_stickcmp_en_l[2])), .clk(clk),
|
2185 |
|
|
.se (se),
|
2186 |
|
|
.si (),
|
2187 |
|
|
.so ()
|
2188 |
|
|
);
|
2189 |
|
|
`else
|
2190 |
|
|
dff_s #(`TLU_ASR_DATA_WIDTH-1) stickcmp2 (
|
2191 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
2192 |
|
|
.q (true_stickcmp2[`TLU_ASR_DATA_WIDTH-2:0]),
|
2193 |
|
|
.clk (stcmp2_clk),
|
2194 |
|
|
.se (se),
|
2195 |
|
|
.si (),
|
2196 |
|
|
.so ()
|
2197 |
|
|
);
|
2198 |
|
|
`endif
|
2199 |
|
|
|
2200 |
|
|
// thread 3
|
2201 |
|
|
// added or modified due to stickcmp clean-up
|
2202 |
|
|
assign stickcmp_intdis_din[3] = tickcmp_intdis_din[3];
|
2203 |
|
|
// added and modified for bug 4763
|
2204 |
|
|
assign stickcmp_intdis_en[3] =
|
2205 |
|
|
~tlu_stickcmp_en_l[3] | local_rst | tlu_por_rstint_g[3];
|
2206 |
|
|
|
2207 |
|
|
dffe_s dffe_stickcmp_intdis3 (
|
2208 |
|
|
.din (stickcmp_intdis_din[3]),
|
2209 |
|
|
.q (true_stickcmp3[`TICKCMP_INTDIS]),
|
2210 |
|
|
.en (stickcmp_intdis_en[3]),
|
2211 |
|
|
.clk (clk),
|
2212 |
|
|
.se (se),
|
2213 |
|
|
.si (),
|
2214 |
|
|
.so ()
|
2215 |
|
|
);
|
2216 |
|
|
|
2217 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
2218 |
|
|
dffe_s #(`TLU_ASR_DATA_WIDTH-1) stickcmp3 (
|
2219 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
2220 |
|
|
.q (true_stickcmp3[`TLU_ASR_DATA_WIDTH-2:0]),
|
2221 |
|
|
.en (~(tlu_stickcmp_en_l[3])), .clk(clk),
|
2222 |
|
|
.se (se),
|
2223 |
|
|
.si (),
|
2224 |
|
|
.so ()
|
2225 |
|
|
);
|
2226 |
|
|
`else
|
2227 |
|
|
dff_s #(`TLU_ASR_DATA_WIDTH-1) stickcmp3 (
|
2228 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
2229 |
|
|
.q (true_stickcmp3[`TLU_ASR_DATA_WIDTH-2:0]),
|
2230 |
|
|
.clk (stcmp3_clk),
|
2231 |
|
|
.se (se),
|
2232 |
|
|
.si (),
|
2233 |
|
|
.so ()
|
2234 |
|
|
);
|
2235 |
|
|
`endif // !`ifdef FPGA_SYN_CLK_DFF
|
2236 |
|
|
|
2237 |
|
|
// Select 1/4 sources. Assume compare is independent of read
|
2238 |
|
|
// and thus needs separate mux
|
2239 |
|
|
|
2240 |
|
|
`ifdef FPGA_SYN_1THREAD
|
2241 |
|
|
assign stickcmp_data[`TLU_ASR_DATA_WIDTH-4:0] = true_stickcmp0[`TLU_ASR_DATA_WIDTH-2:2];
|
2242 |
|
|
assign stickcmp_rdata[`TLU_ASR_DATA_WIDTH-1:0] = true_stickcmp0[`TLU_ASR_DATA_WIDTH-1:0];
|
2243 |
|
|
`else
|
2244 |
|
|
|
2245 |
|
|
mux4ds #(`TLU_ASR_DATA_WIDTH-3) mux_stickcmp_data (
|
2246 |
|
|
.in0 (true_stickcmp0[`TLU_ASR_DATA_WIDTH-2:2]),
|
2247 |
|
|
.in1 (true_stickcmp1[`TLU_ASR_DATA_WIDTH-2:2]),
|
2248 |
|
|
.in2 (true_stickcmp2[`TLU_ASR_DATA_WIDTH-2:2]),
|
2249 |
|
|
.in3 (true_stickcmp3[`TLU_ASR_DATA_WIDTH-2:2]),
|
2250 |
|
|
.sel0 (tlu_tickcmp_sel[0]),
|
2251 |
|
|
.sel1 (tlu_tickcmp_sel[1]),
|
2252 |
|
|
.sel2 (tlu_tickcmp_sel[2]),
|
2253 |
|
|
.sel3 (tlu_tickcmp_sel[3]),
|
2254 |
|
|
.dout (stickcmp_data[`TLU_ASR_DATA_WIDTH-4:0])
|
2255 |
|
|
);
|
2256 |
|
|
//
|
2257 |
|
|
// mux for read
|
2258 |
|
|
mux4ds #(`TLU_ASR_DATA_WIDTH) mux_stickcmp_rdata (
|
2259 |
|
|
.in0 (true_stickcmp0[`TLU_ASR_DATA_WIDTH-1:0]),
|
2260 |
|
|
.in1 (true_stickcmp1[`TLU_ASR_DATA_WIDTH-1:0]),
|
2261 |
|
|
.in2 (true_stickcmp2[`TLU_ASR_DATA_WIDTH-1:0]),
|
2262 |
|
|
.in3 (true_stickcmp3[`TLU_ASR_DATA_WIDTH-1:0]),
|
2263 |
|
|
.sel0 (tlu_thrd_rsel_e[0]),
|
2264 |
|
|
.sel1 (tlu_thrd_rsel_e[1]),
|
2265 |
|
|
.sel2 (tlu_thrd_rsel_e[2]),
|
2266 |
|
|
.sel3 (tlu_thrd_rsel_e[3]),
|
2267 |
|
|
.dout (stickcmp_rdata[`TLU_ASR_DATA_WIDTH-1:0])
|
2268 |
|
|
);
|
2269 |
|
|
`endif // !`ifdef FPGA_SYN_1THREAD
|
2270 |
|
|
|
2271 |
|
|
//
|
2272 |
|
|
// evaluate for stickcmp match
|
2273 |
|
|
assign stick_match =
|
2274 |
|
|
(stickcmp_data[`TICKCMP_RANGE_HI:`TICKCMP_RANGE_LO] ==
|
2275 |
|
|
true_tick[60:0]);
|
2276 |
|
|
//
|
2277 |
|
|
// moved from tlu_tcl
|
2278 |
|
|
assign stickcmp_int[0] =
|
2279 |
|
|
stick_match & ~true_stickcmp0[`TICKCMP_INTDIS] & tlu_tickcmp_sel[0];
|
2280 |
|
|
assign stickcmp_int[1] =
|
2281 |
|
|
stick_match & ~true_stickcmp1[`TICKCMP_INTDIS] & tlu_tickcmp_sel[1];
|
2282 |
|
|
assign stickcmp_int[2] =
|
2283 |
|
|
stick_match & ~true_stickcmp2[`TICKCMP_INTDIS] & tlu_tickcmp_sel[2];
|
2284 |
|
|
assign stickcmp_int[3] =
|
2285 |
|
|
stick_match & ~true_stickcmp3[`TICKCMP_INTDIS] & tlu_tickcmp_sel[3];
|
2286 |
|
|
|
2287 |
|
|
//=========================================================================================
|
2288 |
|
|
// HTICK COMPARE for Threads
|
2289 |
|
|
//=========================================================================================
|
2290 |
|
|
// added for hypervisor support
|
2291 |
|
|
|
2292 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
2293 |
|
|
`else
|
2294 |
|
|
clken_buf clkbf_htcmp0 (
|
2295 |
|
|
.rclk (clk),
|
2296 |
|
|
.enb_l (tlu_htickcmp_en_l[0]),
|
2297 |
|
|
.tmb_l (se_l),
|
2298 |
|
|
.clk (htcmp0_clk)
|
2299 |
|
|
);
|
2300 |
|
|
`endif
|
2301 |
|
|
|
2302 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
2303 |
|
|
`else
|
2304 |
|
|
clken_buf clkbf_htcmp1 (
|
2305 |
|
|
.rclk (clk),
|
2306 |
|
|
.enb_l (tlu_htickcmp_en_l[1]),
|
2307 |
|
|
.tmb_l (se_l),
|
2308 |
|
|
.clk (htcmp1_clk)
|
2309 |
|
|
);
|
2310 |
|
|
`endif
|
2311 |
|
|
|
2312 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
2313 |
|
|
`else
|
2314 |
|
|
clken_buf clkbf_htcmp2 (
|
2315 |
|
|
.rclk (clk),
|
2316 |
|
|
.enb_l (tlu_htickcmp_en_l[2]),
|
2317 |
|
|
.tmb_l (se_l),
|
2318 |
|
|
.clk (htcmp2_clk)
|
2319 |
|
|
);
|
2320 |
|
|
`endif
|
2321 |
|
|
|
2322 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
2323 |
|
|
`else
|
2324 |
|
|
clken_buf clkbf_htcmp3 (
|
2325 |
|
|
.rclk (clk),
|
2326 |
|
|
.enb_l (tlu_htickcmp_en_l[3]),
|
2327 |
|
|
.tmb_l (se_l),
|
2328 |
|
|
.clk (htcmp3_clk)
|
2329 |
|
|
);
|
2330 |
|
|
`endif
|
2331 |
|
|
|
2332 |
|
|
// THREAD0
|
2333 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
2334 |
|
|
dffe_s #(`TLU_ASR_DATA_WIDTH-1) htickcmp0 (
|
2335 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
2336 |
|
|
.q (true_htickcmp0[`TLU_ASR_DATA_WIDTH-2:0]),
|
2337 |
|
|
.en (~(tlu_htickcmp_en_l[0])), .clk(clk),
|
2338 |
|
|
.se (se),
|
2339 |
|
|
.si (),
|
2340 |
|
|
.so ()
|
2341 |
|
|
);
|
2342 |
|
|
`else
|
2343 |
|
|
dff_s #(`TLU_ASR_DATA_WIDTH-1) htickcmp0 (
|
2344 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
2345 |
|
|
.q (true_htickcmp0[`TLU_ASR_DATA_WIDTH-2:0]),
|
2346 |
|
|
.clk (htcmp0_clk),
|
2347 |
|
|
.se (se),
|
2348 |
|
|
.si (),
|
2349 |
|
|
.so ()
|
2350 |
|
|
);
|
2351 |
|
|
`endif
|
2352 |
|
|
|
2353 |
|
|
// THREAD1
|
2354 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
2355 |
|
|
dffe_s #(`TLU_ASR_DATA_WIDTH-1) htickcmp1 (
|
2356 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
2357 |
|
|
.q (true_htickcmp1[`TLU_ASR_DATA_WIDTH-2:0]),
|
2358 |
|
|
.en (~(tlu_htickcmp_en_l[1])), .clk(clk),
|
2359 |
|
|
.se (se),
|
2360 |
|
|
.si (),
|
2361 |
|
|
.so ()
|
2362 |
|
|
);
|
2363 |
|
|
`else
|
2364 |
|
|
dff_s #(`TLU_ASR_DATA_WIDTH-1) htickcmp1 (
|
2365 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
2366 |
|
|
.q (true_htickcmp1[`TLU_ASR_DATA_WIDTH-2:0]),
|
2367 |
|
|
.clk (htcmp1_clk),
|
2368 |
|
|
.se (se),
|
2369 |
|
|
.si (),
|
2370 |
|
|
.so ()
|
2371 |
|
|
);
|
2372 |
|
|
`endif
|
2373 |
|
|
|
2374 |
|
|
// THREAD2
|
2375 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
2376 |
|
|
dffe_s #(`TLU_ASR_DATA_WIDTH-1) htickcmp2 (
|
2377 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
2378 |
|
|
.q (true_htickcmp2[`TLU_ASR_DATA_WIDTH-2:0]),
|
2379 |
|
|
.en (~(tlu_htickcmp_en_l[2])), .clk(clk),
|
2380 |
|
|
.se (se),
|
2381 |
|
|
.si (),
|
2382 |
|
|
.so ()
|
2383 |
|
|
);
|
2384 |
|
|
`else
|
2385 |
|
|
dff_s #(`TLU_ASR_DATA_WIDTH-1) htickcmp2 (
|
2386 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
2387 |
|
|
.q (true_htickcmp2[`TLU_ASR_DATA_WIDTH-2:0]),
|
2388 |
|
|
.clk (htcmp2_clk),
|
2389 |
|
|
.se (se),
|
2390 |
|
|
.si (),
|
2391 |
|
|
.so ()
|
2392 |
|
|
);
|
2393 |
|
|
`endif
|
2394 |
|
|
|
2395 |
|
|
// THREAD3
|
2396 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
2397 |
|
|
dffe_s #(`TLU_ASR_DATA_WIDTH-1) htickcmp3 (
|
2398 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
2399 |
|
|
.q (true_htickcmp3[`TLU_ASR_DATA_WIDTH-2:0]),
|
2400 |
|
|
.en (~(tlu_htickcmp_en_l[3])), .clk(clk),
|
2401 |
|
|
.se (se),
|
2402 |
|
|
.si (),
|
2403 |
|
|
.so ()
|
2404 |
|
|
);
|
2405 |
|
|
`else
|
2406 |
|
|
dff_s #(`TLU_ASR_DATA_WIDTH-1) htickcmp3 (
|
2407 |
|
|
.din (tlu_wsr_data_w[`TLU_ASR_DATA_WIDTH-2:0]),
|
2408 |
|
|
.q (true_htickcmp3[`TLU_ASR_DATA_WIDTH-2:0]),
|
2409 |
|
|
.clk (htcmp3_clk),
|
2410 |
|
|
.se (se),
|
2411 |
|
|
.si (),
|
2412 |
|
|
.so ()
|
2413 |
|
|
);
|
2414 |
|
|
`endif
|
2415 |
|
|
|
2416 |
|
|
|
2417 |
|
|
// Select 1/4 sources. Assume compare is independent of read
|
2418 |
|
|
// and thus needs separate mux
|
2419 |
|
|
`ifdef FPGA_SYN_1THREAD
|
2420 |
|
|
assign htickcmp_data[`TLU_ASR_DATA_WIDTH-4:0] = true_htickcmp0[`TLU_ASR_DATA_WIDTH-2:2];
|
2421 |
|
|
assign htickcmp_rdata[`TLU_ASR_DATA_WIDTH-2:0] = true_htickcmp0[`TLU_ASR_DATA_WIDTH-2:0];
|
2422 |
|
|
`else
|
2423 |
|
|
|
2424 |
|
|
mux4ds #(`TLU_ASR_DATA_WIDTH-3) mux_htickcmp_data (
|
2425 |
|
|
.in0 (true_htickcmp0[`TLU_ASR_DATA_WIDTH-2:2]),
|
2426 |
|
|
.in1 (true_htickcmp1[`TLU_ASR_DATA_WIDTH-2:2]),
|
2427 |
|
|
.in2 (true_htickcmp2[`TLU_ASR_DATA_WIDTH-2:2]),
|
2428 |
|
|
.in3 (true_htickcmp3[`TLU_ASR_DATA_WIDTH-2:2]),
|
2429 |
|
|
.sel0 (tlu_tickcmp_sel[0]),
|
2430 |
|
|
.sel1 (tlu_tickcmp_sel[1]),
|
2431 |
|
|
.sel2 (tlu_tickcmp_sel[2]),
|
2432 |
|
|
.sel3 (tlu_tickcmp_sel[3]),
|
2433 |
|
|
.dout (htickcmp_data[`TLU_ASR_DATA_WIDTH-4:0])
|
2434 |
|
|
);
|
2435 |
|
|
//
|
2436 |
|
|
// mux for read
|
2437 |
|
|
mux4ds #(`TLU_ASR_DATA_WIDTH-1) mux_htickcmp_rdata (
|
2438 |
|
|
.in0 (true_htickcmp0[`TLU_ASR_DATA_WIDTH-2:0]),
|
2439 |
|
|
.in1 (true_htickcmp1[`TLU_ASR_DATA_WIDTH-2:0]),
|
2440 |
|
|
.in2 (true_htickcmp2[`TLU_ASR_DATA_WIDTH-2:0]),
|
2441 |
|
|
.in3 (true_htickcmp3[`TLU_ASR_DATA_WIDTH-2:0]),
|
2442 |
|
|
.sel0 (tlu_thrd_rsel_e[0]),
|
2443 |
|
|
.sel1 (tlu_thrd_rsel_e[1]),
|
2444 |
|
|
.sel2 (tlu_thrd_rsel_e[2]),
|
2445 |
|
|
.sel3 (tlu_thrd_rsel_e[3]),
|
2446 |
|
|
.dout (htickcmp_rdata[`TLU_ASR_DATA_WIDTH-2:0])
|
2447 |
|
|
);
|
2448 |
|
|
`endif // !`ifdef FPGA_SYN_1THREAD
|
2449 |
|
|
|
2450 |
|
|
//
|
2451 |
|
|
// evaluate for htickcmp match
|
2452 |
|
|
assign tlu_htick_match =
|
2453 |
|
|
(htickcmp_data[`TICKCMP_RANGE_HI:`TICKCMP_RANGE_LO] ==
|
2454 |
|
|
true_tick[60:0]);
|
2455 |
|
|
//
|
2456 |
|
|
//=========================================================================================
|
2457 |
|
|
// HINTP REG for Threads
|
2458 |
|
|
//=========================================================================================
|
2459 |
|
|
// added for hypervisor support
|
2460 |
|
|
// modified for timing
|
2461 |
|
|
// creating clocks for accessing the hintp regs
|
2462 |
|
|
assign tlu_hintp_en_l_g[0] =
|
2463 |
|
|
~(tlu_set_hintp_g[0] | tlu_wr_hintp_g[0]);
|
2464 |
|
|
assign tlu_hintp_en_l_g[1] =
|
2465 |
|
|
~(tlu_set_hintp_g[1] | tlu_wr_hintp_g[1]);
|
2466 |
|
|
assign tlu_hintp_en_l_g[2] =
|
2467 |
|
|
~(tlu_set_hintp_g[2] | tlu_wr_hintp_g[2]);
|
2468 |
|
|
assign tlu_hintp_en_l_g[3] =
|
2469 |
|
|
~(tlu_set_hintp_g[3] | tlu_wr_hintp_g[3]);
|
2470 |
|
|
|
2471 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
2472 |
|
|
`else
|
2473 |
|
|
clken_buf clkbf_hintp0 (
|
2474 |
|
|
.rclk (clk),
|
2475 |
|
|
.enb_l (tlu_hintp_en_l_g[0]),
|
2476 |
|
|
.tmb_l (se_l),
|
2477 |
|
|
.clk (hintp0_clk)
|
2478 |
|
|
);
|
2479 |
|
|
`endif
|
2480 |
|
|
|
2481 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
2482 |
|
|
`else
|
2483 |
|
|
clken_buf clkbf_hintp1 (
|
2484 |
|
|
.rclk (clk),
|
2485 |
|
|
.enb_l (tlu_hintp_en_l_g[1]),
|
2486 |
|
|
.tmb_l (se_l),
|
2487 |
|
|
.clk (hintp1_clk)
|
2488 |
|
|
);
|
2489 |
|
|
`endif
|
2490 |
|
|
|
2491 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
2492 |
|
|
`else
|
2493 |
|
|
clken_buf clkbf_hintp2 (
|
2494 |
|
|
.rclk (clk),
|
2495 |
|
|
.enb_l (tlu_hintp_en_l_g[2]),
|
2496 |
|
|
.tmb_l (se_l),
|
2497 |
|
|
.clk (hintp2_clk)
|
2498 |
|
|
);
|
2499 |
|
|
`endif
|
2500 |
|
|
|
2501 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
2502 |
|
|
`else
|
2503 |
|
|
clken_buf clkbf_hintp3 (
|
2504 |
|
|
.rclk (clk),
|
2505 |
|
|
.enb_l (tlu_hintp_en_l_g[3]),
|
2506 |
|
|
.tmb_l (se_l),
|
2507 |
|
|
.clk (hintp3_clk)
|
2508 |
|
|
);
|
2509 |
|
|
`endif
|
2510 |
|
|
//
|
2511 |
|
|
// setting the value of hintp registers
|
2512 |
|
|
//
|
2513 |
|
|
// Thread 0
|
2514 |
|
|
// added for timing
|
2515 |
|
|
assign tlu_set_hintp_g[0] =
|
2516 |
|
|
tlu_set_hintp_sel_g[0] & tlu_htick_match;
|
2517 |
|
|
|
2518 |
|
|
// modified to reflect the physical implementation
|
2519 |
|
|
// assign hintp_din[0] =
|
2520 |
|
|
// (tlu_set_hintp_g[0])? tlu_set_hintp_g[0]: wsr_data_w[0];
|
2521 |
|
|
|
2522 |
|
|
mux2ds mx_hintp_din_0 (
|
2523 |
|
|
.in0 (tlu_set_hintp_g[0]),
|
2524 |
|
|
.in1 (wsr_data_w[0]),
|
2525 |
|
|
.sel0 (tlu_set_hintp_g[0]),
|
2526 |
|
|
.sel1 (~tlu_set_hintp_g[0]),
|
2527 |
|
|
.dout (hintp_din[0])
|
2528 |
|
|
);
|
2529 |
|
|
|
2530 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
2531 |
|
|
dffre_s dffr_hintp0 (
|
2532 |
|
|
.din (hintp_din[0]),
|
2533 |
|
|
.q (tlu_hintp[0]),
|
2534 |
|
|
.en (~(tlu_hintp_en_l_g[0])), .clk(clk),
|
2535 |
|
|
.rst (local_rst),
|
2536 |
|
|
.se (se),
|
2537 |
|
|
.si (),
|
2538 |
|
|
.so ()
|
2539 |
|
|
);
|
2540 |
|
|
`else
|
2541 |
|
|
dffr_s dffr_hintp0 (
|
2542 |
|
|
.din (hintp_din[0]),
|
2543 |
|
|
.q (tlu_hintp[0]),
|
2544 |
|
|
.clk (hintp0_clk),
|
2545 |
|
|
.rst (local_rst),
|
2546 |
|
|
.se (se),
|
2547 |
|
|
.si (),
|
2548 |
|
|
.so ()
|
2549 |
|
|
);
|
2550 |
|
|
`endif
|
2551 |
|
|
|
2552 |
|
|
// Thread 1
|
2553 |
|
|
// added for timing
|
2554 |
|
|
assign tlu_set_hintp_g[1] =
|
2555 |
|
|
tlu_set_hintp_sel_g[1] & tlu_htick_match;
|
2556 |
|
|
|
2557 |
|
|
// modified to reflect the physical implementation
|
2558 |
|
|
// assign hintp_din[1] =
|
2559 |
|
|
// (tlu_set_hintp_g[1])? tlu_set_hintp_g[1]: wsr_data_w[0];
|
2560 |
|
|
|
2561 |
|
|
mux2ds mx_hintp_din_1 (
|
2562 |
|
|
.in0 (tlu_set_hintp_g[1]),
|
2563 |
|
|
.in1 (wsr_data_w[0]),
|
2564 |
|
|
.sel0 (tlu_set_hintp_g[1]),
|
2565 |
|
|
.sel1 (~tlu_set_hintp_g[1]),
|
2566 |
|
|
.dout (hintp_din[1])
|
2567 |
|
|
);
|
2568 |
|
|
|
2569 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
2570 |
|
|
dffre_s dffr_hintp1 (
|
2571 |
|
|
.din (hintp_din[1]),
|
2572 |
|
|
.q (tlu_hintp[1]),
|
2573 |
|
|
.en (~(tlu_hintp_en_l_g[1])), .clk(clk),
|
2574 |
|
|
.rst (local_rst),
|
2575 |
|
|
.se (se),
|
2576 |
|
|
.si (),
|
2577 |
|
|
.so ()
|
2578 |
|
|
);
|
2579 |
|
|
`else
|
2580 |
|
|
dffr_s dffr_hintp1 (
|
2581 |
|
|
.din (hintp_din[1]),
|
2582 |
|
|
.q (tlu_hintp[1]),
|
2583 |
|
|
.clk (hintp1_clk),
|
2584 |
|
|
.rst (local_rst),
|
2585 |
|
|
.se (se),
|
2586 |
|
|
.si (),
|
2587 |
|
|
.so ()
|
2588 |
|
|
);
|
2589 |
|
|
`endif
|
2590 |
|
|
|
2591 |
|
|
// Thread 2
|
2592 |
|
|
// added for timing
|
2593 |
|
|
assign tlu_set_hintp_g[2] =
|
2594 |
|
|
tlu_set_hintp_sel_g[2] & tlu_htick_match;
|
2595 |
|
|
|
2596 |
|
|
// modified to reflect the physical implementation
|
2597 |
|
|
// assign hintp_din[2] =
|
2598 |
|
|
// (tlu_set_hintp_g[2])? tlu_set_hintp_g[2]: wsr_data_w[0];
|
2599 |
|
|
|
2600 |
|
|
mux2ds mx_hintp_din_2 (
|
2601 |
|
|
.in0 (tlu_set_hintp_g[2]),
|
2602 |
|
|
.in1 (wsr_data_w[0]),
|
2603 |
|
|
.sel0 (tlu_set_hintp_g[2]),
|
2604 |
|
|
.sel1 (~tlu_set_hintp_g[2]),
|
2605 |
|
|
.dout (hintp_din[2])
|
2606 |
|
|
);
|
2607 |
|
|
|
2608 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
2609 |
|
|
dffre_s dffr_hintp2 (
|
2610 |
|
|
.din (hintp_din[2]),
|
2611 |
|
|
.q (tlu_hintp[2]),
|
2612 |
|
|
.en (~(tlu_hintp_en_l_g[2])), .clk(clk),
|
2613 |
|
|
.rst (local_rst),
|
2614 |
|
|
.se (se),
|
2615 |
|
|
.si (),
|
2616 |
|
|
.so ()
|
2617 |
|
|
);
|
2618 |
|
|
`else
|
2619 |
|
|
dffr_s dffr_hintp2 (
|
2620 |
|
|
.din (hintp_din[2]),
|
2621 |
|
|
.q (tlu_hintp[2]),
|
2622 |
|
|
.clk (hintp2_clk),
|
2623 |
|
|
.rst (local_rst),
|
2624 |
|
|
.se (se),
|
2625 |
|
|
.si (),
|
2626 |
|
|
.so ()
|
2627 |
|
|
);
|
2628 |
|
|
`endif
|
2629 |
|
|
|
2630 |
|
|
// Thread 3
|
2631 |
|
|
// added for timing
|
2632 |
|
|
assign tlu_set_hintp_g[3] =
|
2633 |
|
|
tlu_set_hintp_sel_g[3] & tlu_htick_match;
|
2634 |
|
|
|
2635 |
|
|
// modified to reflect the physical implementation
|
2636 |
|
|
// assign hintp_din[3] =
|
2637 |
|
|
// (tlu_set_hintp_g[3])? tlu_set_hintp_g[3]: wsr_data_w[0];
|
2638 |
|
|
|
2639 |
|
|
mux2ds mx_hintp_din_3 (
|
2640 |
|
|
.in0 (tlu_set_hintp_g[3]),
|
2641 |
|
|
.in1 (wsr_data_w[0]),
|
2642 |
|
|
.sel0 (tlu_set_hintp_g[3]),
|
2643 |
|
|
.sel1 (~tlu_set_hintp_g[3]),
|
2644 |
|
|
.dout (hintp_din[3])
|
2645 |
|
|
);
|
2646 |
|
|
|
2647 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
2648 |
|
|
dffre_s dffr_hintp3 (
|
2649 |
|
|
.din (hintp_din[3]),
|
2650 |
|
|
.q (tlu_hintp[3]),
|
2651 |
|
|
.en (~(tlu_hintp_en_l_g[3])), .clk(clk),
|
2652 |
|
|
.rst (local_rst),
|
2653 |
|
|
.se (se),
|
2654 |
|
|
.si (),
|
2655 |
|
|
.so ()
|
2656 |
|
|
);
|
2657 |
|
|
`else
|
2658 |
|
|
dffr_s dffr_hintp3 (
|
2659 |
|
|
.din (hintp_din[3]),
|
2660 |
|
|
.q (tlu_hintp[3]),
|
2661 |
|
|
.clk (hintp3_clk),
|
2662 |
|
|
.rst (local_rst),
|
2663 |
|
|
.se (se),
|
2664 |
|
|
.si (),
|
2665 |
|
|
.so ()
|
2666 |
|
|
);
|
2667 |
|
|
`endif
|
2668 |
|
|
|
2669 |
|
|
//=========================================================================================
|
2670 |
|
|
// DONE/RETRY
|
2671 |
|
|
//=========================================================================================
|
2672 |
|
|
|
2673 |
|
|
// PC/nPC will be updated by pc/npc from IFU,
|
2674 |
|
|
// OR, Done/Retry which reads TSA in E stage. Execution of Done/Retry will
|
2675 |
|
|
// put pc/npc temporarily in bypass flop which will then update actual pc/npc
|
2676 |
|
|
// in g. Update of pc/npc by inst_in_w or done/retry thus becomes aligned.
|
2677 |
|
|
// recoded due to lint violations - individualized the components
|
2678 |
|
|
/*
|
2679 |
|
|
dff_s #(`TLU_TSA_WIDTH) poptsa_m (
|
2680 |
|
|
.din (tsa_rdata[`TLU_TSA_WIDTH-1:0]),
|
2681 |
|
|
.q (tsa_data_m[`TLU_TSA_WIDTH-1:0]),
|
2682 |
|
|
.clk (clk),
|
2683 |
|
|
.se (se),
|
2684 |
|
|
.si (),
|
2685 |
|
|
.so ()
|
2686 |
|
|
);
|
2687 |
|
|
//
|
2688 |
|
|
// added, modified for hypervisor and timing
|
2689 |
|
|
assign dnrtry_pstate_m =
|
2690 |
|
|
{2'b0, // old IG, MG - replaced by global register
|
2691 |
|
|
tsa_data_m[`TSA_PSTATE_VRANGE2_HI:`TSA_PSTATE_VRANGE2_LO],
|
2692 |
|
|
2'b0, // memory model has been change to TSO only - bug 2588
|
2693 |
|
|
1'b0, // old RED - replaced by hpstate.red
|
2694 |
|
|
tsa_data_m[`TSA_PSTATE_VRANGE1_HI:`TSA_PSTATE_VRANGE1_LO],
|
2695 |
|
|
1'b0}; // old AG - replaced by global register
|
2696 |
|
|
|
2697 |
|
|
dff_s #(12) dff_pstate_g (
|
2698 |
|
|
.din (dnrtry_pstate_m[`PSTATE_TRUE_WIDTH-1:0]),
|
2699 |
|
|
.q (dnrtry_pstate[`PSTATE_TRUE_WIDTH-1:0]),
|
2700 |
|
|
.clk (clk),
|
2701 |
|
|
.se (se),
|
2702 |
|
|
.si (),
|
2703 |
|
|
.so ()
|
2704 |
|
|
);
|
2705 |
|
|
*/
|
2706 |
|
|
// recoded due to lint violation
|
2707 |
|
|
|
2708 |
|
|
dff_s #(`WSR_PSTATE_VR_WIDTH) dff_dnrtry_pstate_m (
|
2709 |
|
|
.din ({tsa_rdata[`TSA_PSTATE_VRANGE2_HI:`TSA_PSTATE_VRANGE2_LO],
|
2710 |
|
|
tsa_rdata[`TSA_PSTATE_VRANGE1_HI:`TSA_PSTATE_VRANGE1_LO]}),
|
2711 |
|
|
.q (dnrtry_pstate_m[`WSR_PSTATE_VR_WIDTH-1:0]),
|
2712 |
|
|
.clk (clk),
|
2713 |
|
|
.se (se),
|
2714 |
|
|
.si (),
|
2715 |
|
|
.so ()
|
2716 |
|
|
);
|
2717 |
|
|
|
2718 |
|
|
dff_s #(`WSR_PSTATE_VR_WIDTH) dff_pstate_g (
|
2719 |
|
|
.din (dnrtry_pstate_m[`WSR_PSTATE_VR_WIDTH-1:0]),
|
2720 |
|
|
.q (dnrtry_pstate_g[`WSR_PSTATE_VR_WIDTH-1:0]),
|
2721 |
|
|
.clk (clk),
|
2722 |
|
|
.se (se),
|
2723 |
|
|
.si (),
|
2724 |
|
|
.so ()
|
2725 |
|
|
);
|
2726 |
|
|
|
2727 |
|
|
dff_s #(`WSR_PSTATE_VR_WIDTH) dff_pstate_w2 (
|
2728 |
|
|
.din (dnrtry_pstate_g[`WSR_PSTATE_VR_WIDTH-1:0]),
|
2729 |
|
|
.q (dnrtry_pstate_w2[`WSR_PSTATE_VR_WIDTH-1:0]),
|
2730 |
|
|
.clk (clk),
|
2731 |
|
|
.se (se),
|
2732 |
|
|
.si (),
|
2733 |
|
|
.so ()
|
2734 |
|
|
);
|
2735 |
|
|
// assign dnrtry_pstate_m[`WSR_PSTATE_VR_WIDTH-1:0] =
|
2736 |
|
|
// {tsa_data_m[`TSA_PSTATE_VRANGE2_HI:`TSA_PSTATE_VRANGE2_LO],
|
2737 |
|
|
// tsa_data_m[`TSA_PSTATE_VRANGE1_HI:`TSA_PSTATE_VRANGE1_LO]};
|
2738 |
|
|
//
|
2739 |
|
|
// reading hpstate from tsa for recovery
|
2740 |
|
|
// recoded due to lint violations
|
2741 |
|
|
|
2742 |
|
|
dff_s #(`TSA_HTSTATE_WIDTH) dff_tsa_dnrtry_hpstate_m (
|
2743 |
|
|
// .din (tsa_rdata[`TLU_HTSTATE_HI:`TLU_HTSTATE_LO]),
|
2744 |
|
|
.din (tsa_rdata[`TLU_RD_HTSTATE_HI:`TLU_RD_HTSTATE_LO]),
|
2745 |
|
|
.q (tsa_dnrtry_hpstate_m[`TSA_HTSTATE_WIDTH-1:0]),
|
2746 |
|
|
.clk (clk),
|
2747 |
|
|
.se (se),
|
2748 |
|
|
.si (),
|
2749 |
|
|
.so ()
|
2750 |
|
|
);
|
2751 |
|
|
|
2752 |
|
|
dff_s #(`TSA_HTSTATE_WIDTH) dff_tsa_dnrtry_hpstate_g (
|
2753 |
|
|
// .din (tsa_data_m[`TLU_HTSTATE_HI:`TLU_HTSTATE_LO]),
|
2754 |
|
|
.din (tsa_dnrtry_hpstate_m[`TSA_HTSTATE_WIDTH-1:0]),
|
2755 |
|
|
.q (tsa_dnrtry_hpstate_g[`TSA_HTSTATE_WIDTH-1:0]),
|
2756 |
|
|
.clk (clk),
|
2757 |
|
|
.se (se),
|
2758 |
|
|
.si (),
|
2759 |
|
|
.so ()
|
2760 |
|
|
);
|
2761 |
|
|
//
|
2762 |
|
|
// added for timing
|
2763 |
|
|
dff_s #(`TSA_HTSTATE_WIDTH) dff_tsa_dnrtry_hpstate_w2 (
|
2764 |
|
|
.din (tsa_dnrtry_hpstate_g[`TSA_HTSTATE_WIDTH-1:0]),
|
2765 |
|
|
.q (tsa_dnrtry_hpstate_w2[`TSA_HTSTATE_WIDTH-1:0]),
|
2766 |
|
|
.clk (clk),
|
2767 |
|
|
.se (se),
|
2768 |
|
|
.si (),
|
2769 |
|
|
.so ()
|
2770 |
|
|
);
|
2771 |
|
|
|
2772 |
|
|
// reading value of original global registers from tsa for recovery
|
2773 |
|
|
// recoded due to lint cleanup
|
2774 |
|
|
// assign dnrtry_global_m = tsa_data_m[`TLU_GL_HI:`TLU_GL_LO];
|
2775 |
|
|
|
2776 |
|
|
dff_s #(`TSA_GLOBAL_WIDTH) dff_dnrtry_global_m (
|
2777 |
|
|
.din (tsa_rdata[`TLU_GL_HI:`TLU_GL_LO]),
|
2778 |
|
|
.q (dnrtry_global_m[`TSA_GLOBAL_WIDTH-1:0]),
|
2779 |
|
|
.clk (clk),
|
2780 |
|
|
.se (se),
|
2781 |
|
|
.si (),
|
2782 |
|
|
.so ()
|
2783 |
|
|
);
|
2784 |
|
|
|
2785 |
|
|
dff_s #(`TSA_GLOBAL_WIDTH) dff_global_g (
|
2786 |
|
|
.din (dnrtry_global_m[`TSA_GLOBAL_WIDTH-1:0]),
|
2787 |
|
|
.q (tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]),
|
2788 |
|
|
.clk (clk),
|
2789 |
|
|
.se (se),
|
2790 |
|
|
.si (),
|
2791 |
|
|
.so ()
|
2792 |
|
|
);
|
2793 |
|
|
//
|
2794 |
|
|
/* logic moved to tlu_misctl
|
2795 |
|
|
// added due to lint violations
|
2796 |
|
|
dff_s #(47) dff_tsa_pc_m (
|
2797 |
|
|
.din (tsa_rdata[`TLU_PC_HI:`TLU_PC_LO]),
|
2798 |
|
|
.q (tsa_pc_m[46:0]),
|
2799 |
|
|
.clk (clk),
|
2800 |
|
|
.se (se),
|
2801 |
|
|
.si (),
|
2802 |
|
|
.so ()
|
2803 |
|
|
);
|
2804 |
|
|
|
2805 |
|
|
dff_s #(47) dff_tsa_npc_m (
|
2806 |
|
|
.din (tsa_rdata[`TLU_NPC_HI:`TLU_NPC_LO]),
|
2807 |
|
|
.q (tsa_npc_m[46:0]),
|
2808 |
|
|
.clk (clk),
|
2809 |
|
|
.se (se),
|
2810 |
|
|
.si (),
|
2811 |
|
|
.so ()
|
2812 |
|
|
);
|
2813 |
|
|
|
2814 |
|
|
// pstate may have to be staged by an additional cycle.
|
2815 |
|
|
assign dnrtry_pc[48:0] = {tsa_pc_m[46:0],2'b00};
|
2816 |
|
|
assign dnrtry_npc[48:0] = {tsa_npc_m[46:0],2'b00};
|
2817 |
|
|
*/
|
2818 |
|
|
|
2819 |
|
|
//=========================================================================================
|
2820 |
|
|
// PC/nPC
|
2821 |
|
|
//=========================================================================================
|
2822 |
|
|
|
2823 |
|
|
// TRUE PC/NPC. AN INSTRUCTION'S PC/NPC IS VISIBLE IN W2.
|
2824 |
|
|
// F:S:D:E:M:G:W2
|
2825 |
|
|
// Modified by Done/Retry and inst
|
2826 |
|
|
|
2827 |
|
|
/* logic moved to tlu_misctl
|
2828 |
|
|
// On done, npc will become pc.
|
2829 |
|
|
// modified due to bug 3017
|
2830 |
|
|
// pc width increase from 48 -> 49 bits
|
2831 |
|
|
mux3ds #(49) finalpc_sel_m (
|
2832 |
|
|
.in0 (dnrtry_pc[48:0]),
|
2833 |
|
|
.in1 (dnrtry_npc[48:0]),
|
2834 |
|
|
.in2 (ifu_tlu_pc_m[48:0]),
|
2835 |
|
|
.sel0 (tlu_retry_inst_m),
|
2836 |
|
|
.sel1 (tlu_done_inst_m),
|
2837 |
|
|
.sel2 (tlu_dnrtry_inst_m_l),
|
2838 |
|
|
.dout (pc_new[48:0])
|
2839 |
|
|
);
|
2840 |
|
|
// On done, npc will stay npc. The valid to the IFU will
|
2841 |
|
|
// not be signaled along with npc for a done.
|
2842 |
|
|
// modified due to bug 3017
|
2843 |
|
|
// pc width increase from 48 -> 49 bits
|
2844 |
|
|
mux2ds #(49) finalnpc_sel_m (
|
2845 |
|
|
.in0 (dnrtry_npc[48:0]),
|
2846 |
|
|
.in1 (ifu_tlu_npc_m[48:0]),
|
2847 |
|
|
.sel0 (~tlu_dnrtry_inst_m_l),
|
2848 |
|
|
.sel1 (tlu_dnrtry_inst_m_l),
|
2849 |
|
|
.dout (npc_new[48:0])
|
2850 |
|
|
);
|
2851 |
|
|
|
2852 |
|
|
dff_s #(49) dff_pc_new_w (
|
2853 |
|
|
.din (pc_new[48:0]),
|
2854 |
|
|
.q (pc_new_w[48:0]),
|
2855 |
|
|
.clk (clk),
|
2856 |
|
|
.se (se),
|
2857 |
|
|
.si (),
|
2858 |
|
|
.so ()
|
2859 |
|
|
);
|
2860 |
|
|
|
2861 |
|
|
dff_s #(49) dff_npc_new_w (
|
2862 |
|
|
.din (npc_new[48:0]),
|
2863 |
|
|
.q (npc_new_w[48:0]),
|
2864 |
|
|
.clk (clk),
|
2865 |
|
|
.se (se),
|
2866 |
|
|
.si (),
|
2867 |
|
|
.so ()
|
2868 |
|
|
);
|
2869 |
|
|
*/
|
2870 |
|
|
//
|
2871 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
2872 |
|
|
`else
|
2873 |
|
|
clken_buf clkbf_pc0 (
|
2874 |
|
|
.rclk (clk),
|
2875 |
|
|
.enb_l (tlu_update_pc_l_w[0]),
|
2876 |
|
|
.tmb_l (se_l),
|
2877 |
|
|
.clk (pc0_clk)
|
2878 |
|
|
);
|
2879 |
|
|
`endif
|
2880 |
|
|
|
2881 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
2882 |
|
|
`else
|
2883 |
|
|
clken_buf clkbf_pc1 (
|
2884 |
|
|
.rclk (clk),
|
2885 |
|
|
.enb_l (tlu_update_pc_l_w[1]),
|
2886 |
|
|
.tmb_l (se_l),
|
2887 |
|
|
.clk (pc1_clk)
|
2888 |
|
|
);
|
2889 |
|
|
`endif
|
2890 |
|
|
|
2891 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
2892 |
|
|
`else
|
2893 |
|
|
clken_buf clkbf_pc2 (
|
2894 |
|
|
.rclk (clk),
|
2895 |
|
|
.enb_l (tlu_update_pc_l_w[2]),
|
2896 |
|
|
.tmb_l (se_l),
|
2897 |
|
|
.clk (pc2_clk)
|
2898 |
|
|
);
|
2899 |
|
|
`endif
|
2900 |
|
|
|
2901 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
2902 |
|
|
`else
|
2903 |
|
|
clken_buf clkbf_pc3 (
|
2904 |
|
|
.rclk (clk),
|
2905 |
|
|
.enb_l (tlu_update_pc_l_w[3]),
|
2906 |
|
|
.tmb_l (se_l),
|
2907 |
|
|
.clk (pc3_clk)
|
2908 |
|
|
);
|
2909 |
|
|
`endif
|
2910 |
|
|
//
|
2911 |
|
|
// modified for bug 3017
|
2912 |
|
|
// all pc width has been increased from 48 -> 49 bits
|
2913 |
|
|
// Thread 0
|
2914 |
|
|
//
|
2915 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
2916 |
|
|
dffe_s #(49) pc0_true (
|
2917 |
|
|
.din (tlu_pc_new_w[48:0]),
|
2918 |
|
|
.q (true_pc0[48:0]),
|
2919 |
|
|
.en (~(tlu_update_pc_l_w[0])), .clk(clk),
|
2920 |
|
|
.se (se),
|
2921 |
|
|
.si (),
|
2922 |
|
|
.so ()
|
2923 |
|
|
);
|
2924 |
|
|
`else
|
2925 |
|
|
dff_s #(49) pc0_true (
|
2926 |
|
|
.din (tlu_pc_new_w[48:0]),
|
2927 |
|
|
.q (true_pc0[48:0]),
|
2928 |
|
|
.clk (pc0_clk),
|
2929 |
|
|
.se (se),
|
2930 |
|
|
.si (),
|
2931 |
|
|
.so ()
|
2932 |
|
|
);
|
2933 |
|
|
`endif
|
2934 |
|
|
|
2935 |
|
|
// update_pc will be used for both pc and npc - in this case
|
2936 |
|
|
// npc will contain gibberish but it's okay.
|
2937 |
|
|
// modified to avert area growth
|
2938 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
2939 |
|
|
dffe_s #(49) npc0_true (
|
2940 |
|
|
.din (tlu_npc_new_w[48:0]),
|
2941 |
|
|
.q (true_npc0[48:0]),
|
2942 |
|
|
.en (~(tlu_update_pc_l_w[0])), .clk(clk),
|
2943 |
|
|
.se (se),
|
2944 |
|
|
.si (),
|
2945 |
|
|
.so ()
|
2946 |
|
|
);
|
2947 |
|
|
`else
|
2948 |
|
|
dff_s #(49) npc0_true (
|
2949 |
|
|
.din (tlu_npc_new_w[48:0]),
|
2950 |
|
|
.q (true_npc0[48:0]),
|
2951 |
|
|
.clk (pc0_clk),
|
2952 |
|
|
.se (se),
|
2953 |
|
|
.si (),
|
2954 |
|
|
.so ()
|
2955 |
|
|
);
|
2956 |
|
|
`endif
|
2957 |
|
|
//
|
2958 |
|
|
// THREAD1
|
2959 |
|
|
//
|
2960 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
2961 |
|
|
dffe_s #(49) pc1_true (
|
2962 |
|
|
.din (tlu_pc_new_w[48:0]),
|
2963 |
|
|
.q (true_pc1[48:0]),
|
2964 |
|
|
.en (~(tlu_update_pc_l_w[1])), .clk(clk),
|
2965 |
|
|
.se (se),
|
2966 |
|
|
.si (),
|
2967 |
|
|
.so ()
|
2968 |
|
|
);
|
2969 |
|
|
`else
|
2970 |
|
|
dff_s #(49) pc1_true (
|
2971 |
|
|
.din (tlu_pc_new_w[48:0]),
|
2972 |
|
|
.q (true_pc1[48:0]),
|
2973 |
|
|
.clk (pc1_clk),
|
2974 |
|
|
.se (se),
|
2975 |
|
|
.si (),
|
2976 |
|
|
.so ()
|
2977 |
|
|
);
|
2978 |
|
|
`endif
|
2979 |
|
|
|
2980 |
|
|
// update_pc will be used for both pc and npc - in this case
|
2981 |
|
|
// npc will contain gibberish but it's okay.
|
2982 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
2983 |
|
|
dffe_s #(49) npc1_true (
|
2984 |
|
|
.din (tlu_npc_new_w[48:0]),
|
2985 |
|
|
.q (true_npc1[48:0]),
|
2986 |
|
|
.en (~(tlu_update_pc_l_w[1])), .clk(clk),
|
2987 |
|
|
.se (se),
|
2988 |
|
|
.si (),
|
2989 |
|
|
.so ()
|
2990 |
|
|
);
|
2991 |
|
|
`else
|
2992 |
|
|
dff_s #(49) npc1_true (
|
2993 |
|
|
.din (tlu_npc_new_w[48:0]),
|
2994 |
|
|
.q (true_npc1[48:0]),
|
2995 |
|
|
.clk (pc1_clk),
|
2996 |
|
|
.se (se),
|
2997 |
|
|
.si (),
|
2998 |
|
|
.so ()
|
2999 |
|
|
);
|
3000 |
|
|
`endif
|
3001 |
|
|
//
|
3002 |
|
|
// THREAD2
|
3003 |
|
|
//
|
3004 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
3005 |
|
|
dffe_s #(49) pc2_true (
|
3006 |
|
|
.din (tlu_pc_new_w[48:0]),
|
3007 |
|
|
.q (true_pc2[48:0]),
|
3008 |
|
|
.en (~(tlu_update_pc_l_w[2])), .clk(clk),
|
3009 |
|
|
.se (se),
|
3010 |
|
|
.si (),
|
3011 |
|
|
.so ()
|
3012 |
|
|
);
|
3013 |
|
|
`else
|
3014 |
|
|
dff_s #(49) pc2_true (
|
3015 |
|
|
.din (tlu_pc_new_w[48:0]),
|
3016 |
|
|
.q (true_pc2[48:0]),
|
3017 |
|
|
.clk (pc2_clk),
|
3018 |
|
|
.se (se),
|
3019 |
|
|
.si (),
|
3020 |
|
|
.so ()
|
3021 |
|
|
);
|
3022 |
|
|
`endif
|
3023 |
|
|
|
3024 |
|
|
// update_pc will be used for both pc and npc - in this case
|
3025 |
|
|
// npc will contain gibberish but it's okay.
|
3026 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
3027 |
|
|
dffe_s #(49) npc2_true (
|
3028 |
|
|
.din (tlu_npc_new_w[48:0]),
|
3029 |
|
|
.q (true_npc2[48:0]),
|
3030 |
|
|
.en (~(tlu_update_pc_l_w[2])), .clk(clk),
|
3031 |
|
|
.se (se),
|
3032 |
|
|
.si (),
|
3033 |
|
|
.so ()
|
3034 |
|
|
);
|
3035 |
|
|
`else
|
3036 |
|
|
dff_s #(49) npc2_true (
|
3037 |
|
|
.din (tlu_npc_new_w[48:0]),
|
3038 |
|
|
.q (true_npc2[48:0]),
|
3039 |
|
|
.clk (pc2_clk),
|
3040 |
|
|
.se (se),
|
3041 |
|
|
.si (),
|
3042 |
|
|
.so ()
|
3043 |
|
|
);
|
3044 |
|
|
`endif
|
3045 |
|
|
//
|
3046 |
|
|
// THREAD3
|
3047 |
|
|
//
|
3048 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
3049 |
|
|
dffe_s #(49) pc3_true (
|
3050 |
|
|
.din (tlu_pc_new_w[48:0]),
|
3051 |
|
|
.q (true_pc3[48:0]),
|
3052 |
|
|
.en (~(tlu_update_pc_l_w[3])), .clk(clk),
|
3053 |
|
|
.se (se),
|
3054 |
|
|
.si (),
|
3055 |
|
|
.so ()
|
3056 |
|
|
);
|
3057 |
|
|
`else
|
3058 |
|
|
dff_s #(49) pc3_true (
|
3059 |
|
|
.din (tlu_pc_new_w[48:0]),
|
3060 |
|
|
.q (true_pc3[48:0]),
|
3061 |
|
|
.clk (pc3_clk),
|
3062 |
|
|
.se (se),
|
3063 |
|
|
.si (),
|
3064 |
|
|
.so ()
|
3065 |
|
|
);
|
3066 |
|
|
`endif
|
3067 |
|
|
|
3068 |
|
|
// update_pc will be used for both pc and npc - in this case
|
3069 |
|
|
// npc will contain gibberish but it's okay.
|
3070 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
3071 |
|
|
dffe_s #(49) npc3_true (
|
3072 |
|
|
.din (tlu_npc_new_w[48:0]),
|
3073 |
|
|
.q (true_npc3[48:0]),
|
3074 |
|
|
.en (~(tlu_update_pc_l_w[3])), .clk(clk),
|
3075 |
|
|
.se (se),
|
3076 |
|
|
.si (),
|
3077 |
|
|
.so ()
|
3078 |
|
|
);
|
3079 |
|
|
`else
|
3080 |
|
|
dff_s #(49) npc3_true (
|
3081 |
|
|
.din (tlu_npc_new_w[48:0]),
|
3082 |
|
|
.q (true_npc3[48:0]),
|
3083 |
|
|
.clk (pc3_clk),
|
3084 |
|
|
.se (se),
|
3085 |
|
|
.si (),
|
3086 |
|
|
.so ()
|
3087 |
|
|
);
|
3088 |
|
|
`endif
|
3089 |
|
|
|
3090 |
|
|
//=========================================================================================
|
3091 |
|
|
// Generating Trap Vector
|
3092 |
|
|
//=========================================================================================
|
3093 |
|
|
//
|
3094 |
|
|
// Normal Trap Processing.
|
3095 |
|
|
mux2ds mux_pc_bit15_sel (
|
3096 |
|
|
.in0 (tlu_tl_gt_0_w2),
|
3097 |
|
|
.in1 (htba_data[0]),
|
3098 |
|
|
.sel0 (~tlu_trap_hpstate_enb),
|
3099 |
|
|
.sel1 (tlu_trap_hpstate_enb),
|
3100 |
|
|
.dout (pc_bit15_sel)
|
3101 |
|
|
);
|
3102 |
|
|
//
|
3103 |
|
|
// modified to help speed up simulation time
|
3104 |
|
|
//
|
3105 |
|
|
assign tlu_rstvaddr_base[33:0] = `RSTVADDR_BASE;
|
3106 |
|
|
mux3ds #(34) nrmlpc_sel_w2 (
|
3107 |
|
|
.in0 (tlu_rstvaddr_base[33:0]),
|
3108 |
|
|
.in1 ({tba_data[32:0], tlu_tl_gt_0_w2}),
|
3109 |
|
|
.in2 ({htba_data[33:1], pc_bit15_sel}),
|
3110 |
|
|
.sel0 (tlu_pc_mxsel_w2[0]),
|
3111 |
|
|
.sel1 (tlu_pc_mxsel_w2[1]),
|
3112 |
|
|
.sel2 (tlu_pc_mxsel_w2[2]),
|
3113 |
|
|
.dout (partial_trap_pc_w2[33:0])
|
3114 |
|
|
);
|
3115 |
|
|
|
3116 |
|
|
assign tlu_partial_trap_pc_w1[33:0] = partial_trap_pc_w2[33:0];
|
3117 |
|
|
|
3118 |
|
|
// restore pc/npc select
|
3119 |
|
|
// true pc muxed into restore pc; previously restore_pcx was muxed in.
|
3120 |
|
|
// modified due to bug 3017
|
3121 |
|
|
`ifdef FPGA_SYN_1THREAD
|
3122 |
|
|
assign restore_pc_w2[48:0] = true_pc0[48:0];
|
3123 |
|
|
assign restore_npc_w2[48:0] = true_npc0[48:0];
|
3124 |
|
|
`else
|
3125 |
|
|
|
3126 |
|
|
mux4ds #(98) trprsel (
|
3127 |
|
|
.in0 ({true_pc0[48:0],true_npc0[48:0]}),
|
3128 |
|
|
.in1 ({true_pc1[48:0],true_npc1[48:0]}),
|
3129 |
|
|
.in2 ({true_pc2[48:0],true_npc2[48:0]}),
|
3130 |
|
|
.in3 ({true_pc3[48:0],true_npc3[48:0]}),
|
3131 |
|
|
.sel0 (tlu_thrd_wsel_w2[0]),
|
3132 |
|
|
.sel1 (tlu_thrd_wsel_w2[1]),
|
3133 |
|
|
.sel2 (tlu_thrd_wsel_w2[2]),
|
3134 |
|
|
.sel3 (tlu_thrd_wsel_w2[3]),
|
3135 |
|
|
.dout ({restore_pc_w2[48:0],restore_npc_w2[48:0]})
|
3136 |
|
|
);
|
3137 |
|
|
`endif // !`ifdef FPGA_SYN_1THREAD
|
3138 |
|
|
|
3139 |
|
|
//
|
3140 |
|
|
// the matching of the w1 and w2 is intentional
|
3141 |
|
|
assign tlu_restore_pc_w1[48:0] = restore_pc_w2[48:0];
|
3142 |
|
|
assign tlu_restore_npc_w1[48:0] = restore_npc_w2[48:0];
|
3143 |
|
|
|
3144 |
|
|
//=========================================================================================
|
3145 |
|
|
// TAP PC OBSERVABILITY
|
3146 |
|
|
//=========================================================================================
|
3147 |
|
|
//
|
3148 |
|
|
// modified due to spec change
|
3149 |
|
|
// shadow scan
|
3150 |
|
|
// thread 0 data
|
3151 |
|
|
assign sscan_data_test0[`TDP_SSCAN_WIDTH-1:0] =
|
3152 |
|
|
{true_hpstate0[2:0],
|
3153 |
|
|
true_pstate0[`PSTATE_PRIV],
|
3154 |
|
|
true_pstate0[`PSTATE_IE],
|
3155 |
|
|
true_pc0[47:2]};
|
3156 |
|
|
//
|
3157 |
|
|
// thread 1 data
|
3158 |
|
|
assign sscan_data_test1[`TDP_SSCAN_WIDTH-1:0] =
|
3159 |
|
|
{true_hpstate1[2:0],
|
3160 |
|
|
true_pstate1[`PSTATE_PRIV],
|
3161 |
|
|
true_pstate1[`PSTATE_IE],
|
3162 |
|
|
true_pc1[47:2]};
|
3163 |
|
|
//
|
3164 |
|
|
// thread 2 data
|
3165 |
|
|
assign sscan_data_test2[`TDP_SSCAN_WIDTH-1:0] =
|
3166 |
|
|
{true_hpstate2[2:0],
|
3167 |
|
|
true_pstate2[`PSTATE_PRIV],
|
3168 |
|
|
true_pstate2[`PSTATE_IE],
|
3169 |
|
|
true_pc2[47:2]};
|
3170 |
|
|
//
|
3171 |
|
|
// thread 3 data
|
3172 |
|
|
assign sscan_data_test3[`TDP_SSCAN_WIDTH-1:0] =
|
3173 |
|
|
{true_hpstate3[2:0],
|
3174 |
|
|
true_pstate3[`PSTATE_PRIV],
|
3175 |
|
|
true_pstate3[`PSTATE_IE],
|
3176 |
|
|
true_pc3[47:2]};
|
3177 |
|
|
//
|
3178 |
|
|
`ifdef FPGA_SYN_1THREAD
|
3179 |
|
|
assign tdp_sscan_test_data[`TDP_SSCAN_WIDTH-1:0] = sscan_data_test0[`TDP_SSCAN_WIDTH-1:0];
|
3180 |
|
|
`else
|
3181 |
|
|
|
3182 |
|
|
mux4ds #(`TDP_SSCAN_WIDTH) mx_sscan_test_data (
|
3183 |
|
|
.in0 (sscan_data_test0[`TDP_SSCAN_WIDTH-1:0]),
|
3184 |
|
|
.in1 (sscan_data_test1[`TDP_SSCAN_WIDTH-1:0]),
|
3185 |
|
|
.in2 (sscan_data_test2[`TDP_SSCAN_WIDTH-1:0]),
|
3186 |
|
|
.in3 (sscan_data_test3[`TDP_SSCAN_WIDTH-1:0]),
|
3187 |
|
|
.sel0 (sscan_tid_sel[0]),
|
3188 |
|
|
.sel1 (sscan_tid_sel[1]),
|
3189 |
|
|
.sel2 (sscan_tid_sel[2]),
|
3190 |
|
|
.sel3 (sscan_tid_sel[3]),
|
3191 |
|
|
.dout (tdp_sscan_test_data[`TDP_SSCAN_WIDTH-1:0])
|
3192 |
|
|
);
|
3193 |
|
|
`endif // !`ifdef FPGA_SYN_1THREAD
|
3194 |
|
|
|
3195 |
|
|
assign sscan_tid_sel[`TLU_THRD_NUM-1:0] = ctu_sscan_tid[`TLU_THRD_NUM-1:0];
|
3196 |
|
|
|
3197 |
|
|
assign tlu_sscan_test_data[`TDP_SSCAN_WIDTH-1:0] =
|
3198 |
|
|
tdp_sscan_test_data[`TDP_SSCAN_WIDTH-1:0];
|
3199 |
|
|
|
3200 |
|
|
//=========================================================================================
|
3201 |
|
|
// PSTATE for Threads
|
3202 |
|
|
//=========================================================================================
|
3203 |
|
|
|
3204 |
|
|
// pstate needs to be updated on a trap. Assume for now that only non-RED state instruction
|
3205 |
|
|
// related traps are handled.
|
3206 |
|
|
|
3207 |
|
|
// Normal traps, non-red mode.
|
3208 |
|
|
assign pstate_priv_set = tlu_select_tba_w2 | local_rst | tlu_select_redmode;
|
3209 |
|
|
//
|
3210 |
|
|
assign pstate_priv_thrd_set[0] = pstate_priv_set | ~true_hpstate0[`HPSTATE_ENB];
|
3211 |
|
|
assign pstate_priv_thrd_set[1] = pstate_priv_set | ~true_hpstate1[`HPSTATE_ENB];
|
3212 |
|
|
assign pstate_priv_thrd_set[2] = pstate_priv_set | ~true_hpstate2[`HPSTATE_ENB];
|
3213 |
|
|
assign pstate_priv_thrd_set[3] = pstate_priv_set | ~true_hpstate3[`HPSTATE_ENB];
|
3214 |
|
|
//
|
3215 |
|
|
// modified for bug 3349
|
3216 |
|
|
assign pstate_priv_update_w2[0] =
|
3217 |
|
|
~(tlu_update_pstate_l_w2[0] &
|
3218 |
|
|
(true_hpstate0[`HPSTATE_ENB] | tlu_update_hpstate_l_w2[0])) |
|
3219 |
|
|
(~wsr_data_w2[`WSR_HPSTATE_ENB] & tlu_hpstate_din_sel0[1]);
|
3220 |
|
|
assign pstate_priv_update_w2[1] =
|
3221 |
|
|
~(tlu_update_pstate_l_w2[1] &
|
3222 |
|
|
(true_hpstate1[`HPSTATE_ENB] | tlu_update_hpstate_l_w2[1])) |
|
3223 |
|
|
(~wsr_data_w2[`WSR_HPSTATE_ENB] & tlu_hpstate_din_sel1[1]);
|
3224 |
|
|
assign pstate_priv_update_w2[2] =
|
3225 |
|
|
~(tlu_update_pstate_l_w2[2] &
|
3226 |
|
|
(true_hpstate2[`HPSTATE_ENB] | tlu_update_hpstate_l_w2[2])) |
|
3227 |
|
|
(~wsr_data_w2[`WSR_HPSTATE_ENB] & tlu_hpstate_din_sel2[1]);
|
3228 |
|
|
assign pstate_priv_update_w2[3] =
|
3229 |
|
|
~(tlu_update_pstate_l_w2[3] &
|
3230 |
|
|
(true_hpstate3[`HPSTATE_ENB] | tlu_update_hpstate_l_w2[3])) |
|
3231 |
|
|
(~wsr_data_w2[`WSR_HPSTATE_ENB] & tlu_hpstate_din_sel3[1]);
|
3232 |
|
|
//
|
3233 |
|
|
assign hpstate_priv_update_w2[0] =
|
3234 |
|
|
~(tlu_update_hpstate_l_w2[0] &
|
3235 |
|
|
(true_hpstate0[`HPSTATE_ENB] | tlu_update_pstate_l_w2[0]));
|
3236 |
|
|
assign hpstate_priv_update_w2[1] =
|
3237 |
|
|
~(tlu_update_hpstate_l_w2[1] &
|
3238 |
|
|
(true_hpstate1[`HPSTATE_ENB] | tlu_update_pstate_l_w2[1]));
|
3239 |
|
|
assign hpstate_priv_update_w2[2] =
|
3240 |
|
|
~(tlu_update_hpstate_l_w2[2] &
|
3241 |
|
|
(true_hpstate2[`HPSTATE_ENB] | tlu_update_pstate_l_w2[2]));
|
3242 |
|
|
assign hpstate_priv_update_w2[3] =
|
3243 |
|
|
~(tlu_update_hpstate_l_w2[3] &
|
3244 |
|
|
(true_hpstate3[`HPSTATE_ENB] | tlu_update_pstate_l_w2[3]));
|
3245 |
|
|
//
|
3246 |
|
|
// added for bug 2161 and modified for bug 2161
|
3247 |
|
|
assign hpstate_enb_set[0] = true_hpstate0[`HPSTATE_ENB] & ~(local_rst | tlu_select_redmode);
|
3248 |
|
|
assign hpstate_enb_set[1] = true_hpstate1[`HPSTATE_ENB] & ~(local_rst | tlu_select_redmode);
|
3249 |
|
|
assign hpstate_enb_set[2] = true_hpstate2[`HPSTATE_ENB] & ~(local_rst | tlu_select_redmode);
|
3250 |
|
|
assign hpstate_enb_set[3] = true_hpstate3[`HPSTATE_ENB] & ~(local_rst | tlu_select_redmode);
|
3251 |
|
|
|
3252 |
|
|
// added for hpstate.ibe ECO
|
3253 |
|
|
// modified due to timing - tlu_ibrkpt_trap_g has been delayed one stage to tlu_ibrkpt_trap_w2
|
3254 |
|
|
assign hpstate_ibe_set[0] =
|
3255 |
|
|
true_hpstate0[`HPSTATE_IBE] & ~(local_rst | tlu_select_redmode | tlu_ibrkpt_trap_w2);
|
3256 |
|
|
assign hpstate_ibe_set[1] =
|
3257 |
|
|
true_hpstate1[`HPSTATE_IBE] & ~(local_rst | tlu_select_redmode | tlu_ibrkpt_trap_w2);
|
3258 |
|
|
assign hpstate_ibe_set[2] =
|
3259 |
|
|
true_hpstate2[`HPSTATE_IBE] & ~(local_rst | tlu_select_redmode | tlu_ibrkpt_trap_w2);
|
3260 |
|
|
assign hpstate_ibe_set[3] =
|
3261 |
|
|
true_hpstate3[`HPSTATE_IBE] & ~(local_rst | tlu_select_redmode | tlu_ibrkpt_trap_w2);
|
3262 |
|
|
//
|
3263 |
|
|
// added due to TLZ spec change
|
3264 |
|
|
// modified for bug 3505
|
3265 |
|
|
assign hpstate_tlz_set[0] = true_hpstate0[`HPSTATE_TLZ] & ~(local_rst | tlu_select_redmode);
|
3266 |
|
|
assign hpstate_tlz_set[1] = true_hpstate1[`HPSTATE_TLZ] & ~(local_rst | tlu_select_redmode);
|
3267 |
|
|
assign hpstate_tlz_set[2] = true_hpstate2[`HPSTATE_TLZ] & ~(local_rst | tlu_select_redmode);
|
3268 |
|
|
assign hpstate_tlz_set[3] = true_hpstate3[`HPSTATE_TLZ] & ~(local_rst | tlu_select_redmode);
|
3269 |
|
|
//
|
3270 |
|
|
// thread 0
|
3271 |
|
|
assign tlu_select_tle[0] =
|
3272 |
|
|
tlu_pstate_tle[0] & ~(tlu_select_redmode);
|
3273 |
|
|
// modified for timing and bug 3417
|
3274 |
|
|
assign tlu_select_cle[0] =
|
3275 |
|
|
tlu_select_tle[0] &
|
3276 |
|
|
(tlu_select_tba_w2 | ~true_hpstate0[`HPSTATE_ENB]);
|
3277 |
|
|
// tlu_select_tle[0] & tlu_select_tba_w2;
|
3278 |
|
|
//
|
3279 |
|
|
// modified for timing and width cleanup
|
3280 |
|
|
/*
|
3281 |
|
|
assign ntrap_pstate0[`PSTATE_TRUE_WIDTH-1:0] =
|
3282 |
|
|
{2'b0, // tlu_select_int_global - replaced by gl register
|
3283 |
|
|
// tlu_select_mmu_global - replaced by gl register
|
3284 |
|
|
tlu_select_cle[0], // cle<-tle, or 0
|
3285 |
|
|
tlu_select_tle[0], // keep old tle, or 0
|
3286 |
|
|
2'b0,
|
3287 |
|
|
1'b0, // tlu_select_redmode - replaced by hpstate.red
|
3288 |
|
|
1'b1, // fp turned on
|
3289 |
|
|
1'b0, // address masking turned off
|
3290 |
|
|
pstate_priv_thrd_set[0], // enter priv mode for priv traps
|
3291 |
|
|
1'b0, // interrupts disabled
|
3292 |
|
|
1'b0}; // tlu_select_alt_global - replaced by gl register
|
3293 |
|
|
*/
|
3294 |
|
|
assign ntrap_pstate0[`WSR_PSTATE_VR_WIDTH-1:0] =
|
3295 |
|
|
{tlu_select_cle[0], // cle<-tle, or 0
|
3296 |
|
|
tlu_select_tle[0], // keep old tle, or 0
|
3297 |
|
|
1'b1, // fp turned on
|
3298 |
|
|
1'b0, // address masking turned off
|
3299 |
|
|
pstate_priv_thrd_set[0], // enter priv mode for priv traps
|
3300 |
|
|
1'b0}; // interrupts disabled
|
3301 |
|
|
//
|
3302 |
|
|
// thread 1
|
3303 |
|
|
assign tlu_select_tle[1] =
|
3304 |
|
|
tlu_pstate_tle[1] & ~(tlu_select_redmode);
|
3305 |
|
|
// modified for timing and bug 3417
|
3306 |
|
|
assign tlu_select_cle[1] =
|
3307 |
|
|
tlu_select_tle[1] &
|
3308 |
|
|
(tlu_select_tba_w2 | ~true_hpstate1[`HPSTATE_ENB]);
|
3309 |
|
|
// tlu_select_tle[1] & tlu_select_tba_w2;
|
3310 |
|
|
//
|
3311 |
|
|
// modified due to timing
|
3312 |
|
|
/*
|
3313 |
|
|
assign ntrap_pstate1[`PSTATE_TRUE_WIDTH-1:0] =
|
3314 |
|
|
{2'b0, // tlu_select_int_global - replaced by gl register
|
3315 |
|
|
// tlu_select_mmu_global - replaced by gl register
|
3316 |
|
|
tlu_select_cle[1], // cle<-tle, or 0
|
3317 |
|
|
tlu_select_tle[1], // keep old tle, or 0
|
3318 |
|
|
2'b0,
|
3319 |
|
|
1'b0, // tlu_select_redmode - replaced by hpstate.red
|
3320 |
|
|
1'b1, // fp turned on
|
3321 |
|
|
1'b0, // address masking turned off
|
3322 |
|
|
pstate_priv_thrd_set[1], // enter priv mode for priv traps
|
3323 |
|
|
1'b0, // interrupts disabled
|
3324 |
|
|
1'b0}; // tlu_select_alt_global - replaced by gl register
|
3325 |
|
|
*/
|
3326 |
|
|
assign ntrap_pstate1[`WSR_PSTATE_VR_WIDTH-1:0] =
|
3327 |
|
|
{tlu_select_cle[1], // cle<-tle, or 0
|
3328 |
|
|
tlu_select_tle[1], // keep old tle, or 0
|
3329 |
|
|
1'b1, // fp turned on
|
3330 |
|
|
1'b0, // address masking turned off
|
3331 |
|
|
pstate_priv_thrd_set[1], // enter priv mode for priv traps
|
3332 |
|
|
1'b0}; // interrupts disabled//
|
3333 |
|
|
//
|
3334 |
|
|
// thread 2
|
3335 |
|
|
assign tlu_select_tle[2] =
|
3336 |
|
|
tlu_pstate_tle[2] & ~(tlu_select_redmode);
|
3337 |
|
|
// modified for timing and bug 3417
|
3338 |
|
|
assign tlu_select_cle[2] =
|
3339 |
|
|
tlu_select_tle[2] &
|
3340 |
|
|
(tlu_select_tba_w2 | ~true_hpstate2[`HPSTATE_ENB]);
|
3341 |
|
|
// tlu_select_tle[2] & tlu_select_tba_w2;
|
3342 |
|
|
//
|
3343 |
|
|
// modified for timing and width cleanup
|
3344 |
|
|
/*
|
3345 |
|
|
assign ntrap_pstate2[`PSTATE_TRUE_WIDTH-1:0] =
|
3346 |
|
|
{2'b0, // tlu_select_int_global - replaced by gl register
|
3347 |
|
|
// tlu_select_mmu_global - replaced by gl register
|
3348 |
|
|
tlu_select_cle[2], // cle<-tle, or 0
|
3349 |
|
|
tlu_select_tle[2], // keep old tle, or 0
|
3350 |
|
|
2'b0,
|
3351 |
|
|
1'b0, // tlu_select_redmode - replaced by hpstate.red
|
3352 |
|
|
1'b1, // fp turned on
|
3353 |
|
|
1'b0, // address masking turned off
|
3354 |
|
|
pstate_priv_thrd_set[2], // enter priv mode for priv traps
|
3355 |
|
|
1'b0, // interrupts disabled
|
3356 |
|
|
1'b0}; // tlu_select_alt_global - replaced by gl register
|
3357 |
|
|
*/
|
3358 |
|
|
assign ntrap_pstate2[`WSR_PSTATE_VR_WIDTH-1:0] =
|
3359 |
|
|
{tlu_select_cle[2], // cle<-tle, or 0
|
3360 |
|
|
tlu_select_tle[2], // keep old tle, or 0
|
3361 |
|
|
1'b1, // fp turned on
|
3362 |
|
|
1'b0, // address masking turned off
|
3363 |
|
|
pstate_priv_thrd_set[2], // enter priv mode for priv traps
|
3364 |
|
|
1'b0}; // interrupts disabled//
|
3365 |
|
|
//
|
3366 |
|
|
// thread 3
|
3367 |
|
|
assign tlu_select_tle[3] =
|
3368 |
|
|
tlu_pstate_tle[3] & ~(tlu_select_redmode);
|
3369 |
|
|
// modified for timing and bug 3417
|
3370 |
|
|
assign tlu_select_cle[3] =
|
3371 |
|
|
tlu_select_tle[3] &
|
3372 |
|
|
(tlu_select_tba_w2 | ~true_hpstate3[`HPSTATE_ENB]);
|
3373 |
|
|
// tlu_select_tle[3] & tlu_select_tba_w2;
|
3374 |
|
|
//
|
3375 |
|
|
// modified for timing
|
3376 |
|
|
/*
|
3377 |
|
|
assign ntrap_pstate3[`PSTATE_TRUE_WIDTH-1:0] =
|
3378 |
|
|
{2'b0, // tlu_select_int_global - replaced by gl register
|
3379 |
|
|
// tlu_select_mmu_global - replaced by gl register
|
3380 |
|
|
tlu_select_cle[3], // cle<-tle, or 0
|
3381 |
|
|
tlu_select_tle[3], // keep old tle, or 0
|
3382 |
|
|
2'b0,
|
3383 |
|
|
1'b0, // tlu_select_redmode - replaced by hpstate.red
|
3384 |
|
|
1'b1, // fp turned on
|
3385 |
|
|
1'b0, // address masking turned off
|
3386 |
|
|
pstate_priv_thrd_set[3], // enter priv mode for priv traps
|
3387 |
|
|
1'b0, // interrupts disabled
|
3388 |
|
|
1'b0}; // tlu_select_alt_global - replaced by gl register
|
3389 |
|
|
*/
|
3390 |
|
|
assign ntrap_pstate3[`WSR_PSTATE_VR_WIDTH-1:0] =
|
3391 |
|
|
{tlu_select_cle[3], // cle<-tle, or 0
|
3392 |
|
|
tlu_select_tle[3], // keep old tle, or 0
|
3393 |
|
|
1'b1, // fp turned on
|
3394 |
|
|
1'b0, // address masking turned off
|
3395 |
|
|
pstate_priv_thrd_set[3], // enter priv mode for priv traps
|
3396 |
|
|
1'b0}; // interrupts disabled//
|
3397 |
|
|
|
3398 |
|
|
// Clock Enable Buffers
|
3399 |
|
|
//
|
3400 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
3401 |
|
|
`else
|
3402 |
|
|
clken_buf clkbf_ps0 (
|
3403 |
|
|
.rclk (clk),
|
3404 |
|
|
.enb_l (tlu_update_pstate_l_w2[0]),
|
3405 |
|
|
.tmb_l (se_l),
|
3406 |
|
|
.clk (pstate0_clk)
|
3407 |
|
|
);
|
3408 |
|
|
`endif
|
3409 |
|
|
|
3410 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
3411 |
|
|
`else
|
3412 |
|
|
clken_buf clkbf_ps1 (
|
3413 |
|
|
.rclk (clk),
|
3414 |
|
|
.enb_l (tlu_update_pstate_l_w2[1]),
|
3415 |
|
|
.tmb_l (se_l),
|
3416 |
|
|
.clk (pstate1_clk)
|
3417 |
|
|
);
|
3418 |
|
|
`endif
|
3419 |
|
|
|
3420 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
3421 |
|
|
`else
|
3422 |
|
|
clken_buf clkbf_ps2 (
|
3423 |
|
|
.rclk (clk),
|
3424 |
|
|
.enb_l (tlu_update_pstate_l_w2[2]),
|
3425 |
|
|
.tmb_l (se_l),
|
3426 |
|
|
.clk (pstate2_clk)
|
3427 |
|
|
);
|
3428 |
|
|
`endif
|
3429 |
|
|
|
3430 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
3431 |
|
|
`else
|
3432 |
|
|
clken_buf clkbf_ps3 (
|
3433 |
|
|
.rclk (clk),
|
3434 |
|
|
.enb_l (tlu_update_pstate_l_w2[3]),
|
3435 |
|
|
.tmb_l (se_l),
|
3436 |
|
|
.clk (pstate3_clk)
|
3437 |
|
|
);
|
3438 |
|
|
`endif
|
3439 |
|
|
//
|
3440 |
|
|
// added for hypervisor support
|
3441 |
|
|
// clock enable buffers for updating the hpstate registers
|
3442 |
|
|
//
|
3443 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
3444 |
|
|
`else
|
3445 |
|
|
clken_buf clkbf_hps0 (
|
3446 |
|
|
.rclk (clk),
|
3447 |
|
|
.enb_l (tlu_update_hpstate_l_w2[0]),
|
3448 |
|
|
.tmb_l (se_l),
|
3449 |
|
|
.clk (hpstate0_clk)
|
3450 |
|
|
);
|
3451 |
|
|
`endif
|
3452 |
|
|
|
3453 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
3454 |
|
|
`else
|
3455 |
|
|
clken_buf clkbf_hps1 (
|
3456 |
|
|
.rclk (clk),
|
3457 |
|
|
.enb_l (tlu_update_hpstate_l_w2[1]),
|
3458 |
|
|
.tmb_l (se_l),
|
3459 |
|
|
.clk (hpstate1_clk)
|
3460 |
|
|
);
|
3461 |
|
|
`endif
|
3462 |
|
|
|
3463 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
3464 |
|
|
`else
|
3465 |
|
|
clken_buf clkbf_hps2 (
|
3466 |
|
|
.rclk (clk),
|
3467 |
|
|
.enb_l (tlu_update_hpstate_l_w2[2]),
|
3468 |
|
|
.tmb_l (se_l),
|
3469 |
|
|
.clk (hpstate2_clk)
|
3470 |
|
|
);
|
3471 |
|
|
`endif
|
3472 |
|
|
|
3473 |
|
|
`ifdef FPGA_SYN_CLK_EN
|
3474 |
|
|
`else
|
3475 |
|
|
clken_buf clkbf_hps3 (
|
3476 |
|
|
.rclk (clk),
|
3477 |
|
|
.enb_l (tlu_update_hpstate_l_w2[3]),
|
3478 |
|
|
.tmb_l (se_l),
|
3479 |
|
|
.clk (hpstate3_clk)
|
3480 |
|
|
);
|
3481 |
|
|
`endif
|
3482 |
|
|
// assign the initial value of hpstate.red mode
|
3483 |
|
|
//
|
3484 |
|
|
// modified for bug 1893
|
3485 |
|
|
// assign hpstate_redmode =
|
3486 |
|
|
// (local_rst)? 1'b1: tlu_select_redmode;
|
3487 |
|
|
assign hpstate_redmode =
|
3488 |
|
|
local_rst | (~local_rst & tlu_select_redmode);
|
3489 |
|
|
//
|
3490 |
|
|
// extracting hpstate from wsr_data
|
3491 |
|
|
//
|
3492 |
|
|
// modified for timing tlu_wsr_data_w -> wsr_data_w2
|
3493 |
|
|
assign wsr_data_hpstate_w2[`TLU_HPSTATE_WIDTH-1:0] =
|
3494 |
|
|
{wsr_data_w2[`WSR_HPSTATE_IBE],
|
3495 |
|
|
wsr_data_w2[`WSR_HPSTATE_ENB],
|
3496 |
|
|
wsr_data_w2[`WSR_HPSTATE_RED],
|
3497 |
|
|
wsr_data_w2[`WSR_HPSTATE_PRIV],
|
3498 |
|
|
wsr_data_w2[`WSR_HPSTATE_TLZ]
|
3499 |
|
|
};
|
3500 |
|
|
//
|
3501 |
|
|
// added or modified for hypervisor support
|
3502 |
|
|
// modified due to timing
|
3503 |
|
|
/*
|
3504 |
|
|
assign wsr_data_pstate_g[`PSTATE_TRUE_WIDTH-1:0] =
|
3505 |
|
|
{2'b0, // old IG, MG - replaced by global register
|
3506 |
|
|
tlu_wsr_data_w[`PSTATE_VRANGE2_HI:`PSTATE_VRANGE2_LO],
|
3507 |
|
|
2'b0, // memory model has been change to TSO only - bug 2588
|
3508 |
|
|
1'b0, // old red, - replaced by hpstate.red
|
3509 |
|
|
tlu_wsr_data_w[`PSTATE_VRANGE1_HI:`PSTATE_VRANGE1_LO],
|
3510 |
|
|
1'b0}; // old AG - replaced by global register
|
3511 |
|
|
|
3512 |
|
|
assign wsr_data_pstate_g[`WSR_PSTATE_VR_WIDTH-1:0] =
|
3513 |
|
|
{tlu_wsr_data_w[`PSTATE_VRANGE2_HI:`PSTATE_VRANGE2_LO],
|
3514 |
|
|
tlu_wsr_data_w[`PSTATE_VRANGE1_HI:`PSTATE_VRANGE1_LO]};
|
3515 |
|
|
*/
|
3516 |
|
|
assign wsr_data_pstate_w2[`WSR_PSTATE_VR_WIDTH-1:0] =
|
3517 |
|
|
{wsr_data_w2[`PSTATE_VRANGE2_HI:`PSTATE_VRANGE2_LO],
|
3518 |
|
|
wsr_data_w2[`PSTATE_VRANGE1_HI:`PSTATE_VRANGE1_LO]};
|
3519 |
|
|
//
|
3520 |
|
|
// THREAD0
|
3521 |
|
|
// added for bug 1575
|
3522 |
|
|
// modified for bug 2584
|
3523 |
|
|
// assign tlu_pstate_nt_sel0 = ~|(tlu_pstate_din_sel0[1:0]);
|
3524 |
|
|
assign tlu_pstate_nt_sel0 =
|
3525 |
|
|
~(tlu_pstate_din_sel0[0] | tlu_pstate_wsr_sel0);
|
3526 |
|
|
//
|
3527 |
|
|
// modified for bug 3349
|
3528 |
|
|
assign tlu_pstate_wsr_sel0 =
|
3529 |
|
|
tlu_pstate_din_sel0[1] |
|
3530 |
|
|
(~(true_hpstate0[`HPSTATE_ENB] & wsr_data_w2[`WSR_HPSTATE_ENB]) &
|
3531 |
|
|
tlu_hpstate_din_sel0[1]);
|
3532 |
|
|
// (~true_hpstate0[`HPSTATE_ENB] & tlu_hpstate_din_sel0[1]);
|
3533 |
|
|
|
3534 |
|
|
mux3ds #(`WSR_PSTATE_VR_WIDTH) mux_restore_pstate0(
|
3535 |
|
|
.in0 (dnrtry_pstate_w2[`WSR_PSTATE_VR_WIDTH-1:0]),
|
3536 |
|
|
.in1 (wsr_data_pstate_w2[`WSR_PSTATE_VR_WIDTH-1:0]),
|
3537 |
|
|
.in2 (ntrap_pstate0[`WSR_PSTATE_VR_WIDTH-1:0]),
|
3538 |
|
|
.sel0 (tlu_pstate_din_sel0[0]),
|
3539 |
|
|
.sel1 (tlu_pstate_wsr_sel0),
|
3540 |
|
|
.sel2 (tlu_pstate_nt_sel0),
|
3541 |
|
|
.dout (restore_pstate0[`WSR_PSTATE_VR_WIDTH-1:0])
|
3542 |
|
|
);
|
3543 |
|
|
|
3544 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
3545 |
|
|
dffe_s #(`WSR_PSTATE_VR_WIDTH-1) dff_restore_pstate0_w3 (
|
3546 |
|
|
.din ({restore_pstate0[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
|
3547 |
|
|
restore_pstate0[`WSR_PSTATE_VRANGE1_LO]}),
|
3548 |
|
|
.q ({restore_pstate0_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
|
3549 |
|
|
restore_pstate0_w3[`WSR_PSTATE_VRANGE1_LO]}),
|
3550 |
|
|
.en (~(tlu_update_pstate_l_w2[0])), .clk(clk),
|
3551 |
|
|
.se (se),
|
3552 |
|
|
.si (),
|
3553 |
|
|
.so ()
|
3554 |
|
|
);
|
3555 |
|
|
`else
|
3556 |
|
|
dff_s #(`WSR_PSTATE_VR_WIDTH-1) dff_restore_pstate0_w3 (
|
3557 |
|
|
.din ({restore_pstate0[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
|
3558 |
|
|
restore_pstate0[`WSR_PSTATE_VRANGE1_LO]}),
|
3559 |
|
|
.q ({restore_pstate0_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
|
3560 |
|
|
restore_pstate0_w3[`WSR_PSTATE_VRANGE1_LO]}),
|
3561 |
|
|
.clk (pstate0_clk),
|
3562 |
|
|
.se (se),
|
3563 |
|
|
.si (),
|
3564 |
|
|
.so ()
|
3565 |
|
|
);
|
3566 |
|
|
`endif
|
3567 |
|
|
//
|
3568 |
|
|
dffe_s dffe_pstate0_priv (
|
3569 |
|
|
.din (restore_pstate0[`WSR_PSTATE_VR_PRIV]),
|
3570 |
|
|
.q (restore_pstate0_w3[`WSR_PSTATE_VR_PRIV]),
|
3571 |
|
|
.en (pstate_priv_update_w2[0]),
|
3572 |
|
|
.clk (clk),
|
3573 |
|
|
.se (se),
|
3574 |
|
|
.si (),
|
3575 |
|
|
.so ()
|
3576 |
|
|
);
|
3577 |
|
|
//
|
3578 |
|
|
// true_pstate0 assignments
|
3579 |
|
|
assign true_pstate0[`PSTATE_TRUE_WIDTH-1:0] =
|
3580 |
|
|
{2'b0, // tlu_select_int_global - replaced by gl register
|
3581 |
|
|
// tlu_select_mmu_global - replaced by gl register
|
3582 |
|
|
restore_pstate0_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE2_LO],
|
3583 |
|
|
2'b0, // fixed mmodel - TSO
|
3584 |
|
|
1'b0, // redmode - replaced by hpstate.red
|
3585 |
|
|
restore_pstate0_w3[`WSR_PSTATE_VRANGE1_HI:`WSR_PSTATE_VRANGE1_LO],
|
3586 |
|
|
1'b0}; // tlu_select_alt_global - replaced by gl register
|
3587 |
|
|
//
|
3588 |
|
|
// modified for timing
|
3589 |
|
|
/*
|
3590 |
|
|
mux3ds #(9) mux_restore_pstate0(
|
3591 |
|
|
.in0 (dnrtry_pstate[`PSTATE_TRUE_WIDTH-3:1]),
|
3592 |
|
|
.in1 (wsr_data_pstate_g[`PSTATE_TRUE_WIDTH-3:1]),
|
3593 |
|
|
.in2 (ntrap_pstate0[`PSTATE_TRUE_WIDTH-3:1]),
|
3594 |
|
|
.sel0 (tlu_pstate_din_sel0[0]),
|
3595 |
|
|
// modified for bug 2584
|
3596 |
|
|
// .sel1 (tlu_pstate_din_sel0[1]),
|
3597 |
|
|
.sel1 (tlu_pstate_wsr_sel0),
|
3598 |
|
|
.sel2 (tlu_pstate_nt_sel0),
|
3599 |
|
|
.dout (restore_pstate0[`PSTATE_TRUE_WIDTH-3:1])
|
3600 |
|
|
);
|
3601 |
|
|
|
3602 |
|
|
dff_s #(`PSTATE_TRUE_WIDTH) pstate0_1 (
|
3603 |
|
|
.din (restore_pstate0[`PSTATE_TRUE_WIDTH-1:0]),
|
3604 |
|
|
.q (true_pstate0[`PSTATE_TRUE_WIDTH-1:0]),
|
3605 |
|
|
.clk (pstate0_clk),
|
3606 |
|
|
.se (se),
|
3607 |
|
|
.si (),
|
3608 |
|
|
.so ()
|
3609 |
|
|
);
|
3610 |
|
|
//
|
3611 |
|
|
dff_s #(`PSTATE_TRUE_WIDTH-1) dff_true_pstate0 (
|
3612 |
|
|
.din ({restore_pstate0[`PSTATE_TRUE_WIDTH-1:3],
|
3613 |
|
|
restore_pstate0[1:0]}),
|
3614 |
|
|
.q ({true_pstate0[`PSTATE_TRUE_WIDTH-1:3],
|
3615 |
|
|
true_pstate0[1:0]}),
|
3616 |
|
|
.clk (pstate0_clk),
|
3617 |
|
|
.se (se),
|
3618 |
|
|
.si (),
|
3619 |
|
|
.so ()
|
3620 |
|
|
);
|
3621 |
|
|
//
|
3622 |
|
|
dffe_s dffe_pstate0_priv (
|
3623 |
|
|
.din (restore_pstate0[`PSTATE_PRIV]),
|
3624 |
|
|
.q (true_pstate0[`PSTATE_PRIV]),
|
3625 |
|
|
.en (pstate_priv_update_g[0]),
|
3626 |
|
|
.clk (clk),
|
3627 |
|
|
.se (se),
|
3628 |
|
|
.si (),
|
3629 |
|
|
.so ()
|
3630 |
|
|
);
|
3631 |
|
|
// modified for hypervisor support
|
3632 |
|
|
assign restore_pstate0[11:10] = 2'b0;
|
3633 |
|
|
assign restore_pstate0[0] = 1'b0;
|
3634 |
|
|
//
|
3635 |
|
|
// modified to reflect the physical implementation
|
3636 |
|
|
// assign hpstate_dnrtry_priv_w2[0] =
|
3637 |
|
|
(true_hpstate0[`HPSTATE_ENB])?
|
3638 |
|
|
tsa_dnrtry_hpstate_w2[`HPSTATE_PRIV] :
|
3639 |
|
|
dnrtry_pstate_w2[`WSR_PSTATE_VR_PRIV];
|
3640 |
|
|
*/
|
3641 |
|
|
mux2ds mx_hpstate_dnrtry_priv_w2_0 (
|
3642 |
|
|
.in0 (tsa_dnrtry_hpstate_w2[`HPSTATE_PRIV]),
|
3643 |
|
|
.in1 (dnrtry_pstate_w2[`WSR_PSTATE_VR_PRIV]),
|
3644 |
|
|
.sel0 (true_hpstate0[`HPSTATE_ENB]),
|
3645 |
|
|
.sel1 (~true_hpstate0[`HPSTATE_ENB]),
|
3646 |
|
|
.dout (hpstate_dnrtry_priv_w2[0])
|
3647 |
|
|
);
|
3648 |
|
|
//
|
3649 |
|
|
assign dnrtry_hpstate0_w2[`TLU_HPSTATE_WIDTH-1:0] =
|
3650 |
|
|
{tsa_dnrtry_hpstate_w2[`TSA_HTSTATE_WIDTH-1],
|
3651 |
|
|
true_hpstate0[`HPSTATE_ENB],
|
3652 |
|
|
tsa_dnrtry_hpstate_w2[`HPSTATE_RED],
|
3653 |
|
|
hpstate_dnrtry_priv_w2[0],
|
3654 |
|
|
tsa_dnrtry_hpstate_w2[`HPSTATE_TLZ]};
|
3655 |
|
|
|
3656 |
|
|
// added for bug 3747
|
3657 |
|
|
assign hpstate_priv_set = ~(tlu_select_tba_w2) | tlu_select_redmode;
|
3658 |
|
|
//
|
3659 |
|
|
// constructing the hpstate for hyper-privileged traps
|
3660 |
|
|
//
|
3661 |
|
|
assign hntrap_hpstate0_w2[`TLU_HPSTATE_WIDTH-1:0] =
|
3662 |
|
|
{hpstate_ibe_set[0],
|
3663 |
|
|
hpstate_enb_set[0],
|
3664 |
|
|
hpstate_redmode, // Redmode bit
|
3665 |
|
|
// modified for bug 3747
|
3666 |
|
|
hpstate_priv_set, // hyper-privileged bit
|
3667 |
|
|
hpstate_tlz_set[0]}; // TLZ interrupt bit
|
3668 |
|
|
|
3669 |
|
|
assign tlu_hpstate_hnt_sel0 =
|
3670 |
|
|
~(tlu_hpstate_din_sel0[0] | tlu_hpstate_wsr_sel0);
|
3671 |
|
|
//
|
3672 |
|
|
assign tlu_hpstate_wsr_sel0 =
|
3673 |
|
|
tlu_hpstate_din_sel0[1] |
|
3674 |
|
|
(~true_hpstate0[`HPSTATE_ENB] & tlu_pstate_din_sel0[1]);
|
3675 |
|
|
|
3676 |
|
|
mux3ds #(`TLU_HPSTATE_WIDTH) mux_restore_hpstate0(
|
3677 |
|
|
.in0 (dnrtry_hpstate0_w2[`TLU_HPSTATE_WIDTH-1:0]),
|
3678 |
|
|
.in1 (wsr_data_hpstate_w2[`TLU_HPSTATE_WIDTH-1:0]),
|
3679 |
|
|
.in2 (hntrap_hpstate0_w2[`TLU_HPSTATE_WIDTH-1:0]),
|
3680 |
|
|
.sel0 (tlu_hpstate_din_sel0[0]),
|
3681 |
|
|
.sel1 (tlu_hpstate_wsr_sel0),
|
3682 |
|
|
.sel2 (tlu_hpstate_hnt_sel0),
|
3683 |
|
|
.dout (restore_hpstate0[`TLU_HPSTATE_WIDTH-1:0])
|
3684 |
|
|
);
|
3685 |
|
|
//
|
3686 |
|
|
// need to initialize hpstate.enb = 0
|
3687 |
|
|
// need to initialize hpstate.ibe = 0
|
3688 |
|
|
// modified due to the addition of hpstate.ibe
|
3689 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
3690 |
|
|
dffre_s #(2) dffr_true_hpst0_enb_ibe (
|
3691 |
|
|
.din (restore_hpstate0[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
|
3692 |
|
|
.q (true_hpstate0[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
|
3693 |
|
|
.rst (local_rst),
|
3694 |
|
|
.en (~(tlu_update_hpstate_l_w2[0])), .clk(clk),
|
3695 |
|
|
.se (se),
|
3696 |
|
|
.si (),
|
3697 |
|
|
.so ()
|
3698 |
|
|
);
|
3699 |
|
|
`else
|
3700 |
|
|
dffr_s #(2) dffr_true_hpst0_enb_ibe (
|
3701 |
|
|
.din (restore_hpstate0[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
|
3702 |
|
|
.q (true_hpstate0[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
|
3703 |
|
|
.rst (local_rst),
|
3704 |
|
|
.clk (hpstate0_clk),
|
3705 |
|
|
.se (se),
|
3706 |
|
|
.si (),
|
3707 |
|
|
.so ()
|
3708 |
|
|
);
|
3709 |
|
|
`endif
|
3710 |
|
|
//
|
3711 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
3712 |
|
|
dffe_s #(2) dff_true_hpstate0 (
|
3713 |
|
|
.din ({restore_hpstate0[`HPSTATE_RED],
|
3714 |
|
|
restore_hpstate0[`HPSTATE_TLZ]}),
|
3715 |
|
|
.q ({true_hpstate0[`HPSTATE_RED],
|
3716 |
|
|
true_hpstate0[`HPSTATE_TLZ]}),
|
3717 |
|
|
.en (~(tlu_update_hpstate_l_w2[0])), .clk(clk),
|
3718 |
|
|
.se (se),
|
3719 |
|
|
.si (),
|
3720 |
|
|
.so ()
|
3721 |
|
|
);
|
3722 |
|
|
`else
|
3723 |
|
|
dff_s #(2) dff_true_hpstate0 (
|
3724 |
|
|
.din ({restore_hpstate0[`HPSTATE_RED],
|
3725 |
|
|
restore_hpstate0[`HPSTATE_TLZ]}),
|
3726 |
|
|
.q ({true_hpstate0[`HPSTATE_RED],
|
3727 |
|
|
true_hpstate0[`HPSTATE_TLZ]}),
|
3728 |
|
|
.clk (hpstate0_clk),
|
3729 |
|
|
.se (se),
|
3730 |
|
|
.si (),
|
3731 |
|
|
.so ()
|
3732 |
|
|
);
|
3733 |
|
|
`endif
|
3734 |
|
|
//
|
3735 |
|
|
dffe_s dffe_hpstate0_priv (
|
3736 |
|
|
.din (restore_hpstate0[`HPSTATE_PRIV]),
|
3737 |
|
|
.q (true_hpstate0[`HPSTATE_PRIV]),
|
3738 |
|
|
.en (hpstate_priv_update_w2[0]),
|
3739 |
|
|
.clk (clk),
|
3740 |
|
|
.se (se),
|
3741 |
|
|
.si (),
|
3742 |
|
|
.so ()
|
3743 |
|
|
);
|
3744 |
|
|
|
3745 |
|
|
assign tlu_ifu_pstate_pef[0] = true_pstate0[`PSTATE_PEF];
|
3746 |
|
|
assign tlu_lsu_pstate_cle[0] = true_pstate0[`PSTATE_CLE];
|
3747 |
|
|
assign tlu_lsu_pstate_priv[0] = true_pstate0[`PSTATE_PRIV];
|
3748 |
|
|
assign tlu_int_pstate_ie[0] = true_pstate0[`PSTATE_IE];
|
3749 |
|
|
assign local_pstate_ie[0] = true_pstate0[`PSTATE_IE];
|
3750 |
|
|
// assign tlu_pstate_cle[0] = true_pstate0[`PSTATE_CLE];
|
3751 |
|
|
assign tlu_pstate_tle[0] = true_pstate0[`PSTATE_TLE];
|
3752 |
|
|
// assign tlu_pstate_priv[0] = true_pstate0[`PSTATE_PRIV];
|
3753 |
|
|
assign local_pstate_priv[0] = true_pstate0[`PSTATE_PRIV];
|
3754 |
|
|
assign tlu_pstate_am[0] = true_pstate0[`PSTATE_AM];
|
3755 |
|
|
assign tlu_int_redmode[0] = true_hpstate0[`HPSTATE_RED];
|
3756 |
|
|
assign tlu_lsu_redmode[0] = true_hpstate0[`HPSTATE_RED];
|
3757 |
|
|
//
|
3758 |
|
|
// hypervisor privilege indicator
|
3759 |
|
|
assign tlu_hpstate_priv[0] = true_hpstate0[`HPSTATE_PRIV];
|
3760 |
|
|
assign local_hpstate_priv[0] = true_hpstate0[`HPSTATE_PRIV];
|
3761 |
|
|
assign tcl_hpstate_priv[0] = true_hpstate0[`HPSTATE_PRIV];
|
3762 |
|
|
//
|
3763 |
|
|
// hypervisor lite mode selector
|
3764 |
|
|
assign tlu_hpstate_enb[0] = true_hpstate0[`HPSTATE_ENB];
|
3765 |
|
|
assign local_hpstate_enb[0] = true_hpstate0[`HPSTATE_ENB];
|
3766 |
|
|
assign tcl_hpstate_enb[0] = true_hpstate0[`HPSTATE_ENB];
|
3767 |
|
|
|
3768 |
|
|
// hypervisor tlz indicator
|
3769 |
|
|
assign tlu_hpstate_tlz[0] = true_hpstate0[`HPSTATE_TLZ];
|
3770 |
|
|
|
3771 |
|
|
// hypervisor instruction breakpt enable
|
3772 |
|
|
assign tlu_hpstate_ibe[0] = true_hpstate0[`HPSTATE_IBE];
|
3773 |
|
|
|
3774 |
|
|
`ifdef FPGA_SYN_1THREAD
|
3775 |
|
|
assign tlu_ifu_pstate_pef[3:1] = 3'b000;
|
3776 |
|
|
assign tlu_lsu_pstate_cle[3:1] = 3'b000;
|
3777 |
|
|
assign tlu_lsu_pstate_priv[3:1] = 3'b000;
|
3778 |
|
|
assign tlu_int_pstate_ie[3:1] = 3'b000;
|
3779 |
|
|
assign local_pstate_ie[3:1] = 3'b000;
|
3780 |
|
|
assign tlu_pstate_tle[3:1] = 3'b000;
|
3781 |
|
|
assign local_pstate_priv[3:1] = 3'b000;
|
3782 |
|
|
assign tlu_pstate_am[3:1] = 3'b000;
|
3783 |
|
|
assign tlu_int_redmode[3:1] = 3'b000;
|
3784 |
|
|
assign tlu_lsu_redmode[3:1] = 3'b000;
|
3785 |
|
|
assign tlu_hpstate_priv[3:1] = 3'b000;
|
3786 |
|
|
assign local_hpstate_priv[3:1] = 3'b000;
|
3787 |
|
|
assign tcl_hpstate_priv[3:1] = 3'b000;
|
3788 |
|
|
assign tlu_hpstate_enb[3:1] = 3'b000;
|
3789 |
|
|
assign local_hpstate_enb[3:1] = 3'b000;
|
3790 |
|
|
assign tcl_hpstate_enb[3:1] = 3'b000;
|
3791 |
|
|
assign tlu_hpstate_tlz[3:1] = 3'b000;
|
3792 |
|
|
assign tlu_hpstate_ibe[3:1] = 3'b000;
|
3793 |
|
|
|
3794 |
|
|
`else
|
3795 |
|
|
|
3796 |
|
|
// THREAD 1
|
3797 |
|
|
assign tlu_pstate_nt_sel1 =
|
3798 |
|
|
~(tlu_pstate_din_sel1[0] | tlu_pstate_wsr_sel1);
|
3799 |
|
|
//
|
3800 |
|
|
// modified for bug 3349
|
3801 |
|
|
assign tlu_pstate_wsr_sel1 =
|
3802 |
|
|
tlu_pstate_din_sel1[1] |
|
3803 |
|
|
(~(true_hpstate1[`HPSTATE_ENB] & wsr_data_w2[`WSR_HPSTATE_ENB]) &
|
3804 |
|
|
tlu_hpstate_din_sel1[1]);
|
3805 |
|
|
// (~true_hpstate1[`HPSTATE_ENB] & tlu_hpstate_din_sel1[1]);
|
3806 |
|
|
|
3807 |
|
|
mux3ds #(`WSR_PSTATE_VR_WIDTH) mux_restore_pstate1(
|
3808 |
|
|
.in0 (dnrtry_pstate_w2[`WSR_PSTATE_VR_WIDTH-1:0]),
|
3809 |
|
|
.in1 (wsr_data_pstate_w2[`WSR_PSTATE_VR_WIDTH-1:0]),
|
3810 |
|
|
.in2 (ntrap_pstate1[`WSR_PSTATE_VR_WIDTH-1:0]),
|
3811 |
|
|
.sel0 (tlu_pstate_din_sel1[0]),
|
3812 |
|
|
.sel1 (tlu_pstate_wsr_sel1),
|
3813 |
|
|
.sel2 (tlu_pstate_nt_sel1),
|
3814 |
|
|
.dout (restore_pstate1[`WSR_PSTATE_VR_WIDTH-1:0])
|
3815 |
|
|
);
|
3816 |
|
|
|
3817 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
3818 |
|
|
dffe_s #(`WSR_PSTATE_VR_WIDTH-1) dff_restore_pstate1_w3 (
|
3819 |
|
|
.din ({restore_pstate1[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
|
3820 |
|
|
restore_pstate1[`WSR_PSTATE_VRANGE1_LO]}),
|
3821 |
|
|
.q ({restore_pstate1_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
|
3822 |
|
|
restore_pstate1_w3[`WSR_PSTATE_VRANGE1_LO]}),
|
3823 |
|
|
.en (~(tlu_update_pstate_l_w2[1])), .clk(clk),
|
3824 |
|
|
.se (se),
|
3825 |
|
|
.si (),
|
3826 |
|
|
.so ()
|
3827 |
|
|
);
|
3828 |
|
|
`else
|
3829 |
|
|
dff_s #(`WSR_PSTATE_VR_WIDTH-1) dff_restore_pstate1_w3 (
|
3830 |
|
|
.din ({restore_pstate1[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
|
3831 |
|
|
restore_pstate1[`WSR_PSTATE_VRANGE1_LO]}),
|
3832 |
|
|
.q ({restore_pstate1_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
|
3833 |
|
|
restore_pstate1_w3[`WSR_PSTATE_VRANGE1_LO]}),
|
3834 |
|
|
.clk (pstate1_clk),
|
3835 |
|
|
.se (se),
|
3836 |
|
|
.si (),
|
3837 |
|
|
.so ()
|
3838 |
|
|
);
|
3839 |
|
|
`endif
|
3840 |
|
|
//
|
3841 |
|
|
dffe_s dffe_pstate1_priv (
|
3842 |
|
|
.din (restore_pstate1[`WSR_PSTATE_VR_PRIV]),
|
3843 |
|
|
.q (restore_pstate1_w3[`WSR_PSTATE_VR_PRIV]),
|
3844 |
|
|
.en (pstate_priv_update_w2[1]),
|
3845 |
|
|
.clk (clk),
|
3846 |
|
|
.se (se),
|
3847 |
|
|
.si (),
|
3848 |
|
|
.so ()
|
3849 |
|
|
);
|
3850 |
|
|
//
|
3851 |
|
|
// modified to reflect the physical implementation
|
3852 |
|
|
/*
|
3853 |
|
|
assign hpstate_dnrtry_priv_w2[1] =
|
3854 |
|
|
(true_hpstate1[`HPSTATE_ENB])?
|
3855 |
|
|
tsa_dnrtry_hpstate_w2[`HPSTATE_PRIV] :
|
3856 |
|
|
dnrtry_pstate_w2[`WSR_PSTATE_VR_PRIV];
|
3857 |
|
|
*/
|
3858 |
|
|
mux2ds mx_hpstate_dnrtry_priv_w2_1 (
|
3859 |
|
|
.in0 (tsa_dnrtry_hpstate_w2[`HPSTATE_PRIV]),
|
3860 |
|
|
.in1 (dnrtry_pstate_w2[`WSR_PSTATE_VR_PRIV]),
|
3861 |
|
|
.sel0 (true_hpstate1[`HPSTATE_ENB]),
|
3862 |
|
|
.sel1 (~true_hpstate1[`HPSTATE_ENB]),
|
3863 |
|
|
.dout (hpstate_dnrtry_priv_w2[1])
|
3864 |
|
|
);
|
3865 |
|
|
//
|
3866 |
|
|
assign dnrtry_hpstate1_w2[`TLU_HPSTATE_WIDTH-1:0] =
|
3867 |
|
|
{tsa_dnrtry_hpstate_w2[`TSA_HTSTATE_WIDTH-1],
|
3868 |
|
|
true_hpstate1[`HPSTATE_ENB],
|
3869 |
|
|
tsa_dnrtry_hpstate_w2[`HPSTATE_RED],
|
3870 |
|
|
hpstate_dnrtry_priv_w2[1],
|
3871 |
|
|
tsa_dnrtry_hpstate_w2[`HPSTATE_TLZ]};
|
3872 |
|
|
//
|
3873 |
|
|
// true_pstate1 assignments
|
3874 |
|
|
assign true_pstate1[`PSTATE_TRUE_WIDTH-1:0] =
|
3875 |
|
|
{2'b0, // tlu_select_int_global - replaced by gl register
|
3876 |
|
|
// tlu_select_mmu_global - replaced by gl register
|
3877 |
|
|
restore_pstate1_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE2_LO],
|
3878 |
|
|
2'b0, // fixed mmodel - TSO
|
3879 |
|
|
1'b0, // redmode - replaced by hpstate.red
|
3880 |
|
|
restore_pstate1_w3[`WSR_PSTATE_VRANGE1_HI:`WSR_PSTATE_VRANGE1_LO],
|
3881 |
|
|
1'b0}; // tlu_select_alt_global - replaced by gl register
|
3882 |
|
|
//
|
3883 |
|
|
// modified for timing
|
3884 |
|
|
/*
|
3885 |
|
|
mux3ds #(9) mux_restore_pstate1(
|
3886 |
|
|
.in0 (dnrtry_pstate[`PSTATE_TRUE_WIDTH-3:1]),
|
3887 |
|
|
.in1 (wsr_data_pstate_g[`PSTATE_TRUE_WIDTH-3:1]),
|
3888 |
|
|
.in2 (ntrap_pstate1[`PSTATE_TRUE_WIDTH-3:1]),
|
3889 |
|
|
.sel0 (tlu_pstate_din_sel1[0]),
|
3890 |
|
|
// modified for bug 2584
|
3891 |
|
|
// .sel1 (tlu_pstate_din_sel1[1]),
|
3892 |
|
|
.sel1 (tlu_pstate_wsr_sel1),
|
3893 |
|
|
.sel2 (tlu_pstate_nt_sel1),
|
3894 |
|
|
.dout (restore_pstate1[`PSTATE_TRUE_WIDTH-3:1])
|
3895 |
|
|
);
|
3896 |
|
|
|
3897 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
3898 |
|
|
dffe_s #(`PSTATE_TRUE_WIDTH) pstate1_1 (
|
3899 |
|
|
.din (restore_pstate1[`PSTATE_TRUE_WIDTH-1:0]),
|
3900 |
|
|
.q (true_pstate1[`PSTATE_TRUE_WIDTH-1:0]),
|
3901 |
|
|
.en (~(tlu_update_pstate_l_w2[1])), .clk(clk),
|
3902 |
|
|
.se (se),
|
3903 |
|
|
.si (),
|
3904 |
|
|
.so ()
|
3905 |
|
|
);
|
3906 |
|
|
`else
|
3907 |
|
|
dff_s #(`PSTATE_TRUE_WIDTH) pstate1_1 (
|
3908 |
|
|
.din (restore_pstate1[`PSTATE_TRUE_WIDTH-1:0]),
|
3909 |
|
|
.q (true_pstate1[`PSTATE_TRUE_WIDTH-1:0]),
|
3910 |
|
|
.clk (pstate1_clk),
|
3911 |
|
|
.se (se),
|
3912 |
|
|
.si (),
|
3913 |
|
|
.so ()
|
3914 |
|
|
);
|
3915 |
|
|
`endif
|
3916 |
|
|
//
|
3917 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
3918 |
|
|
dffe_s #(`PSTATE_TRUE_WIDTH-1) dff_true_pstate1 (
|
3919 |
|
|
.din ({restore_pstate1[`PSTATE_TRUE_WIDTH-1:3],
|
3920 |
|
|
restore_pstate1[1:0]}),
|
3921 |
|
|
.q ({true_pstate1[`PSTATE_TRUE_WIDTH-1:3],
|
3922 |
|
|
true_pstate1[1:0]}),
|
3923 |
|
|
.en (~(tlu_update_pstate_l_w2[1])), .clk(clk),
|
3924 |
|
|
.se (se),
|
3925 |
|
|
.si (),
|
3926 |
|
|
.so ()
|
3927 |
|
|
);
|
3928 |
|
|
`else
|
3929 |
|
|
dff_s #(`PSTATE_TRUE_WIDTH-1) dff_true_pstate1 (
|
3930 |
|
|
.din ({restore_pstate1[`PSTATE_TRUE_WIDTH-1:3],
|
3931 |
|
|
restore_pstate1[1:0]}),
|
3932 |
|
|
.q ({true_pstate1[`PSTATE_TRUE_WIDTH-1:3],
|
3933 |
|
|
true_pstate1[1:0]}),
|
3934 |
|
|
.clk (pstate1_clk),
|
3935 |
|
|
.se (se),
|
3936 |
|
|
.si (),
|
3937 |
|
|
.so ()
|
3938 |
|
|
);
|
3939 |
|
|
`endif
|
3940 |
|
|
//
|
3941 |
|
|
dffe_s dffe_pstate1_priv (
|
3942 |
|
|
.din (restore_pstate1[`PSTATE_PRIV]),
|
3943 |
|
|
.q (true_pstate1[`PSTATE_PRIV]),
|
3944 |
|
|
.en (pstate_priv_update_g[1]),
|
3945 |
|
|
.clk (clk),
|
3946 |
|
|
.se (se),
|
3947 |
|
|
.si (),
|
3948 |
|
|
.so ()
|
3949 |
|
|
);
|
3950 |
|
|
//
|
3951 |
|
|
// modified for hypervisor support
|
3952 |
|
|
assign restore_pstate1[11:10] = 2'b0;
|
3953 |
|
|
assign restore_pstate1[0] = 1'b0;
|
3954 |
|
|
*/
|
3955 |
|
|
//
|
3956 |
|
|
// constructing the hpstate for hyper-privileged traps
|
3957 |
|
|
//
|
3958 |
|
|
assign hntrap_hpstate1_w2[`TLU_HPSTATE_WIDTH-1:0] =
|
3959 |
|
|
{hpstate_ibe_set[1],
|
3960 |
|
|
hpstate_enb_set[1],
|
3961 |
|
|
hpstate_redmode, // Redmode bit
|
3962 |
|
|
hpstate_priv_set, // hyper-privileged bit
|
3963 |
|
|
hpstate_tlz_set[1]}; // TLZ interrupt bit
|
3964 |
|
|
//
|
3965 |
|
|
assign tlu_hpstate_hnt_sel1 =
|
3966 |
|
|
~(tlu_hpstate_din_sel1[0] | tlu_hpstate_wsr_sel1);
|
3967 |
|
|
//
|
3968 |
|
|
assign tlu_hpstate_wsr_sel1 =
|
3969 |
|
|
tlu_hpstate_din_sel1[1] |
|
3970 |
|
|
(~true_hpstate1[`HPSTATE_ENB] & tlu_pstate_din_sel1[1]);
|
3971 |
|
|
|
3972 |
|
|
mux3ds #(`TLU_HPSTATE_WIDTH) mux_restore_hpstate1 (
|
3973 |
|
|
.in0 (dnrtry_hpstate1_w2[`TLU_HPSTATE_WIDTH-1:0]),
|
3974 |
|
|
.in1 (wsr_data_hpstate_w2[`TLU_HPSTATE_WIDTH-1:0]),
|
3975 |
|
|
.in2 (hntrap_hpstate1_w2[`TLU_HPSTATE_WIDTH-1:0]),
|
3976 |
|
|
.sel0 (tlu_hpstate_din_sel1[0]),
|
3977 |
|
|
.sel1 (tlu_hpstate_wsr_sel1),
|
3978 |
|
|
.sel2 (tlu_hpstate_hnt_sel1),
|
3979 |
|
|
.dout (restore_hpstate1[`TLU_HPSTATE_WIDTH-1:0])
|
3980 |
|
|
);
|
3981 |
|
|
|
3982 |
|
|
// need to initialize hpstate.enb = 0
|
3983 |
|
|
// need to initialize hpstate.ibe = 0
|
3984 |
|
|
// modified due to the addition of hpstate.ibe
|
3985 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
3986 |
|
|
dffre_s #(2) dffr_true_hpst1_enb_ibe (
|
3987 |
|
|
.din (restore_hpstate1[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
|
3988 |
|
|
.q (true_hpstate1[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
|
3989 |
|
|
.rst (local_rst),
|
3990 |
|
|
.en (~(tlu_update_hpstate_l_w2[1])), .clk(clk),
|
3991 |
|
|
.se (se),
|
3992 |
|
|
.si (),
|
3993 |
|
|
.so ()
|
3994 |
|
|
);
|
3995 |
|
|
`else
|
3996 |
|
|
dffr_s #(2) dffr_true_hpst1_enb_ibe (
|
3997 |
|
|
.din (restore_hpstate1[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
|
3998 |
|
|
.q (true_hpstate1[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
|
3999 |
|
|
.rst (local_rst),
|
4000 |
|
|
.clk (hpstate1_clk),
|
4001 |
|
|
.se (se),
|
4002 |
|
|
.si (),
|
4003 |
|
|
.so ()
|
4004 |
|
|
);
|
4005 |
|
|
`endif
|
4006 |
|
|
//
|
4007 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
4008 |
|
|
dffe_s #(2) dff_true_hpstate1 (
|
4009 |
|
|
.din ({restore_hpstate1[`HPSTATE_RED],
|
4010 |
|
|
restore_hpstate1[`HPSTATE_TLZ]}),
|
4011 |
|
|
.q ({true_hpstate1[`HPSTATE_RED],
|
4012 |
|
|
true_hpstate1[`HPSTATE_TLZ]}),
|
4013 |
|
|
.en (~(tlu_update_hpstate_l_w2[1])), .clk(clk),
|
4014 |
|
|
.se (se),
|
4015 |
|
|
.si (),
|
4016 |
|
|
.so ()
|
4017 |
|
|
);
|
4018 |
|
|
`else
|
4019 |
|
|
dff_s #(2) dff_true_hpstate1 (
|
4020 |
|
|
.din ({restore_hpstate1[`HPSTATE_RED],
|
4021 |
|
|
restore_hpstate1[`HPSTATE_TLZ]}),
|
4022 |
|
|
.q ({true_hpstate1[`HPSTATE_RED],
|
4023 |
|
|
true_hpstate1[`HPSTATE_TLZ]}),
|
4024 |
|
|
.clk (hpstate1_clk),
|
4025 |
|
|
.se (se),
|
4026 |
|
|
.si (),
|
4027 |
|
|
.so ()
|
4028 |
|
|
);
|
4029 |
|
|
`endif
|
4030 |
|
|
//
|
4031 |
|
|
dffe_s dffe_hpstate1_priv (
|
4032 |
|
|
.din (restore_hpstate1[`HPSTATE_PRIV]),
|
4033 |
|
|
.q (true_hpstate1[`HPSTATE_PRIV]),
|
4034 |
|
|
.en (hpstate_priv_update_w2[1]),
|
4035 |
|
|
.clk (clk),
|
4036 |
|
|
.se (se),
|
4037 |
|
|
.si (),
|
4038 |
|
|
.so ()
|
4039 |
|
|
);
|
4040 |
|
|
|
4041 |
|
|
assign tlu_ifu_pstate_pef[1] = true_pstate1[`PSTATE_PEF];
|
4042 |
|
|
assign tlu_lsu_pstate_cle[1] = true_pstate1[`PSTATE_CLE];
|
4043 |
|
|
assign tlu_lsu_pstate_priv[1] = true_pstate1[`PSTATE_PRIV];
|
4044 |
|
|
assign tlu_int_pstate_ie[1] = true_pstate1[`PSTATE_IE];
|
4045 |
|
|
assign local_pstate_ie[1] = true_pstate1[`PSTATE_IE];
|
4046 |
|
|
// assign tlu_pstate_cle[1] = true_pstate1[`PSTATE_CLE];
|
4047 |
|
|
assign tlu_pstate_tle[1] = true_pstate1[`PSTATE_TLE];
|
4048 |
|
|
// assign tlu_pstate_priv[1] = true_pstate1[`PSTATE_PRIV];
|
4049 |
|
|
assign local_pstate_priv[1] = true_pstate1[`PSTATE_PRIV];
|
4050 |
|
|
assign tlu_pstate_am[1] = true_pstate1[`PSTATE_AM];
|
4051 |
|
|
// assign tlu_pstate1_mmodel[1:0] = true_pstate1[`PSTATE_MM_HI:`PSTATE_MM_LO];
|
4052 |
|
|
//
|
4053 |
|
|
assign tlu_int_redmode[1] = true_hpstate1[`HPSTATE_RED];
|
4054 |
|
|
assign tlu_lsu_redmode[1] = true_hpstate1[`HPSTATE_RED];
|
4055 |
|
|
//
|
4056 |
|
|
// hypervisor privilege indicator
|
4057 |
|
|
assign tlu_hpstate_priv[1] = true_hpstate1[`HPSTATE_PRIV];
|
4058 |
|
|
assign local_hpstate_priv[1] = true_hpstate1[`HPSTATE_PRIV];
|
4059 |
|
|
assign tcl_hpstate_priv[1] = true_hpstate1[`HPSTATE_PRIV];
|
4060 |
|
|
//
|
4061 |
|
|
// hypervisor lite mode selector
|
4062 |
|
|
assign tlu_hpstate_enb[1] = true_hpstate1[`HPSTATE_ENB];
|
4063 |
|
|
assign local_hpstate_enb[1] = true_hpstate1[`HPSTATE_ENB];
|
4064 |
|
|
assign tcl_hpstate_enb[1] = true_hpstate1[`HPSTATE_ENB];
|
4065 |
|
|
|
4066 |
|
|
// hypervisor tlz indicator
|
4067 |
|
|
assign tlu_hpstate_tlz[1] = true_hpstate1[`HPSTATE_TLZ];
|
4068 |
|
|
|
4069 |
|
|
// hypervisor instruction breakpt enable
|
4070 |
|
|
assign tlu_hpstate_ibe[1] = true_hpstate1[`HPSTATE_IBE];
|
4071 |
|
|
|
4072 |
|
|
// THREAD2
|
4073 |
|
|
// added for bug 1575
|
4074 |
|
|
// modified for bug 2584
|
4075 |
|
|
// assign tlu_pstate_nt_sel2 = ~|(tlu_pstate_din_sel2[1:0]);
|
4076 |
|
|
assign tlu_pstate_nt_sel2 =
|
4077 |
|
|
~(tlu_pstate_din_sel2[0] | tlu_pstate_wsr_sel2);
|
4078 |
|
|
//
|
4079 |
|
|
// modified for bug 3349
|
4080 |
|
|
assign tlu_pstate_wsr_sel2 =
|
4081 |
|
|
tlu_pstate_din_sel2[1] |
|
4082 |
|
|
(~(true_hpstate2[`HPSTATE_ENB] & wsr_data_w2[`WSR_HPSTATE_ENB]) &
|
4083 |
|
|
tlu_hpstate_din_sel2[1]);
|
4084 |
|
|
// (~true_hpstate2[`HPSTATE_ENB] & tlu_hpstate_din_sel2[1]);
|
4085 |
|
|
|
4086 |
|
|
mux3ds #(`WSR_PSTATE_VR_WIDTH) mux_restore_pstate2(
|
4087 |
|
|
.in0 (dnrtry_pstate_w2[`WSR_PSTATE_VR_WIDTH-1:0]),
|
4088 |
|
|
.in1 (wsr_data_pstate_w2[`WSR_PSTATE_VR_WIDTH-1:0]),
|
4089 |
|
|
.in2 (ntrap_pstate2[`WSR_PSTATE_VR_WIDTH-1:0]),
|
4090 |
|
|
.sel0 (tlu_pstate_din_sel2[0]),
|
4091 |
|
|
.sel1 (tlu_pstate_wsr_sel2),
|
4092 |
|
|
.sel2 (tlu_pstate_nt_sel2),
|
4093 |
|
|
.dout (restore_pstate2[`WSR_PSTATE_VR_WIDTH-1:0])
|
4094 |
|
|
);
|
4095 |
|
|
|
4096 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
4097 |
|
|
dffe_s #(`WSR_PSTATE_VR_WIDTH-1) dff_restore_pstate2_w3 (
|
4098 |
|
|
.din ({restore_pstate2[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
|
4099 |
|
|
restore_pstate2[`WSR_PSTATE_VRANGE1_LO]}),
|
4100 |
|
|
.q ({restore_pstate2_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
|
4101 |
|
|
restore_pstate2_w3[`WSR_PSTATE_VRANGE1_LO]}),
|
4102 |
|
|
.en (~(tlu_update_pstate_l_w2[2])), .clk(clk),
|
4103 |
|
|
.se (se),
|
4104 |
|
|
.si (),
|
4105 |
|
|
.so ()
|
4106 |
|
|
);
|
4107 |
|
|
`else
|
4108 |
|
|
dff_s #(`WSR_PSTATE_VR_WIDTH-1) dff_restore_pstate2_w3 (
|
4109 |
|
|
.din ({restore_pstate2[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
|
4110 |
|
|
restore_pstate2[`WSR_PSTATE_VRANGE1_LO]}),
|
4111 |
|
|
.q ({restore_pstate2_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
|
4112 |
|
|
restore_pstate2_w3[`WSR_PSTATE_VRANGE1_LO]}),
|
4113 |
|
|
.clk (pstate2_clk),
|
4114 |
|
|
.se (se),
|
4115 |
|
|
.si (),
|
4116 |
|
|
.so ()
|
4117 |
|
|
);
|
4118 |
|
|
`endif
|
4119 |
|
|
//
|
4120 |
|
|
dffe_s dffe_pstate2_priv (
|
4121 |
|
|
.din (restore_pstate2[`WSR_PSTATE_VR_PRIV]),
|
4122 |
|
|
.q (restore_pstate2_w3[`WSR_PSTATE_VR_PRIV]),
|
4123 |
|
|
.en (pstate_priv_update_w2[2]),
|
4124 |
|
|
.clk (clk),
|
4125 |
|
|
.se (se),
|
4126 |
|
|
.si (),
|
4127 |
|
|
.so ()
|
4128 |
|
|
);
|
4129 |
|
|
//
|
4130 |
|
|
// true_pstate2 assignments
|
4131 |
|
|
assign true_pstate2[`PSTATE_TRUE_WIDTH-1:0] =
|
4132 |
|
|
{2'b0, // tlu_select_int_global - replaced by gl register
|
4133 |
|
|
// tlu_select_mmu_global - replaced by gl register
|
4134 |
|
|
restore_pstate2_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE2_LO],
|
4135 |
|
|
2'b0, // fixed mmodel - TSO
|
4136 |
|
|
1'b0, // redmode - replaced by hpstate.red
|
4137 |
|
|
restore_pstate2_w3[`WSR_PSTATE_VRANGE1_HI:`WSR_PSTATE_VRANGE1_LO],
|
4138 |
|
|
1'b0}; // tlu_select_alt_global - replaced by gl register
|
4139 |
|
|
//
|
4140 |
|
|
// modified for timing
|
4141 |
|
|
/*
|
4142 |
|
|
mux3ds #(9) mux_restore_pstate2(
|
4143 |
|
|
.in0 (dnrtry_pstate[`PSTATE_TRUE_WIDTH-3:1]),
|
4144 |
|
|
.in1 (wsr_data_pstate_g[`PSTATE_TRUE_WIDTH-3:1]),
|
4145 |
|
|
.in2 (ntrap_pstate2[`PSTATE_TRUE_WIDTH-3:1]),
|
4146 |
|
|
.sel0 (tlu_pstate_din_sel2[0]),
|
4147 |
|
|
// modified for bug 2584
|
4148 |
|
|
// .sel1 (tlu_pstate_din_sel2[1]),
|
4149 |
|
|
.sel1 (tlu_pstate_wsr_sel2),
|
4150 |
|
|
.sel2 (tlu_pstate_nt_sel2),
|
4151 |
|
|
.dout (restore_pstate2[`PSTATE_TRUE_WIDTH-3:1])
|
4152 |
|
|
);
|
4153 |
|
|
|
4154 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
4155 |
|
|
dffe_s #(`PSTATE_TRUE_WIDTH) pstate2_1 (
|
4156 |
|
|
.din (restore_pstate2[`PSTATE_TRUE_WIDTH-1:0]),
|
4157 |
|
|
.q (true_pstate2[`PSTATE_TRUE_WIDTH-1:0]),
|
4158 |
|
|
.en (~(tlu_update_pstate_l_w2[2])), .clk(clk),
|
4159 |
|
|
.se (se),
|
4160 |
|
|
.si (),
|
4161 |
|
|
.so ()
|
4162 |
|
|
);
|
4163 |
|
|
`else
|
4164 |
|
|
dff_s #(`PSTATE_TRUE_WIDTH) pstate2_1 (
|
4165 |
|
|
.din (restore_pstate2[`PSTATE_TRUE_WIDTH-1:0]),
|
4166 |
|
|
.q (true_pstate2[`PSTATE_TRUE_WIDTH-1:0]),
|
4167 |
|
|
.clk (pstate2_clk),
|
4168 |
|
|
.se (se),
|
4169 |
|
|
.si (),
|
4170 |
|
|
.so ()
|
4171 |
|
|
);
|
4172 |
|
|
`endif
|
4173 |
|
|
//
|
4174 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
4175 |
|
|
dffe_s #(`PSTATE_TRUE_WIDTH-1) dff_true_pstate2 (
|
4176 |
|
|
.din ({restore_pstate2[`PSTATE_TRUE_WIDTH-1:3],
|
4177 |
|
|
restore_pstate2[1:0]}),
|
4178 |
|
|
.q ({true_pstate2[`PSTATE_TRUE_WIDTH-1:3],
|
4179 |
|
|
true_pstate2[1:0]}),
|
4180 |
|
|
.en (~(tlu_update_pstate_l_w2[2])), .clk(clk),
|
4181 |
|
|
.se (se),
|
4182 |
|
|
.si (),
|
4183 |
|
|
.so ()
|
4184 |
|
|
);
|
4185 |
|
|
`else
|
4186 |
|
|
dff_s #(`PSTATE_TRUE_WIDTH-1) dff_true_pstate2 (
|
4187 |
|
|
.din ({restore_pstate2[`PSTATE_TRUE_WIDTH-1:3],
|
4188 |
|
|
restore_pstate2[1:0]}),
|
4189 |
|
|
.q ({true_pstate2[`PSTATE_TRUE_WIDTH-1:3],
|
4190 |
|
|
true_pstate2[1:0]}),
|
4191 |
|
|
.clk (pstate2_clk),
|
4192 |
|
|
.se (se),
|
4193 |
|
|
.si (),
|
4194 |
|
|
.so ()
|
4195 |
|
|
);
|
4196 |
|
|
`endif
|
4197 |
|
|
//
|
4198 |
|
|
dffe_s dffe_pstate2_priv (
|
4199 |
|
|
.din (restore_pstate2[`PSTATE_PRIV]),
|
4200 |
|
|
.q (true_pstate2[`PSTATE_PRIV]),
|
4201 |
|
|
.en (pstate_priv_update_g[2]),
|
4202 |
|
|
.clk (clk),
|
4203 |
|
|
.se (se),
|
4204 |
|
|
.si (),
|
4205 |
|
|
.so ()
|
4206 |
|
|
);
|
4207 |
|
|
//
|
4208 |
|
|
// modified for hypervisor support
|
4209 |
|
|
assign restore_pstate2[11:10] = 2'b0;
|
4210 |
|
|
assign restore_pstate2[0] = 1'b0;
|
4211 |
|
|
// modified to reflect the physical implementation
|
4212 |
|
|
// restructing the hpstate for done/retry instructions
|
4213 |
|
|
//
|
4214 |
|
|
assign hpstate_dnrtry_priv_w2[2] =
|
4215 |
|
|
(true_hpstate2[`HPSTATE_ENB])?
|
4216 |
|
|
tsa_dnrtry_hpstate_w2[`HPSTATE_PRIV] :
|
4217 |
|
|
dnrtry_pstate_w2[`WSR_PSTATE_VR_PRIV];
|
4218 |
|
|
*/
|
4219 |
|
|
mux2ds mx_hpstate_dnrtry_priv_w2_2 (
|
4220 |
|
|
.in0 (tsa_dnrtry_hpstate_w2[`HPSTATE_PRIV]),
|
4221 |
|
|
.in1 (dnrtry_pstate_w2[`WSR_PSTATE_VR_PRIV]),
|
4222 |
|
|
.sel0 (true_hpstate2[`HPSTATE_ENB]),
|
4223 |
|
|
.sel1 (~true_hpstate2[`HPSTATE_ENB]),
|
4224 |
|
|
.dout (hpstate_dnrtry_priv_w2[2])
|
4225 |
|
|
);
|
4226 |
|
|
//
|
4227 |
|
|
assign dnrtry_hpstate2_w2[`TLU_HPSTATE_WIDTH-1:0] =
|
4228 |
|
|
{tsa_dnrtry_hpstate_w2[`TSA_HTSTATE_WIDTH-1],
|
4229 |
|
|
true_hpstate2[`HPSTATE_ENB],
|
4230 |
|
|
tsa_dnrtry_hpstate_w2[`HPSTATE_RED],
|
4231 |
|
|
hpstate_dnrtry_priv_w2[2],
|
4232 |
|
|
tsa_dnrtry_hpstate_w2[`HPSTATE_TLZ]};
|
4233 |
|
|
//
|
4234 |
|
|
// constructing the hpstate for hyper-privileged traps
|
4235 |
|
|
//
|
4236 |
|
|
assign hntrap_hpstate2_w2[`TLU_HPSTATE_WIDTH-1:0] =
|
4237 |
|
|
{hpstate_ibe_set[2],
|
4238 |
|
|
hpstate_enb_set[2],
|
4239 |
|
|
hpstate_redmode, // Redmode bit
|
4240 |
|
|
hpstate_priv_set, // hyper-privileged bit
|
4241 |
|
|
hpstate_tlz_set[2]}; // TLZ interrupt bit
|
4242 |
|
|
//
|
4243 |
|
|
assign tlu_hpstate_hnt_sel2 =
|
4244 |
|
|
~(tlu_hpstate_din_sel2[0] | tlu_hpstate_wsr_sel2);
|
4245 |
|
|
//
|
4246 |
|
|
assign tlu_hpstate_wsr_sel2 =
|
4247 |
|
|
tlu_hpstate_din_sel2[1] |
|
4248 |
|
|
(~true_hpstate2[`HPSTATE_ENB] & tlu_pstate_din_sel2[1]);
|
4249 |
|
|
|
4250 |
|
|
mux3ds #(`TLU_HPSTATE_WIDTH) mux_restore_hpstate2 (
|
4251 |
|
|
.in0 (dnrtry_hpstate2_w2[`TLU_HPSTATE_WIDTH-1:0]),
|
4252 |
|
|
.in1 (wsr_data_hpstate_w2[`TLU_HPSTATE_WIDTH-1:0]),
|
4253 |
|
|
.in2 (hntrap_hpstate2_w2[`TLU_HPSTATE_WIDTH-1:0]),
|
4254 |
|
|
.sel0 (tlu_hpstate_din_sel2[0]),
|
4255 |
|
|
.sel1 (tlu_hpstate_wsr_sel2),
|
4256 |
|
|
.sel2 (tlu_hpstate_hnt_sel2),
|
4257 |
|
|
.dout (restore_hpstate2[`TLU_HPSTATE_WIDTH-1:0])
|
4258 |
|
|
);
|
4259 |
|
|
//
|
4260 |
|
|
// need to initialize hpstate.enb = 0
|
4261 |
|
|
// need to initialize hpstate.ibe = 0
|
4262 |
|
|
// modified due to the addition of hpstate.ibe
|
4263 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
4264 |
|
|
dffre_s #(2) dffr_true_hpst2_enb_ibe (
|
4265 |
|
|
.din (restore_hpstate2[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
|
4266 |
|
|
.q (true_hpstate2[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
|
4267 |
|
|
.rst (local_rst),
|
4268 |
|
|
.en (~(tlu_update_hpstate_l_w2[2])), .clk(clk),
|
4269 |
|
|
.se (se),
|
4270 |
|
|
.si (),
|
4271 |
|
|
.so ()
|
4272 |
|
|
);
|
4273 |
|
|
`else
|
4274 |
|
|
dffr_s #(2) dffr_true_hpst2_enb_ibe (
|
4275 |
|
|
.din (restore_hpstate2[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
|
4276 |
|
|
.q (true_hpstate2[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
|
4277 |
|
|
.rst (local_rst),
|
4278 |
|
|
.clk (hpstate2_clk),
|
4279 |
|
|
.se (se),
|
4280 |
|
|
.si (),
|
4281 |
|
|
.so ()
|
4282 |
|
|
);
|
4283 |
|
|
`endif
|
4284 |
|
|
//
|
4285 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
4286 |
|
|
dffe_s #(2) dff_true_hpstate2 (
|
4287 |
|
|
.din ({restore_hpstate2[`HPSTATE_RED],
|
4288 |
|
|
restore_hpstate2[`HPSTATE_TLZ]}),
|
4289 |
|
|
.q ({true_hpstate2[`HPSTATE_RED],
|
4290 |
|
|
true_hpstate2[`HPSTATE_TLZ]}),
|
4291 |
|
|
.en (~(tlu_update_hpstate_l_w2[2])), .clk(clk),
|
4292 |
|
|
.se (se),
|
4293 |
|
|
.si (),
|
4294 |
|
|
.so ()
|
4295 |
|
|
);
|
4296 |
|
|
`else
|
4297 |
|
|
dff_s #(2) dff_true_hpstate2 (
|
4298 |
|
|
.din ({restore_hpstate2[`HPSTATE_RED],
|
4299 |
|
|
restore_hpstate2[`HPSTATE_TLZ]}),
|
4300 |
|
|
.q ({true_hpstate2[`HPSTATE_RED],
|
4301 |
|
|
true_hpstate2[`HPSTATE_TLZ]}),
|
4302 |
|
|
.clk (hpstate2_clk),
|
4303 |
|
|
.se (se),
|
4304 |
|
|
.si (),
|
4305 |
|
|
.so ()
|
4306 |
|
|
);
|
4307 |
|
|
`endif
|
4308 |
|
|
//
|
4309 |
|
|
dffe_s dffe_hpstate2_priv (
|
4310 |
|
|
.din (restore_hpstate2[`HPSTATE_PRIV]),
|
4311 |
|
|
.q (true_hpstate2[`HPSTATE_PRIV]),
|
4312 |
|
|
.en (hpstate_priv_update_w2[2]),
|
4313 |
|
|
.clk (clk),
|
4314 |
|
|
.se (se),
|
4315 |
|
|
.si (),
|
4316 |
|
|
.so ()
|
4317 |
|
|
);
|
4318 |
|
|
|
4319 |
|
|
assign tlu_ifu_pstate_pef[2] = true_pstate2[`PSTATE_PEF];
|
4320 |
|
|
assign tlu_lsu_pstate_cle[2] = true_pstate2[`PSTATE_CLE];
|
4321 |
|
|
assign tlu_lsu_pstate_priv[2] = true_pstate2[`PSTATE_PRIV];
|
4322 |
|
|
assign tlu_int_pstate_ie[2] = true_pstate2[`PSTATE_IE];
|
4323 |
|
|
assign local_pstate_ie[2] = true_pstate2[`PSTATE_IE];
|
4324 |
|
|
// assign tlu_pstate_cle[2] = true_pstate2[`PSTATE_CLE];
|
4325 |
|
|
assign tlu_pstate_tle[2] = true_pstate2[`PSTATE_TLE];
|
4326 |
|
|
// assign tlu_pstate_priv[2] = true_pstate2[`PSTATE_PRIV];
|
4327 |
|
|
assign local_pstate_priv[2] = true_pstate2[`PSTATE_PRIV];
|
4328 |
|
|
assign tlu_pstate_am[2] = true_pstate2[`PSTATE_AM];
|
4329 |
|
|
// assign tlu_pstate2_mmodel[1:0] = true_pstate2[`PSTATE_MM_HI:`PSTATE_MM_LO];
|
4330 |
|
|
//
|
4331 |
|
|
// modified for hypervisor support
|
4332 |
|
|
// assign tlu_int_redmode[2] = true_pstate2[`PSTATE_RED];
|
4333 |
|
|
assign tlu_int_redmode[2] = true_hpstate2[`HPSTATE_RED];
|
4334 |
|
|
assign tlu_lsu_redmode[2] = true_hpstate2[`HPSTATE_RED];
|
4335 |
|
|
//
|
4336 |
|
|
// hypervisor privilege indicator
|
4337 |
|
|
assign tlu_hpstate_priv[2] = true_hpstate2[`HPSTATE_PRIV];
|
4338 |
|
|
assign local_hpstate_priv[2] = true_hpstate2[`HPSTATE_PRIV];
|
4339 |
|
|
assign tcl_hpstate_priv[2] = true_hpstate2[`HPSTATE_PRIV];
|
4340 |
|
|
//
|
4341 |
|
|
// hypervisor lite mode selector
|
4342 |
|
|
assign tlu_hpstate_enb[2] = true_hpstate2[`HPSTATE_ENB];
|
4343 |
|
|
assign local_hpstate_enb[2] = true_hpstate2[`HPSTATE_ENB];
|
4344 |
|
|
assign tcl_hpstate_enb[2] = true_hpstate2[`HPSTATE_ENB];
|
4345 |
|
|
|
4346 |
|
|
// hypervisor tlz indicator
|
4347 |
|
|
assign tlu_hpstate_tlz[2] = true_hpstate2[`HPSTATE_TLZ];
|
4348 |
|
|
|
4349 |
|
|
// hypervisor instruction breakpt enable
|
4350 |
|
|
assign tlu_hpstate_ibe[2] = true_hpstate2[`HPSTATE_IBE];
|
4351 |
|
|
|
4352 |
|
|
// THREAD3
|
4353 |
|
|
// added for bug 1575
|
4354 |
|
|
// modified for bug 2584
|
4355 |
|
|
// assign tlu_pstate_nt_sel3 = ~|(tlu_pstate_din_sel3[1:0]);
|
4356 |
|
|
assign tlu_pstate_nt_sel3 =
|
4357 |
|
|
~(tlu_pstate_din_sel3[0] | tlu_pstate_wsr_sel3);
|
4358 |
|
|
//
|
4359 |
|
|
// modified for bug 3349
|
4360 |
|
|
assign tlu_pstate_wsr_sel3 =
|
4361 |
|
|
tlu_pstate_din_sel3[1] |
|
4362 |
|
|
(~(true_hpstate3[`HPSTATE_ENB] & wsr_data_w2[`WSR_HPSTATE_ENB]) &
|
4363 |
|
|
tlu_hpstate_din_sel3[1]);
|
4364 |
|
|
// (~true_hpstate3[`HPSTATE_ENB] & tlu_hpstate_din_sel3[1]);
|
4365 |
|
|
//
|
4366 |
|
|
mux3ds #(`WSR_PSTATE_VR_WIDTH) mux_restore_pstate3(
|
4367 |
|
|
.in0 (dnrtry_pstate_w2[`WSR_PSTATE_VR_WIDTH-1:0]),
|
4368 |
|
|
.in1 (wsr_data_pstate_w2[`WSR_PSTATE_VR_WIDTH-1:0]),
|
4369 |
|
|
.in2 (ntrap_pstate3[`WSR_PSTATE_VR_WIDTH-1:0]),
|
4370 |
|
|
.sel0 (tlu_pstate_din_sel3[0]),
|
4371 |
|
|
.sel1 (tlu_pstate_wsr_sel3),
|
4372 |
|
|
.sel2 (tlu_pstate_nt_sel3),
|
4373 |
|
|
.dout (restore_pstate3[`WSR_PSTATE_VR_WIDTH-1:0])
|
4374 |
|
|
);
|
4375 |
|
|
|
4376 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
4377 |
|
|
dffe_s #(`WSR_PSTATE_VR_WIDTH-1) dff_restore_pstate3_w3 (
|
4378 |
|
|
.din ({restore_pstate3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
|
4379 |
|
|
restore_pstate3[`WSR_PSTATE_VRANGE1_LO]}),
|
4380 |
|
|
.q ({restore_pstate3_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
|
4381 |
|
|
restore_pstate3_w3[`WSR_PSTATE_VRANGE1_LO]}),
|
4382 |
|
|
.en (~(tlu_update_pstate_l_w2[3])), .clk(clk),
|
4383 |
|
|
.se (se),
|
4384 |
|
|
.si (),
|
4385 |
|
|
.so ()
|
4386 |
|
|
);
|
4387 |
|
|
`else
|
4388 |
|
|
dff_s #(`WSR_PSTATE_VR_WIDTH-1) dff_restore_pstate3_w3 (
|
4389 |
|
|
.din ({restore_pstate3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
|
4390 |
|
|
restore_pstate3[`WSR_PSTATE_VRANGE1_LO]}),
|
4391 |
|
|
.q ({restore_pstate3_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE1_HI-1],
|
4392 |
|
|
restore_pstate3_w3[`WSR_PSTATE_VRANGE1_LO]}),
|
4393 |
|
|
.clk (pstate3_clk),
|
4394 |
|
|
.se (se),
|
4395 |
|
|
.si (),
|
4396 |
|
|
.so ()
|
4397 |
|
|
);
|
4398 |
|
|
`endif
|
4399 |
|
|
//
|
4400 |
|
|
dffe_s dffe_pstate3_priv (
|
4401 |
|
|
.din (restore_pstate3[`WSR_PSTATE_VR_PRIV]),
|
4402 |
|
|
.q (restore_pstate3_w3[`WSR_PSTATE_VR_PRIV]),
|
4403 |
|
|
.en (pstate_priv_update_w2[3]),
|
4404 |
|
|
.clk (clk),
|
4405 |
|
|
.se (se),
|
4406 |
|
|
.si (),
|
4407 |
|
|
.so ()
|
4408 |
|
|
);
|
4409 |
|
|
//
|
4410 |
|
|
// true_pstate3 assignments
|
4411 |
|
|
assign true_pstate3[`PSTATE_TRUE_WIDTH-1:0] =
|
4412 |
|
|
{2'b0, // tlu_select_int_global - replaced by gl register
|
4413 |
|
|
// tlu_select_mmu_global - replaced by gl register
|
4414 |
|
|
restore_pstate3_w3[`WSR_PSTATE_VRANGE2_HI:`WSR_PSTATE_VRANGE2_LO],
|
4415 |
|
|
2'b0, // fixed mmodel - TSO
|
4416 |
|
|
1'b0, // redmode - replaced by hpstate.red
|
4417 |
|
|
restore_pstate3_w3[`WSR_PSTATE_VRANGE1_HI:`WSR_PSTATE_VRANGE1_LO],
|
4418 |
|
|
1'b0}; // tlu_select_alt_global - replaced by gl register
|
4419 |
|
|
//
|
4420 |
|
|
// modified for timing
|
4421 |
|
|
/*
|
4422 |
|
|
mux3ds #(9) mux_restore_pstate3(
|
4423 |
|
|
.in0 (dnrtry_pstate[`PSTATE_TRUE_WIDTH-3:1]),
|
4424 |
|
|
.in1 (wsr_data_pstate_g[`PSTATE_TRUE_WIDTH-3:1]),
|
4425 |
|
|
.in2 (ntrap_pstate3[`PSTATE_TRUE_WIDTH-3:1]),
|
4426 |
|
|
.sel0 (tlu_pstate_din_sel3[0]),
|
4427 |
|
|
// modified for bug 2584
|
4428 |
|
|
// .sel1 (tlu_pstate_din_sel3[1]),
|
4429 |
|
|
.sel1 (tlu_pstate_wsr_sel3),
|
4430 |
|
|
.sel2 (tlu_pstate_nt_sel3),
|
4431 |
|
|
.dout (restore_pstate3[`PSTATE_TRUE_WIDTH-3:1])
|
4432 |
|
|
);
|
4433 |
|
|
//
|
4434 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
4435 |
|
|
dffe_s #(`PSTATE_TRUE_WIDTH) pstate3_1 (
|
4436 |
|
|
.din (restore_pstate3[`PSTATE_TRUE_WIDTH-1:0]),
|
4437 |
|
|
.q (true_pstate3[`PSTATE_TRUE_WIDTH-1:0]),
|
4438 |
|
|
.en (~(tlu_update_pstate_l_w2[3])), .clk(clk),
|
4439 |
|
|
.se (se),
|
4440 |
|
|
.si (),
|
4441 |
|
|
.so ()
|
4442 |
|
|
);
|
4443 |
|
|
`else
|
4444 |
|
|
dff_s #(`PSTATE_TRUE_WIDTH) pstate3_1 (
|
4445 |
|
|
.din (restore_pstate3[`PSTATE_TRUE_WIDTH-1:0]),
|
4446 |
|
|
.q (true_pstate3[`PSTATE_TRUE_WIDTH-1:0]),
|
4447 |
|
|
.clk (pstate3_clk),
|
4448 |
|
|
.se (se),
|
4449 |
|
|
.si (),
|
4450 |
|
|
.so ()
|
4451 |
|
|
);
|
4452 |
|
|
`endif
|
4453 |
|
|
//
|
4454 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
4455 |
|
|
dffe_s #(`PSTATE_TRUE_WIDTH-1) pstate3_1 (
|
4456 |
|
|
.din ({restore_pstate3[`PSTATE_TRUE_WIDTH-1:3],
|
4457 |
|
|
restore_pstate3[1:0]}),
|
4458 |
|
|
.q ({true_pstate3[`PSTATE_TRUE_WIDTH-1:3],
|
4459 |
|
|
true_pstate3[1:0]}),
|
4460 |
|
|
.en (~(tlu_update_pstate_l_w2[3])), .clk(clk),
|
4461 |
|
|
.se (se),
|
4462 |
|
|
.si (),
|
4463 |
|
|
.so ()
|
4464 |
|
|
);
|
4465 |
|
|
`else
|
4466 |
|
|
dff_s #(`PSTATE_TRUE_WIDTH-1) pstate3_1 (
|
4467 |
|
|
.din ({restore_pstate3[`PSTATE_TRUE_WIDTH-1:3],
|
4468 |
|
|
restore_pstate3[1:0]}),
|
4469 |
|
|
.q ({true_pstate3[`PSTATE_TRUE_WIDTH-1:3],
|
4470 |
|
|
true_pstate3[1:0]}),
|
4471 |
|
|
.clk (pstate3_clk),
|
4472 |
|
|
.se (se),
|
4473 |
|
|
.si (),
|
4474 |
|
|
.so ()
|
4475 |
|
|
);
|
4476 |
|
|
`endif
|
4477 |
|
|
//
|
4478 |
|
|
dffe_s dffe_pstate3_priv (
|
4479 |
|
|
.din (restore_pstate3[`PSTATE_PRIV]),
|
4480 |
|
|
.q (true_pstate3[`PSTATE_PRIV]),
|
4481 |
|
|
.en (pstate_priv_update_g[3]),
|
4482 |
|
|
.clk (clk),
|
4483 |
|
|
.se (se),
|
4484 |
|
|
.si (),
|
4485 |
|
|
.so ()
|
4486 |
|
|
);
|
4487 |
|
|
//
|
4488 |
|
|
// modified for hypervisor support
|
4489 |
|
|
assign restore_pstate3[11:10] = 2'b0;
|
4490 |
|
|
assign restore_pstate3[0] = 1'b0;
|
4491 |
|
|
//
|
4492 |
|
|
// modified to reflect the physical implementation
|
4493 |
|
|
assign hpstate_dnrtry_priv_w2[3] =
|
4494 |
|
|
(true_hpstate3[`HPSTATE_ENB])?
|
4495 |
|
|
tsa_dnrtry_hpstate_w2[`HPSTATE_PRIV] :
|
4496 |
|
|
dnrtry_pstate_w2[`WSR_PSTATE_VR_PRIV];
|
4497 |
|
|
*/
|
4498 |
|
|
mux2ds mx_hpstate_dnrtry_priv_w2_3 (
|
4499 |
|
|
.in0 (tsa_dnrtry_hpstate_w2[`HPSTATE_PRIV]),
|
4500 |
|
|
.in1 (dnrtry_pstate_w2[`WSR_PSTATE_VR_PRIV]),
|
4501 |
|
|
.sel0 (true_hpstate3[`HPSTATE_ENB]),
|
4502 |
|
|
.sel1 (~true_hpstate3[`HPSTATE_ENB]),
|
4503 |
|
|
.dout (hpstate_dnrtry_priv_w2[3])
|
4504 |
|
|
);
|
4505 |
|
|
//
|
4506 |
|
|
assign dnrtry_hpstate3_w2[`TLU_HPSTATE_WIDTH-1:0] =
|
4507 |
|
|
{tsa_dnrtry_hpstate_w2[`TSA_HTSTATE_WIDTH-1],
|
4508 |
|
|
true_hpstate3[`HPSTATE_ENB],
|
4509 |
|
|
tsa_dnrtry_hpstate_w2[`HPSTATE_RED],
|
4510 |
|
|
hpstate_dnrtry_priv_w2[3],
|
4511 |
|
|
tsa_dnrtry_hpstate_w2[`HPSTATE_TLZ]};
|
4512 |
|
|
//
|
4513 |
|
|
// constructing the hpstate for hyper-privileged traps
|
4514 |
|
|
//
|
4515 |
|
|
assign hntrap_hpstate3_w2[`TLU_HPSTATE_WIDTH-1:0] =
|
4516 |
|
|
{hpstate_ibe_set[3],
|
4517 |
|
|
hpstate_enb_set[3],
|
4518 |
|
|
hpstate_redmode, // Redmode bit
|
4519 |
|
|
hpstate_priv_set, // hyper-privileged bit
|
4520 |
|
|
hpstate_tlz_set[3]}; // TLZ interrupt bit
|
4521 |
|
|
|
4522 |
|
|
assign tlu_hpstate_hnt_sel3 =
|
4523 |
|
|
~(tlu_hpstate_din_sel3[0] | tlu_hpstate_wsr_sel3);
|
4524 |
|
|
//
|
4525 |
|
|
assign tlu_hpstate_wsr_sel3 =
|
4526 |
|
|
tlu_hpstate_din_sel3[1] |
|
4527 |
|
|
(~true_hpstate3[`HPSTATE_ENB] & tlu_pstate_din_sel3[1]);
|
4528 |
|
|
|
4529 |
|
|
mux3ds #(`TLU_HPSTATE_WIDTH) mux_restore_hpstate3 (
|
4530 |
|
|
.in0 (dnrtry_hpstate3_w2[`TLU_HPSTATE_WIDTH-1:0]),
|
4531 |
|
|
.in1 (wsr_data_hpstate_w2[`TLU_HPSTATE_WIDTH-1:0]),
|
4532 |
|
|
.in2 (hntrap_hpstate3_w2[`TLU_HPSTATE_WIDTH-1:0]),
|
4533 |
|
|
.sel0 (tlu_hpstate_din_sel3[0]),
|
4534 |
|
|
.sel1 (tlu_hpstate_wsr_sel3),
|
4535 |
|
|
.sel2 (tlu_hpstate_hnt_sel3),
|
4536 |
|
|
.dout (restore_hpstate3[`TLU_HPSTATE_WIDTH-1:0])
|
4537 |
|
|
);
|
4538 |
|
|
//
|
4539 |
|
|
// need to initialize hpstate.enb = 0
|
4540 |
|
|
// need to initialize hpstate.ibe = 0
|
4541 |
|
|
// modified due to the addition of hpstate.ibe
|
4542 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
4543 |
|
|
dffre_s #(2) dffr_true_hpst3_enb_ibe (
|
4544 |
|
|
.din (restore_hpstate3[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
|
4545 |
|
|
.q (true_hpstate3[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
|
4546 |
|
|
.rst (local_rst),
|
4547 |
|
|
.en (~(tlu_update_hpstate_l_w2[3])), .clk(clk),
|
4548 |
|
|
.se (se),
|
4549 |
|
|
.si (),
|
4550 |
|
|
.so ()
|
4551 |
|
|
);
|
4552 |
|
|
`else
|
4553 |
|
|
dffr_s #(2) dffr_true_hpst3_enb_ibe (
|
4554 |
|
|
.din (restore_hpstate3[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
|
4555 |
|
|
.q (true_hpstate3[`TLU_HPSTATE_WIDTH-1:`TLU_HPSTATE_WIDTH-2]),
|
4556 |
|
|
.rst (local_rst),
|
4557 |
|
|
.clk (hpstate3_clk),
|
4558 |
|
|
.se (se),
|
4559 |
|
|
.si (),
|
4560 |
|
|
.so ()
|
4561 |
|
|
);
|
4562 |
|
|
`endif
|
4563 |
|
|
//
|
4564 |
|
|
//
|
4565 |
|
|
`ifdef FPGA_SYN_CLK_DFF
|
4566 |
|
|
dffe_s #(2) dff_true_hpstate3 (
|
4567 |
|
|
.din ({restore_hpstate3[`HPSTATE_RED],
|
4568 |
|
|
restore_hpstate3[`HPSTATE_TLZ]}),
|
4569 |
|
|
.q ({true_hpstate3[`HPSTATE_RED],
|
4570 |
|
|
true_hpstate3[`HPSTATE_TLZ]}),
|
4571 |
|
|
.en (~(tlu_update_hpstate_l_w2[3])), .clk(clk),
|
4572 |
|
|
.se (se),
|
4573 |
|
|
.si (),
|
4574 |
|
|
.so ()
|
4575 |
|
|
);
|
4576 |
|
|
`else
|
4577 |
|
|
dff_s #(2) dff_true_hpstate3 (
|
4578 |
|
|
.din ({restore_hpstate3[`HPSTATE_RED],
|
4579 |
|
|
restore_hpstate3[`HPSTATE_TLZ]}),
|
4580 |
|
|
.q ({true_hpstate3[`HPSTATE_RED],
|
4581 |
|
|
true_hpstate3[`HPSTATE_TLZ]}),
|
4582 |
|
|
.clk (hpstate3_clk),
|
4583 |
|
|
.se (se),
|
4584 |
|
|
.si (),
|
4585 |
|
|
.so ()
|
4586 |
|
|
);
|
4587 |
|
|
`endif
|
4588 |
|
|
//
|
4589 |
|
|
dffe_s dffe_hpstate3_priv (
|
4590 |
|
|
.din (restore_hpstate3[`HPSTATE_PRIV]),
|
4591 |
|
|
.q (true_hpstate3[`HPSTATE_PRIV]),
|
4592 |
|
|
.en (hpstate_priv_update_w2[3]),
|
4593 |
|
|
.clk (clk),
|
4594 |
|
|
.se (se),
|
4595 |
|
|
.si (),
|
4596 |
|
|
.so ()
|
4597 |
|
|
);
|
4598 |
|
|
|
4599 |
|
|
assign tlu_ifu_pstate_pef[3] = true_pstate3[`PSTATE_PEF];
|
4600 |
|
|
assign tlu_lsu_pstate_cle[3] = true_pstate3[`PSTATE_CLE];
|
4601 |
|
|
assign tlu_lsu_pstate_priv[3] = true_pstate3[`PSTATE_PRIV];
|
4602 |
|
|
assign tlu_int_pstate_ie[3] = true_pstate3[`PSTATE_IE];
|
4603 |
|
|
assign local_pstate_ie[3] = true_pstate3[`PSTATE_IE];
|
4604 |
|
|
// assign tlu_pstate_cle[3] = true_pstate3[`PSTATE_CLE];
|
4605 |
|
|
assign tlu_pstate_tle[3] = true_pstate3[`PSTATE_TLE];
|
4606 |
|
|
// assign tlu_pstate_priv[3] = true_pstate3[`PSTATE_PRIV];
|
4607 |
|
|
assign local_pstate_priv[3] = true_pstate3[`PSTATE_PRIV];
|
4608 |
|
|
assign tlu_pstate_am[3] = true_pstate3[`PSTATE_AM];
|
4609 |
|
|
// assign tlu_pstate3_mmodel[1:0] = true_pstate3[`PSTATE_MM_HI:`PSTATE_MM_LO];
|
4610 |
|
|
//
|
4611 |
|
|
// modified for hypervisor support
|
4612 |
|
|
// assign tlu_int_redmode[3] = true_pstate3[`PSTATE_RED];
|
4613 |
|
|
assign tlu_int_redmode[3] = true_hpstate3[`HPSTATE_RED];
|
4614 |
|
|
assign tlu_lsu_redmode[3] = true_hpstate3[`HPSTATE_RED];
|
4615 |
|
|
//
|
4616 |
|
|
// hypervisor privilege indicator
|
4617 |
|
|
assign tlu_hpstate_priv[3] = true_hpstate3[`HPSTATE_PRIV];
|
4618 |
|
|
assign local_hpstate_priv[3] = true_hpstate3[`HPSTATE_PRIV];
|
4619 |
|
|
assign tcl_hpstate_priv[3] = true_hpstate3[`HPSTATE_PRIV];
|
4620 |
|
|
//
|
4621 |
|
|
// hypervisor lite mode selector
|
4622 |
|
|
assign tlu_hpstate_enb[3] = true_hpstate3[`HPSTATE_ENB];
|
4623 |
|
|
assign local_hpstate_enb[3] = true_hpstate3[`HPSTATE_ENB];
|
4624 |
|
|
assign tcl_hpstate_enb[3] = true_hpstate3[`HPSTATE_ENB];
|
4625 |
|
|
|
4626 |
|
|
// hypervisor tlz indicator
|
4627 |
|
|
assign tlu_hpstate_tlz[3] = true_hpstate3[`HPSTATE_TLZ];
|
4628 |
|
|
|
4629 |
|
|
// hypervisor instruction breakpt enable
|
4630 |
|
|
assign tlu_hpstate_ibe[3] = true_hpstate3[`HPSTATE_IBE];
|
4631 |
|
|
|
4632 |
|
|
`endif // !`ifdef FPGA_SYN_1THREAD
|
4633 |
|
|
|
4634 |
|
|
// Mux to choose the pstate register to read base on thread
|
4635 |
|
|
wire [`PSTATE_TRUE_WIDTH-1:0] pstate_rdata;
|
4636 |
|
|
wire [`RDSR_HPSTATE_WIDTH-1:0] hpstate_rdata;
|
4637 |
|
|
|
4638 |
|
|
`ifdef FPGA_SYN_1THREAD
|
4639 |
|
|
assign pstate_rdata[`PSTATE_TRUE_WIDTH-1:0] = true_pstate0[`PSTATE_TRUE_WIDTH-1:0];
|
4640 |
|
|
assign true_hpstate[`TLU_HPSTATE_WIDTH-1:0] = true_hpstate0[`TLU_HPSTATE_WIDTH-1:0];
|
4641 |
|
|
`else
|
4642 |
|
|
|
4643 |
|
|
mux4ds #(12) pstate_mx_sel (
|
4644 |
|
|
.in0 (true_pstate0[`PSTATE_TRUE_WIDTH-1:0]),
|
4645 |
|
|
.in1 (true_pstate1[`PSTATE_TRUE_WIDTH-1:0]),
|
4646 |
|
|
.in2 (true_pstate2[`PSTATE_TRUE_WIDTH-1:0]),
|
4647 |
|
|
.in3 (true_pstate3[`PSTATE_TRUE_WIDTH-1:0]),
|
4648 |
|
|
.sel0 (tlu_thrd_rsel_e[0]),
|
4649 |
|
|
.sel1 (tlu_thrd_rsel_e[1]),
|
4650 |
|
|
.sel2 (tlu_thrd_rsel_e[2]),
|
4651 |
|
|
.sel3 (tlu_thrd_rsel_e[3]),
|
4652 |
|
|
.dout (pstate_rdata[`PSTATE_TRUE_WIDTH-1:0])
|
4653 |
|
|
);
|
4654 |
|
|
//
|
4655 |
|
|
// added for hypervisor support
|
4656 |
|
|
// mux to choose the pstate register to read base on thread
|
4657 |
|
|
|
4658 |
|
|
mux4ds #(`TLU_HPSTATE_WIDTH) hpstate_mx_sel (
|
4659 |
|
|
.in0 (true_hpstate0[`TLU_HPSTATE_WIDTH-1:0]),
|
4660 |
|
|
.in1 (true_hpstate1[`TLU_HPSTATE_WIDTH-1:0]),
|
4661 |
|
|
.in2 (true_hpstate2[`TLU_HPSTATE_WIDTH-1:0]),
|
4662 |
|
|
.in3 (true_hpstate3[`TLU_HPSTATE_WIDTH-1:0]),
|
4663 |
|
|
.sel0 (tlu_thrd_rsel_e[0]),
|
4664 |
|
|
.sel1 (tlu_thrd_rsel_e[1]),
|
4665 |
|
|
.sel2 (tlu_thrd_rsel_e[2]),
|
4666 |
|
|
.sel3 (tlu_thrd_rsel_e[3]),
|
4667 |
|
|
.dout (true_hpstate[`TLU_HPSTATE_WIDTH-1:0])
|
4668 |
|
|
);
|
4669 |
|
|
`endif // !`ifdef FPGA_SYN_1THREAD
|
4670 |
|
|
|
4671 |
|
|
//
|
4672 |
|
|
// assigned the stored hpstate bits to the ASR positions
|
4673 |
|
|
//
|
4674 |
|
|
assign hpstate_rdata[`WSR_HPSTATE_ENB] = true_hpstate[`HPSTATE_ENB];
|
4675 |
|
|
assign hpstate_rdata[`WSR_HPSTATE_IBE] = true_hpstate[`HPSTATE_IBE];
|
4676 |
|
|
assign hpstate_rdata[`WSR_HPSTATE_RED] = true_hpstate[`HPSTATE_RED];
|
4677 |
|
|
assign hpstate_rdata[`WSR_HPSTATE_PRIV] = true_hpstate[`HPSTATE_PRIV];
|
4678 |
|
|
assign hpstate_rdata[`WSR_HPSTATE_TLZ] = true_hpstate[`HPSTATE_TLZ];
|
4679 |
|
|
//
|
4680 |
|
|
// grounding the reserved bits
|
4681 |
|
|
// modified due to the addition of hpstate.ibe
|
4682 |
|
|
// assign hpstate_rdata[`WSR_HPSTATE_ENB-1 :`WSR_HPSTATE_RED+1] = 5'h00;
|
4683 |
|
|
assign hpstate_rdata[`WSR_HPSTATE_IBE-1 :`WSR_HPSTATE_RED+1] = 4'h0;
|
4684 |
|
|
assign hpstate_rdata[`WSR_HPSTATE_RED-1 :`WSR_HPSTATE_PRIV+1] = 2'b00;
|
4685 |
|
|
assign hpstate_rdata[`WSR_HPSTATE_PRIV-1:`WSR_HPSTATE_TLZ+1] = 1'b0;
|
4686 |
|
|
//
|
4687 |
|
|
// constructing data for htstate
|
4688 |
|
|
//
|
4689 |
|
|
wire [`RDSR_HPSTATE_WIDTH-1:0] htstate_rdata;
|
4690 |
|
|
|
4691 |
|
|
// assign htstate_rdata[`WSR_HPSTATE_RED] = tsa_rdata[`TLU_HTSTATE_HI];
|
4692 |
|
|
// assign htstate_rdata[`WSR_HPSTATE_PRIV] = tsa_rdata[`TLU_HTSTATE_HI-1];
|
4693 |
|
|
/* modified due to logic redistribution
|
4694 |
|
|
assign htstate_rdata[`WSR_HPSTATE_IBE] = tsa_rdata[`TLU_HTSTATE_HI];
|
4695 |
|
|
assign htstate_rdata[`WSR_HPSTATE_RED] = tsa_rdata[`TLU_HTSTATE_HI-1];
|
4696 |
|
|
assign htstate_rdata[`WSR_HPSTATE_PRIV] = tsa_rdata[`TLU_HTSTATE_HI-2];
|
4697 |
|
|
assign htstate_rdata[`WSR_HPSTATE_TLZ] = tsa_rdata[`TLU_HTSTATE_LO];
|
4698 |
|
|
*/
|
4699 |
|
|
assign htstate_rdata[`WSR_HPSTATE_IBE] = tsa_rdata[`TLU_RD_HTSTATE_HI];
|
4700 |
|
|
assign htstate_rdata[`WSR_HPSTATE_RED] = tsa_rdata[`TLU_RD_HTSTATE_HI-1];
|
4701 |
|
|
assign htstate_rdata[`WSR_HPSTATE_PRIV] = tsa_rdata[`TLU_RD_HTSTATE_HI-2];
|
4702 |
|
|
assign htstate_rdata[`WSR_HPSTATE_TLZ] = tsa_rdata[`TLU_RD_HTSTATE_LO];
|
4703 |
|
|
//
|
4704 |
|
|
// grounding the reserved bits
|
4705 |
|
|
// modified due to addition of hpstate.ibe
|
4706 |
|
|
// assign htstate_rdata[`RDSR_HPSTATE_WIDTH-1 :`WSR_HPSTATE_RED+1] = 6'h00;
|
4707 |
|
|
assign htstate_rdata[`RDSR_HPSTATE_WIDTH-1] = 1'b0;
|
4708 |
|
|
assign htstate_rdata[`WSR_HPSTATE_IBE-1 :`WSR_HPSTATE_RED+1] = 4'h0;
|
4709 |
|
|
assign htstate_rdata[`WSR_HPSTATE_RED-1 :`WSR_HPSTATE_PRIV+1] = 2'b00;
|
4710 |
|
|
assign htstate_rdata[`WSR_HPSTATE_PRIV-1:`WSR_HPSTATE_TLZ+1] = 1'b0;
|
4711 |
|
|
|
4712 |
|
|
//=========================================================================================
|
4713 |
|
|
// RDPR - This section has been recoded due to timing
|
4714 |
|
|
//=========================================================================================
|
4715 |
|
|
|
4716 |
|
|
// mux data width - 2b
|
4717 |
|
|
`ifdef FPGA_SYN_1THREAD
|
4718 |
|
|
assign global_rdata[`TSA_GLOBAL_WIDTH-1:0] = tlu_gl_lvl0[`TSA_GLOBAL_WIDTH-1:0];
|
4719 |
|
|
assign hintp_rdata = tlu_hintp[0];
|
4720 |
|
|
`else
|
4721 |
|
|
|
4722 |
|
|
|
4723 |
|
|
mux4ds #(`TSA_GLOBAL_WIDTH) mux_global_rdata (
|
4724 |
|
|
.in0 (tlu_gl_lvl0[`TSA_GLOBAL_WIDTH-1:0]),
|
4725 |
|
|
.in1 (tlu_gl_lvl1[`TSA_GLOBAL_WIDTH-1:0]),
|
4726 |
|
|
.in2 (tlu_gl_lvl2[`TSA_GLOBAL_WIDTH-1:0]),
|
4727 |
|
|
.in3 (tlu_gl_lvl3[`TSA_GLOBAL_WIDTH-1:0]),
|
4728 |
|
|
.sel0 (tlu_thrd_rsel_e[0]),
|
4729 |
|
|
.sel1 (tlu_thrd_rsel_e[1]),
|
4730 |
|
|
.sel2 (tlu_thrd_rsel_e[2]),
|
4731 |
|
|
.sel3 (tlu_thrd_rsel_e[3]),
|
4732 |
|
|
.dout (global_rdata[`TSA_GLOBAL_WIDTH-1:0])
|
4733 |
|
|
);
|
4734 |
|
|
//
|
4735 |
|
|
// htickcmp interrupt enable
|
4736 |
|
|
//
|
4737 |
|
|
mux4ds #(1) mux_hintp_rdata (
|
4738 |
|
|
.in0 (tlu_hintp[0]),
|
4739 |
|
|
.in1 (tlu_hintp[1]),
|
4740 |
|
|
.in2 (tlu_hintp[2]),
|
4741 |
|
|
.in3 (tlu_hintp[3]),
|
4742 |
|
|
.sel0 (tlu_thrd_rsel_e[0]),
|
4743 |
|
|
.sel1 (tlu_thrd_rsel_e[1]),
|
4744 |
|
|
.sel2 (tlu_thrd_rsel_e[2]),
|
4745 |
|
|
.sel3 (tlu_thrd_rsel_e[3]),
|
4746 |
|
|
.dout (hintp_rdata)
|
4747 |
|
|
);
|
4748 |
|
|
`endif // !`ifdef FPGA_SYN_1THREAD
|
4749 |
|
|
|
4750 |
|
|
//
|
4751 |
|
|
// tstate.gl - 2b
|
4752 |
|
|
assign tstate_rdata[`WSR_TSTATE_GL_HI:`WSR_TSTATE_GL_LO] =
|
4753 |
|
|
tsa_rdata[`TLU_GL_HI:`TLU_GL_LO];
|
4754 |
|
|
//
|
4755 |
|
|
// tstate.ccr - 8b
|
4756 |
|
|
assign tstate_rdata[`WSR_TSTATE_CCR_HI:`WSR_TSTATE_CCR_LO] =
|
4757 |
|
|
tsa_rdata[`TLU_CCR_HI:`TLU_CCR_LO];
|
4758 |
|
|
//
|
4759 |
|
|
// tstate.asi - 8b
|
4760 |
|
|
assign tstate_rdata[`WSR_TSTATE_ASI_HI:`WSR_TSTATE_ASI_LO] =
|
4761 |
|
|
tsa_rdata[`TLU_ASI_HI:`TLU_ASI_LO];
|
4762 |
|
|
//
|
4763 |
|
|
// tstate.pstate(valid range 2) - 2b
|
4764 |
|
|
assign tstate_rdata[`WSR_TSTATE_PS2_HI:`WSR_TSTATE_PS2_LO] =
|
4765 |
|
|
tsa_rdata[`TSA_PSTATE_VRANGE2_HI:`TSA_PSTATE_VRANGE2_LO];
|
4766 |
|
|
//
|
4767 |
|
|
// added for to please lint
|
4768 |
|
|
assign tstate_dummy_zero[1:0] =
|
4769 |
|
|
tsa_rdata[`TSA_PSTATE_VRANGE2_LO-1:`TSA_PSTATE_VRANGE1_HI+1] & 2'b0;
|
4770 |
|
|
//
|
4771 |
|
|
// tstate.pstate(valid range 1) - 4b
|
4772 |
|
|
assign tstate_rdata[`WSR_TSTATE_PS1_HI:`WSR_TSTATE_PS1_LO] =
|
4773 |
|
|
tsa_rdata[`TSA_PSTATE_VRANGE1_HI:`TSA_PSTATE_VRANGE1_LO];
|
4774 |
|
|
//
|
4775 |
|
|
// tstate.cwp - 3b
|
4776 |
|
|
assign tstate_rdata[`WSR_TSTATE_CWP_HI:`WSR_TSTATE_CWP_LO] =
|
4777 |
|
|
tsa_rdata[`TLU_CWP_HI:`TLU_CWP_LO];
|
4778 |
|
|
//
|
4779 |
|
|
// reserved bits with ASR - assign to 1'b0
|
4780 |
|
|
assign tstate_rdata[`RDSR_TSTATE_WIDTH-1:`WSR_TSTATE_GL_HI+1] =
|
4781 |
|
|
6'h00;
|
4782 |
|
|
assign tstate_rdata[`WSR_TSTATE_ASI_LO-1:`WSR_TSTATE_PS2_HI+1] =
|
4783 |
|
|
6'h00;
|
4784 |
|
|
assign tstate_rdata[`WSR_TSTATE_PS2_LO-1:`WSR_TSTATE_PS1_HI+1] =
|
4785 |
|
|
{1'b0, tstate_dummy_zero[1:0]};
|
4786 |
|
|
assign tstate_rdata[`WSR_TSTATE_PS1_LO-1:`WSR_TSTATE_CWP_HI+1] =
|
4787 |
|
|
6'h00;
|
4788 |
|
|
//
|
4789 |
|
|
//============================================================================
|
4790 |
|
|
// new rdpr mux coding due to timing changes
|
4791 |
|
|
//============================================================================
|
4792 |
|
|
//
|
4793 |
|
|
// added for bug 2332
|
4794 |
|
|
assign rdpr_mx1_onehot_sel =
|
4795 |
|
|
~(|tlu_rdpr_mx1_sel[3:1]);
|
4796 |
|
|
// mux1- 64b
|
4797 |
|
|
mux4ds #(`TLU_ASR_DATA_WIDTH) rdpr_mx1(
|
4798 |
|
|
.in0({tlu_tick_npt,true_tick[60:0], 2'b0}),
|
4799 |
|
|
.in1(tickcmp_rdata[`TLU_ASR_DATA_WIDTH-1:0]),
|
4800 |
|
|
.in2(stickcmp_rdata[`TLU_ASR_DATA_WIDTH-1:0]),
|
4801 |
|
|
.in3({tlu_htickcmp_intdis,htickcmp_rdata[`TLU_ASR_DATA_WIDTH-2:0]}),
|
4802 |
|
|
.sel0(rdpr_mx1_onehot_sel),
|
4803 |
|
|
.sel1(tlu_rdpr_mx1_sel[1]),
|
4804 |
|
|
.sel2(tlu_rdpr_mx1_sel[2]),
|
4805 |
|
|
.sel3(tlu_rdpr_mx1_sel[3]),
|
4806 |
|
|
.dout(tlu_rdpr_mx1_out[`TLU_ASR_DATA_WIDTH-1:0])
|
4807 |
|
|
);
|
4808 |
|
|
//
|
4809 |
|
|
//
|
4810 |
|
|
// added for bug 2332
|
4811 |
|
|
assign rdpr_mx2_onehot_sel =
|
4812 |
|
|
~(|tlu_rdpr_mx2_sel[3:1]);
|
4813 |
|
|
//
|
4814 |
|
|
// mux2 - 4b
|
4815 |
|
|
mux4ds #(4) rdpr_mx2(
|
4816 |
|
|
.in0({2'b0,global_rdata[`TSA_GLOBAL_WIDTH-1:0]}),
|
4817 |
|
|
.in1({3'b0,hintp_rdata}),
|
4818 |
|
|
.in2({1'b0,tlu_trp_lvl[2:0]}),
|
4819 |
|
|
.in3(tlu_pil[3:0]),
|
4820 |
|
|
.sel0(rdpr_mx2_onehot_sel),
|
4821 |
|
|
.sel1(tlu_rdpr_mx2_sel[1]),
|
4822 |
|
|
.sel2(tlu_rdpr_mx2_sel[2]),
|
4823 |
|
|
.sel3(tlu_rdpr_mx2_sel[3]),
|
4824 |
|
|
.dout(tlu_rdpr_mx2_out[3:0])
|
4825 |
|
|
);
|
4826 |
|
|
//
|
4827 |
|
|
// added for bug 2332
|
4828 |
|
|
assign rdpr_mx3_onehot_sel =
|
4829 |
|
|
~(|tlu_rdpr_mx3_sel[2:1]);
|
4830 |
|
|
//
|
4831 |
|
|
// mux3 - 17b
|
4832 |
|
|
mux3ds #(`SFTINT_WIDTH) rdpr_mx3(
|
4833 |
|
|
.in0(sftint_rdata[`SFTINT_WIDTH-1:0]),
|
4834 |
|
|
.in1({5'b0,pstate_rdata[`PSTATE_TRUE_WIDTH-1:0]}),
|
4835 |
|
|
.in2({5'b0,hpstate_rdata[`RDSR_HPSTATE_WIDTH-1:0]}),
|
4836 |
|
|
.sel0(rdpr_mx3_onehot_sel),
|
4837 |
|
|
.sel1(tlu_rdpr_mx3_sel[1]),
|
4838 |
|
|
.sel2(tlu_rdpr_mx3_sel[2]),
|
4839 |
|
|
.dout(tlu_rdpr_mx3_out[`SFTINT_WIDTH-1:0])
|
4840 |
|
|
);
|
4841 |
|
|
//
|
4842 |
|
|
// added for bug 2332
|
4843 |
|
|
assign rdpr_mx4_onehot_sel =
|
4844 |
|
|
~(|tlu_rdpr_mx4_sel[2:1]);
|
4845 |
|
|
//
|
4846 |
|
|
// mux4 - 48b
|
4847 |
|
|
mux3ds #(`RDSR_TSTATE_WIDTH) rdpr_mx4(
|
4848 |
|
|
.in0({tsa_rdata[`TLU_RD_PC_HI:`TLU_RD_PC_LO],2'b00}),
|
4849 |
|
|
.in1({tsa_rdata[`TLU_RD_NPC_HI:`TLU_NPC_LO],2'b00}),
|
4850 |
|
|
// .in0({tsa_rdata[`TLU_PC_HI-1:`TLU_PC_LO],2'b00}),
|
4851 |
|
|
// .in1({tsa_rdata[`TLU_NPC_HI-1:`TLU_NPC_LO],2'b00}),
|
4852 |
|
|
.in2(tstate_rdata[`RDSR_TSTATE_WIDTH-1:0]),
|
4853 |
|
|
.sel0(rdpr_mx4_onehot_sel),
|
4854 |
|
|
.sel1(tlu_rdpr_mx4_sel[1]),
|
4855 |
|
|
.sel2(tlu_rdpr_mx4_sel[2]),
|
4856 |
|
|
.dout(tlu_rdpr_mx4_out[`RDSR_TSTATE_WIDTH-1:0])
|
4857 |
|
|
);
|
4858 |
|
|
//
|
4859 |
|
|
// added for bug 2332
|
4860 |
|
|
assign rdpr_mx5_onehot_sel =
|
4861 |
|
|
~(|tlu_rdpr_mx5_sel[3:1]);
|
4862 |
|
|
//
|
4863 |
|
|
// mux5 - 64b
|
4864 |
|
|
mux4ds #(`TLU_ASR_DATA_WIDTH) rdpr_mx5(
|
4865 |
|
|
.in0({{16{tba_rdata[`TLU_TBA_WIDTH-1]}},
|
4866 |
|
|
tba_rdata[`TLU_TBA_WIDTH-1:0],15'h0000}),
|
4867 |
|
|
.in1({{16{htba_rdata[`TLU_HTBA_WIDTH-1]}},
|
4868 |
|
|
htba_rdata[`TLU_HTBA_WIDTH-1:0],14'h0000}),
|
4869 |
|
|
.in2(tlu_rdpr_mx1_out[`TLU_ASR_DATA_WIDTH-1:0]),
|
4870 |
|
|
.in3(tlu_pib_rsr_data_e[`TLU_ASR_DATA_WIDTH-1:0]),
|
4871 |
|
|
.sel0(rdpr_mx5_onehot_sel),
|
4872 |
|
|
.sel1(tlu_rdpr_mx5_sel[1]),
|
4873 |
|
|
.sel2(tlu_rdpr_mx5_sel[2]),
|
4874 |
|
|
.sel3(tlu_rdpr_mx5_sel[3]),
|
4875 |
|
|
.dout(tlu_rdpr_mx5_out[`TLU_ASR_DATA_WIDTH-1:0])
|
4876 |
|
|
);
|
4877 |
|
|
//
|
4878 |
|
|
// added for bug 2332
|
4879 |
|
|
assign rdpr_mx6_onehot_sel =
|
4880 |
|
|
~(|tlu_rdpr_mx6_sel[2:0]);
|
4881 |
|
|
//
|
4882 |
|
|
// mux6 - 12b
|
4883 |
|
|
mux4ds #(`SFTINT_WIDTH) rdpr_mx6(
|
4884 |
|
|
.in0({8'b0,tsa_rdata[8:0]}), // ttype
|
4885 |
|
|
.in1({5'b0,htstate_rdata[`RDSR_HPSTATE_WIDTH-1:0]}),
|
4886 |
|
|
.in2({13'b0,tlu_rdpr_mx2_out[3:0]}),
|
4887 |
|
|
.in3({tlu_rdpr_mx3_out[`SFTINT_WIDTH-1:0]}),
|
4888 |
|
|
.sel0(rdpr_mx6_onehot_sel),
|
4889 |
|
|
.sel1(tlu_rdpr_mx6_sel[0]),
|
4890 |
|
|
.sel2(tlu_rdpr_mx6_sel[1]),
|
4891 |
|
|
.sel3(tlu_rdpr_mx6_sel[2]),
|
4892 |
|
|
.dout(tlu_rdpr_mx6_out[`SFTINT_WIDTH-1:0])
|
4893 |
|
|
);
|
4894 |
|
|
//
|
4895 |
|
|
// mux7- 64b
|
4896 |
|
|
mux4ds #(`TLU_ASR_DATA_WIDTH) rdpr_mx7(
|
4897 |
|
|
.in0({{16{tlu_rdpr_mx4_out[`RDSR_TSTATE_WIDTH-1]}},
|
4898 |
|
|
tlu_rdpr_mx4_out[`RDSR_TSTATE_WIDTH-1:0]}),
|
4899 |
|
|
.in1(tlu_rdpr_mx5_out[`TLU_ASR_DATA_WIDTH-1:0]),
|
4900 |
|
|
.in2({47'b0,tlu_rdpr_mx6_out[`SFTINT_WIDTH-1:0]}),
|
4901 |
|
|
.in3({56'b0,lsu_tlu_rsr_data_e[7:0]}),
|
4902 |
|
|
.sel0(tlu_rdpr_mx7_sel[0]),
|
4903 |
|
|
.sel1(tlu_rdpr_mx7_sel[1]),
|
4904 |
|
|
.sel2(tlu_rdpr_mx7_sel[2]),
|
4905 |
|
|
.sel3(tlu_rdpr_mx7_sel[3]),
|
4906 |
|
|
.dout(tlu_rdpr_mx7_out[`TLU_ASR_DATA_WIDTH-1:0])
|
4907 |
|
|
);
|
4908 |
|
|
/*
|
4909 |
|
|
mux4ds #(`TLU_ASR_DATA_WIDTH) rdpr_mx7(
|
4910 |
|
|
.in0({{16{tlu_rdpr_mx4_out[`RDSR_TSTATE_WIDTH-1]}},
|
4911 |
|
|
tlu_rdpr_mx4_out[`RDSR_TSTATE_WIDTH-1:0]}),
|
4912 |
|
|
.in1(tlu_rdpr_mx5_out[`TLU_ASR_DATA_WIDTH-1:0]),
|
4913 |
|
|
.in2({47'b0,tlu_rdpr_mx6_out[`SFTINT_WIDTH-1:0]}),
|
4914 |
|
|
.in3({56'b0,lsu_tlu_rsr_data_e[7:0]}),
|
4915 |
|
|
.sel0(tlu_rdpr_mx7_sel[0]),
|
4916 |
|
|
.sel1(tlu_rdpr_mx7_sel[1]),
|
4917 |
|
|
.sel2(tlu_rdpr_mx7_sel[2]),
|
4918 |
|
|
.sel3(tlu_rdpr_mx7_sel[3]),
|
4919 |
|
|
.dout(tlu_rdpr_mx7_out[`TLU_ASR_DATA_WIDTH-1:0])
|
4920 |
|
|
);
|
4921 |
|
|
*/
|
4922 |
|
|
//
|
4923 |
|
|
// drive rsr data to exu
|
4924 |
|
|
assign tlu_exu_rsr_data_e[`TLU_ASR_DATA_WIDTH-1:0] =
|
4925 |
|
|
tlu_rdpr_mx7_out[`TLU_ASR_DATA_WIDTH-1:0];
|
4926 |
|
|
//
|
4927 |
|
|
// added for timing
|
4928 |
|
|
dff_s #(`TLU_ASR_DATA_WIDTH) dff_tlu_exu_rsr_data_m (
|
4929 |
|
|
.din (tlu_exu_rsr_data_e[`TLU_ASR_DATA_WIDTH-1:0]),
|
4930 |
|
|
.q (tlu_exu_rsr_data_m[`TLU_ASR_DATA_WIDTH-1:0]),
|
4931 |
|
|
.clk (clk),
|
4932 |
|
|
.se (se),
|
4933 |
|
|
.si (),
|
4934 |
|
|
.so ()
|
4935 |
|
|
);
|
4936 |
|
|
|
4937 |
|
|
endmodule
|