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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: fpu.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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///////////////////////////////////////////////////////////////////////////////
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//
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// Floating Point Unit.
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//
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///////////////////////////////////////////////////////////////////////////////
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module fpu (
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pcx_fpio_data_rdy_px2,
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pcx_fpio_data_px2,
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arst_l,
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grst_l,
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gclk,
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cluster_cken,
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fp_cpx_req_cq,
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fp_cpx_data_ca,
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ctu_tst_pre_grst_l,
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global_shift_enable,
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ctu_tst_scan_disable,
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ctu_tst_scanmode,
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ctu_tst_macrotest,
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ctu_tst_short_chain,
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si,
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so
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);
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input pcx_fpio_data_rdy_px2; // FPU request ready from PCX
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input [123:0] pcx_fpio_data_px2; // FPU request data from PCX
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input arst_l; // chip async. reset- asserted low
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input grst_l; // chip sync. reset- asserted low
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input gclk; // chip clock
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input cluster_cken; // cluster clock enable
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output [7:0] fp_cpx_req_cq; // FPU result request to CPX
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output [144:0] fp_cpx_data_ca; // FPU result to CPX
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input ctu_tst_pre_grst_l;
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input global_shift_enable;
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input ctu_tst_scan_disable;
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input ctu_tst_scanmode;
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input ctu_tst_macrotest;
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input ctu_tst_short_chain;
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input si; // scan in
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output so; // scan out
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///////////////////////////////////////////////////////////////////////////////
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//
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// Outputs of fpu_in.
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//
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///////////////////////////////////////////////////////////////////////////////
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wire inq_add; // add pipe request
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wire inq_mul; // multiply pipe request
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wire inq_div; // divide pipe request
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wire [4:0] inq_id; // request ID to the operation pipes
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wire [1:0] inq_rnd_mode; // request rounding mode to op pipes
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wire [1:0] inq_fcc; // request cc ID to op pipes
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wire [7:0] inq_op; // request opcode to op pipes
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wire inq_in1_exp_neq_ffs; // request operand 1 exp!=ff's
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wire inq_in1_exp_eq_0; // request operand 1 exp==0
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wire inq_in1_53_0_neq_0; // request operand 1[53:0]!=0
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wire inq_in1_50_0_neq_0; // request operand 1[50:0]!=0
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wire inq_in1_53_32_neq_0; // request operand 1[53:32]!=0
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wire [63:0] inq_in1; // request operand 1 to op pipes
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wire inq_in2_exp_neq_ffs; // request operand 2 exp!=ff's
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wire inq_in2_exp_eq_0; // request operand 2 exp==0
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wire inq_in2_53_0_neq_0; // request operand 2[53:0]!=0
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wire inq_in2_50_0_neq_0; // request operand 2[50:0]!=0
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wire inq_in2_53_32_neq_0; // request operand 2[53:32]!=0
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wire [63:0] inq_in2; // request operand 2 to op pipes
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wire fadd_clken_l; // add pipe clk enable - asserted low
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wire fmul_clken_l; // multiply pipe clk enable - asserted low
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wire fdiv_clken_l; // divide pipe clk enable - asserted low
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// 6/20/03: New outputs of fpu_in for fpu-level i_fpu_inq_sram
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wire [4:0] fp_id_in; // id to be written into inq_sram
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wire [1:0] fp_rnd_mode_in; // rnd_mode to be written into inq_sram
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wire [1:0] fp_fcc_in; // fcc to be written into inq_sram
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wire [7:0] fp_op_in; // op field to be written into inq_sram
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wire [68:0] fp_src1_in; // operand1, includes pre-computed bits matching special values, such as exp all ffs
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wire [68:0] fp_src2_in; // operand2, includes pre-computed bits matching special values, such as exp all ffs
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wire [3:0] inq_rdaddr; // read address for inq_sram
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wire [3:0] inq_wraddr; // write address for inq_sram
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wire inq_read_en; // read enable for inq_sram
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wire inq_we; // write enable for inq_sram
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///////////////////////////////////////////////////////////////////////////////
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//
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// Outputs of i_fpu_inq_sram
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//
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///////////////////////////////////////////////////////////////////////////////
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wire [154:0] inq_dout; // fpu op packet read out from inq_sram
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wire [4:0] inq_dout_unused; // unused bits from sram
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///////////////////////////////////////////////////////////////////////////////
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//
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// Outputs of fpu_add.
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//
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///////////////////////////////////////////////////////////////////////////////
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wire a1stg_step; // add pipe load
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wire a6stg_fadd_in; // add pipe output request next cycle
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wire [9:0] add_id_out_in; // add pipe output ID next cycle
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wire a6stg_fcmpop; // compare- add 6 stage
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wire [4:0] add_exc_out; // add pipe result- exception flags
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wire a6stg_dbl_dst; // float double result- add 6 stage
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wire a6stg_sng_dst; // float single result- add 6 stage
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wire a6stg_long_dst; // 64bit integer result- add 6 stage
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wire a6stg_int_dst; // 32bit integer result- add 6 stage
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wire add_sign_out; // add sign output
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wire [10:0] add_exp_out; // add exponent output
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wire [63:0] add_frac_out; // add fraction output
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wire [1:0] add_cc_out; // add pipe result- condition
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wire [1:0] add_fcc_out; // add pipe input fcc passed through
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wire add_pipe_active; // add pipe is executing a valid instr
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///////////////////////////////////////////////////////////////////////////////
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//
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// Outputs of fpu_mul.
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//
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///////////////////////////////////////////////////////////////////////////////
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wire m1stg_step; // multiply pipe load
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wire m6stg_fmul_in; // mul pipe output request next cycle
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wire [9:0] m6stg_id_in; // mul pipe output ID next cycle
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wire [4:0] mul_exc_out; // multiply pipe result- exception flags
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wire m6stg_fmul_dbl_dst; // double precision multiply result
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wire m6stg_fmuls; // fmuls- multiply 6 stage
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wire mul_sign_out; // multiply sign output
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wire [10:0] mul_exp_out; // multiply exponent output
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wire [51:0] mul_frac_out; // multiply fraction output
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wire mul_pipe_active; // mul pipe is executing a valid instr
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///////////////////////////////////////////////////////////////////////////////
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//
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// Outputs of fpu_div.
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//
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///////////////////////////////////////////////////////////////////////////////
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wire d1stg_step; // divide pipe load
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wire d8stg_fdiv_in; // div pipe output request next cycle
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wire [9:0] div_id_out_in; // div pipe output ID next cycle
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wire [4:0] div_exc_out; // divide pipe result- exception flags
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wire d8stg_fdivd; // divide double- divide stage 8
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wire d8stg_fdivs; // divide single- divide stage 8
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wire div_sign_out; // divide sign output
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wire [10:0] div_exp_out; // divide exponent output
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wire [51:0] div_frac_out; // divide fraction output
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wire div_pipe_active; // div pipe is executing a valid instr
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///////////////////////////////////////////////////////////////////////////////
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//
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// Outputs of fpu_out.
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//
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///////////////////////////////////////////////////////////////////////////////
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wire [7:0] fp_cpx_req_cq_unbuf; // FPU result request to CPX
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wire add_dest_rdy; // add pipe result request this cycle
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wire mul_dest_rdy; // mul pipe result request this cycle
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wire div_dest_rdy; // div pipe result request this cycle
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wire [144:0] fp_cpx_data_ca_unbuf; // FPU result to CPX
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///////////////////////////////////////////////////////////////////////////////
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//
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// Outputs of cluster_header, test_stub.
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//
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///////////////////////////////////////////////////////////////////////////////
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wire rclk; // ref. clock
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wire sehold; // scan in data hold
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wire fpu_grst_l;
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///////////////////////////////////////////////////////////////////////////////
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//
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// Outputs of fpu_rptr_groups.
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//
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///////////////////////////////////////////////////////////////////////////////
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wire [63:0] inq_in1_add_buf1;
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wire [63:0] inq_in1_mul_buf1;
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wire [63:0] inq_in1_div_buf1;
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wire [63:0] inq_in2_add_buf1;
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wire [63:0] inq_in2_mul_buf1;
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wire [63:0] inq_in2_div_buf1;
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wire [4:0] inq_id_add_buf1;
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wire [4:0] inq_id_mul_buf1;
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wire [4:0] inq_id_div_buf1;
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wire [7:0] inq_op_add_buf1;
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wire [7:0] inq_op_mul_buf1;
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wire [7:0] inq_op_div_buf1;
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wire [1:0] inq_rnd_mode_add_buf1;
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wire [1:0] inq_rnd_mode_mul_buf1;
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wire [1:0] inq_rnd_mode_div_buf1;
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wire inq_in1_50_0_neq_0_add_buf1;
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wire inq_in1_50_0_neq_0_mul_buf1;
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wire inq_in1_50_0_neq_0_div_buf1;
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wire inq_in1_53_0_neq_0_add_buf1;
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wire inq_in1_53_0_neq_0_mul_buf1;
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wire inq_in1_53_0_neq_0_div_buf1;
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wire inq_in1_53_32_neq_0_add_buf1;
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wire inq_in1_53_32_neq_0_mul_buf1;
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wire inq_in1_53_32_neq_0_div_buf1;
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wire inq_in1_exp_eq_0_add_buf1;
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wire inq_in1_exp_eq_0_mul_buf1;
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wire inq_in1_exp_eq_0_div_buf1;
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wire inq_in1_exp_neq_ffs_add_buf1;
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wire inq_in1_exp_neq_ffs_mul_buf1;
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wire inq_in1_exp_neq_ffs_div_buf1;
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wire inq_in2_50_0_neq_0_add_buf1;
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wire inq_in2_50_0_neq_0_mul_buf1;
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wire inq_in2_50_0_neq_0_div_buf1;
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wire inq_in2_53_0_neq_0_add_buf1;
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wire inq_in2_53_0_neq_0_mul_buf1;
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wire inq_in2_53_0_neq_0_div_buf1;
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wire inq_in2_53_32_neq_0_add_buf1;
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wire inq_in2_53_32_neq_0_mul_buf1;
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wire inq_in2_53_32_neq_0_div_buf1;
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wire inq_in2_exp_eq_0_add_buf1;
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wire inq_in2_exp_eq_0_mul_buf1;
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wire inq_in2_exp_eq_0_div_buf1;
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wire inq_in2_exp_neq_ffs_add_buf1;
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wire inq_in2_exp_neq_ffs_mul_buf1;
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wire inq_in2_exp_neq_ffs_div_buf1;
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wire [123:0] pcx_fpio_data_px2_buf1;
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wire [155:0] inq_sram_din_buf1;
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///////////////////////////////////////////////////////////////////////////////
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//
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// Instantiations.
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//
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///////////////////////////////////////////////////////////////////////////////
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fpu_in fpu_in (
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| 269 |
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.pcx_fpio_data_rdy_px2 (pcx_fpio_data_rdy_px2_buf1),
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| 270 |
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.pcx_fpio_data_px2 (pcx_fpio_data_px2_buf1[123:0]),
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| 271 |
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.a1stg_step (a1stg_step),
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| 272 |
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.m1stg_step (m1stg_step),
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| 273 |
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.d1stg_step (d1stg_step),
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| 274 |
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.add_pipe_active (add_pipe_active),
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| 275 |
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.mul_pipe_active (mul_pipe_active),
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| 276 |
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.div_pipe_active (div_pipe_active),
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| 277 |
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.inq_dout (inq_dout[154:0]),
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.sehold (sehold),
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| 279 |
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.arst_l (arst_l_in_buf3),
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.grst_l (fpu_grst_l_in_buf2),
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| 281 |
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.rclk (rclk),
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| 282 |
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| 283 |
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.fadd_clken_l (fadd_clken_l),
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| 284 |
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.fmul_clken_l (fmul_clken_l),
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.fdiv_clken_l (fdiv_clken_l),
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| 286 |
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| 287 |
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.inq_add (inq_add),
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.inq_mul (inq_mul),
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.inq_div (inq_div),
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.inq_id (inq_id[4:0]),
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.inq_rnd_mode (inq_rnd_mode[1:0]),
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.inq_fcc (inq_fcc[1:0]),
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| 293 |
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.inq_op (inq_op[7:0]),
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| 294 |
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.inq_in1_exp_neq_ffs (inq_in1_exp_neq_ffs),
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| 295 |
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.inq_in1_exp_eq_0 (inq_in1_exp_eq_0),
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| 296 |
|
|
.inq_in1_53_0_neq_0 (inq_in1_53_0_neq_0),
|
| 297 |
|
|
.inq_in1_50_0_neq_0 (inq_in1_50_0_neq_0),
|
| 298 |
|
|
.inq_in1_53_32_neq_0 (inq_in1_53_32_neq_0),
|
| 299 |
|
|
.inq_in1 (inq_in1[63:0]),
|
| 300 |
|
|
.inq_in2_exp_neq_ffs (inq_in2_exp_neq_ffs),
|
| 301 |
|
|
.inq_in2_exp_eq_0 (inq_in2_exp_eq_0),
|
| 302 |
|
|
.inq_in2_53_0_neq_0 (inq_in2_53_0_neq_0),
|
| 303 |
|
|
.inq_in2_50_0_neq_0 (inq_in2_50_0_neq_0),
|
| 304 |
|
|
.inq_in2_53_32_neq_0 (inq_in2_53_32_neq_0),
|
| 305 |
|
|
.inq_in2 (inq_in2[63:0]),
|
| 306 |
|
|
|
| 307 |
|
|
// new outputs of fpu_in to drive i_fpu_inq_sram
|
| 308 |
|
|
.fp_id_in (fp_id_in[4:0]),
|
| 309 |
|
|
.fp_rnd_mode_in (fp_rnd_mode_in[1:0]),
|
| 310 |
|
|
.fp_fcc_in (fp_fcc_in[1:0]),
|
| 311 |
|
|
.fp_op_in (fp_op_in[7:0]),
|
| 312 |
|
|
.fp_src1_in (fp_src1_in[68:0]),
|
| 313 |
|
|
.fp_src2_in (fp_src2_in[68:0]),
|
| 314 |
|
|
.inq_rdaddr (inq_rdaddr[3:0]),
|
| 315 |
|
|
.inq_wraddr (inq_wraddr[3:0]),
|
| 316 |
|
|
.inq_read_en (inq_read_en),
|
| 317 |
|
|
.inq_we (inq_we),
|
| 318 |
|
|
|
| 319 |
|
|
.se (se_in_buf3),
|
| 320 |
|
|
.si (manual_scan_0),
|
| 321 |
|
|
.so (scan_manual_1)
|
| 322 |
|
|
);
|
| 323 |
|
|
|
| 324 |
|
|
|
| 325 |
|
|
// 7/30/03: updated scan ports from si to si_r, si_w and so to so_r, so_w
|
| 326 |
|
|
// 06/20/03: Pulled up i_fpu_inq_sram from fpu_in_dp into fpu
|
| 327 |
|
|
|
| 328 |
|
|
bw_r_rf16x160 i_fpu_inq_sram (
|
| 329 |
|
|
.din ({inq_sram_din_buf1[155:0], 4'b0000}),
|
| 330 |
|
|
.rd_adr (inq_rdaddr[3:0]),
|
| 331 |
|
|
.wr_adr (inq_wraddr[3:0]),
|
| 332 |
|
|
.read_en (inq_read_en),
|
| 333 |
|
|
.wr_en (inq_we),
|
| 334 |
|
|
.word_wen (4'hf),
|
| 335 |
|
|
.byte_wen (20'hfffff),
|
| 336 |
|
|
.rd_clk (rclk),
|
| 337 |
|
|
.wr_clk (rclk),
|
| 338 |
|
|
.se (se),
|
| 339 |
|
|
.si_r (si_buf1),
|
| 340 |
|
|
.si_w (scan_inq_sram_w),
|
| 341 |
|
|
.reset_l (arst_l_in_buf3),
|
| 342 |
|
|
.sehold (sehold),
|
| 343 |
|
|
.rst_tri_en (rst_tri_en),
|
| 344 |
|
|
.dout ({inq_dout[154:0], inq_dout_unused[4:0]}),
|
| 345 |
|
|
.so_r (scan_inq_sram_w),
|
| 346 |
|
|
.so_w (manual_scan_0)
|
| 347 |
|
|
);
|
| 348 |
|
|
|
| 349 |
|
|
|
| 350 |
|
|
fpu_add fpu_add (
|
| 351 |
|
|
.inq_op (inq_op_add_buf1[7:0]),
|
| 352 |
|
|
.inq_rnd_mode (inq_rnd_mode_add_buf1[1:0]),
|
| 353 |
|
|
.inq_id (inq_id_add_buf1[4:0]),
|
| 354 |
|
|
.inq_fcc (inq_fcc[1:0]),
|
| 355 |
|
|
.inq_in1 (inq_in1_add_buf1[63:0]),
|
| 356 |
|
|
.inq_in1_50_0_neq_0 (inq_in1_50_0_neq_0_add_buf1),
|
| 357 |
|
|
.inq_in1_53_32_neq_0 (inq_in1_53_32_neq_0_add_buf1),
|
| 358 |
|
|
.inq_in1_exp_eq_0 (inq_in1_exp_eq_0_add_buf1),
|
| 359 |
|
|
.inq_in1_exp_neq_ffs (inq_in1_exp_neq_ffs_add_buf1),
|
| 360 |
|
|
.inq_in2 (inq_in2_add_buf1[63:0]),
|
| 361 |
|
|
.inq_in2_50_0_neq_0 (inq_in2_50_0_neq_0_add_buf1),
|
| 362 |
|
|
.inq_in2_53_32_neq_0 (inq_in2_53_32_neq_0_add_buf1),
|
| 363 |
|
|
.inq_in2_exp_eq_0 (inq_in2_exp_eq_0_add_buf1),
|
| 364 |
|
|
.inq_in2_exp_neq_ffs (inq_in2_exp_neq_ffs_add_buf1),
|
| 365 |
|
|
.inq_add (inq_add),
|
| 366 |
|
|
.add_dest_rdy (add_dest_rdy),
|
| 367 |
|
|
.fadd_clken_l (fadd_clken_l),
|
| 368 |
|
|
.arst_l (arst_l_add_buf4),
|
| 369 |
|
|
.grst_l (fpu_grst_l_add_buf3),
|
| 370 |
|
|
.rclk (rclk),
|
| 371 |
|
|
|
| 372 |
|
|
.add_pipe_active (add_pipe_active),
|
| 373 |
|
|
.a1stg_step (a1stg_step),
|
| 374 |
|
|
.a6stg_fadd_in (a6stg_fadd_in),
|
| 375 |
|
|
.add_id_out_in (add_id_out_in[9:0]),
|
| 376 |
|
|
.a6stg_fcmpop (a6stg_fcmpop),
|
| 377 |
|
|
.add_exc_out (add_exc_out[4:0]),
|
| 378 |
|
|
.a6stg_dbl_dst (a6stg_dbl_dst),
|
| 379 |
|
|
.a6stg_sng_dst (a6stg_sng_dst),
|
| 380 |
|
|
.a6stg_long_dst (a6stg_long_dst),
|
| 381 |
|
|
.a6stg_int_dst (a6stg_int_dst),
|
| 382 |
|
|
.add_sign_out (add_sign_out),
|
| 383 |
|
|
.add_exp_out (add_exp_out[10:0]),
|
| 384 |
|
|
.add_frac_out (add_frac_out[63:0]),
|
| 385 |
|
|
.add_cc_out (add_cc_out[1:0]),
|
| 386 |
|
|
.add_fcc_out (add_fcc_out[1:0]),
|
| 387 |
|
|
|
| 388 |
|
|
.se_add_exp (se_add_exp_buf2),
|
| 389 |
|
|
.se_add_frac (se_add_frac_buf2),
|
| 390 |
|
|
.si (scan_manual_1),
|
| 391 |
|
|
.so (scan_manual_2)
|
| 392 |
|
|
);
|
| 393 |
|
|
|
| 394 |
|
|
|
| 395 |
|
|
fpu_mul fpu_mul (
|
| 396 |
|
|
.inq_op (inq_op_mul_buf1[7:0]),
|
| 397 |
|
|
.inq_rnd_mode (inq_rnd_mode_mul_buf1[1:0]),
|
| 398 |
|
|
.inq_id (inq_id_mul_buf1[4:0]),
|
| 399 |
|
|
.inq_in1 (inq_in1_mul_buf1[63:0]),
|
| 400 |
|
|
.inq_in1_53_0_neq_0 (inq_in1_53_0_neq_0),
|
| 401 |
|
|
.inq_in1_50_0_neq_0 (inq_in1_50_0_neq_0_mul_buf1),
|
| 402 |
|
|
.inq_in1_53_32_neq_0 (inq_in1_53_32_neq_0_mul_buf1),
|
| 403 |
|
|
.inq_in1_exp_eq_0 (inq_in1_exp_eq_0_mul_buf1),
|
| 404 |
|
|
.inq_in1_exp_neq_ffs (inq_in1_exp_neq_ffs_mul_buf1),
|
| 405 |
|
|
.inq_in2 (inq_in2_mul_buf1[63:0]),
|
| 406 |
|
|
.inq_in2_53_0_neq_0 (inq_in2_53_0_neq_0),
|
| 407 |
|
|
.inq_in2_50_0_neq_0 (inq_in2_50_0_neq_0_mul_buf1),
|
| 408 |
|
|
.inq_in2_53_32_neq_0 (inq_in2_53_32_neq_0_mul_buf1),
|
| 409 |
|
|
.inq_in2_exp_eq_0 (inq_in2_exp_eq_0_mul_buf1),
|
| 410 |
|
|
.inq_in2_exp_neq_ffs (inq_in2_exp_neq_ffs_mul_buf1),
|
| 411 |
|
|
.inq_mul (inq_mul),
|
| 412 |
|
|
.mul_dest_rdy (mul_dest_rdy),
|
| 413 |
|
|
.mul_dest_rdya (mul_dest_rdy),
|
| 414 |
|
|
.fmul_clken_l (fmul_clken_l),
|
| 415 |
|
|
.fmul_clken_l_buf1 (fmul_clken_l_buf1),
|
| 416 |
|
|
.arst_l (arst_l_mul_buf2),
|
| 417 |
|
|
.grst_l (fpu_grst_l_mul_buf1),
|
| 418 |
|
|
.rclk (rclk),
|
| 419 |
|
|
|
| 420 |
|
|
.mul_pipe_active (mul_pipe_active),
|
| 421 |
|
|
.m1stg_step (m1stg_step),
|
| 422 |
|
|
.m6stg_fmul_in (m6stg_fmul_in),
|
| 423 |
|
|
.m6stg_id_in (m6stg_id_in[9:0]),
|
| 424 |
|
|
.mul_exc_out (mul_exc_out[4:0]),
|
| 425 |
|
|
.m6stg_fmul_dbl_dst (m6stg_fmul_dbl_dst),
|
| 426 |
|
|
.m6stg_fmuls (m6stg_fmuls),
|
| 427 |
|
|
.mul_sign_out (mul_sign_out),
|
| 428 |
|
|
.mul_exp_out (mul_exp_out[10:0]),
|
| 429 |
|
|
.mul_frac_out (mul_frac_out[51:0]),
|
| 430 |
|
|
|
| 431 |
|
|
.se_mul (se_mul_buf4),
|
| 432 |
|
|
.se_mul64 (se_mul64_buf2),
|
| 433 |
|
|
.si (scan_manual_2),
|
| 434 |
|
|
.so (scan_manual_3)
|
| 435 |
|
|
);
|
| 436 |
|
|
|
| 437 |
|
|
|
| 438 |
|
|
fpu_div fpu_div (
|
| 439 |
|
|
.inq_op (inq_op_div_buf1[7:0]),
|
| 440 |
|
|
.inq_rnd_mode (inq_rnd_mode_div_buf1[1:0]),
|
| 441 |
|
|
.inq_id (inq_id_div_buf1[4:0]),
|
| 442 |
|
|
.inq_in1 (inq_in1_div_buf1[63:0]),
|
| 443 |
|
|
.inq_in1_53_0_neq_0 (inq_in1_53_0_neq_0_div_buf1),
|
| 444 |
|
|
.inq_in1_50_0_neq_0 (inq_in1_50_0_neq_0_div_buf1),
|
| 445 |
|
|
.inq_in1_53_32_neq_0 (inq_in1_53_32_neq_0_div_buf1),
|
| 446 |
|
|
.inq_in1_exp_eq_0 (inq_in1_exp_eq_0_div_buf1),
|
| 447 |
|
|
.inq_in1_exp_neq_ffs (inq_in1_exp_neq_ffs_div_buf1),
|
| 448 |
|
|
.inq_in2 (inq_in2_div_buf1[63:0]),
|
| 449 |
|
|
.inq_in2_53_0_neq_0 (inq_in2_53_0_neq_0_div_buf1),
|
| 450 |
|
|
.inq_in2_50_0_neq_0 (inq_in2_50_0_neq_0_div_buf1),
|
| 451 |
|
|
.inq_in2_53_32_neq_0 (inq_in2_53_32_neq_0_div_buf1),
|
| 452 |
|
|
.inq_in2_exp_eq_0 (inq_in2_exp_eq_0_div_buf1),
|
| 453 |
|
|
.inq_in2_exp_neq_ffs (inq_in2_exp_neq_ffs_div_buf1),
|
| 454 |
|
|
.inq_div (inq_div),
|
| 455 |
|
|
.div_dest_rdy (div_dest_rdy),
|
| 456 |
|
|
.fdiv_clken_l (fdiv_clken_l_div_frac_buf1),
|
| 457 |
|
|
.fdiv_clken_l_div_exp_buf1 (fdiv_clken_l_div_exp_buf1),
|
| 458 |
|
|
.arst_l (arst_l_div_buf2),
|
| 459 |
|
|
.grst_l (fpu_grst_l),
|
| 460 |
|
|
.rclk (rclk),
|
| 461 |
|
|
|
| 462 |
|
|
.div_pipe_active (div_pipe_active),
|
| 463 |
|
|
.d1stg_step (d1stg_step),
|
| 464 |
|
|
.d8stg_fdiv_in (d8stg_fdiv_in),
|
| 465 |
|
|
.div_id_out_in (div_id_out_in[9:0]),
|
| 466 |
|
|
.div_exc_out (div_exc_out[4:0]),
|
| 467 |
|
|
.d8stg_fdivd (d8stg_fdivd),
|
| 468 |
|
|
.d8stg_fdivs (d8stg_fdivs),
|
| 469 |
|
|
.div_sign_out (div_sign_out),
|
| 470 |
|
|
.div_exp_outa (div_exp_out[10:0]),
|
| 471 |
|
|
.div_frac_outa (div_frac_out[51:0]),
|
| 472 |
|
|
|
| 473 |
|
|
.se (se_div_buf5),
|
| 474 |
|
|
.si (scan_manual_3),
|
| 475 |
|
|
.so (scan_manual_4)
|
| 476 |
|
|
);
|
| 477 |
|
|
|
| 478 |
|
|
|
| 479 |
|
|
fpu_out fpu_out (
|
| 480 |
|
|
.d8stg_fdiv_in (d8stg_fdiv_in),
|
| 481 |
|
|
.m6stg_fmul_in (m6stg_fmul_in),
|
| 482 |
|
|
.a6stg_fadd_in (a6stg_fadd_in),
|
| 483 |
|
|
.div_id_out_in (div_id_out_in[9:0]),
|
| 484 |
|
|
.m6stg_id_in (m6stg_id_in[9:0]),
|
| 485 |
|
|
.add_id_out_in (add_id_out_in[9:0]),
|
| 486 |
|
|
.div_exc_out (div_exc_out[4:0]),
|
| 487 |
|
|
.d8stg_fdivd (d8stg_fdivd),
|
| 488 |
|
|
.d8stg_fdivs (d8stg_fdivs),
|
| 489 |
|
|
.div_sign_out (div_sign_out),
|
| 490 |
|
|
.div_exp_out (div_exp_out[10:0]),
|
| 491 |
|
|
.div_frac_out (div_frac_out[51:0]),
|
| 492 |
|
|
.mul_exc_out (mul_exc_out[4:0]),
|
| 493 |
|
|
.m6stg_fmul_dbl_dst (m6stg_fmul_dbl_dst),
|
| 494 |
|
|
.m6stg_fmuls (m6stg_fmuls),
|
| 495 |
|
|
.mul_sign_out (mul_sign_out),
|
| 496 |
|
|
.mul_exp_out (mul_exp_out[10:0]),
|
| 497 |
|
|
.mul_frac_out (mul_frac_out[51:0]),
|
| 498 |
|
|
.add_exc_out (add_exc_out[4:0]),
|
| 499 |
|
|
.a6stg_fcmpop (a6stg_fcmpop),
|
| 500 |
|
|
.add_cc_out (add_cc_out[1:0]),
|
| 501 |
|
|
.add_fcc_out (add_fcc_out[1:0]),
|
| 502 |
|
|
.a6stg_dbl_dst (a6stg_dbl_dst),
|
| 503 |
|
|
.a6stg_sng_dst (a6stg_sng_dst),
|
| 504 |
|
|
.a6stg_long_dst (a6stg_long_dst),
|
| 505 |
|
|
.a6stg_int_dst (a6stg_int_dst),
|
| 506 |
|
|
.add_sign_out (add_sign_out),
|
| 507 |
|
|
.add_exp_out (add_exp_out[10:0]),
|
| 508 |
|
|
.add_frac_out (add_frac_out[63:0]),
|
| 509 |
|
|
.arst_l (arst_l_out_buf3),
|
| 510 |
|
|
.grst_l (fpu_grst_l_add_buf3),
|
| 511 |
|
|
.rclk (rclk),
|
| 512 |
|
|
|
| 513 |
|
|
.fp_cpx_req_cq (fp_cpx_req_cq_unbuf[7:0]),
|
| 514 |
|
|
.add_dest_rdy (add_dest_rdy),
|
| 515 |
|
|
.mul_dest_rdy (mul_dest_rdy),
|
| 516 |
|
|
.div_dest_rdy (div_dest_rdy),
|
| 517 |
|
|
.fp_cpx_data_ca (fp_cpx_data_ca_unbuf[144:0]),
|
| 518 |
|
|
|
| 519 |
|
|
.se (se_out_buf2),
|
| 520 |
|
|
.si (scan_manual_4),
|
| 521 |
|
|
.so (scan_manual_5)
|
| 522 |
|
|
);
|
| 523 |
|
|
|
| 524 |
|
|
///////////////////////////////////////////////////////////////////////////////
|
| 525 |
|
|
//
|
| 526 |
|
|
// FPU test_stub.
|
| 527 |
|
|
//
|
| 528 |
|
|
///////////////////////////////////////////////////////////////////////////////
|
| 529 |
|
|
|
| 530 |
|
|
test_stub_scan test_stub (
|
| 531 |
|
|
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l_buf1),
|
| 532 |
|
|
.arst_l (arst_l_add_buf4),
|
| 533 |
|
|
.global_shift_enable (global_shift_enable_buf1),
|
| 534 |
|
|
.ctu_tst_scan_disable (ctu_tst_scan_disable_buf1),
|
| 535 |
|
|
.ctu_tst_scanmode (ctu_tst_scanmode_buf1),
|
| 536 |
|
|
.ctu_tst_macrotest (ctu_tst_macrotest_buf1),
|
| 537 |
|
|
.ctu_tst_short_chain (ctu_tst_short_chain_buf1),
|
| 538 |
|
|
.long_chain_so_0 (scan_manual_6_buf1), // connect to long scan chain
|
| 539 |
|
|
.short_chain_so_0 (manual_scan_0), // connect to short scan chain (from fpu_inq_sram)
|
| 540 |
|
|
.long_chain_so_1 (1'b0),
|
| 541 |
|
|
.short_chain_so_1 (1'b0),
|
| 542 |
|
|
.long_chain_so_2 (1'b0),
|
| 543 |
|
|
.short_chain_so_2 (1'b0),
|
| 544 |
|
|
|
| 545 |
|
|
.mux_drive_disable (),
|
| 546 |
|
|
.mem_write_disable (rst_tri_en),
|
| 547 |
|
|
.sehold (sehold),
|
| 548 |
|
|
.se (se),
|
| 549 |
|
|
.testmode_l (),
|
| 550 |
|
|
.mem_bypass (),
|
| 551 |
|
|
.so_0 (so_unbuf),
|
| 552 |
|
|
.so_1 (),
|
| 553 |
|
|
.so_2 ()
|
| 554 |
|
|
);
|
| 555 |
|
|
|
| 556 |
|
|
///////////////////////////////////////////////////////////////////////////////
|
| 557 |
|
|
//
|
| 558 |
|
|
// FPU cluster_header.
|
| 559 |
|
|
//
|
| 560 |
|
|
///////////////////////////////////////////////////////////////////////////////
|
| 561 |
|
|
|
| 562 |
|
|
bw_clk_cl_fpu_cmp cluster_header (
|
| 563 |
|
|
.gclk (gclk),
|
| 564 |
|
|
.cluster_cken (cluster_cken_buf1),
|
| 565 |
|
|
.arst_l (arst_l_cluster_header_buf2),
|
| 566 |
|
|
.grst_l (grst_l_buf1),
|
| 567 |
|
|
.adbginit_l (1'b1),
|
| 568 |
|
|
.gdbginit_l (1'b1),
|
| 569 |
|
|
.dbginit_l (),
|
| 570 |
|
|
.cluster_grst_l (fpu_grst_l),
|
| 571 |
|
|
.rclk (rclk),
|
| 572 |
|
|
.se (se_cluster_header_buf2),
|
| 573 |
|
|
.si (scan_manual_5),
|
| 574 |
|
|
.so (scan_manual_6)
|
| 575 |
|
|
);
|
| 576 |
|
|
|
| 577 |
|
|
|
| 578 |
|
|
///////////////////////////////////////////////////////////////////////////////
|
| 579 |
|
|
//
|
| 580 |
|
|
// FPU repeater_groups.
|
| 581 |
|
|
//
|
| 582 |
|
|
///////////////////////////////////////////////////////////////////////////////
|
| 583 |
|
|
|
| 584 |
|
|
// 3/14/03: Added repeater groups
|
| 585 |
|
|
fpu_rptr_groups fpu_rptr_groups (
|
| 586 |
|
|
.inq_in1 (inq_in1[63:0]),
|
| 587 |
|
|
.inq_in2 (inq_in2[63:0]),
|
| 588 |
|
|
.inq_id (inq_id[4:0]),
|
| 589 |
|
|
.inq_op (inq_op[7:0]),
|
| 590 |
|
|
.inq_rnd_mode (inq_rnd_mode[1:0]),
|
| 591 |
|
|
.inq_in1_50_0_neq_0 (inq_in1_50_0_neq_0),
|
| 592 |
|
|
.inq_in1_53_0_neq_0 (inq_in1_53_0_neq_0),
|
| 593 |
|
|
.inq_in1_53_32_neq_0 (inq_in1_53_32_neq_0),
|
| 594 |
|
|
.inq_in1_exp_eq_0 (inq_in1_exp_eq_0),
|
| 595 |
|
|
.inq_in1_exp_neq_ffs (inq_in1_exp_neq_ffs),
|
| 596 |
|
|
.inq_in2_50_0_neq_0 (inq_in2_50_0_neq_0),
|
| 597 |
|
|
.inq_in2_53_0_neq_0 (inq_in2_53_0_neq_0),
|
| 598 |
|
|
.inq_in2_53_32_neq_0 (inq_in2_53_32_neq_0),
|
| 599 |
|
|
.inq_in2_exp_eq_0 (inq_in2_exp_eq_0),
|
| 600 |
|
|
.inq_in2_exp_neq_ffs (inq_in2_exp_neq_ffs),
|
| 601 |
|
|
|
| 602 |
|
|
.ctu_tst_macrotest (ctu_tst_macrotest),
|
| 603 |
|
|
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
|
| 604 |
|
|
.ctu_tst_scan_disable (ctu_tst_scan_disable),
|
| 605 |
|
|
.ctu_tst_scanmode (ctu_tst_scanmode),
|
| 606 |
|
|
.ctu_tst_short_chain (ctu_tst_short_chain),
|
| 607 |
|
|
.global_shift_enable (global_shift_enable),
|
| 608 |
|
|
|
| 609 |
|
|
.grst_l (grst_l),
|
| 610 |
|
|
.cluster_cken (cluster_cken),
|
| 611 |
|
|
|
| 612 |
|
|
.se (se),
|
| 613 |
|
|
|
| 614 |
|
|
.arst_l (arst_l),
|
| 615 |
|
|
|
| 616 |
|
|
.fpu_grst_l (fpu_grst_l),
|
| 617 |
|
|
|
| 618 |
|
|
.fmul_clken_l (fmul_clken_l),
|
| 619 |
|
|
.fdiv_clken_l (fdiv_clken_l),
|
| 620 |
|
|
|
| 621 |
|
|
.scan_manual_6 (scan_manual_6),
|
| 622 |
|
|
|
| 623 |
|
|
.si (si),
|
| 624 |
|
|
.so_unbuf (so_unbuf),
|
| 625 |
|
|
|
| 626 |
|
|
.pcx_fpio_data_px2 (pcx_fpio_data_px2[123:0]),
|
| 627 |
|
|
.pcx_fpio_data_rdy_px2 (pcx_fpio_data_rdy_px2),
|
| 628 |
|
|
|
| 629 |
|
|
.fp_cpx_data_ca (fp_cpx_data_ca_unbuf[144:0]),
|
| 630 |
|
|
.fp_cpx_req_cq (fp_cpx_req_cq_unbuf[7:0]),
|
| 631 |
|
|
|
| 632 |
|
|
.inq_sram_din_unbuf ({fp_id_in[4:0],
|
| 633 |
|
|
fp_rnd_mode_in[1:0],
|
| 634 |
|
|
fp_fcc_in[1:0],
|
| 635 |
|
|
fp_op_in[7:0],
|
| 636 |
|
|
fp_src1_in[68:0],
|
| 637 |
|
|
fp_src2_in[68:0], 1'b0}),
|
| 638 |
|
|
|
| 639 |
|
|
.inq_in1_add_buf1 (inq_in1_add_buf1[63:0]),
|
| 640 |
|
|
.inq_in1_mul_buf1 (inq_in1_mul_buf1[63:0]),
|
| 641 |
|
|
.inq_in1_div_buf1 (inq_in1_div_buf1[63:0]),
|
| 642 |
|
|
.inq_in2_add_buf1 (inq_in2_add_buf1[63:0]),
|
| 643 |
|
|
.inq_in2_mul_buf1 (inq_in2_mul_buf1[63:0]),
|
| 644 |
|
|
.inq_in2_div_buf1 (inq_in2_div_buf1[63:0]),
|
| 645 |
|
|
.inq_id_add_buf1 (inq_id_add_buf1[4:0]),
|
| 646 |
|
|
.inq_id_div_buf1 (inq_id_div_buf1[4:0]),
|
| 647 |
|
|
.inq_id_mul_buf1 (inq_id_mul_buf1[4:0]),
|
| 648 |
|
|
.inq_op_add_buf1 (inq_op_add_buf1[7:0]),
|
| 649 |
|
|
.inq_op_mul_buf1 (inq_op_mul_buf1[7:0]),
|
| 650 |
|
|
.inq_op_div_buf1 (inq_op_div_buf1[7:0]),
|
| 651 |
|
|
.inq_rnd_mode_add_buf1 (inq_rnd_mode_add_buf1[1:0]),
|
| 652 |
|
|
.inq_rnd_mode_mul_buf1 (inq_rnd_mode_mul_buf1[1:0]),
|
| 653 |
|
|
.inq_rnd_mode_div_buf1 (inq_rnd_mode_div_buf1[1:0]),
|
| 654 |
|
|
.inq_in1_50_0_neq_0_add_buf1 (inq_in1_50_0_neq_0_add_buf1),
|
| 655 |
|
|
.inq_in1_50_0_neq_0_mul_buf1 (inq_in1_50_0_neq_0_mul_buf1),
|
| 656 |
|
|
.inq_in1_50_0_neq_0_div_buf1 (inq_in1_50_0_neq_0_div_buf1),
|
| 657 |
|
|
.inq_in1_53_0_neq_0_add_buf1 (inq_in1_53_0_neq_0_add_buf1),
|
| 658 |
|
|
.inq_in1_53_0_neq_0_mul_buf1 (inq_in1_53_0_neq_0_mul_buf1),
|
| 659 |
|
|
.inq_in1_53_0_neq_0_div_buf1 (inq_in1_53_0_neq_0_div_buf1),
|
| 660 |
|
|
.inq_in1_53_32_neq_0_add_buf1 (inq_in1_53_32_neq_0_add_buf1),
|
| 661 |
|
|
.inq_in1_53_32_neq_0_mul_buf1 (inq_in1_53_32_neq_0_mul_buf1),
|
| 662 |
|
|
.inq_in1_53_32_neq_0_div_buf1 (inq_in1_53_32_neq_0_div_buf1),
|
| 663 |
|
|
.inq_in1_exp_eq_0_add_buf1 (inq_in1_exp_eq_0_add_buf1),
|
| 664 |
|
|
.inq_in1_exp_eq_0_mul_buf1 (inq_in1_exp_eq_0_mul_buf1),
|
| 665 |
|
|
.inq_in1_exp_eq_0_div_buf1 (inq_in1_exp_eq_0_div_buf1),
|
| 666 |
|
|
.inq_in1_exp_neq_ffs_add_buf1 (inq_in1_exp_neq_ffs_add_buf1),
|
| 667 |
|
|
.inq_in1_exp_neq_ffs_mul_buf1 (inq_in1_exp_neq_ffs_mul_buf1),
|
| 668 |
|
|
.inq_in1_exp_neq_ffs_div_buf1 (inq_in1_exp_neq_ffs_div_buf1),
|
| 669 |
|
|
.inq_in2_50_0_neq_0_add_buf1 (inq_in2_50_0_neq_0_add_buf1),
|
| 670 |
|
|
.inq_in2_50_0_neq_0_mul_buf1 (inq_in2_50_0_neq_0_mul_buf1),
|
| 671 |
|
|
.inq_in2_50_0_neq_0_div_buf1 (inq_in2_50_0_neq_0_div_buf1),
|
| 672 |
|
|
.inq_in2_53_0_neq_0_add_buf1 (inq_in2_53_0_neq_0_add_buf1),
|
| 673 |
|
|
.inq_in2_53_0_neq_0_mul_buf1 (inq_in2_53_0_neq_0_mul_buf1),
|
| 674 |
|
|
.inq_in2_53_0_neq_0_div_buf1 (inq_in2_53_0_neq_0_div_buf1),
|
| 675 |
|
|
.inq_in2_53_32_neq_0_add_buf1 (inq_in2_53_32_neq_0_add_buf1),
|
| 676 |
|
|
.inq_in2_53_32_neq_0_mul_buf1 (inq_in2_53_32_neq_0_mul_buf1),
|
| 677 |
|
|
.inq_in2_53_32_neq_0_div_buf1 (inq_in2_53_32_neq_0_div_buf1),
|
| 678 |
|
|
.inq_in2_exp_eq_0_add_buf1 (inq_in2_exp_eq_0_add_buf1),
|
| 679 |
|
|
.inq_in2_exp_eq_0_mul_buf1 (inq_in2_exp_eq_0_mul_buf1),
|
| 680 |
|
|
.inq_in2_exp_eq_0_div_buf1 (inq_in2_exp_eq_0_div_buf1),
|
| 681 |
|
|
.inq_in2_exp_neq_ffs_add_buf1 (inq_in2_exp_neq_ffs_add_buf1),
|
| 682 |
|
|
.inq_in2_exp_neq_ffs_mul_buf1 (inq_in2_exp_neq_ffs_mul_buf1),
|
| 683 |
|
|
.inq_in2_exp_neq_ffs_div_buf1 (inq_in2_exp_neq_ffs_div_buf1),
|
| 684 |
|
|
|
| 685 |
|
|
.ctu_tst_macrotest_buf1 (ctu_tst_macrotest_buf1),
|
| 686 |
|
|
.ctu_tst_pre_grst_l_buf1 (ctu_tst_pre_grst_l_buf1),
|
| 687 |
|
|
.ctu_tst_scan_disable_buf1 (ctu_tst_scan_disable_buf1),
|
| 688 |
|
|
.ctu_tst_scanmode_buf1 (ctu_tst_scanmode_buf1),
|
| 689 |
|
|
.ctu_tst_short_chain_buf1 (ctu_tst_short_chain_buf1),
|
| 690 |
|
|
.global_shift_enable_buf1 (global_shift_enable_buf1),
|
| 691 |
|
|
|
| 692 |
|
|
.grst_l_buf1 (grst_l_buf1),
|
| 693 |
|
|
.cluster_cken_buf1 (cluster_cken_buf1),
|
| 694 |
|
|
|
| 695 |
|
|
.se_add_exp_buf2 (se_add_exp_buf2),
|
| 696 |
|
|
.se_add_frac_buf2 (se_add_frac_buf2),
|
| 697 |
|
|
.se_out_buf2 (se_out_buf2),
|
| 698 |
|
|
.se_mul64_buf2 (se_mul64_buf2),
|
| 699 |
|
|
.se_cluster_header_buf2 (se_cluster_header_buf2),
|
| 700 |
|
|
.se_in_buf3 (se_in_buf3),
|
| 701 |
|
|
.se_mul_buf4 (se_mul_buf4),
|
| 702 |
|
|
.se_div_buf5 (se_div_buf5),
|
| 703 |
|
|
|
| 704 |
|
|
.arst_l_div_buf2 (arst_l_div_buf2),
|
| 705 |
|
|
.arst_l_mul_buf2 (arst_l_mul_buf2),
|
| 706 |
|
|
.arst_l_cluster_header_buf2 (arst_l_cluster_header_buf2),
|
| 707 |
|
|
.arst_l_in_buf3 (arst_l_in_buf3),
|
| 708 |
|
|
.arst_l_out_buf3 (arst_l_out_buf3),
|
| 709 |
|
|
.arst_l_add_buf4 (arst_l_add_buf4),
|
| 710 |
|
|
|
| 711 |
|
|
.fpu_grst_l_mul_buf1 (fpu_grst_l_mul_buf1),
|
| 712 |
|
|
.fpu_grst_l_in_buf2 (fpu_grst_l_in_buf2),
|
| 713 |
|
|
.fpu_grst_l_add_buf3 (fpu_grst_l_add_buf3),
|
| 714 |
|
|
|
| 715 |
|
|
.fmul_clken_l_buf1 (fmul_clken_l_buf1),
|
| 716 |
|
|
.fdiv_clken_l_div_exp_buf1 (fdiv_clken_l_div_exp_buf1),
|
| 717 |
|
|
.fdiv_clken_l_div_frac_buf1 (fdiv_clken_l_div_frac_buf1),
|
| 718 |
|
|
|
| 719 |
|
|
.scan_manual_6_buf1 (scan_manual_6_buf1),
|
| 720 |
|
|
|
| 721 |
|
|
.si_buf1 (si_buf1),
|
| 722 |
|
|
.so (so),
|
| 723 |
|
|
|
| 724 |
|
|
.pcx_fpio_data_px2_buf1 (pcx_fpio_data_px2_buf1[123:0]),
|
| 725 |
|
|
.pcx_fpio_data_rdy_px2_buf1 (pcx_fpio_data_rdy_px2_buf1),
|
| 726 |
|
|
|
| 727 |
|
|
.fp_cpx_data_ca_buf1 (fp_cpx_data_ca[144:0]),
|
| 728 |
|
|
.fp_cpx_req_cq_buf1 (fp_cpx_req_cq[7:0]),
|
| 729 |
|
|
|
| 730 |
|
|
.inq_sram_din_buf1 (inq_sram_din_buf1[155:0])
|
| 731 |
|
|
|
| 732 |
|
|
);
|
| 733 |
|
|
|
| 734 |
|
|
|
| 735 |
|
|
endmodule
|
| 736 |
|
|
|
| 737 |
|
|
// Local Variables:
|
| 738 |
|
|
// verilog-library-directories:("." "../../../srams/rtl")
|
| 739 |
|
|
// End:
|
| 740 |
|
|
|
