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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: fpu_add.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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///////////////////////////////////////////////////////////////////////////////
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//
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// FPU add pipe.
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//
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///////////////////////////////////////////////////////////////////////////////
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module fpu_add (
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inq_op,
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inq_rnd_mode,
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inq_id,
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inq_fcc,
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inq_in1,
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inq_in1_50_0_neq_0,
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inq_in1_53_32_neq_0,
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inq_in1_exp_eq_0,
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inq_in1_exp_neq_ffs,
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inq_in2,
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inq_in2_50_0_neq_0,
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inq_in2_53_32_neq_0,
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inq_in2_exp_eq_0,
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inq_in2_exp_neq_ffs,
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inq_add,
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add_dest_rdy,
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fadd_clken_l,
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arst_l,
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grst_l,
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rclk,
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add_pipe_active,
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a1stg_step,
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a6stg_fadd_in,
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add_id_out_in,
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a6stg_fcmpop,
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add_exc_out,
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a6stg_dbl_dst,
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a6stg_sng_dst,
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a6stg_long_dst,
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a6stg_int_dst,
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add_sign_out,
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add_exp_out,
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add_frac_out,
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add_cc_out,
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add_fcc_out,
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se_add_exp,
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se_add_frac,
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si,
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so
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);
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input [7:0] inq_op; // request opcode to op pipes
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input [1:0] inq_rnd_mode; // request rounding mode to op pipes
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input [4:0] inq_id; // request ID to the operation pipes
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input [1:0] inq_fcc; // request cc ID to op pipes
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input [63:0] inq_in1; // request operand 1 to op pipes
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input inq_in1_50_0_neq_0; // request operand 1[50:0]!=0
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input inq_in1_53_32_neq_0; // request operand 1[53:32]!=0
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input inq_in1_exp_eq_0; // request operand 1 exp==0
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input inq_in1_exp_neq_ffs; // request operand 1 exp!=0xff's
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input [63:0] inq_in2; // request operand 2 to op pipes
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input inq_in2_50_0_neq_0; // request operand 2[50:0]!=0
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input inq_in2_53_32_neq_0; // request operand 2[53:32]!=0
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input inq_in2_exp_eq_0; // request operand 2 exp==0
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input inq_in2_exp_neq_ffs; // request operand 2 exp!=0xff's
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input inq_add; // add pipe request
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input add_dest_rdy; // add result req accepted for CPX
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input fadd_clken_l; // fadd clock enable
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input arst_l; // global async. reset- asserted low
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input grst_l; // global sync. reset- asserted low
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input rclk; // global clock
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output add_pipe_active; // add pipe is executing a valid instr
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output a1stg_step; // add pipe load
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output a6stg_fadd_in; // add pipe output request next cycle
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output [9:0] add_id_out_in; // add pipe output ID next cycle
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output a6stg_fcmpop; // compare- add 6 stage
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output [4:0] add_exc_out; // add pipe result- exception flags
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output a6stg_dbl_dst; // float double result- add 6 stage
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output a6stg_sng_dst; // float single result- add 6 stage
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output a6stg_long_dst; // 64bit integer result- add 6 stage
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output a6stg_int_dst; // 32bit integer result- add 6 stage
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output add_sign_out; // add sign output
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output [10:0] add_exp_out; // add exponent output
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output [63:0] add_frac_out; // add fraction output
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output [1:0] add_cc_out; // add pipe result- condition
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output [1:0] add_fcc_out; // add pipe input fcc passed through
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input se_add_exp; // scan_enable for add_exp_dp, add_ctl
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input se_add_frac; // scan_enable for add_frac_dp
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input si; // scan in
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output so; // scan out
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///////////////////////////////////////////////////////////////////////////////
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//
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// Outputs of fpu_add_ctl.
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//
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///////////////////////////////////////////////////////////////////////////////
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wire a1stg_denorm_sng_in1; // select line to normalized fraction 1
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wire a1stg_denorm_dbl_in1; // select line to normalized fraction 1
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wire a1stg_denorm_sng_in2; // select line to normalized fraction 2
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wire a1stg_denorm_dbl_in2; // select line to normalized fraction 2
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wire a1stg_norm_sng_in1; // select line to normalized fraction 1
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wire a1stg_norm_dbl_in1; // select line to normalized fraction 1
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wire a1stg_norm_sng_in2; // select line to normalized fraction 2
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wire a1stg_norm_dbl_in2; // select line to normalized fraction 2
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wire a1stg_step; // add pipe load
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wire a1stg_stepa; // add pipe load- copy
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wire a1stg_sngop; // single precision operation- add 1 stg
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wire a1stg_intlngop; // integer/long input- add 1 stage
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wire a1stg_fsdtoix; // float to integer convert- add 1 stg
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wire a1stg_fstod; // fstod- add 1 stage
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wire a1stg_fstoi; // fstoi- add 1 stage
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wire a1stg_fstox; // fstox- add 1 stage
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wire a1stg_fdtoi; // fdtoi- add 1 stage
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wire a1stg_fdtox; // fdtox- add 1 stage
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wire a1stg_faddsubs; // add/subtract single- add 1 stg
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wire a1stg_faddsubd; // add/subtract double- add 1 stg
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wire a1stg_fdtos; // fdtos- add 1 stage
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wire a2stg_faddsubop; // float add or subtract- add 2 stage
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wire a2stg_fsdtoix_fdtos; // float to integer convert- add 2 stg
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wire a2stg_fitos; // fitos- add 2 stage
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wire a2stg_fitod; // fitod- add 2 stage
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wire a2stg_fxtos; // fxtos- add 2 stage
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wire a2stg_fxtod; // fxtod- add 2 stage
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wire a3stg_faddsubop; // denorm compare lead0[10] input select
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wire [1:0] a3stg_faddsubopa; // denorm compare lead0[10] input select
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wire a4stg_dblop; // double precision operation- add 4 stg
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wire a6stg_fadd_in; // add pipe output request next cycle
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wire [9:0] add_id_out_in; // add pipe output ID next cycle
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wire [1:0] add_fcc_out; // add pipe input fcc passed through
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wire a6stg_dbl_dst; // float double result- add 6 stage
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wire a6stg_sng_dst; // float single result- add 6 stage
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wire a6stg_long_dst; // 64bit integer result- add 6 stage
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wire a6stg_int_dst; // 32bit integer result- add 6 stage
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wire a6stg_fcmpop; // compare- add 6 stage
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wire a6stg_step; // advance the add pipe
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wire a3stg_sub_in; // subtract in main adder- add 3 stage
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wire add_sign_out; // add sign output
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wire [1:0] add_cc_out; // add pipe result- condition
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wire a4stg_in_of; // add overflow- select exp out
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wire [4:0] add_exc_out; // add pipe result- exception flags
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wire a2stg_frac1_in_frac1; // select line to a2stg_frac1
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wire a2stg_frac1_in_frac2; // select line to a2stg_frac1
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wire a1stg_2nan_in_inv; // 2 NaN inputs- a1 stage
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wire a1stg_faddsubop_inv; // add/subtract- a1 stage
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wire a2stg_frac1_in_qnan; // make fraction 1 a QNaN
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wire a2stg_frac1_in_nv; // NV- make a new QNaN
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wire a2stg_frac1_in_nv_dbl; // NV- make a new double prec QNaN
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wire a2stg_frac2_in_frac1; // select line to a2stg_frac2
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wire a2stg_frac2_in_qnan; // make fraction 2 a QNaN
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wire [5:0] a2stg_shr_cnt_in; // right shift count input- add 1 stage
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wire a2stg_shr_cnt_5_inv_in; // right shift count input[5]- add 1 stg
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wire a2stg_shr_frac2_shr_int; // select line to a3stg_frac2
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wire a2stg_shr_frac2_shr_dbl; // select line to a3stg_frac2
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wire a2stg_shr_frac2_shr_sng; // select line to a3stg_frac2
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wire a2stg_shr_frac2_max; // select line to a3stg_frac2
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wire a2stg_sub_step; // select line to a3stg_frac2
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wire a2stg_fracadd_frac2_inv_in; // sel line to main adder input 2
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wire a2stg_fracadd_frac2_inv_shr1_in; // sel line to main adder in 2
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wire a2stg_fracadd_frac2; // select line to main adder input 2
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wire a2stg_fracadd_cin_in; // carry in to main adder- add 1 stage
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wire a3stg_exp_7ff; // select line to a3stg_exp
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wire a3stg_exp_ff; // select line to a3stg_exp
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wire a3stg_exp_add; // select line to a3stg_exp
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wire a2stg_expdec_neq_0; // exponent will be < 54
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wire a3stg_exp10_0_eq0; // exponent[10:0]==0- add 3 stage
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wire a3stg_exp10_1_eq0; // exponent[10:1]==0- add 3 stage
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wire a3stg_fdtos_inv; // double to single convert- add 3 stg
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wire a4stg_fixtos_fxtod_inv; // int to single/double cvt- add 4 stg
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wire a4stg_rnd_frac_add_inv; // select line to a4stg_rnd_frac
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wire [9:0] a4stg_shl_cnt_in; // postnorm shift left count- add 3 stg
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wire a4stg_rnd_sng; // round to single precision- add 4 stg
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wire a4stg_rnd_dbl; // round to double precision- add 4 stg
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wire add_frac_out_rndadd; // select line to add_frac_out
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wire add_frac_out_rnd_frac; // select line to add_frac_out
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wire add_frac_out_shl; // select line to add_frac_out
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wire a4stg_to_0; // result to max finite on overflow
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wire add_exp_out_expinc; // select line to add_exp_out
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wire add_exp_out_exp; // select line to add_exp_out
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wire add_exp_out_exp1; // select line to add_exp_out
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wire add_exp_out_expadd; // select line to add_exp_out
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wire a4stg_to_0_inv; // result to infinity on overflow
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wire add_pipe_active; // add pipe is executing a valid instr
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///////////////////////////////////////////////////////////////////////////////
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//
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// Outputs of fpu_add_exp_dp.
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//
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///////////////////////////////////////////////////////////////////////////////
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wire a1stg_expadd3_11; // exponent adder 3 output- add 1 stage
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wire [11:0] a1stg_expadd1_11_0; // exponent adder 1 output- add 1 stage
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wire [10:0] a1stg_expadd4_inv; // exponent adder 4 output- add 1 stage
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wire [5:0] a1stg_expadd2_5_0; // exponent adder 2 output- add 1 stage
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wire [11:0] a2stg_exp; // exponent- add 2 stage
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wire [12:0] a2stg_expadd; // exponent adder- add 2 stage
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wire [10:0] a3stg_exp_10_0; // exponent adder- add 3 stage
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wire [11:0] a4stg_exp_11_0; // exponent adder- add 4 stage
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wire [10:0] add_exp_out; // add exponent output
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///////////////////////////////////////////////////////////////////////////////
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//
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// Outputs of fpu_add_frac_dp.
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//
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///////////////////////////////////////////////////////////////////////////////
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| 231 |
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wire a1stg_in2_neq_in1_frac; // operand 2 fraction != oprnd 1 frac
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wire a1stg_in2_gt_in1_frac; // operand 2 fraction > oprnd 1 frac
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| 234 |
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wire a1stg_in2_eq_in1_exp; // operand 2 exponent == oprnd 1 exp
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| 235 |
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wire a2stg_frac2_63; // fraction 2 bit[63]- add 2 stage
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| 236 |
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wire a2stg_frac2hi_neq_0; // fraction 2[62:32]in add 2 stage != 0
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| 237 |
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wire a2stg_frac2lo_neq_0; // fraction 2[31:11] in add 2 stage != 0
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| 238 |
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wire a3stg_fsdtoix_nx; // inexact result for flt -> ints
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| 239 |
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wire a3stg_fsdtoi_nx; // inexact result for flt -> 32b ints
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| 240 |
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wire a3stg_denorm; // denorm output- add 3 stage
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| 241 |
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wire a3stg_denorm_inv; // result is not a denorm- add 3 stage
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| 242 |
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wire [5:0] a3stg_lead0; // leading 0's count- add 3 stage
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| 243 |
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wire a4stg_round; // round the result- add 4 stage
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| 244 |
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wire [5:0] a4stg_shl_cnt; // subtract in main adder- add 4 stage
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| 245 |
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wire a4stg_denorm_inv; // 0 the exponent
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| 246 |
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wire a3stg_inc_exp_inv; // increment the exponent- add 3 stg
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| 247 |
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wire a3stg_same_exp_inv; // keep the exponent- add 3 stg
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| 248 |
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wire a3stg_dec_exp_inv; // decrement the exponent- add 3 stg
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| 249 |
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wire a4stg_rnd_frac_40; // rounded fraction[40]- add 4 stage
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| 250 |
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wire a4stg_rnd_frac_39; // rounded fraction[39]- add 4 stage
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| 251 |
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wire a4stg_rnd_frac_11; // rounded fraction[11]- add 4 stage
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| 252 |
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wire a4stg_rnd_frac_10; // rounded fraction[10]- add 4 stage
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| 253 |
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wire a4stg_rndadd_cout; // fraction rounding adder carry out
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| 254 |
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wire a4stg_frac_9_0_nx; // inexact double precision result
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wire a4stg_frac_dbl_nx; // inexact double precision result
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wire a4stg_frac_38_0_nx; // inexact single precision result
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| 257 |
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wire a4stg_frac_sng_nx; // inexact single precision result
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| 258 |
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wire a4stg_frac_neq_0; // fraction != 0- add 4 stage
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| 259 |
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wire a4stg_shl_data_neq_0; // left shift result != 0- add 4 stage
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| 260 |
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wire add_of_out_cout; // fraction rounding adder carry out
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| 261 |
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wire [63:0] add_frac_out; // add fraction output
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///////////////////////////////////////////////////////////////////////////////
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//
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// Instantiations.
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| 267 |
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//
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| 268 |
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///////////////////////////////////////////////////////////////////////////////
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| 269 |
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|
| 270 |
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fpu_add_ctl fpu_add_ctl (
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| 271 |
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.inq_in1_51 (inq_in1[51]),
|
| 272 |
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.inq_in1_54 (inq_in1[54]),
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| 273 |
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.inq_in1_63 (inq_in1[63]),
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| 274 |
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.inq_in1_50_0_neq_0 (inq_in1_50_0_neq_0),
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| 275 |
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.inq_in1_53_32_neq_0 (inq_in1_53_32_neq_0),
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| 276 |
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.inq_in1_exp_eq_0 (inq_in1_exp_eq_0),
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| 277 |
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.inq_in1_exp_neq_ffs (inq_in1_exp_neq_ffs),
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| 278 |
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.inq_in2_51 (inq_in2[51]),
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| 279 |
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.inq_in2_54 (inq_in2[54]),
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| 280 |
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.inq_in2_63 (inq_in2[63]),
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| 281 |
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.inq_in2_50_0_neq_0 (inq_in2_50_0_neq_0),
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| 282 |
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.inq_in2_53_32_neq_0 (inq_in2_53_32_neq_0),
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| 283 |
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.inq_in2_exp_eq_0 (inq_in2_exp_eq_0),
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| 284 |
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.inq_in2_exp_neq_ffs (inq_in2_exp_neq_ffs),
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| 285 |
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.inq_op (inq_op[7:0]),
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| 286 |
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.inq_rnd_mode (inq_rnd_mode[1:0]),
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| 287 |
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.inq_id (inq_id[4:0]),
|
| 288 |
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.inq_fcc (inq_fcc[1:0]),
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| 289 |
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.inq_add (inq_add),
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| 290 |
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.add_dest_rdy (add_dest_rdy),
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| 291 |
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.a1stg_in2_neq_in1_frac (a1stg_in2_neq_in1_frac),
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| 292 |
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.a1stg_in2_gt_in1_frac (a1stg_in2_gt_in1_frac),
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| 293 |
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.a1stg_in2_eq_in1_exp (a1stg_in2_eq_in1_exp),
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| 294 |
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.a1stg_expadd1 (a1stg_expadd1_11_0[11:0]),
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| 295 |
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.a2stg_expadd (a2stg_expadd[11:0]),
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| 296 |
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.a2stg_frac2hi_neq_0 (a2stg_frac2hi_neq_0),
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| 297 |
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.a2stg_frac2lo_neq_0 (a2stg_frac2lo_neq_0),
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| 298 |
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.a2stg_exp (a2stg_exp[11:0]),
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| 299 |
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.a3stg_fsdtoix_nx (a3stg_fsdtoix_nx),
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| 300 |
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.a3stg_fsdtoi_nx (a3stg_fsdtoi_nx),
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| 301 |
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.a2stg_frac2_63 (a2stg_frac2_63),
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| 302 |
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.a4stg_exp (a4stg_exp_11_0[11:0]),
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| 303 |
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.add_of_out_cout (add_of_out_cout),
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| 304 |
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.a4stg_frac_neq_0 (a4stg_frac_neq_0),
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| 305 |
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.a4stg_shl_data_neq_0 (a4stg_shl_data_neq_0),
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| 306 |
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.a4stg_frac_dbl_nx (a4stg_frac_dbl_nx),
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| 307 |
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.a4stg_frac_sng_nx (a4stg_frac_sng_nx),
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| 308 |
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.a1stg_expadd2 (a1stg_expadd2_5_0[5:0]),
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| 309 |
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.a1stg_expadd4_inv (a1stg_expadd4_inv[10:0]),
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| 310 |
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.a3stg_denorm (a3stg_denorm),
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| 311 |
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.a3stg_denorm_inv (a3stg_denorm_inv),
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| 312 |
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.a4stg_denorm_inv (a4stg_denorm_inv),
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| 313 |
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.a3stg_exp (a3stg_exp_10_0[10:0]),
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| 314 |
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.a4stg_round (a4stg_round),
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| 315 |
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.a3stg_lead0 (a3stg_lead0[5:0]),
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| 316 |
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.a4stg_rnd_frac_40 (a4stg_rnd_frac_40),
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| 317 |
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.a4stg_rnd_frac_39 (a4stg_rnd_frac_39),
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| 318 |
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.a4stg_rnd_frac_11 (a4stg_rnd_frac_11),
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| 319 |
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.a4stg_rnd_frac_10 (a4stg_rnd_frac_10),
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| 320 |
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.a4stg_frac_38_0_nx (a4stg_frac_38_0_nx),
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| 321 |
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.a4stg_frac_9_0_nx (a4stg_frac_9_0_nx),
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| 322 |
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.arst_l (arst_l),
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| 323 |
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.grst_l (grst_l),
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| 324 |
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.rclk (rclk),
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| 325 |
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|
| 326 |
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.add_pipe_active (add_pipe_active),
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| 327 |
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.a1stg_denorm_sng_in1 (a1stg_denorm_sng_in1),
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| 328 |
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.a1stg_denorm_dbl_in1 (a1stg_denorm_dbl_in1),
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| 329 |
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.a1stg_denorm_sng_in2 (a1stg_denorm_sng_in2),
|
| 330 |
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.a1stg_denorm_dbl_in2 (a1stg_denorm_dbl_in2),
|
| 331 |
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.a1stg_norm_sng_in1 (a1stg_norm_sng_in1),
|
| 332 |
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.a1stg_norm_dbl_in1 (a1stg_norm_dbl_in1),
|
| 333 |
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.a1stg_norm_sng_in2 (a1stg_norm_sng_in2),
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| 334 |
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.a1stg_norm_dbl_in2 (a1stg_norm_dbl_in2),
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| 335 |
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.a1stg_step (a1stg_step),
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| 336 |
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.a1stg_stepa (a1stg_stepa),
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| 337 |
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.a1stg_sngop (a1stg_sngop),
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| 338 |
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.a1stg_intlngop (a1stg_intlngop),
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| 339 |
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.a1stg_fsdtoix (a1stg_fsdtoix),
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| 340 |
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.a1stg_fstod (a1stg_fstod),
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| 341 |
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.a1stg_fstoi (a1stg_fstoi),
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| 342 |
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.a1stg_fstox (a1stg_fstox),
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| 343 |
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.a1stg_fdtoi (a1stg_fdtoi),
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| 344 |
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.a1stg_fdtox (a1stg_fdtox),
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| 345 |
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.a1stg_faddsubs (a1stg_faddsubs),
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| 346 |
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.a1stg_faddsubd (a1stg_faddsubd),
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| 347 |
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.a1stg_fdtos (a1stg_fdtos),
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| 348 |
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.a2stg_faddsubop (a2stg_faddsubop),
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| 349 |
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.a2stg_fsdtoix_fdtos (a2stg_fsdtoix_fdtos),
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| 350 |
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.a2stg_fitos (a2stg_fitos),
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| 351 |
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.a2stg_fitod (a2stg_fitod),
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| 352 |
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.a2stg_fxtos (a2stg_fxtos),
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| 353 |
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.a2stg_fxtod (a2stg_fxtod),
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| 354 |
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.a3stg_faddsubop (a3stg_faddsubop),
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| 355 |
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.a3stg_faddsubopa (a3stg_faddsubopa[1:0]),
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| 356 |
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.a4stg_dblop (a4stg_dblop),
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| 357 |
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.a6stg_fadd_in (a6stg_fadd_in),
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| 358 |
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.add_id_out_in (add_id_out_in[9:0]),
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| 359 |
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.add_fcc_out (add_fcc_out[1:0]),
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| 360 |
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.a6stg_dbl_dst (a6stg_dbl_dst),
|
| 361 |
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.a6stg_sng_dst (a6stg_sng_dst),
|
| 362 |
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.a6stg_long_dst (a6stg_long_dst),
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| 363 |
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.a6stg_int_dst (a6stg_int_dst),
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| 364 |
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.a6stg_fcmpop (a6stg_fcmpop),
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| 365 |
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.a6stg_step (a6stg_step),
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| 366 |
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.a3stg_sub_in (a3stg_sub_in),
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| 367 |
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.add_sign_out (add_sign_out),
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| 368 |
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.add_cc_out (add_cc_out[1:0]),
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| 369 |
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.a4stg_in_of (a4stg_in_of),
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| 370 |
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.add_exc_out (add_exc_out[4:0]),
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| 371 |
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.a2stg_frac1_in_frac1 (a2stg_frac1_in_frac1),
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| 372 |
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.a2stg_frac1_in_frac2 (a2stg_frac1_in_frac2),
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| 373 |
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.a1stg_2nan_in_inv (a1stg_2nan_in_inv),
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| 374 |
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.a1stg_faddsubop_inv (a1stg_faddsubop_inv),
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| 375 |
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.a2stg_frac1_in_qnan (a2stg_frac1_in_qnan),
|
| 376 |
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.a2stg_frac1_in_nv (a2stg_frac1_in_nv),
|
| 377 |
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.a2stg_frac1_in_nv_dbl (a2stg_frac1_in_nv_dbl),
|
| 378 |
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.a2stg_frac2_in_frac1 (a2stg_frac2_in_frac1),
|
| 379 |
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.a2stg_frac2_in_qnan (a2stg_frac2_in_qnan),
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| 380 |
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.a2stg_shr_cnt_in (a2stg_shr_cnt_in[5:0]),
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| 381 |
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.a2stg_shr_cnt_5_inv_in (a2stg_shr_cnt_5_inv_in),
|
| 382 |
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.a2stg_shr_frac2_shr_int (a2stg_shr_frac2_shr_int),
|
| 383 |
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.a2stg_shr_frac2_shr_dbl (a2stg_shr_frac2_shr_dbl),
|
| 384 |
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.a2stg_shr_frac2_shr_sng (a2stg_shr_frac2_shr_sng),
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| 385 |
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.a2stg_shr_frac2_max (a2stg_shr_frac2_max),
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| 386 |
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.a2stg_sub_step (a2stg_sub_step),
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| 387 |
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.a2stg_fracadd_frac2_inv_in (a2stg_fracadd_frac2_inv_in),
|
| 388 |
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.a2stg_fracadd_frac2_inv_shr1_in (a2stg_fracadd_frac2_inv_shr1_in),
|
| 389 |
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.a2stg_fracadd_frac2 (a2stg_fracadd_frac2),
|
| 390 |
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.a2stg_fracadd_cin_in (a2stg_fracadd_cin_in),
|
| 391 |
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.a3stg_exp_7ff (a3stg_exp_7ff),
|
| 392 |
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.a3stg_exp_ff (a3stg_exp_ff),
|
| 393 |
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.a3stg_exp_add (a3stg_exp_add),
|
| 394 |
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.a2stg_expdec_neq_0 (a2stg_expdec_neq_0),
|
| 395 |
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.a3stg_exp10_0_eq0 (a3stg_exp10_0_eq0),
|
| 396 |
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.a3stg_exp10_1_eq0 (a3stg_exp10_1_eq0),
|
| 397 |
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.a3stg_fdtos_inv (a3stg_fdtos_inv),
|
| 398 |
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.a4stg_fixtos_fxtod_inv (a4stg_fixtos_fxtod_inv),
|
| 399 |
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.a4stg_rnd_frac_add_inv (a4stg_rnd_frac_add_inv),
|
| 400 |
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.a4stg_shl_cnt_in (a4stg_shl_cnt_in[9:0]),
|
| 401 |
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.a4stg_rnd_sng (a4stg_rnd_sng),
|
| 402 |
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.a4stg_rnd_dbl (a4stg_rnd_dbl),
|
| 403 |
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.add_frac_out_rndadd (add_frac_out_rndadd),
|
| 404 |
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.add_frac_out_rnd_frac (add_frac_out_rnd_frac),
|
| 405 |
|
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.add_frac_out_shl (add_frac_out_shl),
|
| 406 |
|
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.a4stg_to_0 (a4stg_to_0),
|
| 407 |
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.add_exp_out_expinc (add_exp_out_expinc),
|
| 408 |
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.add_exp_out_exp (add_exp_out_exp),
|
| 409 |
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.add_exp_out_exp1 (add_exp_out_exp1),
|
| 410 |
|
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.add_exp_out_expadd (add_exp_out_expadd),
|
| 411 |
|
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.a4stg_to_0_inv (a4stg_to_0_inv),
|
| 412 |
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|
|
| 413 |
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.se (se_add_exp),
|
| 414 |
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.si (si),
|
| 415 |
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.so (scan_out_fpu_add_ctl)
|
| 416 |
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);
|
| 417 |
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|
| 418 |
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|
| 419 |
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fpu_add_exp_dp fpu_add_exp_dp (
|
| 420 |
|
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.inq_in1 (inq_in1[62:52]),
|
| 421 |
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.inq_in2 (inq_in2[62:52]),
|
| 422 |
|
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.inq_op (inq_op[1:0]),
|
| 423 |
|
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.inq_op_7 (inq_op[7]),
|
| 424 |
|
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.a1stg_step (a1stg_stepa),
|
| 425 |
|
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.a1stg_faddsubd (a1stg_faddsubd),
|
| 426 |
|
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.a1stg_faddsubs (a1stg_faddsubs),
|
| 427 |
|
|
.a1stg_fsdtoix (a1stg_fsdtoix),
|
| 428 |
|
|
.a6stg_step (a6stg_step),
|
| 429 |
|
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.a1stg_fstod (a1stg_fstod),
|
| 430 |
|
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.a1stg_fdtos (a1stg_fdtos),
|
| 431 |
|
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.a1stg_fstoi (a1stg_fstoi),
|
| 432 |
|
|
.a1stg_fstox (a1stg_fstox),
|
| 433 |
|
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.a1stg_fdtoi (a1stg_fdtoi),
|
| 434 |
|
|
.a1stg_fdtox (a1stg_fdtox),
|
| 435 |
|
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.a2stg_fsdtoix_fdtos (a2stg_fsdtoix_fdtos),
|
| 436 |
|
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.a2stg_faddsubop (a2stg_faddsubop),
|
| 437 |
|
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.a2stg_fitos (a2stg_fitos),
|
| 438 |
|
|
.a2stg_fitod (a2stg_fitod),
|
| 439 |
|
|
.a2stg_fxtos (a2stg_fxtos),
|
| 440 |
|
|
.a2stg_fxtod (a2stg_fxtod),
|
| 441 |
|
|
.a3stg_exp_7ff (a3stg_exp_7ff),
|
| 442 |
|
|
.a3stg_exp_ff (a3stg_exp_ff),
|
| 443 |
|
|
.a3stg_exp_add (a3stg_exp_add),
|
| 444 |
|
|
.a3stg_inc_exp_inv (a3stg_inc_exp_inv),
|
| 445 |
|
|
.a3stg_same_exp_inv (a3stg_same_exp_inv),
|
| 446 |
|
|
.a3stg_dec_exp_inv (a3stg_dec_exp_inv),
|
| 447 |
|
|
.a3stg_faddsubop (a3stg_faddsubop),
|
| 448 |
|
|
.a3stg_fdtos_inv (a3stg_fdtos_inv),
|
| 449 |
|
|
.a4stg_fixtos_fxtod_inv (a4stg_fixtos_fxtod_inv),
|
| 450 |
|
|
.a4stg_shl_cnt (a4stg_shl_cnt[5:0]),
|
| 451 |
|
|
.a4stg_denorm_inv (a4stg_denorm_inv),
|
| 452 |
|
|
.a4stg_rndadd_cout (a4stg_rndadd_cout),
|
| 453 |
|
|
.add_exp_out_expinc (add_exp_out_expinc),
|
| 454 |
|
|
.add_exp_out_exp (add_exp_out_exp),
|
| 455 |
|
|
.add_exp_out_exp1 (add_exp_out_exp1),
|
| 456 |
|
|
.a4stg_in_of (a4stg_in_of),
|
| 457 |
|
|
.add_exp_out_expadd (add_exp_out_expadd),
|
| 458 |
|
|
.a4stg_dblop (a4stg_dblop),
|
| 459 |
|
|
.a4stg_to_0_inv (a4stg_to_0_inv),
|
| 460 |
|
|
.fadd_clken_l (fadd_clken_l),
|
| 461 |
|
|
.rclk (rclk),
|
| 462 |
|
|
|
| 463 |
|
|
.a1stg_expadd3_11 (a1stg_expadd3_11),
|
| 464 |
|
|
.a1stg_expadd1_11_0 (a1stg_expadd1_11_0[11:0]),
|
| 465 |
|
|
.a1stg_expadd4_inv (a1stg_expadd4_inv[10:0]),
|
| 466 |
|
|
.a1stg_expadd2_5_0 (a1stg_expadd2_5_0[5:0]),
|
| 467 |
|
|
.a2stg_exp (a2stg_exp[11:0]),
|
| 468 |
|
|
.a2stg_expadd (a2stg_expadd[12:0]),
|
| 469 |
|
|
.a3stg_exp_10_0 (a3stg_exp_10_0[10:0]),
|
| 470 |
|
|
.a4stg_exp_11_0 (a4stg_exp_11_0[11:0]),
|
| 471 |
|
|
.add_exp_out (add_exp_out[10:0]),
|
| 472 |
|
|
|
| 473 |
|
|
.se (se_add_exp),
|
| 474 |
|
|
.si (scan_out_fpu_add_ctl),
|
| 475 |
|
|
.so (scan_out_fpu_add_exp_dp)
|
| 476 |
|
|
);
|
| 477 |
|
|
|
| 478 |
|
|
|
| 479 |
|
|
fpu_add_frac_dp fpu_add_frac_dp (
|
| 480 |
|
|
.inq_in1 (inq_in1[62:0]),
|
| 481 |
|
|
.inq_in2 (inq_in2[63:0]),
|
| 482 |
|
|
.a1stg_step (a1stg_stepa),
|
| 483 |
|
|
.a1stg_sngop (a1stg_sngop),
|
| 484 |
|
|
.a1stg_expadd3_11 (a1stg_expadd3_11),
|
| 485 |
|
|
.a1stg_norm_dbl_in1 (a1stg_norm_dbl_in1),
|
| 486 |
|
|
.a1stg_denorm_dbl_in1 (a1stg_denorm_dbl_in1),
|
| 487 |
|
|
.a1stg_norm_sng_in1 (a1stg_norm_sng_in1),
|
| 488 |
|
|
.a1stg_denorm_sng_in1 (a1stg_denorm_sng_in1),
|
| 489 |
|
|
.a1stg_norm_dbl_in2 (a1stg_norm_dbl_in2),
|
| 490 |
|
|
.a1stg_denorm_dbl_in2 (a1stg_denorm_dbl_in2),
|
| 491 |
|
|
.a1stg_norm_sng_in2 (a1stg_norm_sng_in2),
|
| 492 |
|
|
.a1stg_denorm_sng_in2 (a1stg_denorm_sng_in2),
|
| 493 |
|
|
.a1stg_intlngop (a1stg_intlngop),
|
| 494 |
|
|
.a2stg_frac1_in_frac1 (a2stg_frac1_in_frac1),
|
| 495 |
|
|
.a2stg_frac1_in_frac2 (a2stg_frac1_in_frac2),
|
| 496 |
|
|
.a1stg_2nan_in_inv (a1stg_2nan_in_inv),
|
| 497 |
|
|
.a1stg_faddsubop_inv (a1stg_faddsubop_inv),
|
| 498 |
|
|
.a2stg_frac1_in_qnan (a2stg_frac1_in_qnan),
|
| 499 |
|
|
.a2stg_frac1_in_nv (a2stg_frac1_in_nv),
|
| 500 |
|
|
.a2stg_frac1_in_nv_dbl (a2stg_frac1_in_nv_dbl),
|
| 501 |
|
|
.a6stg_step (a6stg_step),
|
| 502 |
|
|
.a2stg_frac2_in_frac1 (a2stg_frac2_in_frac1),
|
| 503 |
|
|
.a2stg_frac2_in_qnan (a2stg_frac2_in_qnan),
|
| 504 |
|
|
.a2stg_shr_cnt_in (a2stg_shr_cnt_in[5:0]),
|
| 505 |
|
|
.a2stg_shr_cnt_5_inv_in (a2stg_shr_cnt_5_inv_in),
|
| 506 |
|
|
.a2stg_shr_frac2_shr_int (a2stg_shr_frac2_shr_int),
|
| 507 |
|
|
.a2stg_shr_frac2_shr_dbl (a2stg_shr_frac2_shr_dbl),
|
| 508 |
|
|
.a2stg_shr_frac2_shr_sng (a2stg_shr_frac2_shr_sng),
|
| 509 |
|
|
.a2stg_shr_frac2_max (a2stg_shr_frac2_max),
|
| 510 |
|
|
.a2stg_expadd_11 (a2stg_expadd[12]),
|
| 511 |
|
|
.a2stg_sub_step (a2stg_sub_step),
|
| 512 |
|
|
.a2stg_fracadd_frac2_inv_in (a2stg_fracadd_frac2_inv_in),
|
| 513 |
|
|
.a2stg_fracadd_frac2_inv_shr1_in (a2stg_fracadd_frac2_inv_shr1_in),
|
| 514 |
|
|
.a2stg_fracadd_frac2 (a2stg_fracadd_frac2),
|
| 515 |
|
|
.a2stg_fracadd_cin_in (a2stg_fracadd_cin_in),
|
| 516 |
|
|
.a2stg_exp (a2stg_exp[5:0]),
|
| 517 |
|
|
.a2stg_expdec_neq_0 (a2stg_expdec_neq_0),
|
| 518 |
|
|
.a3stg_faddsubopa (a3stg_faddsubopa[1:0]),
|
| 519 |
|
|
.a3stg_sub_in (a3stg_sub_in),
|
| 520 |
|
|
.a3stg_exp10_0_eq0 (a3stg_exp10_0_eq0),
|
| 521 |
|
|
.a3stg_exp10_1_eq0 (a3stg_exp10_1_eq0),
|
| 522 |
|
|
.a3stg_exp_0 (a3stg_exp_10_0[0]),
|
| 523 |
|
|
.a4stg_rnd_frac_add_inv (a4stg_rnd_frac_add_inv),
|
| 524 |
|
|
.a3stg_fdtos_inv (a3stg_fdtos_inv),
|
| 525 |
|
|
.a4stg_fixtos_fxtod_inv (a4stg_fixtos_fxtod_inv),
|
| 526 |
|
|
.a4stg_rnd_sng (a4stg_rnd_sng),
|
| 527 |
|
|
.a4stg_rnd_dbl (a4stg_rnd_dbl),
|
| 528 |
|
|
.a4stg_shl_cnt_in (a4stg_shl_cnt_in[9:0]),
|
| 529 |
|
|
.add_frac_out_rndadd (add_frac_out_rndadd),
|
| 530 |
|
|
.add_frac_out_rnd_frac (add_frac_out_rnd_frac),
|
| 531 |
|
|
.a4stg_in_of (a4stg_in_of),
|
| 532 |
|
|
.add_frac_out_shl (add_frac_out_shl),
|
| 533 |
|
|
.a4stg_to_0 (a4stg_to_0),
|
| 534 |
|
|
.fadd_clken_l (fadd_clken_l),
|
| 535 |
|
|
.rclk (rclk),
|
| 536 |
|
|
|
| 537 |
|
|
.a1stg_in2_neq_in1_frac (a1stg_in2_neq_in1_frac),
|
| 538 |
|
|
.a1stg_in2_gt_in1_frac (a1stg_in2_gt_in1_frac),
|
| 539 |
|
|
.a1stg_in2_eq_in1_exp (a1stg_in2_eq_in1_exp),
|
| 540 |
|
|
.a2stg_frac2_63 (a2stg_frac2_63),
|
| 541 |
|
|
.a2stg_frac2hi_neq_0 (a2stg_frac2hi_neq_0),
|
| 542 |
|
|
.a2stg_frac2lo_neq_0 (a2stg_frac2lo_neq_0),
|
| 543 |
|
|
.a3stg_fsdtoix_nx (a3stg_fsdtoix_nx),
|
| 544 |
|
|
.a3stg_fsdtoi_nx (a3stg_fsdtoi_nx),
|
| 545 |
|
|
.a3stg_denorm (a3stg_denorm),
|
| 546 |
|
|
.a3stg_denorm_inv (a3stg_denorm_inv),
|
| 547 |
|
|
.a3stg_lead0 (a3stg_lead0[5:0]),
|
| 548 |
|
|
.a4stg_round (a4stg_round),
|
| 549 |
|
|
.a4stg_shl_cnt (a4stg_shl_cnt[5:0]),
|
| 550 |
|
|
.a4stg_denorm_inv (a4stg_denorm_inv),
|
| 551 |
|
|
.a3stg_inc_exp_inv (a3stg_inc_exp_inv),
|
| 552 |
|
|
.a3stg_same_exp_inv (a3stg_same_exp_inv),
|
| 553 |
|
|
.a3stg_dec_exp_inv (a3stg_dec_exp_inv),
|
| 554 |
|
|
.a4stg_rnd_frac_40 (a4stg_rnd_frac_40),
|
| 555 |
|
|
.a4stg_rnd_frac_39 (a4stg_rnd_frac_39),
|
| 556 |
|
|
.a4stg_rnd_frac_11 (a4stg_rnd_frac_11),
|
| 557 |
|
|
.a4stg_rnd_frac_10 (a4stg_rnd_frac_10),
|
| 558 |
|
|
.a4stg_rndadd_cout (a4stg_rndadd_cout),
|
| 559 |
|
|
.a4stg_frac_9_0_nx (a4stg_frac_9_0_nx),
|
| 560 |
|
|
.a4stg_frac_dbl_nx (a4stg_frac_dbl_nx),
|
| 561 |
|
|
.a4stg_frac_38_0_nx (a4stg_frac_38_0_nx),
|
| 562 |
|
|
.a4stg_frac_sng_nx (a4stg_frac_sng_nx),
|
| 563 |
|
|
.a4stg_frac_neq_0 (a4stg_frac_neq_0),
|
| 564 |
|
|
.a4stg_shl_data_neq_0 (a4stg_shl_data_neq_0),
|
| 565 |
|
|
.add_of_out_cout (add_of_out_cout),
|
| 566 |
|
|
.add_frac_out (add_frac_out[63:0]),
|
| 567 |
|
|
|
| 568 |
|
|
.se (se_add_frac),
|
| 569 |
|
|
.si (scan_out_fpu_add_exp_dp),
|
| 570 |
|
|
.so (so)
|
| 571 |
|
|
);
|
| 572 |
|
|
|
| 573 |
|
|
|
| 574 |
|
|
endmodule
|
| 575 |
|
|
|
| 576 |
|
|
|
