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[/] [sparc64soc/] [trunk/] [T1-FPU/] [fpu_add_ctl.v] - Blame information for rev 2

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1 2 dmitryr
// ========== Copyright Header Begin ==========================================
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// 
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// OpenSPARC T1 Processor File: fpu_add_ctl.v
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// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// 
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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// 
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// The above named program is distributed in the hope that it will be 
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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// General Public License for more details.
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// 
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// 
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// ========== Copyright Header End ============================================
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///////////////////////////////////////////////////////////////////////////////
22
//
23
//      Add pipeline synthesizable logic
24
//              - special input cases
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//              - opcode pipeline
26
//              - sign logic
27
//              - exception logic
28
//              - datapath control- select lines and control logic
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//
30
///////////////////////////////////////////////////////////////////////////////
31
 
32
module fpu_add_ctl (
33
        inq_in1_51,
34
        inq_in1_54,
35
        inq_in1_63,
36
        inq_in1_50_0_neq_0,
37
        inq_in1_53_32_neq_0,
38
        inq_in1_exp_eq_0,
39
        inq_in1_exp_neq_ffs,
40
        inq_in2_51,
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        inq_in2_54,
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        inq_in2_63,
43
        inq_in2_50_0_neq_0,
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        inq_in2_53_32_neq_0,
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        inq_in2_exp_eq_0,
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        inq_in2_exp_neq_ffs,
47
        inq_op,
48
        inq_rnd_mode,
49
        inq_id,
50
        inq_fcc,
51
        inq_add,
52
        add_dest_rdy,
53
        a1stg_in2_neq_in1_frac,
54
        a1stg_in2_gt_in1_frac,
55
        a1stg_in2_eq_in1_exp,
56
        a1stg_expadd1,
57
        a2stg_expadd,
58
        a2stg_frac2hi_neq_0,
59
        a2stg_frac2lo_neq_0,
60
        a2stg_exp,
61
        a3stg_fsdtoix_nx,
62
        a3stg_fsdtoi_nx,
63
        a2stg_frac2_63,
64
        a4stg_exp,
65
        add_of_out_cout,
66
        a4stg_frac_neq_0,
67
        a4stg_shl_data_neq_0,
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        a4stg_frac_dbl_nx,
69
        a4stg_frac_sng_nx,
70
        a1stg_expadd2,
71
        a1stg_expadd4_inv,
72
        a3stg_denorm,
73
        a3stg_denorm_inv,
74
        a4stg_denorm_inv,
75
        a3stg_exp,
76
        a4stg_round,
77
        a3stg_lead0,
78
        a4stg_rnd_frac_40,
79
        a4stg_rnd_frac_39,
80
        a4stg_rnd_frac_11,
81
        a4stg_rnd_frac_10,
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        a4stg_frac_38_0_nx,
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        a4stg_frac_9_0_nx,
84
        arst_l,
85
        grst_l,
86
        rclk,
87
 
88
        add_pipe_active,
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        a1stg_denorm_sng_in1,
90
        a1stg_denorm_dbl_in1,
91
        a1stg_denorm_sng_in2,
92
        a1stg_denorm_dbl_in2,
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        a1stg_norm_sng_in1,
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        a1stg_norm_dbl_in1,
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        a1stg_norm_sng_in2,
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        a1stg_norm_dbl_in2,
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        a1stg_step,
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        a1stg_stepa,
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        a1stg_sngop,
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        a1stg_intlngop,
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        a1stg_fsdtoix,
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        a1stg_fstod,
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        a1stg_fstoi,
104
        a1stg_fstox,
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        a1stg_fdtoi,
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        a1stg_fdtox,
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        a1stg_faddsubs,
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        a1stg_faddsubd,
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        a1stg_fdtos,
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        a2stg_faddsubop,
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        a2stg_fsdtoix_fdtos,
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        a2stg_fitos,
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        a2stg_fitod,
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        a2stg_fxtos,
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        a2stg_fxtod,
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        a3stg_faddsubop,
117
        a3stg_faddsubopa,
118
        a4stg_dblop,
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        a6stg_fadd_in,
120
        add_id_out_in,
121
        add_fcc_out,
122
        a6stg_dbl_dst,
123
        a6stg_sng_dst,
124
        a6stg_long_dst,
125
        a6stg_int_dst,
126
        a6stg_fcmpop,
127
        a6stg_step,
128
        a3stg_sub_in,
129
        add_sign_out,
130
        add_cc_out,
131
        a4stg_in_of,
132
        add_exc_out,
133
        a2stg_frac1_in_frac1,
134
        a2stg_frac1_in_frac2,
135
        a1stg_2nan_in_inv,
136
        a1stg_faddsubop_inv,
137
        a2stg_frac1_in_qnan,
138
        a2stg_frac1_in_nv,
139
        a2stg_frac1_in_nv_dbl,
140
        a2stg_frac2_in_frac1,
141
        a2stg_frac2_in_qnan,
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        a2stg_shr_cnt_in,
143
        a2stg_shr_cnt_5_inv_in,
144
        a2stg_shr_frac2_shr_int,
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        a2stg_shr_frac2_shr_dbl,
146
        a2stg_shr_frac2_shr_sng,
147
        a2stg_shr_frac2_max,
148
        a2stg_sub_step,
149
        a2stg_fracadd_frac2_inv_in,
150
        a2stg_fracadd_frac2_inv_shr1_in,
151
        a2stg_fracadd_frac2,
152
        a2stg_fracadd_cin_in,
153
        a3stg_exp_7ff,
154
        a3stg_exp_ff,
155
        a3stg_exp_add,
156
        a2stg_expdec_neq_0,
157
        a3stg_exp10_0_eq0,
158
        a3stg_exp10_1_eq0,
159
        a3stg_fdtos_inv,
160
        a4stg_fixtos_fxtod_inv,
161
        a4stg_rnd_frac_add_inv,
162
        a4stg_shl_cnt_in,
163
        a4stg_rnd_sng,
164
        a4stg_rnd_dbl,
165
        add_frac_out_rndadd,
166
        add_frac_out_rnd_frac,
167
        add_frac_out_shl,
168
        a4stg_to_0,
169
        add_exp_out_expinc,
170
        add_exp_out_exp,
171
        add_exp_out_exp1,
172
        add_exp_out_expadd,
173
        a4stg_to_0_inv,
174
 
175
        se,
176
        si,
177
        so
178
);
179
 
180
 
181
parameter
182
                FADDS=  8'h41,
183
                FADDD=  8'h42,
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                FSUBS=  8'h45,
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                FSUBD=  8'h46,
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                FCMPS=  8'h51,
187
                FCMPD=  8'h52,
188
                FCMPES= 8'h55,
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                FCMPED= 8'h56,
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                FSTOX=  8'h81,
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                FDTOX=  8'h82,
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                FSTOI=  8'hd1,
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                FDTOI=  8'hd2,
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                FSTOD=  8'hc9,
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                FDTOS=  8'hc6,
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                FXTOS=  8'h84,
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                FXTOD=  8'h88,
198
                FITOS=  8'hc4,
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                FITOD=  8'hc8;
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201
 
202
input           inq_in1_51;             // request operand 1[51]
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input           inq_in1_54;             // request operand 1[54]
204
input           inq_in1_63;             // request operand 1[63]
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input           inq_in1_50_0_neq_0;     // request operand 1[50:0]!=0
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input           inq_in1_53_32_neq_0;    // request operand 1[53:32]!=0
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input           inq_in1_exp_eq_0;       // request operand 1[62:52]==0
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input           inq_in1_exp_neq_ffs;    // request operand 1[62:52]!=0x7ff
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input           inq_in2_51;             // request operand 2[51]
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input           inq_in2_54;             // request operand 2[54]
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input           inq_in2_63;             // request operand 2[63]
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input           inq_in2_50_0_neq_0;     // request operand 2[50:0]!=0
213
input           inq_in2_53_32_neq_0;    // request operand 2[53:32]!=0
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input           inq_in2_exp_eq_0;       // request operand 2[62:52]==0
215
input           inq_in2_exp_neq_ffs;    // request operand 2[62:52]!=0x7ff
216
input [7:0]      inq_op;                 // request opcode to op pipes
217
input [1:0]      inq_rnd_mode;           // request rounding mode to op pipes
218
input [4:0]      inq_id;                 // request ID to the operation pipes
219
input [1:0]      inq_fcc;                // request cc ID to op pipes
220
input           inq_add;                // add pipe request
221
input           add_dest_rdy;           // add result req accepted for CPX
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input           a1stg_in2_neq_in1_frac; // operand 2 fraction != oprnd 1 frac
223
input           a1stg_in2_gt_in1_frac;  // operand 2 fraction > oprnd 1 frac
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input           a1stg_in2_eq_in1_exp;   // operand 2 exponent == oprnd 1 exp
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input [11:0]     a1stg_expadd1;          // exponent adder 1 output- add 1 stage
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input [11:0]     a2stg_expadd;           // exponent adder- add 2 stage
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input           a2stg_frac2hi_neq_0;    // fraction 2[62:32]in add 2 stage != 0
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input           a2stg_frac2lo_neq_0;    // fraction 2[31:11] in add 2 stage != 0
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input [11:0]     a2stg_exp;              // exponent- add 2 stage
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input           a3stg_fsdtoix_nx;       // inexact result for flt -> ints
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input           a3stg_fsdtoi_nx;        // inexact result for flt -> 32b ints
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input           a2stg_frac2_63;         // fraction 2 bit[63]- add 2 stage
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input [11:0]     a4stg_exp;              // exponent- add 4 stage
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input           add_of_out_cout;        // fraction rounding adder carry out
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input           a4stg_frac_neq_0;       // fraction != 0- add 4 stage
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input           a4stg_shl_data_neq_0;   // left shift result != 0- add 4 stage
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input           a4stg_frac_dbl_nx;      // inexact double precision result
238
input           a4stg_frac_sng_nx;      // inexact single precision result
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input [5:0]      a1stg_expadd2;          // exponent adder 2 output- add 1 stage
240
input [10:0]     a1stg_expadd4_inv;      // exponent adder 4 output- add 1 stage
241
input           a3stg_denorm;           // denorm output- add 3 stage
242
input           a3stg_denorm_inv;       // result is not a denorm- add 3 stage
243
input           a4stg_denorm_inv;       // 0 the exponent
244
input [10:0]     a3stg_exp;              // exponent- add 3 stage
245
input           a4stg_round;            // round the result- add 4 stage
246
input [5:0]      a3stg_lead0;            // leading 0's count- add 3 stage
247
input           a4stg_rnd_frac_40;      // rounded fraction[40]- add 4 stage
248
input           a4stg_rnd_frac_39;      // rounded fraction[39]- add 4 stage
249
input           a4stg_rnd_frac_11;      // rounded fraction[11]- add 4 stage
250
input           a4stg_rnd_frac_10;      // rounded fraction[10]- add 4 stage
251
input           a4stg_frac_38_0_nx;     // inexact single precision result
252
input           a4stg_frac_9_0_nx;      // inexact double precision result
253
input           arst_l;                 // global asynchronous reset- asserted low
254
input           grst_l;                 // global synchronous reset- asserted low
255
input           rclk;           // global clock
256
 
257
output          add_pipe_active;        // add pipe is executing a valid instr
258
output          a1stg_denorm_sng_in1;   // select line to normalized fraction 1
259
output          a1stg_denorm_dbl_in1;   // select line to normalized fraction 1
260
output          a1stg_denorm_sng_in2;   // select line to normalized fraction 2
261
output          a1stg_denorm_dbl_in2;   // select line to normalized fraction 2
262
output          a1stg_norm_sng_in1;     // select line to normalized fraction 1
263
output          a1stg_norm_dbl_in1;     // select line to normalized fraction 1
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output          a1stg_norm_sng_in2;     // select line to normalized fraction 2
265
output          a1stg_norm_dbl_in2;     // select line to normalized fraction 2
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output          a1stg_step;             // add pipe load
267
output          a1stg_stepa;            // add pipe load- copy
268
output          a1stg_sngop;            // single precision operation- add 1 stg
269
output          a1stg_intlngop;         // integer/long input- add 1 stage
270
output          a1stg_fsdtoix;          // float to integer convert- add 1 stg
271
output          a1stg_fstod;            // fstod- add 1 stage
272
output          a1stg_fstoi;            // fstoi- add 1 stage
273
output          a1stg_fstox;            // fstox- add 1 stage
274
output          a1stg_fdtoi;            // fdtoi- add 1 stage
275
output          a1stg_fdtox;            // fdtox- add 1 stage
276
output          a1stg_faddsubs;         // add/subtract single- add 1 stg
277
output          a1stg_faddsubd;         // add/subtract double- add 1 stg
278
output          a1stg_fdtos;            // fdtos- add 1 stage
279
output          a2stg_faddsubop;        // float add or subtract- add 2 stage
280
output          a2stg_fsdtoix_fdtos;    // float to integer convert- add 2 stg
281
output          a2stg_fitos;            // fitos- add 2 stage
282
output          a2stg_fitod;            // fitod- add 2 stage
283
output          a2stg_fxtos;            // fxtos- add 2 stage
284
output          a2stg_fxtod;            // fxtod- add 2 stage
285
output          a3stg_faddsubop;        // denorm compare lead0[10] input select
286
output [1:0]     a3stg_faddsubopa;       // denorm compare lead0[10] input select
287
output          a4stg_dblop;            // double precision operation- add 4 stg
288
output          a6stg_fadd_in;          // add pipe output request next cycle
289
output [9:0]     add_id_out_in;          // add pipe output ID next cycle
290
output [1:0]     add_fcc_out;            // add pipe input fcc passed through
291
output          a6stg_dbl_dst;          // float double result- add 6 stage
292
output          a6stg_sng_dst;          // float single result- add 6 stage
293
output          a6stg_long_dst;         // 64bit integer result- add 6 stage
294
output          a6stg_int_dst;          // 32bit integer result- add 6 stage
295
output          a6stg_fcmpop;           // compare- add 6 stage
296
output          a6stg_step;             // advance the add pipe
297
output          a3stg_sub_in;           // subtract in main adder- add 3 stage
298
output          add_sign_out;           // add sign output
299
output [1:0]     add_cc_out;             // add pipe result- condition
300
output          a4stg_in_of;            // add overflow- select exp out
301
output [4:0]     add_exc_out;            // add pipe result- exception flags
302
output          a2stg_frac1_in_frac1;   // select line to a2stg_frac1
303
output          a2stg_frac1_in_frac2;   // select line to a2stg_frac1
304
output          a1stg_2nan_in_inv;      // 2 NaN inputs- a1 stage
305
output          a1stg_faddsubop_inv;    // add/subtract- a1 stage
306
output          a2stg_frac1_in_qnan;    // make fraction 1 a QNaN
307
output          a2stg_frac1_in_nv;      // NV- make a new QNaN
308
output          a2stg_frac1_in_nv_dbl;  // NV- make a new double prec QNaN
309
output          a2stg_frac2_in_frac1;   // select line to a2stg_frac2
310
output          a2stg_frac2_in_qnan;    // make fraction 2 a QNaN
311
output [5:0]     a2stg_shr_cnt_in;       // right shift count input- add 1 stage
312
output    a2stg_shr_cnt_5_inv_in; // right shift count input[5]- add 1 stg
313
output          a2stg_shr_frac2_shr_int; // select line to a3stg_frac2
314
output          a2stg_shr_frac2_shr_dbl; // select line to a3stg_frac2
315
output          a2stg_shr_frac2_shr_sng; // select line to a3stg_frac2
316
output          a2stg_shr_frac2_max;    // select line to a3stg_frac2
317
output          a2stg_sub_step;         // select line to a3stg_frac2
318
output          a2stg_fracadd_frac2_inv_in; // sel line to main adder input 2
319
output          a2stg_fracadd_frac2_inv_shr1_in; // sel line to main adder in 2
320
output          a2stg_fracadd_frac2;    // select line to main adder input 2
321
output          a2stg_fracadd_cin_in;   // carry in to main adder- add 1 stage
322
output          a3stg_exp_7ff;          // select line to a3stg_exp
323
output          a3stg_exp_ff;           // select line to a3stg_exp
324
output          a3stg_exp_add;          // select line to a3stg_exp
325
output          a2stg_expdec_neq_0;     // exponent will be < 54
326
output          a3stg_exp10_0_eq0;      // exponent[10:0]==0- add 3 stage
327
output          a3stg_exp10_1_eq0;      // exponent[10:1]==0- add 3 stage
328
output          a3stg_fdtos_inv;        // double to single convert- add 3 stg
329
output          a4stg_fixtos_fxtod_inv; // int to single/double cvt- add 4 stg
330
output          a4stg_rnd_frac_add_inv; // select line to a4stg_rnd_frac
331
output [9:0]     a4stg_shl_cnt_in;       // postnorm shift left count- add 3 stg
332
output          a4stg_rnd_sng;          // round to single precision- add 4 stg
333
output          a4stg_rnd_dbl;          // round to double precision- add 4 stg
334
output          add_frac_out_rndadd;    // select line to add_frac_out
335
output          add_frac_out_rnd_frac;  // select line to add_frac_out
336
output          add_frac_out_shl;       // select line to add_frac_out
337
output          a4stg_to_0;             // result to max finite on overflow
338
output          add_exp_out_expinc;     // select line to add_exp_out
339
output          add_exp_out_exp;        // select line to add_exp_out
340
output          add_exp_out_exp1;       // select line to add_exp_out
341
output          add_exp_out_expadd;     // select line to add_exp_out
342
output          a4stg_to_0_inv;         // result to infinity on overflow
343
 
344
input           se;                     // scan_enable
345
input           si;                     // scan in
346
output          so;                     // scan out
347
 
348
 
349
wire            reset;
350
wire            a1stg_in1_51;
351
wire            a1stg_in1_54;
352
wire            a1stg_in1_63;
353
wire            a1stg_in1_50_0_neq_0;
354
wire            a1stg_in1_53_32_neq_0;
355
wire            a1stg_in1_exp_eq_0;
356
wire            a1stg_in1_exp_neq_ffs;
357
wire            a1stg_in2_51;
358
wire            a1stg_in2_54;
359
wire            a1stg_in2_63;
360
wire            a1stg_in2_50_0_neq_0;
361
wire            a1stg_in2_53_32_neq_0;
362
wire            a1stg_in2_exp_eq_0;
363
wire            a1stg_in2_exp_neq_ffs;
364
wire            a1stg_denorm_sng_in1;
365
wire            a1stg_denorm_dbl_in1;
366
wire            a1stg_denorm_sng_in2;
367
wire            a1stg_denorm_dbl_in2;
368
wire            a1stg_norm_sng_in1;
369
wire            a1stg_norm_dbl_in1;
370
wire            a1stg_norm_sng_in2;
371
wire            a1stg_norm_dbl_in2;
372
wire            a1stg_snan_sng_in1;
373
wire            a1stg_snan_dbl_in1;
374
wire            a1stg_snan_sng_in2;
375
wire            a1stg_snan_dbl_in2;
376
wire            a1stg_qnan_sng_in1;
377
wire            a1stg_qnan_dbl_in1;
378
wire            a1stg_qnan_sng_in2;
379
wire            a1stg_qnan_dbl_in2;
380
wire            a1stg_snan_in1;
381
wire            a1stg_snan_in2;
382
wire            a1stg_qnan_in1;
383
wire            a1stg_qnan_in2;
384
wire            a1stg_nan_sng_in1;
385
wire            a1stg_nan_dbl_in1;
386
wire            a1stg_nan_sng_in2;
387
wire            a1stg_nan_dbl_in2;
388
wire            a1stg_nan_in1;
389
wire            a1stg_nan_in2;
390
wire            a1stg_nan_in;
391
wire            a1stg_2nan_in;
392
wire            a1stg_inf_sng_in1;
393
wire            a1stg_inf_dbl_in1;
394
wire            a1stg_inf_sng_in2;
395
wire            a1stg_inf_dbl_in2;
396
wire            a1stg_inf_in1;
397
wire            a1stg_inf_in2;
398
wire            a1stg_2inf_in;
399
wire            a1stg_infnan_sng_in1;
400
wire            a1stg_infnan_dbl_in1;
401
wire            a1stg_infnan_sng_in2;
402
wire            a1stg_infnan_dbl_in2;
403
wire            a1stg_infnan_in1;
404
wire            a1stg_infnan_in2;
405
wire            a1stg_infnan_in;
406
wire            a1stg_2zero_in;
407
wire            a1stg_step;
408
wire            a1stg_stepa;
409
wire [7:0]       a1stg_op_in;
410
wire [7:0]       a1stg_op;
411
wire            a1stg_sngop;
412
wire [3:0]       a1stg_sngopa;
413
wire            a1stg_dblop;
414
wire [3:0]       a1stg_dblopa;
415
wire [1:0]       a1stg_rnd_mode;
416
wire [4:0]       a1stg_id;
417
wire [1:0]       a1stg_fcc;
418
wire            a1stg_fadd;
419
wire            a1stg_dbl_dst;
420
wire            a1stg_sng_dst;
421
wire            a1stg_long_dst;
422
wire            a1stg_int_dst;
423
wire            a1stg_intlngop;
424
wire            a1stg_faddsubop;
425
wire            a1stg_fsubop;
426
wire            a1stg_fsdtox;
427
wire            a1stg_fcmpesd;
428
wire            a1stg_fcmpsd;
429
wire            a1stg_faddsub_dtosop;
430
wire            a1stg_fdtoix;
431
wire            a1stg_fstoix;
432
wire            a1stg_fsdtoix;
433
wire            a1stg_fixtosd;
434
wire            a1stg_fstod;
435
wire            a1stg_fstoi;
436
wire            a1stg_fstox;
437
wire            a1stg_fdtoi;
438
wire            a1stg_fdtox;
439
wire            a1stg_fsdtoix_fdtos;
440
wire            a1stg_fitos;
441
wire            a1stg_fitod;
442
wire            a1stg_fxtos;
443
wire            a1stg_fcmpop;
444
wire            a1stg_f4cycop;
445
wire            a1stg_fixtos_fxtod;
446
wire            a1stg_faddsubs_fdtos;
447
wire            a1stg_faddsubs;
448
wire            a1stg_faddsubd;
449
wire            a1stg_fdtos;
450
wire            a1stg_fistod;
451
wire            a1stg_fixtos;
452
wire            a1stg_fxtod;
453
wire            a1stg_opdec_36;
454
wire [34:28]    a1stg_opdec;
455
wire [3:0]      a1stg_opdec_24_21;
456
wire [8:0]      a1stg_opdec_19_11;
457
wire [9:0]      a1stg_opdec_9_0;
458
wire            fixtosd_hold;
459
wire [30:0]      a2stg_opdec_in;
460
wire            a2stg_opdec_36;
461
wire [34:28]    a2stg_opdec;
462
wire [3:0]      a2stg_opdec_24_21;
463
wire [8:0]      a2stg_opdec_19_11;
464
wire [9:0]      a2stg_opdec_9_0;
465
wire [1:0]       a2stg_rnd_mode;
466
wire [4:0]       a2stg_id;
467
wire [1:0]       a2stg_fcc;
468
wire            a2stg_fadd;
469
wire            a2stg_long_dst;
470
wire            a2stg_faddsubop;
471
wire            a2stg_fsubop;
472
wire            a2stg_faddsub_dtosop;
473
wire            a2stg_fdtoix;
474
wire            a2stg_fstoix;
475
wire            a2stg_fsdtoix;
476
wire            a2stg_fstod;
477
wire            a2stg_fstoi;
478
wire            a2stg_fstox;
479
wire            a2stg_fdtoi;
480
wire            a2stg_fdtox;
481
wire            a2stg_fsdtoix_fdtos;
482
wire            a2stg_fitos;
483
wire            a2stg_fitod;
484
wire            a2stg_fxtos;
485
wire            a2stg_fcmpop;
486
wire            a2stg_fixtos_fxtod;
487
wire            a2stg_fdtos;
488
wire            a2stg_fxtod;
489
wire            a3stg_opdec_36;
490
wire [34:29]    a3stg_opdec;
491
wire            a3stg_opdec_24;
492
wire            a3stg_opdec_21;
493
wire [9:0]      a3stg_opdec_9_0;
494
wire [1:0]       a3stg_rnd_mode;
495
wire [4:0]       a3stg_id;
496
wire [1:0]       a3stg_fcc;
497
wire            a3stg_fadd;
498
wire            a3stg_int_dst;
499
wire            a3stg_faddsubop;
500
wire [1:0]       a3stg_faddsubopa;
501
wire            a3stg_fsdtoix;
502
wire            a3stg_f4cycop;
503
wire            a3stg_fixtos_fxtod;
504
wire            a3stg_fdtos;
505
wire            a4stg_opdec_36;
506
wire [34:29]    a4stg_opdec;
507
wire            a4stg_opdec_24;
508
wire            a4stg_opdec_21;
509
wire            a4stg_opdec_9;
510
wire [7:0]      a4stg_opdec_7_0;
511
wire [1:0]       a4stg_rnd_mode_in;
512
wire [1:0]       a4stg_rnd_mode;
513
wire [1:0]       a4stg_rnd_mode2;
514
wire [9:0]       a4stg_id_in;
515
wire [9:0]       a4stg_id;
516
wire [1:0]       a4stg_fcc;
517
wire            a4stg_dblop;
518
wire            a4stg_fadd;
519
wire            a4stg_faddsubop;
520
wire            a4stg_faddsub_dtosop;
521
wire            a4stg_fsdtoix;
522
wire            a4stg_fcmpop;
523
wire            a4stg_fixtos_fxtod;
524
wire            a4stg_faddsubs_fdtos;
525
wire            a4stg_faddsubs;
526
wire            a4stg_faddsubd;
527
wire            a4stg_fdtos;
528
wire            a4stg_fistod;
529
wire [34:30]    a5stg_opdec;
530
wire            a5stg_opdec_9;
531
wire            a5stg_opdec_7;
532
wire            a5stg_opdec_1;
533
wire            a5stg_opdec_0;
534
wire [9:0]       a5stg_id;
535
wire            a5stg_fadd;
536
wire            a5stg_fixtos_fxtod;
537
wire            a5stg_fixtos;
538
wire            a5stg_fxtod;
539
wire [34:30]    a6stg_opdec_in;
540
wire            a6stg_opdec_in_9;
541
wire            a6stg_fadd_in;
542
wire [34:30]    a6stg_opdec;
543
wire            a6stg_opdec_9;
544
wire [9:0]       add_id_out_in;
545
wire [9:0]       add_id_out;
546
wire [1:0]       add_fcc_out_in;
547
wire [1:0]       add_fcc_out;
548
wire            a6stg_fadd;
549
wire            a6stg_dbl_dst;
550
wire            a6stg_sng_dst;
551
wire            a6stg_long_dst;
552
wire            a6stg_int_dst;
553
wire            a6stg_fcmpop;
554
wire            a6stg_hold;
555
wire            a6stg_step;
556
wire            a1stg_sub;
557
wire            a2stg_sign1;
558
wire            a2stg_sign2;
559
wire            a2stg_sub;
560
wire            a2stg_in2_neq_in1_frac;
561
wire            a2stg_in2_gt_in1_frac;
562
wire            a2stg_in2_eq_in1_exp;
563
wire            a2stg_in2_gt_in1_exp;
564
wire            a2stg_nan_in;
565
wire            a2stg_nan_in2;
566
wire            a2stg_snan_in2;
567
wire            a2stg_qnan_in2;
568
wire            a2stg_snan_in1;
569
wire            a2stg_qnan_in1;
570
wire            a2stg_2zero_in;
571
wire            a2stg_2inf_in;
572
wire            a2stg_in2_eq_in1;
573
wire            a2stg_in2_gt_in1;
574
wire            a3stg_sub_in;
575
wire            a2stg_faddsub_sign;
576
wire            a3stg_sign_in;
577
wire            a3stg_sign;
578
wire            a2stg_cc_1;
579
wire            a2stg_cc_0;
580
wire [1:0]       a2stg_cc;
581
wire [1:0]       a3stg_cc;
582
wire            a4stg_sign_in;
583
wire            a4stg_sign;
584
wire            a4stg_sign2;
585
wire [1:0]       a4stg_cc;
586
wire            add_sign_out;
587
wire [1:0]       add_cc_out_in;
588
wire [1:0]       add_cc_out;
589
wire            a1stg_nv;
590
wire            a2stg_nv;
591
wire            a1stg_of_mask;
592
wire            a2stg_of_mask;
593
wire            a3stg_nv_in;
594
wire            a3stg_nv;
595
wire            a3stg_of_mask;
596
wire            a2stg_nx_tmp1;
597
wire            a2stg_nx_tmp2;
598
wire            a2stg_nx_tmp3;
599
wire            a3stg_a2_expadd_11;
600
wire            a3stg_nx_tmp1;
601
wire            a3stg_nx_tmp2;
602
wire            a3stg_nx_tmp3;
603
wire            a3stg_nx;
604
wire            a4stg_nv_in;
605
wire            a4stg_nv;
606
wire            a4stg_nv2;
607
wire            a4stg_of_mask_in;
608
wire            a4stg_of_mask;
609
wire            a4stg_of_mask2;
610
wire            a4stg_nx_in;
611
wire            a4stg_nx;
612
wire            a4stg_nx2;
613
wire            add_nv_out;
614
wire            a4stg_in_of;
615
wire            add_of_out_tmp1_in;
616
wire            add_of_out_tmp1;
617
wire            add_of_out_tmp2;
618
wire            add_of_out;
619
wire            a4stg_uf;
620
wire            add_uf_out;
621
wire            add_nx_out_in;
622
wire            add_nx_out;
623
wire [4:0]       add_exc_out;
624
wire            a2stg_frac1_in_frac1;
625
wire            a2stg_frac1_in_frac2;
626
wire            a1stg_2nan_in_inv;
627
wire            a1stg_faddsubop_inv;
628
wire            a2stg_frac1_in_qnan;
629
wire            a2stg_frac1_in_nv;
630
wire            a2stg_frac1_in_nv_dbl;
631
wire            a2stg_frac2_in_frac1;
632
wire            a2stg_frac2_in_qnan;
633
wire            a1stg_exp_diff_add1;
634
wire            a1stg_exp_diff_add2;
635
wire            a1stg_exp_diff_5;
636
wire [10:0]      a1stg_exp_diff;
637
wire [5:0]       a1stg_clamp63;
638
wire [5:0]       a2stg_shr_cnt_in;
639
wire    a2stg_shr_cnt_5_inv_in;
640
wire            a2stg_shr_frac2_shr_int;
641
wire            a2stg_shr_frac2_shr_dbl;
642
wire            a2stg_shr_frac2_shr_sng;
643
wire            a2stg_shr_frac2_max;
644
wire            a2stg_sub_step;
645
wire            a1stg_faddsub_clamp63_0;
646
wire            a2stg_fracadd_frac2_inv_in;
647
wire            a2stg_fracadd_frac2_inv_shr1_in;
648
wire            a2stg_fracadd_frac2_in;
649
wire            a2stg_fracadd_frac2;
650
wire            a2stg_fracadd_cin_in;
651
wire            a3stg_exp_7ff;
652
wire            a3stg_exp_ff;
653
wire            a3stg_exp_add;
654
wire            a2stg_expdec_neq_0;
655
wire            a3stg_exp10_0_eq0;
656
wire            a3stg_exp10_1_eq0;
657
wire            a3stg_fdtos_inv;
658
wire            a4stg_fixtos_fxtod_inv;
659
wire            a4stg_rnd_frac_add_inv;
660
wire [9:0]       a4stg_shl_cnt_in;
661
wire            a4stg_rnd_sng;
662
wire            a4stg_rnd_dbl;
663
wire            a4stg_rndup_sng;
664
wire            a4stg_rndup_dbl;
665
wire            a4stg_rndup;
666
wire            a5stg_rndup;
667
wire            add_frac_out_rndadd;
668
wire            add_frac_out_rnd_frac;
669
wire            add_frac_out_shl;
670
wire            a4stg_to_0;
671
wire            add_exp_out_expinc;
672
wire            add_exp_out_exp;
673
wire            add_exp_out_exp1;
674
wire            add_exp_out_expadd;
675
wire            a4stg_to_0_inv;
676
wire            add_pipe_active_in;
677
wire            add_pipe_active;
678
 
679
 
680
dffrl_async #(1)  dffrl_add_ctl (
681
  .din  (grst_l),
682
  .clk  (rclk),
683
  .rst_l(arst_l),
684
  .q    (add_ctl_rst_l),
685
        .se (se),
686
        .si (),
687
        .so ()
688
  );
689
 
690
assign reset= (!add_ctl_rst_l);
691
 
692
 
693
///////////////////////////////////////////////////////////////////////////////
694
//
695
//      Add pipeline special input cases.
696
//
697
///////////////////////////////////////////////////////////////////////////////
698
 
699
dffe_s #(1) i_a1stg_in1_51 (
700
        .din    (inq_in1_51),
701
        .en     (a1stg_step),
702
        .clk    (rclk),
703
 
704
        .q      (a1stg_in1_51),
705
 
706
        .se     (se),
707
        .si     (),
708
        .so     ()
709
);
710
 
711
dffe_s #(1) i_a1stg_in1_54 (
712
        .din    (inq_in1_54),
713
        .en     (a1stg_step),
714
        .clk    (rclk),
715
 
716
        .q      (a1stg_in1_54),
717
 
718
        .se     (se),
719
        .si     (),
720
        .so     ()
721
);
722
 
723
dffe_s #(1) i_a1stg_in1_63 (
724
        .din    (inq_in1_63),
725
        .en     (a1stg_step),
726
        .clk    (rclk),
727
 
728
        .q      (a1stg_in1_63),
729
 
730
        .se     (se),
731
        .si     (),
732
        .so     ()
733
);
734
 
735
dffe_s #(1) i_a1stg_in1_50_0_neq_0 (
736
        .din    (inq_in1_50_0_neq_0),
737
        .en     (a1stg_step),
738
        .clk    (rclk),
739
 
740
        .q      (a1stg_in1_50_0_neq_0),
741
 
742
        .se     (se),
743
        .si     (),
744
        .so     ()
745
);
746
 
747
dffe_s #(1) i_a1stg_in1_53_32_neq_0 (
748
        .din    (inq_in1_53_32_neq_0),
749
        .en     (a1stg_step),
750
        .clk    (rclk),
751
 
752
        .q      (a1stg_in1_53_32_neq_0),
753
 
754
        .se     (se),
755
        .si     (),
756
        .so     ()
757
);
758
 
759
dffe_s #(1) i_a1stg_in1_exp_eq_0 (
760
        .din    (inq_in1_exp_eq_0),
761
        .en     (a1stg_step),
762
        .clk    (rclk),
763
 
764
        .q      (a1stg_in1_exp_eq_0),
765
 
766
        .se     (se),
767
        .si     (),
768
        .so     ()
769
);
770
 
771
dffe_s #(1) i_a1stg_in1_exp_neq_ffs (
772
        .din    (inq_in1_exp_neq_ffs),
773
        .en     (a1stg_step),
774
        .clk    (rclk),
775
 
776
        .q      (a1stg_in1_exp_neq_ffs),
777
 
778
        .se     (se),
779
        .si     (),
780
        .so     ()
781
);
782
 
783
dffe_s #(1) i_a1stg_in2_51 (
784
        .din    (inq_in2_51),
785
        .en     (a1stg_step),
786
        .clk    (rclk),
787
 
788
        .q      (a1stg_in2_51),
789
 
790
        .se     (se),
791
        .si     (),
792
        .so     ()
793
);
794
 
795
dffe_s #(1) i_a1stg_in2_54 (
796
        .din    (inq_in2_54),
797
        .en     (a1stg_step),
798
        .clk    (rclk),
799
 
800
        .q      (a1stg_in2_54),
801
 
802
        .se     (se),
803
        .si     (),
804
        .so     ()
805
);
806
 
807
dffe_s #(1) i_a1stg_in2_63 (
808
        .din    (inq_in2_63),
809
        .en     (a1stg_step),
810
        .clk    (rclk),
811
 
812
        .q      (a1stg_in2_63),
813
 
814
        .se     (se),
815
        .si     (),
816
        .so     ()
817
);
818
 
819
dffe_s #(1) i_a1stg_in2_50_0_neq_0 (
820
        .din    (inq_in2_50_0_neq_0),
821
        .en     (a1stg_step),
822
        .clk    (rclk),
823
 
824
        .q      (a1stg_in2_50_0_neq_0),
825
 
826
        .se     (se),
827
        .si     (),
828
        .so     ()
829
);
830
 
831
dffe_s #(1) i_a1stg_in2_53_32_neq_0 (
832
        .din    (inq_in2_53_32_neq_0),
833
        .en     (a1stg_step),
834
        .clk    (rclk),
835
 
836
        .q      (a1stg_in2_53_32_neq_0),
837
 
838
        .se     (se),
839
        .si     (),
840
        .so     ()
841
);
842
 
843
dffe_s #(1) i_a1stg_in2_exp_eq_0 (
844
        .din    (inq_in2_exp_eq_0),
845
         .en    (a1stg_step),
846
        .clk    (rclk),
847
 
848
        .q      (a1stg_in2_exp_eq_0),
849
 
850
        .se     (se),
851
        .si     (),
852
        .so     ()
853
);
854
 
855
dffe_s #(1) i_a1stg_in2_exp_neq_ffs (
856
        .din    (inq_in2_exp_neq_ffs),
857
        .en     (a1stg_step),
858
        .clk    (rclk),
859
 
860
        .q      (a1stg_in2_exp_neq_ffs),
861
 
862
        .se     (se),
863
        .si     (),
864
        .so     ()
865
);
866
 
867
 
868
///////////////////////////////////////////////////////////////////////////////
869
//
870
//      Denorm add inputs.
871
//
872
///////////////////////////////////////////////////////////////////////////////
873
 
874
assign a1stg_denorm_sng_in1= a1stg_in1_exp_eq_0 && a1stg_sngopa[0];
875
 
876
assign a1stg_denorm_dbl_in1= a1stg_in1_exp_eq_0 && a1stg_dblopa[0];
877
 
878
assign a1stg_denorm_sng_in2= a1stg_in2_exp_eq_0 && a1stg_sngopa[0];
879
 
880
assign a1stg_denorm_dbl_in2= a1stg_in2_exp_eq_0 && a1stg_dblopa[0];
881
 
882
 
883
///////////////////////////////////////////////////////////////////////////////
884
//
885
//      Non-denorm add inputs.
886
//
887
///////////////////////////////////////////////////////////////////////////////
888
 
889
assign a1stg_norm_sng_in1= (!a1stg_in1_exp_eq_0) && a1stg_sngopa[0];
890
 
891
assign a1stg_norm_dbl_in1= (!a1stg_in1_exp_eq_0) && a1stg_dblopa[0];
892
 
893
assign a1stg_norm_sng_in2= (!a1stg_in2_exp_eq_0) && a1stg_sngopa[0];
894
 
895
assign a1stg_norm_dbl_in2= (!a1stg_in2_exp_eq_0) && a1stg_dblopa[0];
896
 
897
 
898
///////////////////////////////////////////////////////////////////////////////
899
//
900
//      Nan add inputs.
901
//
902
///////////////////////////////////////////////////////////////////////////////
903
 
904
assign a1stg_snan_sng_in1= (!a1stg_in1_exp_neq_ffs) && (!a1stg_in1_54)
905
                && a1stg_in1_53_32_neq_0 && a1stg_sngopa[1];
906
 
907
assign a1stg_snan_dbl_in1= (!a1stg_in1_exp_neq_ffs) && (!a1stg_in1_51)
908
                && a1stg_in1_50_0_neq_0 && a1stg_dblopa[1];
909
 
910
assign a1stg_snan_sng_in2= (!a1stg_in2_exp_neq_ffs) && (!a1stg_in2_54)
911
                && a1stg_in2_53_32_neq_0 && a1stg_sngopa[1];
912
 
913
assign a1stg_snan_dbl_in2= (!a1stg_in2_exp_neq_ffs) && (!a1stg_in2_51)
914
                && a1stg_in2_50_0_neq_0 && a1stg_dblopa[1];
915
 
916
assign a1stg_qnan_sng_in1= (!a1stg_in1_exp_neq_ffs) && a1stg_in1_54
917
                && a1stg_sngopa[1];
918
 
919
assign a1stg_qnan_dbl_in1= (!a1stg_in1_exp_neq_ffs) && a1stg_in1_51
920
                && a1stg_dblopa[1];
921
 
922
assign a1stg_qnan_sng_in2= (!a1stg_in2_exp_neq_ffs) && a1stg_in2_54
923
                && a1stg_sngopa[1];
924
 
925
assign a1stg_qnan_dbl_in2= (!a1stg_in2_exp_neq_ffs) && a1stg_in2_51
926
                && a1stg_dblopa[1];
927
 
928
assign a1stg_snan_in1= a1stg_snan_sng_in1 || a1stg_snan_dbl_in1;
929
 
930
assign a1stg_snan_in2= a1stg_snan_sng_in2 || a1stg_snan_dbl_in2;
931
 
932
assign a1stg_qnan_in1= a1stg_qnan_sng_in1 || a1stg_qnan_dbl_in1;
933
 
934
assign a1stg_qnan_in2= a1stg_qnan_sng_in2 || a1stg_qnan_dbl_in2;
935
 
936
assign a1stg_nan_sng_in1= (!a1stg_in1_exp_neq_ffs)
937
                && (a1stg_in1_54 || a1stg_in1_53_32_neq_0)
938
                && a1stg_sngopa[2];
939
 
940
assign a1stg_nan_dbl_in1= (!a1stg_in1_exp_neq_ffs)
941
                && (a1stg_in1_51 || a1stg_in1_50_0_neq_0)
942
                && a1stg_dblopa[2];
943
 
944
assign a1stg_nan_sng_in2= (!a1stg_in2_exp_neq_ffs)
945
                && (a1stg_in2_54 || a1stg_in2_53_32_neq_0)
946
                && a1stg_sngopa[2];
947
 
948
assign a1stg_nan_dbl_in2= (!a1stg_in2_exp_neq_ffs)
949
                && (a1stg_in2_51 || a1stg_in2_50_0_neq_0)
950
                && a1stg_dblopa[2];
951
 
952
assign a1stg_nan_in1= a1stg_nan_sng_in1 || a1stg_nan_dbl_in1;
953
 
954
assign a1stg_nan_in2= a1stg_nan_sng_in2 || a1stg_nan_dbl_in2;
955
 
956
assign a1stg_nan_in= a1stg_nan_in1 || a1stg_nan_in2;
957
 
958
assign a1stg_2nan_in= a1stg_nan_in1 && a1stg_nan_in2;
959
 
960
 
961
///////////////////////////////////////////////////////////////////////////////
962
//
963
//      Infinity add inputs.
964
//
965
///////////////////////////////////////////////////////////////////////////////
966
 
967
assign a1stg_inf_sng_in1= (!a1stg_in1_exp_neq_ffs)
968
                && (!a1stg_in1_54) && (!a1stg_in1_53_32_neq_0)
969
                && a1stg_sngopa[2];
970
 
971
assign a1stg_inf_dbl_in1= (!a1stg_in1_exp_neq_ffs)
972
                && (!a1stg_in1_51) && (!a1stg_in1_50_0_neq_0)
973
                && a1stg_dblopa[2];
974
 
975
assign a1stg_inf_sng_in2= (!a1stg_in2_exp_neq_ffs)
976
                && (!a1stg_in2_54) && (!a1stg_in2_53_32_neq_0)
977
                && a1stg_sngopa[2];
978
 
979
assign a1stg_inf_dbl_in2= (!a1stg_in2_exp_neq_ffs)
980
                && (!a1stg_in2_51) && (!a1stg_in2_50_0_neq_0)
981
                && a1stg_dblopa[2];
982
 
983
assign a1stg_inf_in1= a1stg_inf_sng_in1 || a1stg_inf_dbl_in1;
984
 
985
assign a1stg_inf_in2= a1stg_inf_sng_in2 || a1stg_inf_dbl_in2;
986
 
987
assign a1stg_2inf_in= a1stg_inf_in1 && a1stg_inf_in2;
988
 
989
 
990
///////////////////////////////////////////////////////////////////////////////
991
//
992
//      Infinity/Nan add inputs.
993
//
994
///////////////////////////////////////////////////////////////////////////////
995
 
996
assign a1stg_infnan_sng_in1= (!a1stg_in1_exp_neq_ffs) && a1stg_sngopa[3];
997
 
998
assign a1stg_infnan_dbl_in1= (!a1stg_in1_exp_neq_ffs) && a1stg_dblopa[3];
999
 
1000
assign a1stg_infnan_sng_in2= (!a1stg_in2_exp_neq_ffs) && a1stg_sngopa[3];
1001
 
1002
assign a1stg_infnan_dbl_in2= (!a1stg_in2_exp_neq_ffs) && a1stg_dblopa[3];
1003
 
1004
assign a1stg_infnan_in1= a1stg_infnan_sng_in1 || a1stg_infnan_dbl_in1;
1005
 
1006
assign a1stg_infnan_in2= a1stg_infnan_sng_in2 || a1stg_infnan_dbl_in2;
1007
 
1008
assign a1stg_infnan_in= a1stg_infnan_in1 || a1stg_infnan_in2;
1009
 
1010
 
1011
///////////////////////////////////////////////////////////////////////////////
1012
//
1013
//      Zero inputs.
1014
//
1015
///////////////////////////////////////////////////////////////////////////////
1016
 
1017
// Austin update
1018
// correctly detect case where both single precision operands are zero
1019
 
1020
// assign a1stg_2zero_in= a1stg_in1_exp_eq_0 && (!a1stg_in1_51)
1021
//              && (!a1stg_in1_50_0_neq_0)
1022
//              && a1stg_in2_exp_eq_0 && (!a1stg_in2_51)
1023
//              && (!a1stg_in2_50_0_neq_0);
1024
 
1025
assign a1stg_2zero_in =
1026
 
1027
                a1stg_in1_exp_eq_0                          &&
1028
                (!a1stg_in1_54          || a1stg_dblopa[3]) &&  // (!bit54          ) || dp
1029
                (!a1stg_in1_53_32_neq_0 || a1stg_dblopa[3]) &&  // (!bit53 && !bit52) || dp
1030
                (!a1stg_in1_51)                             &&
1031
                (!a1stg_in1_50_0_neq_0)                     &&
1032
 
1033
                a1stg_in2_exp_eq_0                          &&
1034
                (!a1stg_in2_54          || a1stg_dblopa[3]) &&  // (!bit54          ) || dp
1035
                (!a1stg_in2_53_32_neq_0 || a1stg_dblopa[3]) &&  // (!bit53 && !bit52) || dp
1036
                (!a1stg_in2_51)                             &&
1037
                (!a1stg_in2_50_0_neq_0);
1038
 
1039
 
1040
///////////////////////////////////////////////////////////////////////////////
1041
//
1042
//      Floating point add control pipeline.
1043
//
1044
///////////////////////////////////////////////////////////////////////////////
1045
 
1046
///////////////////////////////////////////////////////////////////////////////
1047
//
1048
//      Opcode pipeline- add input stage.
1049
//
1050
///////////////////////////////////////////////////////////////////////////////
1051
 
1052
assign a1stg_step= (!fixtosd_hold) && (!a6stg_hold);
1053
 
1054
assign a1stg_stepa= a1stg_step;
1055
 
1056
assign a1stg_op_in[7:0]= ({8{inq_add}}
1057
                            & inq_op[7:0]);
1058
 
1059
dffre_s #(8) i_a1stg_op (
1060
        .din    (a1stg_op_in[7:0]),
1061
        .en     (a1stg_step),
1062
        .rst    (reset),
1063
        .clk    (rclk),
1064
 
1065
        .q      (a1stg_op[7:0]),
1066
 
1067
        .se     (se),
1068
        .si     (),
1069
        .so     ()
1070
);
1071
 
1072
dffe_s #(1) i_a1stg_sngop (
1073
        .din    (inq_op[0]),
1074
        .en     (a1stg_step),
1075
        .clk    (rclk),
1076
 
1077
        .q      (a1stg_sngop),
1078
 
1079
        .se     (se),
1080
        .si     (),
1081
        .so     ()
1082
);
1083
 
1084
dffe_s #(4) i_a1stg_sngopa (
1085
        .din    ({4{inq_op[0]}}),
1086
        .en     (a1stg_step),
1087
        .clk    (rclk),
1088
 
1089
        .q      (a1stg_sngopa[3:0]),
1090
 
1091
        .se     (se),
1092
        .si     (),
1093
        .so     ()
1094
);
1095
 
1096
dffe_s #(1) i_a1stg_dblop (
1097
        .din    (inq_op[1]),
1098
        .en     (a1stg_step),
1099
        .clk    (rclk),
1100
 
1101
        .q      (a1stg_dblop),
1102
 
1103
        .se     (se),
1104
        .si     (),
1105
        .so     ()
1106
);
1107
 
1108
dffe_s #(4) i_a1stg_dblopa (
1109
        .din    ({4{inq_op[1]}}),
1110
        .en     (a1stg_step),
1111
        .clk    (rclk),
1112
 
1113
        .q      (a1stg_dblopa[3:0]),
1114
 
1115
        .se     (se),
1116
        .si     (),
1117
        .so     ()
1118
);
1119
 
1120
dffe_s #(2) i_a1stg_rnd_mode (
1121
        .din    (inq_rnd_mode[1:0]),
1122
        .en     (a1stg_step),
1123
        .clk    (rclk),
1124
 
1125
        .q      (a1stg_rnd_mode[1:0]),
1126
 
1127
        .se     (se),
1128
        .si     (),
1129
        .so     ()
1130
);
1131
 
1132
dffe_s #(5) i_a1stg_id (
1133
        .din    (inq_id[4:0]),
1134
        .en     (a1stg_step),
1135
        .clk    (rclk),
1136
 
1137
        .q      (a1stg_id[4:0]),
1138
 
1139
        .se     (se),
1140
        .si     (),
1141
        .so     ()
1142
);
1143
 
1144
dffe_s #(2) i_a1stg_fcc (
1145
        .din    (inq_fcc[1:0]),
1146
        .en     (a1stg_step),
1147
        .clk    (rclk),
1148
 
1149
        .q      (a1stg_fcc[1:0]),
1150
 
1151
        .se     (se),
1152
        .si     (),
1153
        .so     ()
1154
);
1155
 
1156
 
1157
///////////////////////////////////////////////////////////////////////////////
1158
//
1159
//      Opcode decode- add stage 1.
1160
//
1161
///////////////////////////////////////////////////////////////////////////////
1162
 
1163
assign a1stg_fadd= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FADDD)
1164
                || (a1stg_op[7:0]==FSUBS) || (a1stg_op[7:0]==FSUBD)
1165
                || (a1stg_op[7:0]==FCMPES) || (a1stg_op[7:0]==FCMPED)
1166
                || (a1stg_op[7:0]==FCMPS) || (a1stg_op[7:0]==FCMPD)
1167
                || (a1stg_op[7:0]==FITOS) || (a1stg_op[7:0]==FITOD)
1168
                || (a1stg_op[7:0]==FXTOS) || (a1stg_op[7:0]==FXTOD)
1169
                || (a1stg_op[7:0]==FSTOI) || (a1stg_op[7:0]==FSTOX)
1170
                || (a1stg_op[7:0]==FDTOI) || (a1stg_op[7:0]==FDTOX)
1171
                || (a1stg_op[7:0]==FSTOD) || (a1stg_op[7:0]==FDTOS);
1172
 
1173
assign a1stg_dbl_dst= (a1stg_op[7:0]==FADDD) || (a1stg_op[7:0]==FSUBD)
1174
                || (a1stg_op[7:0]==FITOD) || (a1stg_op[7:0]==FXTOD)
1175
                || (a1stg_op[7:0]==FSTOD);
1176
 
1177
assign a1stg_sng_dst= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FSUBS)
1178
                || (a1stg_op[7:0]==FITOS) || (a1stg_op[7:0]==FXTOS)
1179
                || (a1stg_op[7:0]==FDTOS);
1180
 
1181
assign a1stg_long_dst= (a1stg_op[7:0]==FSTOX) || (a1stg_op[7:0]==FDTOX);
1182
 
1183
assign a1stg_int_dst= (a1stg_op[7:0]==FSTOI) || (a1stg_op[7:0]==FDTOI);
1184
 
1185
assign a1stg_intlngop= (!(a1stg_sngopa[3] || a1stg_dblop));
1186
 
1187
assign a1stg_faddsubop= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FADDD)
1188
                || (a1stg_op[7:0]==FSUBS) || (a1stg_op[7:0]==FSUBD);
1189
 
1190
assign a1stg_fsubop= (a1stg_op[7:0]==FSUBS) || (a1stg_op[7:0]==FSUBD);
1191
 
1192
assign a1stg_fsdtox= (a1stg_op[7:0]==FSTOX) || (a1stg_op[7:0]==FDTOX);
1193
 
1194
assign a1stg_fcmpesd= (a1stg_op[7:0]==FCMPES) || (a1stg_op[7:0]==FCMPED);
1195
 
1196
assign a1stg_fcmpsd= (a1stg_op[7:0]==FCMPS) || (a1stg_op[7:0]==FCMPD);
1197
 
1198
assign a1stg_faddsub_dtosop= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FADDD)
1199
                || (a1stg_op[7:0]==FSUBS) || (a1stg_op[7:0]==FSUBD)
1200
                || (a1stg_op[7:0]==FDTOS);
1201
 
1202
assign a1stg_fdtoix= (a1stg_op[7:0]==FDTOI) || (a1stg_op[7:0]==FDTOX);
1203
 
1204
assign a1stg_fstoix= (a1stg_op[7:0]==FSTOI) || (a1stg_op[7:0]==FSTOX);
1205
 
1206
assign a1stg_fsdtoix= (a1stg_op[7:0]==FSTOI) || (a1stg_op[7:0]==FSTOX)
1207
                || (a1stg_op[7:0]==FDTOI) || (a1stg_op[7:0]==FDTOX);
1208
 
1209
assign a1stg_fixtosd= (a1stg_op[7:0]==FITOS) || (a1stg_op[7:0]==FITOD)
1210
                || (a1stg_op[7:0]==FXTOS) || (a1stg_op[7:0]==FXTOD);
1211
 
1212
assign a1stg_fstod= (a1stg_op[7:0]==FSTOD);
1213
 
1214
assign a1stg_fstoi= (a1stg_op[7:0]==FSTOI);
1215
 
1216
assign a1stg_fstox= (a1stg_op[7:0]==FSTOX);
1217
 
1218
assign a1stg_fdtoi= (a1stg_op[7:0]==FDTOI);
1219
 
1220
assign a1stg_fdtox= (a1stg_op[7:0]==FDTOX);
1221
 
1222
assign a1stg_fsdtoix_fdtos= (a1stg_op[7:0]==FSTOI) || (a1stg_op[7:0]==FSTOX)
1223
                || (a1stg_op[7:0]==FDTOI) || (a1stg_op[7:0]==FDTOX)
1224
                || (a1stg_op[7:0]==FDTOS);
1225
 
1226
assign a1stg_fitos= (a1stg_op[7:0]==FITOS);
1227
 
1228
assign a1stg_fitod= (a1stg_op[7:0]==FITOD);
1229
 
1230
assign a1stg_fxtos= (a1stg_op[7:0]==FXTOS);
1231
 
1232
assign a1stg_fcmpop= (a1stg_op[7:0]==FCMPS) || (a1stg_op[7:0]==FCMPD)
1233
                || (a1stg_op[7:0]==FCMPES) || (a1stg_op[7:0]==FCMPED);
1234
 
1235
assign a1stg_f4cycop= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FADDD)
1236
                || (a1stg_op[7:0]==FSUBS) || (a1stg_op[7:0]==FSUBD)
1237
                || (a1stg_op[7:0]==FDTOS) || (a1stg_op[7:0]==FSTOD)
1238
                || (a1stg_op[7:0]==FITOD);
1239
 
1240
assign a1stg_fixtos_fxtod= (a1stg_op[7:0]==FITOS) || (a1stg_op[7:0]==FXTOS)
1241
                || (a1stg_op[7:0]==FXTOD);
1242
 
1243
assign a1stg_faddsubs_fdtos= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FSUBS)
1244
                || (a1stg_op[7:0]==FDTOS);
1245
 
1246
assign a1stg_faddsubs= (a1stg_op[7:0]==FADDS) || (a1stg_op[7:0]==FSUBS);
1247
 
1248
assign a1stg_faddsubd= (a1stg_op[7:0]==FADDD) || (a1stg_op[7:0]==FSUBD);
1249
 
1250
assign a1stg_fdtos= (a1stg_op[7:0]==FDTOS);
1251
 
1252
assign a1stg_fistod= (a1stg_op[7:0]==FITOD) || (a1stg_op[7:0]==FSTOD);
1253
 
1254
assign a1stg_fixtos= (a1stg_op[7:0]==FITOS) || (a1stg_op[7:0]==FXTOS);
1255
 
1256
assign a1stg_fxtod= (a1stg_op[7:0]==FXTOD);
1257
 
1258
assign a1stg_opdec_36 = a1stg_dblop;
1259
 
1260
assign a1stg_opdec[34:28] =
1261
                         {a1stg_fadd,
1262
                          a1stg_dbl_dst,
1263
                          a1stg_sng_dst,
1264
                          a1stg_long_dst,
1265
                          a1stg_int_dst,
1266
                          a1stg_faddsubop,
1267
                          a1stg_fsubop};
1268
 
1269
assign a1stg_opdec_24_21[3:0] =
1270
                         {a1stg_faddsub_dtosop,
1271
                          a1stg_fdtoix,
1272
                          a1stg_fstoix,
1273
                          a1stg_fsdtoix};
1274
 
1275
assign a1stg_opdec_19_11[8:0] =
1276
                         {a1stg_fstod,
1277
                          a1stg_fstoi,
1278
                          a1stg_fstox,
1279
                          a1stg_fdtoi,
1280
                          a1stg_fdtox,
1281
                          a1stg_fsdtoix_fdtos,
1282
                          a1stg_fitos,
1283
                          a1stg_fitod,
1284
                          a1stg_fxtos};
1285
 
1286
assign a1stg_opdec_9_0[9:0] =
1287
                         {a1stg_fcmpop,
1288
                          a1stg_f4cycop,
1289
                          a1stg_fixtos_fxtod,
1290
                          a1stg_faddsubs_fdtos,
1291
                          a1stg_faddsubs,
1292
                          a1stg_faddsubd,
1293
                          a1stg_fdtos,
1294
                          a1stg_fistod,
1295
                          a1stg_fixtos,
1296
                          a1stg_fxtod};
1297
 
1298
assign fixtosd_hold= a2stg_fixtos_fxtod
1299
                && (!(a1stg_op[7] && (!a1stg_op[1]) && (!a1stg_op[0])
1300
                        && (a1stg_op[2] || (!a1stg_op[6]))));
1301
 
1302
assign a2stg_opdec_in[30:0]= {31{(!fixtosd_hold)}}
1303
                            & {a1stg_opdec_36, a1stg_opdec[34:28],
1304
                               a1stg_opdec_24_21[3:0], a1stg_opdec_19_11[8:0],
1305
                               a1stg_opdec_9_0[9:0]};
1306
 
1307
dffre_s #(31) i_a2stg_opdec (
1308
        .din    (a2stg_opdec_in[30:0]),
1309
        .en     (a6stg_step),
1310
        .rst    (reset),
1311
        .clk    (rclk),
1312
 
1313
        .q      ({a2stg_opdec_36, a2stg_opdec[34:28], a2stg_opdec_24_21[3:0],
1314
                  a2stg_opdec_19_11[8:0], a2stg_opdec_9_0[9:0]}),
1315
 
1316
        .se     (se),
1317
        .si     (),
1318
        .so     ()
1319
);
1320
 
1321
dffe_s #(2) i_a2stg_rnd_mode (
1322
        .din    (a1stg_rnd_mode[1:0]),
1323
        .en     (a6stg_step),
1324
        .clk    (rclk),
1325
 
1326
        .q      (a2stg_rnd_mode[1:0]),
1327
 
1328
        .se     (se),
1329
        .si     (),
1330
        .so     ()
1331
);
1332
 
1333
dffe_s #(5) i_a2stg_id (
1334
        .din    (a1stg_id[4:0]),
1335
        .en     (a6stg_step),
1336
        .clk    (rclk),
1337
 
1338
        .q      (a2stg_id[4:0]),
1339
 
1340
        .se     (se),
1341
        .si     (),
1342
        .so     ()
1343
);
1344
 
1345
dffe_s #(2) i_a2stg_fcc (
1346
        .din    (a1stg_fcc[1:0]),
1347
        .en     (a6stg_step),
1348
        .clk    (rclk),
1349
 
1350
        .q      (a2stg_fcc[1:0]),
1351
 
1352
        .se     (se),
1353
        .si     (),
1354
        .so     ()
1355
);
1356
 
1357
 
1358
///////////////////////////////////////////////////////////////////////////////
1359
//
1360
//      Opcode pipeline- add stage 2.
1361
//
1362
///////////////////////////////////////////////////////////////////////////////
1363
 
1364
assign a2stg_fadd= a2stg_opdec[34];
1365
assign a2stg_long_dst= a2stg_opdec[31];
1366
assign a2stg_faddsubop= a2stg_opdec[29];
1367
assign a2stg_fsubop= a2stg_opdec[28];
1368
assign a2stg_faddsub_dtosop= a2stg_opdec_24_21[3];
1369
assign a2stg_fdtoix= a2stg_opdec_24_21[2];
1370
assign a2stg_fstoix= a2stg_opdec_24_21[1];
1371
assign a2stg_fsdtoix= a2stg_opdec_24_21[0];
1372
assign a2stg_fstod= a2stg_opdec_19_11[8];
1373
assign a2stg_fstoi= a2stg_opdec_19_11[7];
1374
assign a2stg_fstox= a2stg_opdec_19_11[6];
1375
assign a2stg_fdtoi= a2stg_opdec_19_11[5];
1376
assign a2stg_fdtox= a2stg_opdec_19_11[4];
1377
assign a2stg_fsdtoix_fdtos= a2stg_opdec_19_11[3];
1378
assign a2stg_fitos= a2stg_opdec_19_11[2];
1379
assign a2stg_fitod= a2stg_opdec_19_11[1];
1380
assign a2stg_fxtos= a2stg_opdec_19_11[0];
1381
assign a2stg_fcmpop= a2stg_opdec_9_0[9];
1382
assign a2stg_fixtos_fxtod= a2stg_opdec_9_0[7];
1383
assign a2stg_fdtos= a2stg_opdec_9_0[3];
1384
assign a2stg_fxtod= a2stg_opdec_9_0[0];
1385
 
1386
dffre_s #(19) i_a3stg_opdec (
1387
        .din    ({a2stg_opdec_36, a2stg_opdec[34:29], a2stg_opdec_24_21[3],
1388
                  a2stg_opdec_24_21[0], a2stg_opdec_9_0[9:0]}),
1389
        .en     (a6stg_step),
1390
        .rst    (reset),
1391
        .clk    (rclk),
1392
 
1393
        .q      ({a3stg_opdec_36, a3stg_opdec[34:29], a3stg_opdec_24,
1394
                  a3stg_opdec_21, a3stg_opdec_9_0[9:0]}),
1395
 
1396
        .se     (se),
1397
        .si     (),
1398
        .so     ()
1399
);
1400
 
1401
dffre_s #(2) i_a3stg_faddsubopa (
1402
        .din    ({2{a2stg_faddsubop}}),
1403
        .en     (a6stg_step),
1404
        .rst    (reset),
1405
        .clk    (rclk),
1406
 
1407
        .q      (a3stg_faddsubopa[1:0]),
1408
 
1409
        .se     (se),
1410
        .si     (),
1411
        .so     ()
1412
);
1413
 
1414
dffe_s #(2) i_a3stg_rnd_mode (
1415
        .din    (a2stg_rnd_mode[1:0]),
1416
        .en     (a6stg_step),
1417
        .clk    (rclk),
1418
 
1419
        .q      (a3stg_rnd_mode[1:0]),
1420
 
1421
        .se     (se),
1422
        .si     (),
1423
        .so     ()
1424
);
1425
 
1426
dffe_s #(5) i_a3stg_id (
1427
        .din    (a2stg_id[4:0]),
1428
        .en     (a6stg_step),
1429
        .clk    (rclk),
1430
 
1431
        .q      (a3stg_id[4:0]),
1432
 
1433
        .se     (se),
1434
        .si     (),
1435
        .so     ()
1436
);
1437
 
1438
dffe_s #(2) i_a3stg_fcc (
1439
        .din    (a2stg_fcc[1:0]),
1440
        .en     (a6stg_step),
1441
        .clk    (rclk),
1442
 
1443
        .q      (a3stg_fcc[1:0]),
1444
 
1445
        .se     (se),
1446
        .si     (),
1447
        .so     ()
1448
);
1449
 
1450
 
1451
///////////////////////////////////////////////////////////////////////////////
1452
//
1453
//      Opcode pipeline- add stage 3.
1454
//
1455
///////////////////////////////////////////////////////////////////////////////
1456
 
1457
assign a3stg_fadd= a3stg_opdec[34];
1458
assign a3stg_int_dst= a3stg_opdec[30];
1459
assign a3stg_faddsubop= a3stg_opdec[29];
1460
assign a3stg_fsdtoix= a3stg_opdec_21;
1461
assign a3stg_f4cycop= a3stg_opdec_9_0[8];
1462
assign a3stg_fixtos_fxtod= a3stg_opdec_9_0[7];
1463
assign a3stg_fdtos= a3stg_opdec_9_0[3];
1464
 
1465
dffre_s #(18) i_a4stg_opdec (
1466
        .din    ({a3stg_opdec_36, a3stg_opdec[34:29], a3stg_opdec_24,
1467
                  a3stg_opdec_21, a3stg_opdec_9_0[9], a3stg_opdec_9_0[7:0]}),
1468
        .en     (a6stg_step),
1469
        .rst    (reset),
1470
        .clk    (rclk),
1471
 
1472
        .q      ({a4stg_opdec_36, a4stg_opdec[34:29], a4stg_opdec_24,
1473
                  a4stg_opdec_21, a4stg_opdec_9, a4stg_opdec_7_0[7:0]}),
1474
 
1475
        .se     (se),
1476
        .si     (),
1477
        .so     ()
1478
);
1479
 
1480
assign a4stg_rnd_mode_in[1:0]= ({2{a3stg_f4cycop}}
1481
                            & a3stg_rnd_mode[1:0])
1482
                | ({2{(!a3stg_f4cycop)}}
1483
                            & a4stg_rnd_mode2[1:0]);
1484
 
1485
dffe_s #(2) i_a4stg_rnd_mode (
1486
        .din    (a4stg_rnd_mode_in[1:0]),
1487
        .en     (a6stg_step),
1488
        .clk    (rclk),
1489
 
1490
        .q      (a4stg_rnd_mode[1:0]),
1491
 
1492
        .se     (se),
1493
        .si     (),
1494
        .so     ()
1495
);
1496
 
1497
dffe_s #(2) i_a4stg_rnd_mode2 (
1498
        .din    (a3stg_rnd_mode[1:0]),
1499
        .en     (a6stg_step),
1500
        .clk    (rclk),
1501
 
1502
        .q      (a4stg_rnd_mode2[1:0]),
1503
 
1504
        .se     (se),
1505
        .si     (),
1506
        .so     ()
1507
);
1508
 
1509
assign a4stg_id_in[9:0]= {(a3stg_id[4:2]==3'o7),
1510
                                (a3stg_id[4:2]==3'o6),
1511
                                (a3stg_id[4:2]==3'o5),
1512
                                (a3stg_id[4:2]==3'o4),
1513
                                (a3stg_id[4:2]==3'o3),
1514
                                (a3stg_id[4:2]==3'o2),
1515
                                (a3stg_id[4:2]==3'o1),
1516
                                (a3stg_id[4:2]==3'o0),
1517
                                a3stg_id[1:0]};
1518
 
1519
dffe_s #(10) i_a4stg_id (
1520
        .din    (a4stg_id_in[9:0]),
1521
        .en     (a6stg_step),
1522
        .clk    (rclk),
1523
 
1524
        .q      (a4stg_id[9:0]),
1525
 
1526
        .se     (se),
1527
        .si     (),
1528
        .so     ()
1529
);
1530
 
1531
dffe_s #(2) i_a4stg_fcc (
1532
        .din    (a3stg_fcc[1:0]),
1533
        .en     (a6stg_step),
1534
        .clk    (rclk),
1535
 
1536
        .q      (a4stg_fcc[1:0]),
1537
 
1538
        .se     (se),
1539
        .si     (),
1540
        .so     ()
1541
);
1542
 
1543
 
1544
///////////////////////////////////////////////////////////////////////////////
1545
//
1546
//      Opcode pipeline- add stages 4 and 5.
1547
//
1548
///////////////////////////////////////////////////////////////////////////////
1549
 
1550
assign a4stg_dblop= a4stg_opdec_36;
1551
assign a4stg_fadd= a4stg_opdec[34];
1552
assign a4stg_faddsubop= a4stg_opdec[29];
1553
assign a4stg_faddsub_dtosop= a4stg_opdec_24;
1554
assign a4stg_fsdtoix= a4stg_opdec_21;
1555
assign a4stg_fcmpop= a4stg_opdec_9;
1556
assign a4stg_fixtos_fxtod= a4stg_opdec_7_0[7];
1557
assign a4stg_faddsubs_fdtos= a4stg_opdec_7_0[6];
1558
assign a4stg_faddsubs= a4stg_opdec_7_0[5];
1559
assign a4stg_faddsubd= a4stg_opdec_7_0[4];
1560
assign a4stg_fdtos= a4stg_opdec_7_0[3];
1561
assign a4stg_fistod= a4stg_opdec_7_0[2];
1562
 
1563
dffre_s #(9) i_a5stg_opdec (
1564
        .din    ({a4stg_opdec[34:30], a4stg_opdec_9, a4stg_opdec_7_0[7],
1565
                  a4stg_opdec_7_0[1], a4stg_opdec_7_0[0]}),
1566
        .en     (a6stg_step),
1567
        .rst    (reset),
1568
        .clk    (rclk),
1569
 
1570
        .q      ({a5stg_opdec[34:30], a5stg_opdec_9, a5stg_opdec_7,
1571
                  a5stg_opdec_1, a5stg_opdec_0}),
1572
 
1573
        .se     (se),
1574
        .si     (),
1575
        .so     ()
1576
);
1577
 
1578
dffe_s #(10) i_a5stg_id (
1579
        .din    (a4stg_id[9:0]),
1580
        .en     (a6stg_step),
1581
        .clk    (rclk),
1582
 
1583
        .q      (a5stg_id[9:0]),
1584
 
1585
        .se     (se),
1586
        .si     (),
1587
        .so     ()
1588
);
1589
 
1590
assign a5stg_fadd= a5stg_opdec[34];
1591
assign a5stg_fixtos_fxtod= a5stg_opdec_7;
1592
assign a5stg_fixtos= a5stg_opdec_1;
1593
assign a5stg_fxtod= a5stg_opdec_0;
1594
 
1595
assign a6stg_opdec_in[34:30] = ({5{a5stg_fixtos_fxtod}}
1596
                            & a5stg_opdec[34:30])
1597
                | ({5{((!a4stg_fixtos_fxtod) && (!a5stg_fixtos_fxtod))}}
1598
                            & a4stg_opdec[34:30]);
1599
 
1600
assign a6stg_opdec_in_9 = (a5stg_fixtos_fxtod
1601
                            & a5stg_opdec_9)
1602
                | (((!a4stg_fixtos_fxtod) && (!a5stg_fixtos_fxtod))
1603
                            & a4stg_opdec_9);
1604
 
1605
assign a6stg_fadd_in= (a5stg_fixtos_fxtod && a6stg_step && (!reset)
1606
                        && a5stg_fadd)
1607
                || ((!a4stg_fixtos_fxtod) && (!a5stg_fixtos_fxtod)
1608
                        && a6stg_step && (!reset) && a4stg_fadd)
1609
                || ((!a6stg_step) && (!reset) && a6stg_fadd);
1610
 
1611
dffre_s #(6) i_a6stg_opdec (
1612
        .din    ({a6stg_opdec_in[34:30], a6stg_opdec_in_9}),
1613
        .en     (a6stg_step),
1614
        .rst    (reset),
1615
        .clk    (rclk),
1616
 
1617
        .q      ({a6stg_opdec[34:30], a6stg_opdec_9}),
1618
 
1619
        .se     (se),
1620
        .si     (),
1621
        .so     ()
1622
);
1623
 
1624
assign add_id_out_in[9:0]= ({10{((!a5stg_fixtos_fxtod) && a6stg_step)}}
1625
                            & a4stg_id[9:0])
1626
                | ({10{(a5stg_fixtos_fxtod && a6stg_step)}}
1627
                            & a5stg_id[9:0])
1628
                | ({10{(!a6stg_step)}}
1629
                            & add_id_out[9:0]);
1630
 
1631
dff_s #(10) i_add_id_out (
1632
        .din    (add_id_out_in[9:0]),
1633
        .clk    (rclk),
1634
 
1635
        .q      (add_id_out[9:0]),
1636
 
1637
        .se     (se),
1638
        .si     (),
1639
        .so     ()
1640
);
1641
 
1642
assign add_fcc_out_in[1:0]= ({2{a4stg_fcmpop}}
1643
                            & a4stg_fcc);
1644
 
1645
dffe_s #(2) i_add_fcc_out (
1646
        .din    (add_fcc_out_in[1:0]),
1647
        .en     (a6stg_step),
1648
        .clk    (rclk),
1649
 
1650
        .q      (add_fcc_out[1:0]),
1651
 
1652
        .se     (se),
1653
        .si     (),
1654
        .so     ()
1655
);
1656
 
1657
 
1658
///////////////////////////////////////////////////////////////////////////////
1659
//
1660
//      Opcode pipeline- add pipeline output.
1661
//
1662
///////////////////////////////////////////////////////////////////////////////
1663
 
1664
assign a6stg_fadd= a6stg_opdec[34];
1665
assign a6stg_dbl_dst= a6stg_opdec[33];
1666
assign a6stg_sng_dst= a6stg_opdec[32];
1667
assign a6stg_long_dst= a6stg_opdec[31];
1668
assign a6stg_int_dst= a6stg_opdec[30];
1669
assign a6stg_fcmpop= a6stg_opdec_9;
1670
 
1671
assign a6stg_hold= a6stg_fadd && (!add_dest_rdy);
1672
 
1673
assign a6stg_step= (!a6stg_hold);
1674
 
1675
// Austin update
1676
// Power management update
1677
 
1678
assign add_pipe_active_in =  // add pipe is executing a valid instr
1679
   a1stg_fadd || a2stg_fadd || a3stg_fadd || a4stg_fadd || a5stg_fadd || a6stg_fadd;
1680
 
1681
dffre_s #(1) i_add_pipe_active (
1682
        .din    (add_pipe_active_in),
1683
        .en     (1'b1),
1684
        .rst    (reset),
1685
        .clk    (rclk),
1686
 
1687
        .q      (add_pipe_active),
1688
 
1689
        .se     (se),
1690
        .si     (),
1691
        .so     ()
1692
);
1693
 
1694
 
1695
///////////////////////////////////////////////////////////////////////////////
1696
//
1697
//      Add sign and exception logic.
1698
//
1699
///////////////////////////////////////////////////////////////////////////////
1700
 
1701
///////////////////////////////////////////////////////////////////////////////
1702
//
1703
//      Add sign logic.
1704
//
1705
//      Add stage 1.
1706
//
1707
///////////////////////////////////////////////////////////////////////////////
1708
 
1709
assign a1stg_sub= (a1stg_fsubop ^ (a1stg_in1_63 ^ a1stg_in2_63))
1710
                && (!a1stg_fdtos)
1711
                && (!(a1stg_faddsubop && a1stg_nan_in));
1712
 
1713
dffe_s #(1) i_a2stg_sign1 (
1714
        .din    (a1stg_in1_63),
1715
        .en     (a6stg_step),
1716
        .clk    (rclk),
1717
 
1718
        .q      (a2stg_sign1),
1719
 
1720
        .se     (se),
1721
        .si     (),
1722
        .so     ()
1723
);
1724
 
1725
dffe_s #(1) i_a2stg_sign2 (
1726
        .din    (a1stg_in2_63),
1727
        .en     (a6stg_step),
1728
        .clk    (rclk),
1729
 
1730
        .q      (a2stg_sign2),
1731
 
1732
        .se     (se),
1733
        .si     (),
1734
        .so     ()
1735
);
1736
 
1737
dffe_s #(1) i_a2stg_sub (
1738
        .din    (a1stg_sub),
1739
        .en     (a6stg_step),
1740
        .clk    (rclk),
1741
 
1742
        .q      (a2stg_sub),
1743
 
1744
        .se     (se),
1745
        .si     (),
1746
        .so     ()
1747
);
1748
 
1749
dffe_s #(1) i_a2stg_in2_neq_in1_frac (
1750
        .din    (a1stg_in2_neq_in1_frac),
1751
        .en     (a6stg_step),
1752
        .clk    (rclk),
1753
 
1754
        .q      (a2stg_in2_neq_in1_frac),
1755
 
1756
        .se     (se),
1757
        .si     (),
1758
        .so     ()
1759
);
1760
 
1761
dffe_s #(1) i_a2stg_in2_gt_in1_frac (
1762
        .din    (a1stg_in2_gt_in1_frac),
1763
        .en     (a6stg_step),
1764
        .clk    (rclk),
1765
 
1766
        .q      (a2stg_in2_gt_in1_frac),
1767
 
1768
        .se     (se),
1769
        .si     (),
1770
        .so     ()
1771
);
1772
 
1773
dffe_s #(1) i_a2stg_in2_eq_in1_exp (
1774
        .din    (a1stg_in2_eq_in1_exp),
1775
        .en     (a6stg_step),
1776
        .clk    (rclk),
1777
 
1778
        .q      (a2stg_in2_eq_in1_exp),
1779
 
1780
        .se     (se),
1781
        .si     (),
1782
        .so     ()
1783
);
1784
 
1785
dffe_s #(1) i_a2stg_in2_gt_in1_exp (
1786
        .din    (a1stg_expadd1[11]),
1787
        .en     (a6stg_step),
1788
        .clk    (rclk),
1789
 
1790
        .q      (a2stg_in2_gt_in1_exp),
1791
 
1792
        .se     (se),
1793
        .si     (),
1794
        .so     ()
1795
);
1796
 
1797
dffe_s #(1) i_a2stg_nan_in (
1798
        .din    (a1stg_nan_in),
1799
        .en     (a6stg_step),
1800
        .clk    (rclk),
1801
 
1802
        .q      (a2stg_nan_in),
1803
 
1804
        .se     (se),
1805
        .si     (),
1806
        .so     ()
1807
);
1808
 
1809
dffe_s #(1) i_a2stg_nan_in2 (
1810
        .din    (a1stg_nan_in2),
1811
        .en     (a6stg_step),
1812
        .clk    (rclk),
1813
 
1814
        .q      (a2stg_nan_in2),
1815
 
1816
        .se     (se),
1817
        .si     (),
1818
        .so     ()
1819
);
1820
 
1821
dffe_s #(1) i_a2stg_snan_in2 (
1822
        .din    (a1stg_snan_in2),
1823
        .en     (a6stg_step),
1824
        .clk    (rclk),
1825
 
1826
        .q      (a2stg_snan_in2),
1827
 
1828
        .se     (se),
1829
        .si     (),
1830
        .so     ()
1831
);
1832
 
1833
dffe_s #(1) i_a2stg_qnan_in2 (
1834
        .din    (a1stg_qnan_in2),
1835
        .en     (a6stg_step),
1836
        .clk    (rclk),
1837
 
1838
        .q      (a2stg_qnan_in2),
1839
 
1840
        .se     (se),
1841
        .si     (),
1842
        .so     ()
1843
);
1844
 
1845
dffe_s #(1) i_a2stg_snan_in1 (
1846
        .din    (a1stg_snan_in1),
1847
        .en     (a6stg_step),
1848
        .clk    (rclk),
1849
 
1850
        .q      (a2stg_snan_in1),
1851
 
1852
        .se     (se),
1853
        .si     (),
1854
        .so     ()
1855
);
1856
 
1857
dffe_s #(1) i_a2stg_qnan_in1 (
1858
        .din    (a1stg_qnan_in1),
1859
        .en     (a6stg_step),
1860
        .clk    (rclk),
1861
 
1862
        .q      (a2stg_qnan_in1),
1863
 
1864
        .se     (se),
1865
        .si     (),
1866
        .so     ()
1867
);
1868
 
1869
dffe_s #(1) i_a2stg_2zero_in (
1870
        .din    (a1stg_2zero_in),
1871
        .en     (a6stg_step),
1872
        .clk    (rclk),
1873
 
1874
        .q      (a2stg_2zero_in),
1875
 
1876
        .se     (se),
1877
        .si     (),
1878
        .so     ()
1879
);
1880
 
1881
dffe_s #(1) i_a2stg_2inf_in (
1882
        .din    (a1stg_2inf_in),
1883
        .en     (a6stg_step),
1884
        .clk    (rclk),
1885
 
1886
        .q      (a2stg_2inf_in),
1887
 
1888
        .se     (se),
1889
        .si     (),
1890
        .so     ()
1891
);
1892
 
1893
 
1894
///////////////////////////////////////////////////////////////////////////////
1895
//
1896
//      Add sign logic.
1897
//
1898
//      Add stage 2.
1899
//
1900
///////////////////////////////////////////////////////////////////////////////
1901
 
1902
assign a2stg_in2_eq_in1= a2stg_in2_eq_in1_exp && (!a2stg_in2_neq_in1_frac);
1903
 
1904
assign a2stg_in2_gt_in1= a2stg_in2_gt_in1_exp
1905
                || (a2stg_in2_eq_in1_exp && a2stg_in2_neq_in1_frac
1906
                        && a2stg_in2_gt_in1_frac);
1907
 
1908
assign a3stg_sub_in= a2stg_sub
1909
                && (!a2stg_nan_in)
1910
                && (!(a2stg_fsdtoix && (!a2stg_expadd[11])));
1911
 
1912
assign a2stg_faddsub_sign= (a2stg_sign1
1913
                        && (!a2stg_nan_in)
1914
                        && (a2stg_sign2 ^ a2stg_fsubop)
1915
                        && (!(a2stg_2inf_in && a2stg_sub)))
1916
                || (a2stg_sign1
1917
                        && (!a2stg_nan_in)
1918
                        && (!a2stg_in2_eq_in1)
1919
                        && (!a2stg_in2_gt_in1)
1920
                        && (!(a2stg_2inf_in && a2stg_sub)))
1921
                || ((!a2stg_in2_eq_in1)
1922
                        && a2stg_in2_gt_in1
1923
                        && (!a2stg_nan_in)
1924
                        && (a2stg_sign2 ^ a2stg_fsubop)
1925
                        && (!(a2stg_2inf_in && a2stg_sub)))
1926
                || (a2stg_sign2
1927
                        && (a2stg_snan_in2
1928
                                || (a2stg_qnan_in2 && (!a2stg_snan_in1))))
1929
                || (a2stg_sign1
1930
                        && ((a2stg_snan_in1 && (!a2stg_snan_in2))
1931
                                || (a2stg_qnan_in1 && (!a2stg_nan_in2))))
1932
                || ((a2stg_rnd_mode[1:0]==2'b11)
1933
                        && a2stg_in2_eq_in1
1934
                        && (a2stg_sign1 ^ (a2stg_sign2 ^ a2stg_fsubop))
1935
                        && (!a2stg_nan_in)
1936
                        && (!a2stg_2inf_in));
1937
 
1938
assign a3stg_sign_in= (a2stg_faddsubop && a2stg_faddsub_sign)
1939
                || ((!a2stg_faddsubop) && a2stg_sign2);
1940
 
1941
dffe_s #(1) i_a3stg_sign (
1942
        .din    (a3stg_sign_in),
1943
        .en     (a6stg_step),
1944
        .clk    (rclk),
1945
 
1946
        .q      (a3stg_sign),
1947
 
1948
        .se     (se),
1949
        .si     (),
1950
        .so     ()
1951
);
1952
 
1953
assign a2stg_cc_1= ((a2stg_sign2 && (!a2stg_2zero_in) && a2stg_sub)
1954
                        || ((!a2stg_in2_eq_in1) && (!a2stg_sub)
1955
                                && (a2stg_in2_gt_in1 ^ (!a2stg_sign2)))
1956
                        || a2stg_nan_in)
1957
                && a2stg_fcmpop;
1958
 
1959
assign a2stg_cc_0= (((!a2stg_sign2) && (!a2stg_2zero_in) && a2stg_sub)
1960
                        || ((!a2stg_in2_eq_in1) && (!a2stg_sub)
1961
                                && (a2stg_in2_gt_in1 ^ a2stg_sign2))
1962
                        || a2stg_nan_in)
1963
                && a2stg_fcmpop;
1964
 
1965
assign a2stg_cc[1:0]= {a2stg_cc_1, a2stg_cc_0};
1966
 
1967
dffe_s #(2) i_a3stg_cc (
1968
        .din    (a2stg_cc[1:0]),
1969
        .en     (a6stg_step),
1970
        .clk    (rclk),
1971
 
1972
        .q      (a3stg_cc[1:0]),
1973
 
1974
        .se     (se),
1975
        .si     (),
1976
        .so     ()
1977
);
1978
 
1979
 
1980
///////////////////////////////////////////////////////////////////////////////
1981
//
1982
//      Add sign logic.
1983
//
1984
//      Add stage 3.
1985
//
1986
///////////////////////////////////////////////////////////////////////////////
1987
 
1988
assign a4stg_sign_in= (a3stg_f4cycop && a3stg_sign)
1989
                || ((!a3stg_f4cycop) && a4stg_sign2);
1990
 
1991
dffe_s #(1) i_a4stg_sign (
1992
        .din    (a4stg_sign_in),
1993
        .en     (a6stg_step),
1994
        .clk    (rclk),
1995
 
1996
        .q      (a4stg_sign),
1997
 
1998
        .se     (se),
1999
        .si     (),
2000
        .so     ()
2001
);
2002
 
2003
dffe_s #(1) i_a4stg_sign2 (
2004
        .din    (a3stg_sign),
2005
        .en     (a6stg_step),
2006
        .clk    (rclk),
2007
 
2008
        .q      (a4stg_sign2),
2009
 
2010
        .se     (se),
2011
        .si     (),
2012
        .so     ()
2013
);
2014
 
2015
dffe_s #(2) i_a4stg_cc (
2016
        .din    (a3stg_cc[1:0]),
2017
        .en     (a6stg_step),
2018
        .clk    (rclk),
2019
 
2020
        .q      (a4stg_cc[1:0]),
2021
 
2022
        .se     (se),
2023
        .si     (),
2024
        .so     ()
2025
);
2026
 
2027
 
2028
///////////////////////////////////////////////////////////////////////////////
2029
//
2030
//      Add sign logic.
2031
//
2032
//      Add stage 4.
2033
//
2034
///////////////////////////////////////////////////////////////////////////////
2035
 
2036
dffe_s #(1) i_add_sign_out (
2037
        .din    (a4stg_sign),
2038
        .en     (a6stg_step),
2039
        .clk    (rclk),
2040
 
2041
        .q      (add_sign_out),
2042
 
2043
        .se     (se),
2044
        .si     (),
2045
        .so     ()
2046
);
2047
 
2048
assign add_cc_out_in[1:0]= ({2{a4stg_fcmpop}}
2049
                            & a4stg_cc[1:0]);
2050
 
2051
dffe_s #(2) i_add_cc_out (
2052
        .din    (add_cc_out_in[1:0]),
2053
        .en     (a6stg_step),
2054
        .clk    (rclk),
2055
 
2056
        .q      (add_cc_out[1:0]),
2057
 
2058
        .se     (se),
2059
        .si     (),
2060
        .so     ()
2061
);
2062
 
2063
 
2064
///////////////////////////////////////////////////////////////////////////////
2065
//
2066
//      Add exception logic.
2067
//
2068
//      Add stage 1.
2069
//
2070
///////////////////////////////////////////////////////////////////////////////
2071
 
2072
assign a1stg_nv= (a1stg_faddsubop
2073
                        && ((a1stg_2inf_in && a1stg_sub)
2074
                                || a1stg_snan_in1
2075
                                || a1stg_snan_in2))
2076
                || (a1stg_fstod && a1stg_snan_in2)
2077
                || (a1stg_fdtos && a1stg_snan_in2)
2078
                || (a1stg_fcmpesd && a1stg_nan_in)
2079
                || (a1stg_fcmpsd
2080
                        && (a1stg_snan_in1 || a1stg_snan_in2));
2081
 
2082
dffe_s #(1) i_a2stg_nv (
2083
        .din    (a1stg_nv),
2084
        .en     (a6stg_step),
2085
        .clk    (rclk),
2086
 
2087
        .q      (a2stg_nv),
2088
 
2089
        .se     (se),
2090
        .si     (),
2091
        .so     ()
2092
);
2093
 
2094
assign a1stg_of_mask= (!(a1stg_faddsub_dtosop && a1stg_infnan_in));
2095
 
2096
dffe_s #(1) i_a2stg_of_mask (
2097
        .din    (a1stg_of_mask),
2098
        .en     (a6stg_step),
2099
        .clk    (rclk),
2100
 
2101
        .q      (a2stg_of_mask),
2102
 
2103
        .se     (se),
2104
        .si     (),
2105
        .so     ()
2106
);
2107
 
2108
 
2109
///////////////////////////////////////////////////////////////////////////////
2110
//
2111
//      Add exception logic.
2112
//
2113
//      Add stage 2.
2114
//
2115
///////////////////////////////////////////////////////////////////////////////
2116
 
2117
assign a3stg_nv_in= ((!a2stg_expadd[11])
2118
                        && a2stg_fsdtoix
2119
                        && ((!a2stg_sign2)
2120
                                || (|a2stg_expadd[10:0])
2121
                                || a2stg_frac2hi_neq_0
2122
                                || (a2stg_long_dst && a2stg_frac2lo_neq_0)))
2123
                || a2stg_nv;
2124
 
2125
dffe_s #(1) i_a3stg_nv (
2126
        .din    (a3stg_nv_in),
2127
        .en     (a6stg_step),
2128
        .clk    (rclk),
2129
 
2130
        .q      (a3stg_nv),
2131
 
2132
        .se     (se),
2133
        .si     (),
2134
        .so     ()
2135
);
2136
 
2137
dffe_s #(1) i_a3stg_of_mask (
2138
        .din    (a2stg_of_mask),
2139
        .en     (a6stg_step),
2140
        .clk    (rclk),
2141
 
2142
        .q      (a3stg_of_mask),
2143
 
2144
        .se     (se),
2145
        .si     (),
2146
        .so     ()
2147
);
2148
 
2149
assign a2stg_nx_tmp1= (a2stg_fdtoix && (|a2stg_exp[11:10]))
2150
                || (a2stg_fstoix && (|a2stg_exp[11:7]));
2151
 
2152
assign a2stg_nx_tmp2= ((a2stg_fdtoix && (!(|a2stg_exp[11:10])))
2153
                        || (a2stg_fstoix && (!(|a2stg_exp[11:7]))))
2154
                && ((|a2stg_exp[10:1])
2155
                        || a2stg_frac2hi_neq_0
2156
                        || a2stg_frac2lo_neq_0
2157
                        || a2stg_frac2_63);
2158
 
2159
assign a2stg_nx_tmp3= (a2stg_exp[11:0]==12'h41f)
2160
                && a2stg_sign2
2161
                && (!a2stg_frac2hi_neq_0)
2162
                && a2stg_frac2lo_neq_0
2163
                && a2stg_fdtoi;
2164
 
2165
dffe_s #(1) i_a3stg_a2_expadd_11 (
2166
        .din    (a2stg_expadd[11]),
2167
        .en     (a6stg_step),
2168
        .clk    (rclk),
2169
 
2170
        .q      (a3stg_a2_expadd_11),
2171
 
2172
        .se     (se),
2173
        .si     (),
2174
        .so     ()
2175
);
2176
 
2177
dffe_s #(1) i_a3stg_nx_tmp1 (
2178
        .din    (a2stg_nx_tmp1),
2179
        .en     (a6stg_step),
2180
        .clk    (rclk),
2181
 
2182
        .q      (a3stg_nx_tmp1),
2183
 
2184
        .se     (se),
2185
        .si     (),
2186
        .so     ()
2187
);
2188
 
2189
dffe_s #(1) i_a3stg_nx_tmp2 (
2190
        .din    (a2stg_nx_tmp2),
2191
        .en     (a6stg_step),
2192
        .clk    (rclk),
2193
 
2194
        .q      (a3stg_nx_tmp2),
2195
 
2196
        .se     (se),
2197
        .si     (),
2198
        .so     ()
2199
);
2200
 
2201
dffe_s #(1) i_a3stg_nx_tmp3 (
2202
        .din    (a2stg_nx_tmp3),
2203
        .en     (a6stg_step),
2204
        .clk    (rclk),
2205
 
2206
        .q      (a3stg_nx_tmp3),
2207
 
2208
        .se     (se),
2209
        .si     (),
2210
        .so     ()
2211
);
2212
 
2213
 
2214
///////////////////////////////////////////////////////////////////////////////
2215
//
2216
//      Add exception logic.
2217
//
2218
//      Add stage 3.
2219
//
2220
///////////////////////////////////////////////////////////////////////////////
2221
 
2222
assign a3stg_nx= (a3stg_a2_expadd_11
2223
                    && ((a3stg_nx_tmp1
2224
                                && ((a3stg_fsdtoi_nx && a3stg_int_dst)
2225
                                        || a3stg_fsdtoix_nx))
2226
                        || a3stg_nx_tmp2))
2227
                || a3stg_nx_tmp3;
2228
 
2229
assign a4stg_nv_in= ((a3stg_fadd && (!a3stg_fixtos_fxtod))
2230
                        && a3stg_nv)
2231
                || ((!(a3stg_fadd && (!a3stg_fixtos_fxtod)))
2232
                        && a4stg_nv2);
2233
dffe_s #(1) i_a4stg_nv (
2234
        .din    (a4stg_nv_in),
2235
        .en     (a6stg_step),
2236
        .clk    (rclk),
2237
 
2238
        .q      (a4stg_nv),
2239
 
2240
        .se     (se),
2241
        .si     (),
2242
        .so     ()
2243
);
2244
 
2245
dffe_s #(1) i_a4stg_nv2 (
2246
        .din    (a3stg_nv),
2247
        .en     (a6stg_step),
2248
        .clk    (rclk),
2249
 
2250
        .q      (a4stg_nv2),
2251
 
2252
        .se     (se),
2253
        .si     (),
2254
        .so     ()
2255
);
2256
 
2257
assign a4stg_of_mask_in= ((a3stg_fadd && (!a3stg_fixtos_fxtod))
2258
                        && a3stg_of_mask)
2259
                || ((!(a3stg_fadd && (!a3stg_fixtos_fxtod)))
2260
                        && a4stg_of_mask2);
2261
 
2262
dffe_s #(1) i_a4stg_of_mask (
2263
        .din    (a4stg_of_mask_in),
2264
        .en     (a6stg_step),
2265
        .clk    (rclk),
2266
 
2267
        .q      (a4stg_of_mask),
2268
 
2269
        .se     (se),
2270
        .si     (),
2271
        .so     ()
2272
);
2273
 
2274
dffe_s #(1) i_a4stg_of_mask2 (
2275
        .din    (a3stg_of_mask),
2276
        .en     (a6stg_step),
2277
        .clk    (rclk),
2278
 
2279
        .q      (a4stg_of_mask2),
2280
 
2281
        .se     (se),
2282
        .si     (),
2283
        .so     ()
2284
);
2285
 
2286
assign a4stg_nx_in= ((a3stg_fadd && (!a3stg_fixtos_fxtod))
2287
                        && a3stg_nx)
2288
                || ((!(a3stg_fadd && (!a3stg_fixtos_fxtod)))
2289
                        && a4stg_nx2);
2290
 
2291
dffe_s #(1) i_a4stg_nx (
2292
        .din    (a4stg_nx_in),
2293
        .en     (a6stg_step),
2294
        .clk    (rclk),
2295
 
2296
        .q      (a4stg_nx),
2297
 
2298
        .se     (se),
2299
        .si     (),
2300
        .so     ()
2301
);
2302
 
2303
dffe_s #(1) i_a4stg_nx2 (
2304
        .din    (a3stg_nx),
2305
        .en     (a6stg_step),
2306
        .clk    (rclk),
2307
 
2308
        .q      (a4stg_nx2),
2309
 
2310
        .se     (se),
2311
        .si     (),
2312
        .so     ()
2313
);
2314
 
2315
 
2316
///////////////////////////////////////////////////////////////////////////////
2317
//
2318
//      Add exception logic.
2319
//
2320
//      Add stage 4.
2321
//
2322
///////////////////////////////////////////////////////////////////////////////
2323
 
2324
dffe_s #(1) i_add_nv_out (
2325
        .din    (a4stg_nv),
2326
        .en     (a6stg_step),
2327
        .clk    (rclk),
2328
 
2329
        .q      (add_nv_out),
2330
 
2331
        .se     (se),
2332
        .si     (),
2333
        .so     ()
2334
);
2335
 
2336
assign a4stg_in_of= ((a4stg_exp[11] || (&a4stg_exp[10:0]))
2337
                        && a4stg_faddsubd
2338
                        && a4stg_of_mask)
2339
                || (((|a4stg_exp[11:8]) || (&a4stg_exp[7:0]))
2340
                        && a4stg_faddsubs_fdtos
2341
                        && a4stg_of_mask);
2342
 
2343
assign add_of_out_tmp1_in= ((&a4stg_exp[10:1]) && a4stg_rndup && a4stg_round
2344
                        && a4stg_faddsubd
2345
                        && a4stg_of_mask)
2346
                || ((&a4stg_exp[7:1]) && a4stg_rndup
2347
                        && (a4stg_round || a4stg_fdtos)
2348
                        && a4stg_faddsubs_fdtos
2349
                        && a4stg_of_mask);
2350
 
2351
dffe_s #(1) i_add_of_out_tmp1 (
2352
        .din    (add_of_out_tmp1_in),
2353
        .en     (a6stg_step),
2354
        .clk    (rclk),
2355
 
2356
        .q      (add_of_out_tmp1),
2357
 
2358
        .se     (se),
2359
        .si     (),
2360
        .so     ()
2361
);
2362
 
2363
dffe_s #(1) i_add_of_out_tmp2 (
2364
        .din    (a4stg_in_of),
2365
        .en     (a6stg_step),
2366
        .clk    (rclk),
2367
 
2368
        .q      (add_of_out_tmp2),
2369
 
2370
        .se     (se),
2371
        .si     (),
2372
        .so     ()
2373
);
2374
 
2375
assign add_of_out= add_of_out_tmp2
2376
                || (add_of_out_tmp1 && add_of_out_cout);
2377
 
2378
assign a4stg_uf= ((!(|a4stg_exp[10:0]))
2379
                        && a4stg_frac_neq_0
2380
                        && (a4stg_round || a4stg_fdtos)
2381
                        && a4stg_faddsub_dtosop)
2382
                || (a4stg_faddsubop
2383
                        && (!(a4stg_round || a4stg_fdtos))
2384
                        && (!a4stg_denorm_inv)
2385
                        && a4stg_shl_data_neq_0);
2386
 
2387
dffe_s #(1) i_add_uf_out (
2388
        .din    (a4stg_uf),
2389
        .en     (a6stg_step),
2390
        .clk    (rclk),
2391
 
2392
        .q      (add_uf_out),
2393
 
2394
        .se     (se),
2395
        .si     (),
2396
        .so     ()
2397
);
2398
 
2399
assign add_nx_out_in= (a4stg_of_mask
2400
                        && a4stg_frac_dbl_nx
2401
                        && (a4stg_faddsubd || a5stg_fxtod)
2402
                        && ((!a4stg_faddsubd) || a4stg_round))
2403
                || (a4stg_of_mask
2404
                        && a4stg_frac_sng_nx
2405
                        && (a4stg_faddsubs_fdtos || a5stg_fixtos)
2406
                        && ((!a4stg_faddsubs) || a4stg_round))
2407
                || a4stg_nx;
2408
 
2409
dffe_s #(1) i_add_nx_out (
2410
        .din    (add_nx_out_in),
2411
        .en     (a6stg_step),
2412
        .clk    (rclk),
2413
 
2414
        .q      (add_nx_out),
2415
 
2416
        .se     (se),
2417
        .si     (),
2418
        .so     ()
2419
);
2420
 
2421
 
2422
///////////////////////////////////////////////////////////////////////////////
2423
//
2424
//      Add pipe exception output.
2425
//
2426
///////////////////////////////////////////////////////////////////////////////
2427
 
2428
// Austin update
2429
// Overflow is always accompanied by inexact.
2430
// Previously this was handled within the FFU.
2431
 
2432
// assign add_exc_out[4:0]= {add_nv_out, add_of_out, add_uf_out, 1'b0, add_nx_out};
2433
 
2434
assign add_exc_out[4:0] =
2435
  {add_nv_out,
2436
   add_of_out,
2437
   add_uf_out,
2438
   1'b0,
2439
   (add_nx_out || add_of_out)};  // Overflow is always accompanied by inexact
2440
 
2441
///////////////////////////////////////////////////////////////////////////////
2442
//
2443
//      Add pipeline control logic.
2444
//
2445
///////////////////////////////////////////////////////////////////////////////
2446
 
2447
///////////////////////////////////////////////////////////////////////////////
2448
//
2449
//      Select lines- add normalization and special input injection.
2450
//
2451
//      Add stage 1.
2452
//
2453
///////////////////////////////////////////////////////////////////////////////
2454
 
2455
assign a2stg_frac1_in_frac1= a1stg_snan_in2
2456
                || (a1stg_qnan_in2 && (!a1stg_snan_in1));
2457
 
2458
assign a2stg_frac1_in_frac2= a1stg_faddsubop
2459
                && ((!a1stg_2nan_in)
2460
                        || a1stg_snan_in2
2461
                        || (a1stg_qnan_in2 && (!a1stg_snan_in1)));
2462
 
2463
assign a1stg_2nan_in_inv= (!a1stg_2nan_in);
2464
 
2465
assign a1stg_faddsubop_inv= (!a1stg_faddsubop);
2466
 
2467
assign a2stg_frac1_in_qnan= (a1stg_nan_in
2468
                        || (a1stg_2inf_in && a1stg_sub))
2469
                && a1stg_faddsubop;
2470
 
2471
assign a2stg_frac1_in_nv= a1stg_2inf_in && a1stg_sub && a1stg_faddsubop;
2472
 
2473
assign a2stg_frac1_in_nv_dbl= a1stg_2inf_in && a1stg_sub && a1stg_faddsubd;
2474
 
2475
assign a2stg_frac2_in_frac1= a1stg_faddsubop && (!a1stg_infnan_in);
2476
 
2477
assign a2stg_frac2_in_qnan= a1stg_snan_in2 && (!a1stg_faddsubop);
2478
 
2479
 
2480
///////////////////////////////////////////////////////////////////////////////
2481
//
2482
//      Select lines and control logic- add pipe right shift count
2483
//              count calculation.
2484
//
2485
//      Add stage 1.
2486
//
2487
///////////////////////////////////////////////////////////////////////////////
2488
 
2489
assign a1stg_exp_diff_add1= a1stg_faddsub_dtosop && (!a1stg_expadd1[11]);
2490
 
2491
assign a1stg_exp_diff_add2= a1stg_faddsubop && a1stg_expadd1[11];
2492
 
2493
assign a1stg_exp_diff_5= (!a1stg_expadd2[5]) && a1stg_fsdtox;
2494
 
2495
assign a1stg_exp_diff[10:0]= ({11{a1stg_exp_diff_add1}}
2496
                            & a1stg_expadd1[10:0])
2497
                | ({11{a1stg_exp_diff_add2}}
2498
                            & (~a1stg_expadd4_inv[10:0]))
2499
                | ({11{a1stg_fsdtoix}}
2500
                            & {5'b0, a1stg_exp_diff_5, (~a1stg_expadd2[4:0])});
2501
 
2502
assign a1stg_clamp63[5:0]= a1stg_exp_diff[5:0] | {6{(|a1stg_exp_diff[10:6])}};
2503
 
2504
assign a2stg_shr_cnt_in[5:0]= a1stg_clamp63[5:0];
2505
 
2506
assign a2stg_shr_cnt_5_inv_in= (!a1stg_clamp63[5]);
2507
 
2508
 
2509
///////////////////////////////////////////////////////////////////////////////
2510
//
2511
//      Select lines- add pipe right shift.
2512
//
2513
//      Add stage 2.
2514
//
2515
///////////////////////////////////////////////////////////////////////////////
2516
 
2517
assign a2stg_shr_frac2_shr_int= a2stg_faddsub_dtosop && a6stg_step;
2518
 
2519
assign a2stg_shr_frac2_shr_dbl= ((a2stg_fdtox && (|a2stg_exp[11:10]))
2520
                        || (a2stg_fstox && (|a2stg_exp[11:7])))
2521
                && a6stg_step;
2522
 
2523
assign a2stg_shr_frac2_shr_sng= ((a2stg_fdtoi && (|a2stg_exp[11:10]))
2524
                        || (a2stg_fstoi && (|a2stg_exp[11:7])))
2525
                && a6stg_step;
2526
 
2527
assign a2stg_shr_frac2_max= a2stg_fsdtoix && a6stg_step;
2528
 
2529
assign a2stg_sub_step= a2stg_sub && a6stg_step;
2530
 
2531
 
2532
///////////////////////////////////////////////////////////////////////////////
2533
//
2534
//      Select lines- add pipe adder.
2535
//
2536
//      Add stage 2.
2537
//
2538
///////////////////////////////////////////////////////////////////////////////
2539
 
2540
assign a1stg_faddsub_clamp63_0= (|(({6{a1stg_expadd1[11]}}
2541
                            & (~{a1stg_expadd4_inv[10:6],
2542
                                                a1stg_expadd4_inv[0]}))
2543
                | ({6{(!a1stg_expadd1[11])}}
2544
                            & {a1stg_expadd1[10:6], a1stg_expadd1[0]})));
2545
 
2546
assign a2stg_fracadd_frac2_inv_in= (a1stg_fixtosd && a1stg_in2_63)
2547
                || (a1stg_faddsubop && a1stg_sub
2548
                        && (!a1stg_faddsub_clamp63_0));
2549
 
2550
assign a2stg_fracadd_frac2_inv_shr1_in= a1stg_faddsubop && a1stg_sub
2551
                        && a1stg_faddsub_clamp63_0;
2552
 
2553
assign a2stg_fracadd_frac2_in= (a1stg_fixtosd && (!a1stg_in2_63))
2554
                || a1stg_fstod
2555
                || (a1stg_faddsubop && (!a1stg_sub));
2556
 
2557
dffe_s #(1) i_a2stg_fracadd_frac2 (
2558
        .din    (a2stg_fracadd_frac2_in),
2559
        .en     (a6stg_step),
2560
        .clk    (rclk),
2561
 
2562
        .q      (a2stg_fracadd_frac2),
2563
 
2564
        .se     (se),
2565
        .si     (),
2566
        .so     ()
2567
);
2568
 
2569
assign a2stg_fracadd_cin_in= (a1stg_fixtosd && a1stg_in2_63)
2570
                || (a1stg_faddsubop && a1stg_sub);
2571
 
2572
 
2573
///////////////////////////////////////////////////////////////////////////////
2574
//
2575
//      Select lines- add pipe exponent adjustment.
2576
//
2577
//      Add stage 2.
2578
//
2579
///////////////////////////////////////////////////////////////////////////////
2580
 
2581
assign a3stg_exp_7ff= a2stg_fstod && (&a2stg_exp[7:0]);
2582
 
2583
assign a3stg_exp_ff= a2stg_fdtos && (&a2stg_exp[10:0]);
2584
 
2585
assign a3stg_exp_add= (a2stg_fstod && (!(&a2stg_exp[7:0])))
2586
                || (a2stg_fdtos && (!(&a2stg_exp[10:0])));
2587
 
2588
 
2589
///////////////////////////////////////////////////////////////////////////////
2590
//
2591
//      Select lines- add pipe exponent decode- used to identify denorm results.
2592
//
2593
//      Add stage 2.
2594
//
2595
///////////////////////////////////////////////////////////////////////////////
2596
 
2597
assign a2stg_expdec_neq_0= a2stg_faddsubop && (a2stg_exp[10:0]<11'h36);
2598
 
2599
 
2600
///////////////////////////////////////////////////////////////////////////////
2601
//
2602
//      Select lines and control logic
2603
//              - add pipe main adder
2604
//              - add pipe exponent increment/decrement adjustment
2605
//
2606
//      Add stage 3.
2607
//
2608
///////////////////////////////////////////////////////////////////////////////
2609
 
2610
assign a3stg_exp10_0_eq0= (a3stg_exp[10:0]==11'b0);
2611
 
2612
assign a3stg_exp10_1_eq0= (a3stg_exp[10:1]==10'b0);
2613
 
2614
assign a3stg_fdtos_inv= (!a3stg_fdtos);
2615
 
2616
assign a4stg_fixtos_fxtod_inv= (!a4stg_fixtos_fxtod);
2617
 
2618
assign a4stg_rnd_frac_add_inv= (!(a3stg_fsdtoix
2619
                || (a3stg_faddsubop && a3stg_exp10_0_eq0)));
2620
 
2621
 
2622
///////////////////////////////////////////////////////////////////////////////
2623
//
2624
//      Control logic- add pipe left shift count.
2625
//
2626
//      Add stage 3.
2627
//
2628
///////////////////////////////////////////////////////////////////////////////
2629
 
2630
assign a4stg_shl_cnt_in[9:0]= ({10{a3stg_denorm}}
2631
                            & {(a3stg_exp[5:4]==2'b11),
2632
                                (a3stg_exp[5:4]==2'b10),
2633
                                (a3stg_exp[5:4]==2'b01),
2634
                                (a3stg_exp[5:4]==2'b00),
2635
                                a3stg_exp[5:0]})
2636
                | ({10{a3stg_denorm_inv}}
2637
                            & {(a3stg_lead0[5:4]==2'b11),
2638
                                (a3stg_lead0[5:4]==2'b10),
2639
                                (a3stg_lead0[5:4]==2'b01),
2640
                                (a3stg_lead0[5:4]==2'b00),
2641
                                a3stg_lead0[5:0]});
2642
 
2643
 
2644
///////////////////////////////////////////////////////////////////////////////
2645
//
2646
//      Select lines and control logic- add pipe rounding adder.
2647
//
2648
//      Add stage 4.
2649
//
2650
///////////////////////////////////////////////////////////////////////////////
2651
 
2652
assign a4stg_rnd_sng= a5stg_fixtos || a4stg_faddsubs_fdtos;
2653
 
2654
assign a4stg_rnd_dbl= a5stg_fxtod || a4stg_faddsubd;
2655
 
2656
 
2657
///////////////////////////////////////////////////////////////////////////////
2658
//
2659
//      Select lines and control logic- add pipe fraction output.
2660
//
2661
//      Add stage 4.
2662
//
2663
///////////////////////////////////////////////////////////////////////////////
2664
 
2665
assign a4stg_rndup_sng= ((a4stg_rnd_mode==2'b10) && (!a4stg_sign)
2666
                        && a4stg_frac_sng_nx)
2667
                || ((a4stg_rnd_mode==2'b11) && a4stg_sign
2668
                        && a4stg_frac_sng_nx)
2669
                || ((a4stg_rnd_mode==2'b00) && a4stg_rnd_frac_39
2670
                        && (a4stg_frac_38_0_nx || a4stg_rnd_frac_40));
2671
 
2672
assign a4stg_rndup_dbl= ((a4stg_rnd_mode==2'b10) && (!a4stg_sign)
2673
                        && a4stg_frac_dbl_nx)
2674
                || ((a4stg_rnd_mode==2'b11) && a4stg_sign
2675
                        && a4stg_frac_dbl_nx)
2676
                || ((a4stg_rnd_mode==2'b00) && a4stg_rnd_frac_10
2677
                        && (a4stg_frac_9_0_nx || a4stg_rnd_frac_11));
2678
 
2679
assign a4stg_rndup= (a4stg_faddsubd && a4stg_rndup_dbl)
2680
                || (a4stg_faddsubs && a4stg_rndup_sng)
2681
                || (a4stg_fdtos && a4stg_rndup_sng && a4stg_of_mask);
2682
 
2683
assign a5stg_rndup= (a5stg_fxtod && a4stg_rndup_dbl)
2684
                || (a5stg_fixtos && a4stg_rndup_sng);
2685
 
2686
assign add_frac_out_rndadd= (a4stg_faddsubop && a4stg_round && a4stg_rndup
2687
                        && (!a4stg_in_of))
2688
                || (a4stg_fdtos && a4stg_rndup && (!a4stg_in_of))
2689
                || (a5stg_fixtos_fxtod && a5stg_rndup);
2690
 
2691
assign add_frac_out_rnd_frac= (a4stg_faddsubop && a4stg_round && (!a4stg_rndup)
2692
                        && (!a4stg_in_of))
2693
                || (a4stg_fdtos && (!a4stg_rndup) && (!a4stg_in_of))
2694
                || (a5stg_fixtos_fxtod && (!a5stg_rndup))
2695
                || a4stg_fsdtoix;
2696
 
2697
assign add_frac_out_shl= (a4stg_faddsubop && (!a4stg_round) && (!a4stg_in_of))
2698
                || a4stg_fistod;
2699
 
2700
assign a4stg_to_0= (!((a4stg_rnd_mode==2'b00)
2701
                        || ((a4stg_rnd_mode==2'b10) && (!a4stg_sign))
2702
                        || ((a4stg_rnd_mode==2'b11) && a4stg_sign)));
2703
 
2704
 
2705
///////////////////////////////////////////////////////////////////////////////
2706
//
2707
//      Select lines and control logic- add pipe exponent output.
2708
//
2709
//      Add stage 4.
2710
//
2711
///////////////////////////////////////////////////////////////////////////////
2712
 
2713
assign add_exp_out_expinc= (a4stg_faddsubop && a4stg_round && a4stg_rndup
2714
                        && (!a4stg_in_of))
2715
                || (a4stg_fdtos && a4stg_rndup
2716
                        && (!a4stg_in_of))
2717
                || (a5stg_fixtos_fxtod && a5stg_rndup);
2718
 
2719
assign add_exp_out_exp= (a4stg_faddsubop && a4stg_round
2720
                        && (!a4stg_in_of))
2721
                || (a4stg_fdtos
2722
                        && (!a4stg_in_of))
2723
                || a5stg_fixtos_fxtod;
2724
 
2725
assign add_exp_out_exp1= (a4stg_faddsubop && a4stg_round
2726
                        && (!a4stg_rndup)
2727
                        && (!a4stg_in_of))
2728
                || (a4stg_fdtos
2729
                        && (!a4stg_rndup)
2730
                        && (!a4stg_in_of))
2731
                || (a5stg_fixtos_fxtod
2732
                        && (!a5stg_rndup));
2733
 
2734
assign add_exp_out_expadd= (a4stg_faddsubop && (!a4stg_round) && (!a4stg_in_of))
2735
                || a4stg_fistod;
2736
 
2737
assign a4stg_to_0_inv= (!a4stg_to_0);
2738
 
2739
 
2740
endmodule
2741
 
2742
 

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