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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: fpu_cnt_lead0_53b.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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///////////////////////////////////////////////////////////////////////////////
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//
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// 53 bit lead 0 counter.
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//
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///////////////////////////////////////////////////////////////////////////////
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module fpu_cnt_lead0_53b (
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din,
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lead0
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);
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input [52:0] din; // data in- count its leading 0's
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output [5:0] lead0; // number of leading 0's in data in
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wire din_52_49_eq_0;
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wire din_52_51_eq_0;
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wire lead0_52_49_0;
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wire din_48_45_eq_0;
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wire din_48_47_eq_0;
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wire lead0_48_45_0;
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wire din_44_41_eq_0;
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wire din_44_43_eq_0;
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wire lead0_44_41_0;
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wire din_40_37_eq_0;
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wire din_40_39_eq_0;
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wire lead0_40_37_0;
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wire din_36_33_eq_0;
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wire din_36_35_eq_0;
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wire lead0_36_33_0;
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wire din_32_29_eq_0;
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wire din_32_31_eq_0;
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wire lead0_32_29_0;
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wire din_28_25_eq_0;
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wire din_28_27_eq_0;
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wire lead0_28_25_0;
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wire din_24_21_eq_0;
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wire din_24_23_eq_0;
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wire lead0_24_21_0;
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wire din_20_17_eq_0;
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wire din_20_19_eq_0;
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wire lead0_20_17_0;
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wire din_16_13_eq_0;
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wire din_16_15_eq_0;
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wire lead0_16_13_0;
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wire din_12_9_eq_0;
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wire din_12_11_eq_0;
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wire lead0_12_9_0;
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wire din_8_5_eq_0;
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wire din_8_7_eq_0;
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wire lead0_8_5_0;
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wire din_4_1_eq_0;
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wire din_4_3_eq_0;
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wire lead0_4_1_0;
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wire lead0_0_0;
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wire din_52_45_eq_0;
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wire lead0_52_45_1;
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wire lead0_52_45_0;
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wire din_44_37_eq_0;
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wire lead0_44_37_1;
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wire lead0_44_37_0;
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wire din_36_29_eq_0;
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wire lead0_36_29_1;
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wire lead0_36_29_0;
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wire din_28_21_eq_0;
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wire lead0_28_21_1;
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wire lead0_28_21_0;
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wire din_20_13_eq_0;
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wire lead0_20_13_1;
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wire lead0_20_13_0;
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wire din_12_5_eq_0;
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wire lead0_12_5_1;
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wire lead0_12_5_0;
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wire lead0_4_0_1;
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wire lead0_4_0_0;
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wire din_52_37_eq_0;
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wire lead0_52_37_2;
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wire lead0_52_37_1;
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wire lead0_52_37_0;
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wire din_36_21_eq_0;
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wire lead0_36_21_2;
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wire lead0_36_21_1;
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wire lead0_36_21_0;
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wire din_20_5_eq_0;
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wire lead0_20_5_2;
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wire lead0_20_5_1;
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wire lead0_20_5_0;
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wire lead0_4_0_2;
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wire din_52_21_eq_0;
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wire lead0_52_21_3;
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wire lead0_52_21_2;
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wire lead0_52_21_1;
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wire lead0_52_21_0;
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wire lead0_20_0_3;
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wire lead0_20_0_2;
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wire lead0_20_0_1;
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wire lead0_20_0_0;
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wire lead0_5;
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wire lead0_4;
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wire lead0_3;
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wire lead0_2;
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wire lead0_1;
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wire lead0_0;
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wire [5:0] lead0;
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///////////////////////////////////////////////////////////////////////////////
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//
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// Instantiations of lead 0 building blocks.
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//
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///////////////////////////////////////////////////////////////////////////////
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_52_49 (
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.din (din[52:49]),
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.din_3_0_eq_0 (din_52_49_eq_0),
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.din_3_2_eq_0 (din_52_51_eq_0),
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.lead0_4b_0 (lead0_52_49_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_48_45 (
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.din (din[48:45]),
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.din_3_0_eq_0 (din_48_45_eq_0),
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.din_3_2_eq_0 (din_48_47_eq_0),
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.lead0_4b_0 (lead0_48_45_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_44_41 (
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.din (din[44:41]),
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.din_3_0_eq_0 (din_44_41_eq_0),
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.din_3_2_eq_0 (din_44_43_eq_0),
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.lead0_4b_0 (lead0_44_41_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_40_37 (
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.din (din[40:37]),
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.din_3_0_eq_0 (din_40_37_eq_0),
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.din_3_2_eq_0 (din_40_39_eq_0),
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.lead0_4b_0 (lead0_40_37_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_36_33 (
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.din (din[36:33]),
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.din_3_0_eq_0 (din_36_33_eq_0),
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.din_3_2_eq_0 (din_36_35_eq_0),
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.lead0_4b_0 (lead0_36_33_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_32_29 (
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.din (din[32:29]),
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.din_3_0_eq_0 (din_32_29_eq_0),
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.din_3_2_eq_0 (din_32_31_eq_0),
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.lead0_4b_0 (lead0_32_29_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_28_25 (
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.din (din[28:25]),
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.din_3_0_eq_0 (din_28_25_eq_0),
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.din_3_2_eq_0 (din_28_27_eq_0),
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.lead0_4b_0 (lead0_28_25_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_24_21 (
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.din (din[24:21]),
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.din_3_0_eq_0 (din_24_21_eq_0),
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.din_3_2_eq_0 (din_24_23_eq_0),
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.lead0_4b_0 (lead0_24_21_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_20_17 (
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.din (din[20:17]),
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.din_3_0_eq_0 (din_20_17_eq_0),
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.din_3_2_eq_0 (din_20_19_eq_0),
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.lead0_4b_0 (lead0_20_17_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_16_13 (
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.din (din[16:13]),
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.din_3_0_eq_0 (din_16_13_eq_0),
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.din_3_2_eq_0 (din_16_15_eq_0),
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.lead0_4b_0 (lead0_16_13_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_12_9 (
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.din (din[12:9]),
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.din_3_0_eq_0 (din_12_9_eq_0),
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.din_3_2_eq_0 (din_12_11_eq_0),
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.lead0_4b_0 (lead0_12_9_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_8_5 (
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.din (din[8:5]),
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.din_3_0_eq_0 (din_8_5_eq_0),
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.din_3_2_eq_0 (din_8_7_eq_0),
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.lead0_4b_0 (lead0_8_5_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_4_1 (
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.din (din[4:1]),
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.din_3_0_eq_0 (din_4_1_eq_0),
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.din_3_2_eq_0 (din_4_3_eq_0),
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.lead0_4b_0 (lead0_4_1_0)
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);
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assign lead0_0_0= (!din[0]);
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fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_52_45 (
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.din_7_4_eq_0 (din_52_49_eq_0),
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.din_7_6_eq_0 (din_52_51_eq_0),
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.lead0_4b_0_hi (lead0_52_49_0),
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.din_3_0_eq_0 (din_48_45_eq_0),
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.din_3_2_eq_0 (din_48_47_eq_0),
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| 249 |
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.lead0_4b_0_lo (lead0_48_45_0),
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.din_7_0_eq_0 (din_52_45_eq_0),
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| 252 |
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.lead0_8b_1 (lead0_52_45_1),
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.lead0_8b_0 (lead0_52_45_0)
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);
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fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_44_37 (
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| 257 |
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.din_7_4_eq_0 (din_44_41_eq_0),
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| 258 |
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.din_7_6_eq_0 (din_44_43_eq_0),
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| 259 |
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.lead0_4b_0_hi (lead0_44_41_0),
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| 260 |
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.din_3_0_eq_0 (din_40_37_eq_0),
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| 261 |
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.din_3_2_eq_0 (din_40_39_eq_0),
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| 262 |
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.lead0_4b_0_lo (lead0_40_37_0),
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| 263 |
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| 264 |
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.din_7_0_eq_0 (din_44_37_eq_0),
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| 265 |
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.lead0_8b_1 (lead0_44_37_1),
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| 266 |
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.lead0_8b_0 (lead0_44_37_0)
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);
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| 268 |
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| 269 |
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fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_36_29 (
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| 270 |
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.din_7_4_eq_0 (din_36_33_eq_0),
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| 271 |
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.din_7_6_eq_0 (din_36_35_eq_0),
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| 272 |
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.lead0_4b_0_hi (lead0_36_33_0),
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| 273 |
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.din_3_0_eq_0 (din_32_29_eq_0),
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| 274 |
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.din_3_2_eq_0 (din_32_31_eq_0),
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| 275 |
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.lead0_4b_0_lo (lead0_32_29_0),
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| 276 |
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| 277 |
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.din_7_0_eq_0 (din_36_29_eq_0),
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| 278 |
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.lead0_8b_1 (lead0_36_29_1),
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| 279 |
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.lead0_8b_0 (lead0_36_29_0)
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| 280 |
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);
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| 281 |
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| 282 |
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fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_28_21 (
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| 283 |
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.din_7_4_eq_0 (din_28_25_eq_0),
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| 284 |
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.din_7_6_eq_0 (din_28_27_eq_0),
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| 285 |
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.lead0_4b_0_hi (lead0_28_25_0),
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| 286 |
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.din_3_0_eq_0 (din_24_21_eq_0),
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| 287 |
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.din_3_2_eq_0 (din_24_23_eq_0),
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| 288 |
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.lead0_4b_0_lo (lead0_24_21_0),
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| 289 |
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| 290 |
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.din_7_0_eq_0 (din_28_21_eq_0),
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| 291 |
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.lead0_8b_1 (lead0_28_21_1),
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| 292 |
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.lead0_8b_0 (lead0_28_21_0)
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| 293 |
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);
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| 294 |
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| 295 |
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fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_20_13 (
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| 296 |
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.din_7_4_eq_0 (din_20_17_eq_0),
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| 297 |
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.din_7_6_eq_0 (din_20_19_eq_0),
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| 298 |
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.lead0_4b_0_hi (lead0_20_17_0),
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| 299 |
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.din_3_0_eq_0 (din_16_13_eq_0),
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| 300 |
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.din_3_2_eq_0 (din_16_15_eq_0),
|
| 301 |
|
|
.lead0_4b_0_lo (lead0_16_13_0),
|
| 302 |
|
|
|
| 303 |
|
|
.din_7_0_eq_0 (din_20_13_eq_0),
|
| 304 |
|
|
.lead0_8b_1 (lead0_20_13_1),
|
| 305 |
|
|
.lead0_8b_0 (lead0_20_13_0)
|
| 306 |
|
|
);
|
| 307 |
|
|
|
| 308 |
|
|
fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_12_5 (
|
| 309 |
|
|
.din_7_4_eq_0 (din_12_9_eq_0),
|
| 310 |
|
|
.din_7_6_eq_0 (din_12_11_eq_0),
|
| 311 |
|
|
.lead0_4b_0_hi (lead0_12_9_0),
|
| 312 |
|
|
.din_3_0_eq_0 (din_8_5_eq_0),
|
| 313 |
|
|
.din_3_2_eq_0 (din_8_7_eq_0),
|
| 314 |
|
|
.lead0_4b_0_lo (lead0_8_5_0),
|
| 315 |
|
|
|
| 316 |
|
|
.din_7_0_eq_0 (din_12_5_eq_0),
|
| 317 |
|
|
.lead0_8b_1 (lead0_12_5_1),
|
| 318 |
|
|
.lead0_8b_0 (lead0_12_5_0)
|
| 319 |
|
|
);
|
| 320 |
|
|
|
| 321 |
|
|
assign lead0_4_0_1= (!din_4_1_eq_0) && din_4_3_eq_0;
|
| 322 |
|
|
|
| 323 |
|
|
assign lead0_4_0_0= ((!din_4_1_eq_0) && lead0_4_1_0)
|
| 324 |
|
|
|| (din_4_1_eq_0 && lead0_0_0);
|
| 325 |
|
|
|
| 326 |
|
|
|
| 327 |
|
|
fpu_cnt_lead0_lvl3 i_fpu_cnt_lead0_lvl3_52_37 (
|
| 328 |
|
|
.din_15_8_eq_0 (din_52_45_eq_0),
|
| 329 |
|
|
.din_15_12_eq_0 (din_52_49_eq_0),
|
| 330 |
|
|
.lead0_8b_1_hi (lead0_52_45_1),
|
| 331 |
|
|
.lead0_8b_0_hi (lead0_52_45_0),
|
| 332 |
|
|
.din_7_0_eq_0 (din_44_37_eq_0),
|
| 333 |
|
|
.din_7_4_eq_0 (din_44_41_eq_0),
|
| 334 |
|
|
.lead0_8b_1_lo (lead0_44_37_1),
|
| 335 |
|
|
.lead0_8b_0_lo (lead0_44_37_0),
|
| 336 |
|
|
|
| 337 |
|
|
.din_15_0_eq_0 (din_52_37_eq_0),
|
| 338 |
|
|
.lead0_16b_2 (lead0_52_37_2),
|
| 339 |
|
|
.lead0_16b_1 (lead0_52_37_1),
|
| 340 |
|
|
.lead0_16b_0 (lead0_52_37_0)
|
| 341 |
|
|
);
|
| 342 |
|
|
|
| 343 |
|
|
fpu_cnt_lead0_lvl3 i_fpu_cnt_lead0_lvl3_36_21 (
|
| 344 |
|
|
.din_15_8_eq_0 (din_36_29_eq_0),
|
| 345 |
|
|
.din_15_12_eq_0 (din_36_33_eq_0),
|
| 346 |
|
|
.lead0_8b_1_hi (lead0_36_29_1),
|
| 347 |
|
|
.lead0_8b_0_hi (lead0_36_29_0),
|
| 348 |
|
|
.din_7_0_eq_0 (din_28_21_eq_0),
|
| 349 |
|
|
.din_7_4_eq_0 (din_28_25_eq_0),
|
| 350 |
|
|
.lead0_8b_1_lo (lead0_28_21_1),
|
| 351 |
|
|
.lead0_8b_0_lo (lead0_28_21_0),
|
| 352 |
|
|
|
| 353 |
|
|
.din_15_0_eq_0 (din_36_21_eq_0),
|
| 354 |
|
|
.lead0_16b_2 (lead0_36_21_2),
|
| 355 |
|
|
.lead0_16b_1 (lead0_36_21_1),
|
| 356 |
|
|
.lead0_16b_0 (lead0_36_21_0)
|
| 357 |
|
|
);
|
| 358 |
|
|
|
| 359 |
|
|
fpu_cnt_lead0_lvl3 i_fpu_cnt_lead0_lvl3_20_5 (
|
| 360 |
|
|
.din_15_8_eq_0 (din_20_13_eq_0),
|
| 361 |
|
|
.din_15_12_eq_0 (din_20_17_eq_0),
|
| 362 |
|
|
.lead0_8b_1_hi (lead0_20_13_1),
|
| 363 |
|
|
.lead0_8b_0_hi (lead0_20_13_0),
|
| 364 |
|
|
.din_7_0_eq_0 (din_12_5_eq_0),
|
| 365 |
|
|
.din_7_4_eq_0 (din_12_9_eq_0),
|
| 366 |
|
|
.lead0_8b_1_lo (lead0_12_5_1),
|
| 367 |
|
|
.lead0_8b_0_lo (lead0_12_5_0),
|
| 368 |
|
|
|
| 369 |
|
|
.din_15_0_eq_0 (din_20_5_eq_0),
|
| 370 |
|
|
.lead0_16b_2 (lead0_20_5_2),
|
| 371 |
|
|
.lead0_16b_1 (lead0_20_5_1),
|
| 372 |
|
|
.lead0_16b_0 (lead0_20_5_0)
|
| 373 |
|
|
);
|
| 374 |
|
|
|
| 375 |
|
|
assign lead0_4_0_2= din_4_1_eq_0;
|
| 376 |
|
|
|
| 377 |
|
|
|
| 378 |
|
|
fpu_cnt_lead0_lvl4 i_fpu_cnt_lead0_lvl4_52_21 (
|
| 379 |
|
|
.din_31_16_eq_0 (din_52_37_eq_0),
|
| 380 |
|
|
.din_31_24_eq_0 (din_52_45_eq_0),
|
| 381 |
|
|
.lead0_16b_2_hi (lead0_52_37_2),
|
| 382 |
|
|
.lead0_16b_1_hi (lead0_52_37_1),
|
| 383 |
|
|
.lead0_16b_0_hi (lead0_52_37_0),
|
| 384 |
|
|
.din_15_0_eq_0 (din_36_21_eq_0),
|
| 385 |
|
|
.din_15_8_eq_0 (din_36_29_eq_0),
|
| 386 |
|
|
.lead0_16b_2_lo (lead0_36_21_2),
|
| 387 |
|
|
.lead0_16b_1_lo (lead0_36_21_1),
|
| 388 |
|
|
.lead0_16b_0_lo (lead0_36_21_0),
|
| 389 |
|
|
|
| 390 |
|
|
.din_31_0_eq_0 (din_52_21_eq_0),
|
| 391 |
|
|
.lead0_32b_3 (lead0_52_21_3),
|
| 392 |
|
|
.lead0_32b_2 (lead0_52_21_2),
|
| 393 |
|
|
.lead0_32b_1 (lead0_52_21_1),
|
| 394 |
|
|
.lead0_32b_0 (lead0_52_21_0)
|
| 395 |
|
|
);
|
| 396 |
|
|
|
| 397 |
|
|
fpu_cnt_lead0_lvl4 i_fpu_cnt_lead0_lvl4_20_0 (
|
| 398 |
|
|
.din_31_16_eq_0 (din_20_5_eq_0),
|
| 399 |
|
|
.din_31_24_eq_0 (din_20_13_eq_0),
|
| 400 |
|
|
.lead0_16b_2_hi (lead0_20_5_2),
|
| 401 |
|
|
.lead0_16b_1_hi (lead0_20_5_1),
|
| 402 |
|
|
.lead0_16b_0_hi (lead0_20_5_0),
|
| 403 |
|
|
.din_15_0_eq_0 (1'b0),
|
| 404 |
|
|
.din_15_8_eq_0 (1'b0),
|
| 405 |
|
|
.lead0_16b_2_lo (lead0_4_0_2),
|
| 406 |
|
|
.lead0_16b_1_lo (lead0_4_0_1),
|
| 407 |
|
|
.lead0_16b_0_lo (lead0_4_0_0),
|
| 408 |
|
|
|
| 409 |
|
|
.din_31_0_eq_0 ( ),
|
| 410 |
|
|
.lead0_32b_3 (lead0_20_0_3),
|
| 411 |
|
|
.lead0_32b_2 (lead0_20_0_2),
|
| 412 |
|
|
.lead0_32b_1 (lead0_20_0_1),
|
| 413 |
|
|
.lead0_32b_0 (lead0_20_0_0)
|
| 414 |
|
|
);
|
| 415 |
|
|
|
| 416 |
|
|
assign lead0_5= din_52_21_eq_0;
|
| 417 |
|
|
|
| 418 |
|
|
assign lead0_4= ((!din_52_21_eq_0) && din_52_37_eq_0)
|
| 419 |
|
|
|| (din_52_21_eq_0 && din_20_5_eq_0);
|
| 420 |
|
|
|
| 421 |
|
|
assign lead0_3= ((!din_52_21_eq_0) && lead0_52_21_3)
|
| 422 |
|
|
|| (din_52_21_eq_0 && lead0_20_0_3);
|
| 423 |
|
|
|
| 424 |
|
|
assign lead0_2= ((!din_52_21_eq_0) && lead0_52_21_2)
|
| 425 |
|
|
|| (din_52_21_eq_0 && lead0_20_0_2);
|
| 426 |
|
|
|
| 427 |
|
|
assign lead0_1= ((!din_52_21_eq_0) && lead0_52_21_1)
|
| 428 |
|
|
|| (din_52_21_eq_0 && lead0_20_0_1);
|
| 429 |
|
|
|
| 430 |
|
|
assign lead0_0= ((!din_52_21_eq_0) && lead0_52_21_0)
|
| 431 |
|
|
|| (din_52_21_eq_0 && lead0_20_0_0);
|
| 432 |
|
|
|
| 433 |
|
|
assign lead0[5:0]= {lead0_5, lead0_4, lead0_3, lead0_2, lead0_1, lead0_0};
|
| 434 |
|
|
|
| 435 |
|
|
|
| 436 |
|
|
endmodule
|
| 437 |
|
|
|
| 438 |
|
|
|
