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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: fpu_cnt_lead0_64b.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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///////////////////////////////////////////////////////////////////////////////
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//
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// 64 bit lead 0 counter.
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//
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///////////////////////////////////////////////////////////////////////////////
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module fpu_cnt_lead0_64b (
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din,
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lead0
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);
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input [63:0] din; // data in- count its leading 0's
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output [5:0] lead0; // number of leading 0's in data in
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wire din_63_60_eq_0;
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wire din_63_62_eq_0;
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wire lead0_63_60_0;
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wire din_59_56_eq_0;
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wire din_59_58_eq_0;
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wire lead0_59_56_0;
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wire din_55_52_eq_0;
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wire din_55_54_eq_0;
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wire lead0_55_52_0;
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wire din_51_48_eq_0;
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wire din_51_50_eq_0;
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wire lead0_51_48_0;
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wire din_47_44_eq_0;
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wire din_47_46_eq_0;
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wire lead0_47_44_0;
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wire din_43_40_eq_0;
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wire din_43_42_eq_0;
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wire lead0_43_40_0;
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wire din_39_36_eq_0;
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wire din_39_38_eq_0;
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wire lead0_39_36_0;
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wire din_35_32_eq_0;
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wire din_35_34_eq_0;
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wire lead0_35_32_0;
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wire din_31_28_eq_0;
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wire din_31_30_eq_0;
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wire lead0_31_28_0;
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wire din_27_24_eq_0;
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wire din_27_26_eq_0;
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wire lead0_27_24_0;
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wire din_23_20_eq_0;
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wire din_23_22_eq_0;
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wire lead0_23_20_0;
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wire din_19_16_eq_0;
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wire din_19_18_eq_0;
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wire lead0_19_16_0;
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wire din_15_12_eq_0;
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wire din_15_14_eq_0;
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wire lead0_15_12_0;
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wire din_11_8_eq_0;
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wire din_11_10_eq_0;
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wire lead0_11_8_0;
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wire din_7_4_eq_0;
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wire din_7_6_eq_0;
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wire lead0_7_4_0;
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wire din_3_0_eq_0;
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wire din_3_2_eq_0;
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wire lead0_3_0_0;
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wire din_63_56_eq_0;
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wire lead0_63_56_1;
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wire lead0_63_56_0;
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wire din_55_48_eq_0;
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wire lead0_55_48_1;
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wire lead0_55_48_0;
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wire din_47_40_eq_0;
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wire lead0_47_40_1;
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wire lead0_47_40_0;
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wire din_39_32_eq_0;
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wire lead0_39_32_1;
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wire lead0_39_32_0;
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wire din_31_24_eq_0;
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wire lead0_31_24_1;
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wire lead0_31_24_0;
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wire din_23_16_eq_0;
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wire lead0_23_16_1;
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wire lead0_23_16_0;
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wire din_15_8_eq_0;
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wire lead0_15_8_1;
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wire lead0_15_8_0;
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wire din_7_0_eq_0;
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wire lead0_7_0_1;
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wire lead0_7_0_0;
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wire din_63_48_eq_0;
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wire lead0_63_48_2;
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wire lead0_63_48_1;
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wire lead0_63_48_0;
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wire din_47_32_eq_0;
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wire lead0_47_32_2;
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wire lead0_47_32_1;
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wire lead0_47_32_0;
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wire din_31_16_eq_0;
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wire lead0_31_16_2;
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wire lead0_31_16_1;
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wire lead0_31_16_0;
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wire din_15_0_eq_0;
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wire lead0_15_0_2;
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wire lead0_15_0_1;
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wire lead0_15_0_0;
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wire din_63_32_eq_0;
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wire lead0_63_32_3;
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wire lead0_63_32_2;
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wire lead0_63_32_1;
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wire din_31_0_eq_0;
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wire lead0_31_0_3;
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wire lead0_31_0_2;
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wire lead0_31_0_1;
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wire lead0_31_0_0;
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wire lead0_6;
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wire lead0_5;
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wire lead0_4;
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wire lead0_3;
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wire lead0_2;
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wire lead0_1;
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wire lead0_0;
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wire [5:0] lead0;
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///////////////////////////////////////////////////////////////////////////////
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//
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// Instantiations of lead 0 building blocks.
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//
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///////////////////////////////////////////////////////////////////////////////
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_63_60 (
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.din (din[63:60]),
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.din_3_0_eq_0 (din_63_60_eq_0),
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.din_3_2_eq_0 (din_63_62_eq_0),
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.lead0_4b_0 (lead0_63_60_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_59_56 (
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.din (din[59:56]),
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.din_3_0_eq_0 (din_59_56_eq_0),
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.din_3_2_eq_0 (din_59_58_eq_0),
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.lead0_4b_0 (lead0_59_56_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_55_52 (
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.din (din[55:52]),
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.din_3_0_eq_0 (din_55_52_eq_0),
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.din_3_2_eq_0 (din_55_54_eq_0),
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.lead0_4b_0 (lead0_55_52_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_51_48 (
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.din (din[51:48]),
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.din_3_0_eq_0 (din_51_48_eq_0),
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.din_3_2_eq_0 (din_51_50_eq_0),
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.lead0_4b_0 (lead0_51_48_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_47_44 (
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.din (din[47:44]),
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.din_3_0_eq_0 (din_47_44_eq_0),
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.din_3_2_eq_0 (din_47_46_eq_0),
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.lead0_4b_0 (lead0_47_44_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_43_40 (
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.din (din[43:40]),
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.din_3_0_eq_0 (din_43_40_eq_0),
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.din_3_2_eq_0 (din_43_42_eq_0),
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.lead0_4b_0 (lead0_43_40_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_39_36 (
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.din (din[39:36]),
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.din_3_0_eq_0 (din_39_36_eq_0),
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.din_3_2_eq_0 (din_39_38_eq_0),
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.lead0_4b_0 (lead0_39_36_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_35_32 (
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.din (din[35:32]),
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.din_3_0_eq_0 (din_35_32_eq_0),
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.din_3_2_eq_0 (din_35_34_eq_0),
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.lead0_4b_0 (lead0_35_32_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_31_28 (
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.din (din[31:28]),
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.din_3_0_eq_0 (din_31_28_eq_0),
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.din_3_2_eq_0 (din_31_30_eq_0),
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.lead0_4b_0 (lead0_31_28_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_27_24 (
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.din (din[27:24]),
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.din_3_0_eq_0 (din_27_24_eq_0),
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.din_3_2_eq_0 (din_27_26_eq_0),
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.lead0_4b_0 (lead0_27_24_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_23_20 (
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.din (din[23:20]),
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.din_3_0_eq_0 (din_23_20_eq_0),
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.din_3_2_eq_0 (din_23_22_eq_0),
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.lead0_4b_0 (lead0_23_20_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_19_16 (
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.din (din[19:16]),
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.din_3_0_eq_0 (din_19_16_eq_0),
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.din_3_2_eq_0 (din_19_18_eq_0),
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.lead0_4b_0 (lead0_19_16_0)
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_15_12 (
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.din (din[15:12]),
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| 251 |
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.din_3_0_eq_0 (din_15_12_eq_0),
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| 252 |
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.din_3_2_eq_0 (din_15_14_eq_0),
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| 253 |
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.lead0_4b_0 (lead0_15_12_0)
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| 254 |
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);
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_11_8 (
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.din (din[11:8]),
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| 259 |
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.din_3_0_eq_0 (din_11_8_eq_0),
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| 260 |
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.din_3_2_eq_0 (din_11_10_eq_0),
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| 261 |
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.lead0_4b_0 (lead0_11_8_0)
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| 262 |
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);
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| 263 |
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| 264 |
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_7_4 (
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| 265 |
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.din (din[7:4]),
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| 266 |
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| 267 |
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.din_3_0_eq_0 (din_7_4_eq_0),
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| 268 |
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.din_3_2_eq_0 (din_7_6_eq_0),
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| 269 |
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.lead0_4b_0 (lead0_7_4_0)
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| 270 |
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);
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| 271 |
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| 272 |
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fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_3_0 (
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| 273 |
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.din (din[3:0]),
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| 274 |
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| 275 |
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.din_3_0_eq_0 (din_3_0_eq_0),
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| 276 |
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.din_3_2_eq_0 (din_3_2_eq_0),
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| 277 |
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.lead0_4b_0 (lead0_3_0_0)
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| 278 |
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);
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| 279 |
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| 280 |
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| 281 |
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fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_63_56 (
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| 282 |
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.din_7_4_eq_0 (din_63_60_eq_0),
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| 283 |
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.din_7_6_eq_0 (din_63_62_eq_0),
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| 284 |
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.lead0_4b_0_hi (lead0_63_60_0),
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| 285 |
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.din_3_0_eq_0 (din_59_56_eq_0),
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| 286 |
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.din_3_2_eq_0 (din_59_58_eq_0),
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| 287 |
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.lead0_4b_0_lo (lead0_59_56_0),
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| 288 |
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| 289 |
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.din_7_0_eq_0 (din_63_56_eq_0),
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| 290 |
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.lead0_8b_1 (lead0_63_56_1),
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| 291 |
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.lead0_8b_0 (lead0_63_56_0)
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| 292 |
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);
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| 293 |
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| 294 |
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fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_55_48 (
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| 295 |
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.din_7_4_eq_0 (din_55_52_eq_0),
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| 296 |
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.din_7_6_eq_0 (din_55_54_eq_0),
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| 297 |
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.lead0_4b_0_hi (lead0_55_52_0),
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| 298 |
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.din_3_0_eq_0 (din_51_48_eq_0),
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| 299 |
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.din_3_2_eq_0 (din_51_50_eq_0),
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| 300 |
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.lead0_4b_0_lo (lead0_51_48_0),
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| 301 |
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| 302 |
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.din_7_0_eq_0 (din_55_48_eq_0),
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| 303 |
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.lead0_8b_1 (lead0_55_48_1),
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| 304 |
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.lead0_8b_0 (lead0_55_48_0)
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| 305 |
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);
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| 306 |
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| 307 |
|
|
fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_47_40 (
|
| 308 |
|
|
.din_7_4_eq_0 (din_47_44_eq_0),
|
| 309 |
|
|
.din_7_6_eq_0 (din_47_46_eq_0),
|
| 310 |
|
|
.lead0_4b_0_hi (lead0_47_44_0),
|
| 311 |
|
|
.din_3_0_eq_0 (din_43_40_eq_0),
|
| 312 |
|
|
.din_3_2_eq_0 (din_43_42_eq_0),
|
| 313 |
|
|
.lead0_4b_0_lo (lead0_43_40_0),
|
| 314 |
|
|
|
| 315 |
|
|
.din_7_0_eq_0 (din_47_40_eq_0),
|
| 316 |
|
|
.lead0_8b_1 (lead0_47_40_1),
|
| 317 |
|
|
.lead0_8b_0 (lead0_47_40_0)
|
| 318 |
|
|
);
|
| 319 |
|
|
|
| 320 |
|
|
fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_39_32 (
|
| 321 |
|
|
.din_7_4_eq_0 (din_39_36_eq_0),
|
| 322 |
|
|
.din_7_6_eq_0 (din_39_38_eq_0),
|
| 323 |
|
|
.lead0_4b_0_hi (lead0_39_36_0),
|
| 324 |
|
|
.din_3_0_eq_0 (din_35_32_eq_0),
|
| 325 |
|
|
.din_3_2_eq_0 (din_35_34_eq_0),
|
| 326 |
|
|
.lead0_4b_0_lo (lead0_35_32_0),
|
| 327 |
|
|
|
| 328 |
|
|
.din_7_0_eq_0 (din_39_32_eq_0),
|
| 329 |
|
|
.lead0_8b_1 (lead0_39_32_1),
|
| 330 |
|
|
.lead0_8b_0 (lead0_39_32_0)
|
| 331 |
|
|
);
|
| 332 |
|
|
|
| 333 |
|
|
fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_31_24 (
|
| 334 |
|
|
.din_7_4_eq_0 (din_31_28_eq_0),
|
| 335 |
|
|
.din_7_6_eq_0 (din_31_30_eq_0),
|
| 336 |
|
|
.lead0_4b_0_hi (lead0_31_28_0),
|
| 337 |
|
|
.din_3_0_eq_0 (din_27_24_eq_0),
|
| 338 |
|
|
.din_3_2_eq_0 (din_27_26_eq_0),
|
| 339 |
|
|
.lead0_4b_0_lo (lead0_27_24_0),
|
| 340 |
|
|
|
| 341 |
|
|
.din_7_0_eq_0 (din_31_24_eq_0),
|
| 342 |
|
|
.lead0_8b_1 (lead0_31_24_1),
|
| 343 |
|
|
.lead0_8b_0 (lead0_31_24_0)
|
| 344 |
|
|
);
|
| 345 |
|
|
|
| 346 |
|
|
fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_23_16 (
|
| 347 |
|
|
.din_7_4_eq_0 (din_23_20_eq_0),
|
| 348 |
|
|
.din_7_6_eq_0 (din_23_22_eq_0),
|
| 349 |
|
|
.lead0_4b_0_hi (lead0_23_20_0),
|
| 350 |
|
|
.din_3_0_eq_0 (din_19_16_eq_0),
|
| 351 |
|
|
.din_3_2_eq_0 (din_19_18_eq_0),
|
| 352 |
|
|
.lead0_4b_0_lo (lead0_19_16_0),
|
| 353 |
|
|
|
| 354 |
|
|
.din_7_0_eq_0 (din_23_16_eq_0),
|
| 355 |
|
|
.lead0_8b_1 (lead0_23_16_1),
|
| 356 |
|
|
.lead0_8b_0 (lead0_23_16_0)
|
| 357 |
|
|
);
|
| 358 |
|
|
|
| 359 |
|
|
fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_15_8 (
|
| 360 |
|
|
.din_7_4_eq_0 (din_15_12_eq_0),
|
| 361 |
|
|
.din_7_6_eq_0 (din_15_14_eq_0),
|
| 362 |
|
|
.lead0_4b_0_hi (lead0_15_12_0),
|
| 363 |
|
|
.din_3_0_eq_0 (din_11_8_eq_0),
|
| 364 |
|
|
.din_3_2_eq_0 (din_11_10_eq_0),
|
| 365 |
|
|
.lead0_4b_0_lo (lead0_11_8_0),
|
| 366 |
|
|
|
| 367 |
|
|
.din_7_0_eq_0 (din_15_8_eq_0),
|
| 368 |
|
|
.lead0_8b_1 (lead0_15_8_1),
|
| 369 |
|
|
.lead0_8b_0 (lead0_15_8_0)
|
| 370 |
|
|
);
|
| 371 |
|
|
|
| 372 |
|
|
fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_7_0 (
|
| 373 |
|
|
.din_7_4_eq_0 (din_7_4_eq_0),
|
| 374 |
|
|
.din_7_6_eq_0 (din_7_6_eq_0),
|
| 375 |
|
|
.lead0_4b_0_hi (lead0_7_4_0),
|
| 376 |
|
|
.din_3_0_eq_0 (din_3_0_eq_0),
|
| 377 |
|
|
.din_3_2_eq_0 (din_3_2_eq_0),
|
| 378 |
|
|
.lead0_4b_0_lo (lead0_3_0_0),
|
| 379 |
|
|
|
| 380 |
|
|
.din_7_0_eq_0 (din_7_0_eq_0),
|
| 381 |
|
|
.lead0_8b_1 (lead0_7_0_1),
|
| 382 |
|
|
.lead0_8b_0 (lead0_7_0_0)
|
| 383 |
|
|
);
|
| 384 |
|
|
|
| 385 |
|
|
|
| 386 |
|
|
fpu_cnt_lead0_lvl3 i_fpu_cnt_lead0_lvl3_63_48 (
|
| 387 |
|
|
.din_15_8_eq_0 (din_63_56_eq_0),
|
| 388 |
|
|
.din_15_12_eq_0 (din_63_60_eq_0),
|
| 389 |
|
|
.lead0_8b_1_hi (lead0_63_56_1),
|
| 390 |
|
|
.lead0_8b_0_hi (lead0_63_56_0),
|
| 391 |
|
|
.din_7_0_eq_0 (din_55_48_eq_0),
|
| 392 |
|
|
.din_7_4_eq_0 (din_55_52_eq_0),
|
| 393 |
|
|
.lead0_8b_1_lo (lead0_55_48_1),
|
| 394 |
|
|
.lead0_8b_0_lo (lead0_55_48_0),
|
| 395 |
|
|
|
| 396 |
|
|
.din_15_0_eq_0 (din_63_48_eq_0),
|
| 397 |
|
|
.lead0_16b_2 (lead0_63_48_2),
|
| 398 |
|
|
.lead0_16b_1 (lead0_63_48_1),
|
| 399 |
|
|
.lead0_16b_0 (lead0_63_48_0)
|
| 400 |
|
|
);
|
| 401 |
|
|
|
| 402 |
|
|
fpu_cnt_lead0_lvl3 i_fpu_cnt_lead0_lvl3_47_32 (
|
| 403 |
|
|
.din_15_8_eq_0 (din_47_40_eq_0),
|
| 404 |
|
|
.din_15_12_eq_0 (din_47_44_eq_0),
|
| 405 |
|
|
.lead0_8b_1_hi (lead0_47_40_1),
|
| 406 |
|
|
.lead0_8b_0_hi (lead0_47_40_0),
|
| 407 |
|
|
.din_7_0_eq_0 (din_39_32_eq_0),
|
| 408 |
|
|
.din_7_4_eq_0 (din_39_36_eq_0),
|
| 409 |
|
|
.lead0_8b_1_lo (lead0_39_32_1),
|
| 410 |
|
|
.lead0_8b_0_lo (lead0_39_32_0),
|
| 411 |
|
|
|
| 412 |
|
|
.din_15_0_eq_0 (din_47_32_eq_0),
|
| 413 |
|
|
.lead0_16b_2 (lead0_47_32_2),
|
| 414 |
|
|
.lead0_16b_1 (lead0_47_32_1),
|
| 415 |
|
|
.lead0_16b_0 (lead0_47_32_0)
|
| 416 |
|
|
);
|
| 417 |
|
|
|
| 418 |
|
|
fpu_cnt_lead0_lvl3 i_fpu_cnt_lead0_lvl3_31_16 (
|
| 419 |
|
|
.din_15_8_eq_0 (din_31_24_eq_0),
|
| 420 |
|
|
.din_15_12_eq_0 (din_31_28_eq_0),
|
| 421 |
|
|
.lead0_8b_1_hi (lead0_31_24_1),
|
| 422 |
|
|
.lead0_8b_0_hi (lead0_31_24_0),
|
| 423 |
|
|
.din_7_0_eq_0 (din_23_16_eq_0),
|
| 424 |
|
|
.din_7_4_eq_0 (din_23_20_eq_0),
|
| 425 |
|
|
.lead0_8b_1_lo (lead0_23_16_1),
|
| 426 |
|
|
.lead0_8b_0_lo (lead0_23_16_0),
|
| 427 |
|
|
|
| 428 |
|
|
.din_15_0_eq_0 (din_31_16_eq_0),
|
| 429 |
|
|
.lead0_16b_2 (lead0_31_16_2),
|
| 430 |
|
|
.lead0_16b_1 (lead0_31_16_1),
|
| 431 |
|
|
.lead0_16b_0 (lead0_31_16_0)
|
| 432 |
|
|
);
|
| 433 |
|
|
|
| 434 |
|
|
fpu_cnt_lead0_lvl3 i_fpu_cnt_lead0_lvl3_15_0 (
|
| 435 |
|
|
.din_15_8_eq_0 (din_15_8_eq_0),
|
| 436 |
|
|
.din_15_12_eq_0 (din_15_12_eq_0),
|
| 437 |
|
|
.lead0_8b_1_hi (lead0_15_8_1),
|
| 438 |
|
|
.lead0_8b_0_hi (lead0_15_8_0),
|
| 439 |
|
|
.din_7_0_eq_0 (din_7_0_eq_0),
|
| 440 |
|
|
.din_7_4_eq_0 (din_7_4_eq_0),
|
| 441 |
|
|
.lead0_8b_1_lo (lead0_7_0_1),
|
| 442 |
|
|
.lead0_8b_0_lo (lead0_7_0_0),
|
| 443 |
|
|
|
| 444 |
|
|
.din_15_0_eq_0 (din_15_0_eq_0),
|
| 445 |
|
|
.lead0_16b_2 (lead0_15_0_2),
|
| 446 |
|
|
.lead0_16b_1 (lead0_15_0_1),
|
| 447 |
|
|
.lead0_16b_0 (lead0_15_0_0)
|
| 448 |
|
|
);
|
| 449 |
|
|
|
| 450 |
|
|
|
| 451 |
|
|
fpu_cnt_lead0_lvl4 i_fpu_cnt_lead0_lvl4_63_32 (
|
| 452 |
|
|
.din_31_16_eq_0 (din_63_48_eq_0),
|
| 453 |
|
|
.din_31_24_eq_0 (din_63_56_eq_0),
|
| 454 |
|
|
.lead0_16b_2_hi (lead0_63_48_2),
|
| 455 |
|
|
.lead0_16b_1_hi (lead0_63_48_1),
|
| 456 |
|
|
.lead0_16b_0_hi (lead0_63_48_0),
|
| 457 |
|
|
.din_15_0_eq_0 (din_47_32_eq_0),
|
| 458 |
|
|
.din_15_8_eq_0 (din_47_40_eq_0),
|
| 459 |
|
|
.lead0_16b_2_lo (lead0_47_32_2),
|
| 460 |
|
|
.lead0_16b_1_lo (lead0_47_32_1),
|
| 461 |
|
|
.lead0_16b_0_lo (lead0_47_32_0),
|
| 462 |
|
|
|
| 463 |
|
|
.din_31_0_eq_0 (din_63_32_eq_0),
|
| 464 |
|
|
.lead0_32b_3 (lead0_63_32_3),
|
| 465 |
|
|
.lead0_32b_2 (lead0_63_32_2),
|
| 466 |
|
|
.lead0_32b_1 (lead0_63_32_1),
|
| 467 |
|
|
.lead0_32b_0 (lead0_63_32_0)
|
| 468 |
|
|
);
|
| 469 |
|
|
|
| 470 |
|
|
fpu_cnt_lead0_lvl4 i_fpu_cnt_lead0_lvl4_31_0 (
|
| 471 |
|
|
.din_31_16_eq_0 (din_31_16_eq_0),
|
| 472 |
|
|
.din_31_24_eq_0 (din_31_24_eq_0),
|
| 473 |
|
|
.lead0_16b_2_hi (lead0_31_16_2),
|
| 474 |
|
|
.lead0_16b_1_hi (lead0_31_16_1),
|
| 475 |
|
|
.lead0_16b_0_hi (lead0_31_16_0),
|
| 476 |
|
|
.din_15_0_eq_0 (din_15_0_eq_0),
|
| 477 |
|
|
.din_15_8_eq_0 (din_15_8_eq_0),
|
| 478 |
|
|
.lead0_16b_2_lo (lead0_15_0_2),
|
| 479 |
|
|
.lead0_16b_1_lo (lead0_15_0_1),
|
| 480 |
|
|
.lead0_16b_0_lo (lead0_15_0_0),
|
| 481 |
|
|
|
| 482 |
|
|
.din_31_0_eq_0 (din_31_0_eq_0),
|
| 483 |
|
|
.lead0_32b_3 (lead0_31_0_3),
|
| 484 |
|
|
.lead0_32b_2 (lead0_31_0_2),
|
| 485 |
|
|
.lead0_32b_1 (lead0_31_0_1),
|
| 486 |
|
|
.lead0_32b_0 (lead0_31_0_0)
|
| 487 |
|
|
);
|
| 488 |
|
|
|
| 489 |
|
|
|
| 490 |
|
|
assign lead0_6= din_63_32_eq_0 && din_31_0_eq_0;
|
| 491 |
|
|
|
| 492 |
|
|
assign lead0_5= (!lead0_6) && din_63_32_eq_0;
|
| 493 |
|
|
|
| 494 |
|
|
assign lead0_4= ((!din_63_32_eq_0) && din_63_48_eq_0)
|
| 495 |
|
|
|| (din_63_32_eq_0 && din_31_16_eq_0 && (!lead0_6));
|
| 496 |
|
|
|
| 497 |
|
|
assign lead0_3= ((!din_63_32_eq_0) && lead0_63_32_3)
|
| 498 |
|
|
|| (din_63_32_eq_0 && lead0_31_0_3 && (!lead0_6));
|
| 499 |
|
|
|
| 500 |
|
|
assign lead0_2= ((!din_63_32_eq_0) && lead0_63_32_2)
|
| 501 |
|
|
|| (din_63_32_eq_0 && lead0_31_0_2 && (!lead0_6));
|
| 502 |
|
|
|
| 503 |
|
|
assign lead0_1= ((!din_63_32_eq_0) && lead0_63_32_1)
|
| 504 |
|
|
|| (din_63_32_eq_0 && lead0_31_0_1 && (!lead0_6));
|
| 505 |
|
|
|
| 506 |
|
|
assign lead0_0= ((!din_63_32_eq_0) && lead0_63_32_0)
|
| 507 |
|
|
|| (din_63_32_eq_0 && lead0_31_0_0 && (!lead0_6));
|
| 508 |
|
|
|
| 509 |
|
|
assign lead0[5:0]= {lead0_5, lead0_4, lead0_3, lead0_2, lead0_1,
|
| 510 |
|
|
lead0_0};
|
| 511 |
|
|
|
| 512 |
|
|
|
| 513 |
|
|
endmodule
|
| 514 |
|
|
|
| 515 |
|
|
|
