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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: fpu_cnt_lead0_lvl3.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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///////////////////////////////////////////////////////////////////////////////
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//
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// 3rd level of lead 0 counters. Lead 0 count for 16 bits.
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//
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///////////////////////////////////////////////////////////////////////////////
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module fpu_cnt_lead0_lvl3 (
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din_15_8_eq_0,
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din_15_12_eq_0,
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lead0_8b_1_hi,
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lead0_8b_0_hi,
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din_7_0_eq_0,
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din_7_4_eq_0,
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lead0_8b_1_lo,
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lead0_8b_0_lo,
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din_15_0_eq_0,
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lead0_16b_2,
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lead0_16b_1,
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lead0_16b_0
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);
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input din_15_8_eq_0; // data in[15:8] is zero
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input din_15_12_eq_0; // data in[15:12] is zero
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input lead0_8b_1_hi; // bit[1] of lead 0 count- din[15:8]
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input lead0_8b_0_hi; // bit[0] of lead 0 count- din[15:8]
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input din_7_0_eq_0; // data in[7:0] is zero
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input din_7_4_eq_0; // data in[7:4] is zero
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input lead0_8b_1_lo; // bit[1] of lead 0 count- din[7:0]
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input lead0_8b_0_lo; // bit[0] of lead 0 count- din[7:0]
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output din_15_0_eq_0; // data in[15:0] is zero
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output lead0_16b_2; // bit[2] of lead 0 count
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output lead0_16b_1; // bit[1] of lead 0 count
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output lead0_16b_0; // bit[0] of lead 0 count
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wire din_15_0_eq_0;
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wire lead0_16b_2;
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wire lead0_16b_1;
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wire lead0_16b_0;
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assign din_15_0_eq_0= din_7_0_eq_0 && din_15_8_eq_0;
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assign lead0_16b_2= ((!din_15_8_eq_0) && din_15_12_eq_0)
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|| (din_15_8_eq_0 && din_7_4_eq_0);
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assign lead0_16b_1= ((!din_15_8_eq_0) && lead0_8b_1_hi)
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|| (din_15_8_eq_0 && lead0_8b_1_lo);
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assign lead0_16b_0= ((!din_15_8_eq_0) && lead0_8b_0_hi)
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|| (din_15_8_eq_0 && lead0_8b_0_lo);
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endmodule
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