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[/] [sparc64soc/] [trunk/] [T1-FPU/] [fpu_denorm_3b.v] - Blame information for rev 2

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1 2 dmitryr
// ========== Copyright Header Begin ==========================================
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// 
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// OpenSPARC T1 Processor File: fpu_denorm_3b.v
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// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// 
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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// 
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// The above named program is distributed in the hope that it will be 
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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// General Public License for more details.
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// 
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// 
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// ========== Copyright Header End ============================================
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///////////////////////////////////////////////////////////////////////////////
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//
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//      Three bit comparison of two inputs when both will always have
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//              leading 0s.
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//
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///////////////////////////////////////////////////////////////////////////////
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module fpu_denorm_3b (
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        din1,
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        din2,
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        din2_din1_nz,
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        din2_din1_denorm
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);
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input [2:0]     din1;                   // input 1- 3 bits
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input [2:0]     din2;                   // input 2- 3 bits
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output          din2_din1_nz;           // input 1 and input 2 are not 0
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output          din2_din1_denorm;       // input 1 is a denorm
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wire [2:0]       din2_din1_zero;
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wire            din2_din1_nz;
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wire            din2_din1_denorm;
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assign din2_din1_zero[2:0]= (~(din1 | din2));
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assign din2_din1_nz= (!(&din2_din1_zero[2:0]));
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assign din2_din1_denorm= din2[2]
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                || (din2_din1_zero[2] && din2[1])
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                || ((&din2_din1_zero[2:1]) && din2[0]);
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endmodule
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