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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: fpu_div.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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///////////////////////////////////////////////////////////////////////////////
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//
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// FPU divide pipe.
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//
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///////////////////////////////////////////////////////////////////////////////
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module fpu_div (
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inq_op,
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inq_rnd_mode,
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inq_id,
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inq_in1,
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inq_in1_53_0_neq_0,
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inq_in1_50_0_neq_0,
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inq_in1_53_32_neq_0,
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inq_in1_exp_eq_0,
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inq_in1_exp_neq_ffs,
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inq_in2,
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inq_in2_53_0_neq_0,
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inq_in2_50_0_neq_0,
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inq_in2_53_32_neq_0,
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inq_in2_exp_eq_0,
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inq_in2_exp_neq_ffs,
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inq_div,
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div_dest_rdy,
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fdiv_clken_l,
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fdiv_clken_l_div_exp_buf1,
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arst_l,
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grst_l,
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rclk,
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div_pipe_active,
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d1stg_step,
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d8stg_fdiv_in,
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div_id_out_in,
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div_exc_out,
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d8stg_fdivd,
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d8stg_fdivs,
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div_sign_out,
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div_exp_outa,
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div_frac_outa,
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se,
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si,
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so
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);
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input [7:0] inq_op; // request opcode to op pipes
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input [1:0] inq_rnd_mode; // request rounding mode to op pipes
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input [4:0] inq_id; // request ID to the operation pipes
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input [63:0] inq_in1; // request operand 1 to op pipes
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input inq_in1_53_0_neq_0; // request operand 1[53:0]!=0
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input inq_in1_50_0_neq_0; // request operand 1[50:0]!=0
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input inq_in1_53_32_neq_0; // request operand 1[53:32]!=0
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input inq_in1_exp_eq_0; // request operand 1 exp==0
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input inq_in1_exp_neq_ffs; // request operand 1 exp!=0xff's
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input [63:0] inq_in2; // request operand 2 to op pipes
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input inq_in2_53_0_neq_0; // request operand 2[53:0]!=0
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input inq_in2_50_0_neq_0; // request operand 2[50:0]!=0
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input inq_in2_53_32_neq_0; // request operand 2[53:32]!=0
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input inq_in2_exp_eq_0; // request operand 2 exp==0
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input inq_in2_exp_neq_ffs; // request operand 2 exp!=0xff's
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input inq_div; // divide pipe request
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input div_dest_rdy; // divide result req accepted for CPX
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input fdiv_clken_l; // fdiv clock enable for div_frac_dp
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input fdiv_clken_l_div_exp_buf1; // fdiv clock enable for div_exp_dp
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input arst_l; // global async. reset- asserted low
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input grst_l; // global sync. reset- asserted low
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input rclk; // global clock
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output div_pipe_active; // div pipe is executing a valid instr
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output d1stg_step; // divide pipe load
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output d8stg_fdiv_in; // div pipe output request next cycle
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output [9:0] div_id_out_in; // div pipe output ID next cycle
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output [4:0] div_exc_out; // divide pipe result- exception flags
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output d8stg_fdivd; // divide double- divide stage 8
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output d8stg_fdivs; // divide single- divide stage 8
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output div_sign_out; // divide sign output
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output [10:0] div_exp_outa; // divide exponent output
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output [51:0] div_frac_outa; // divide fraction output
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input se; // scan_enable
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input si; // scan in
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output so; // scan out
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///////////////////////////////////////////////////////////////////////////////
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//
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// Outputs of fpu_div_ctl.
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//
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///////////////////////////////////////////////////////////////////////////////
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wire d1stg_snan_sng_in1; // operand 1 is single signalling NaN
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wire d1stg_snan_dbl_in1; // operand 1 is double signalling NaN
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wire d1stg_snan_sng_in2; // operand 2 is single signalling NaN
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wire d1stg_snan_dbl_in2; // operand 2 is double signalling NaN
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wire d1stg_step; // divide pipe load
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wire d1stg_dblop; // double precision operation- d1 stg
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wire d234stg_fdiv; // select line to div_expadd1
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wire d3stg_fdiv; // divide operation- divide stage 3
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wire d4stg_fdiv; // divide operation- divide stage 4
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wire d5stg_fdiva; // divide operation- divide stage 5
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wire d5stg_fdivb; // divide operation- divide stage 5
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wire d5stg_fdivs; // divide single- divide stage 5
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wire d5stg_fdivd; // divide double- divide stage 5
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wire d6stg_fdiv; // divide operation- divide stage 6
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wire d6stg_fdivs; // divide single- divide stage 6
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wire d6stg_fdivd; // divide double- divide stage 6
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wire d7stg_fdiv; // divide operation- divide stage 7
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wire d7stg_fdivd; // divide double- divide stage 7
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wire d8stg_fdiv_in; // div pipe output request next cycle
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wire d8stg_fdivs; // divide single- divide stage 8
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wire d8stg_fdivd; // divide double- divide stage 8
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wire [9:0] div_id_out_in; // div pipe output ID next cycle
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wire div_sign_out; // divide sign output
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wire [4:0] div_exc_out; // divide pipe result- exception flags
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wire div_norm_frac_in1_dbl_norm; // select line to div_norm
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wire div_norm_frac_in1_dbl_dnrm; // select line to div_norm
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wire div_norm_frac_in1_sng_norm; // select line to div_norm
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wire div_norm_frac_in1_sng_dnrm; // select line to div_norm
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wire div_norm_frac_in2_dbl_norm; // select line to div_norm
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wire div_norm_frac_in2_dbl_dnrm; // select line to div_norm
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wire div_norm_frac_in2_sng_norm; // select line to div_norm
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wire div_norm_frac_in2_sng_dnrm; // select line to div_norm
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wire div_norm_inf; // select line to div_norm
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wire div_norm_qnan; // select line to div_norm
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wire div_norm_zero; // select line to div_norm
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wire div_frac_add_in2_load; // load enable to div_frac_add_in2
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wire d6stg_frac_out_shl1; // select line to d6stg_frac
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wire d6stg_frac_out_nosh; // select line to d6stg_frac
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wire div_frac_add_in1_add; // select line to div_frac_add_in1
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wire div_frac_add_in1_load; // load enable to div_frac_add_in1
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wire d7stg_rndup_inv; // no rounding increment
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wire d7stg_to_0; // result to max finite on overflow
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wire d7stg_to_0_inv; // result to infinity on overflow
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wire div_frac_out_add_in1; // select line to div_frac_out
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wire div_frac_out_add; // select line to div_frac_out
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wire div_frac_out_shl1_dbl; // select line to div_frac_out
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wire div_frac_out_shl1_sng; // select line to div_frac_out
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wire div_frac_out_of; // select line to div_frac_out
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wire div_frac_out_load; // load enable to div_frac_out
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wire div_expadd1_in1_dbl; // select line to div_expadd1
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wire div_expadd1_in1_sng; // select line to div_expadd1
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wire div_expadd1_in2_exp_in2_dbl; // select line to div_expadd1
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wire div_expadd1_in2_exp_in2_sng; //select line to div_expadd1
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wire div_exp1_expadd1; // select line to div_exp1
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wire div_exp1_0835; // select line to div_exp1
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wire div_exp1_0118; // select line to div_exp1
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wire div_exp1_zero; // select line to div_exp1
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wire div_exp1_load; // load enable to div_exp1
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wire div_expadd2_in1_exp_out; // select line to div_expadd2
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wire div_expadd2_no_decr_inv; // no exponent decrement
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wire div_expadd2_cin; // carry in to 2nd exponent adder
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wire div_exp_out_expadd22_inv; // select line to div_exp_out
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wire div_exp_out_expadd2; // select line to div_exp_out
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wire div_exp_out_of; // overflow to exponent output
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wire div_exp_out_exp_out; // select line to div_exp_out
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wire div_exp_out_load; // load enable to div_exp_out
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wire div_pipe_active; // div pipe is executing a valid instr
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///////////////////////////////////////////////////////////////////////////////
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//
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// Outputs of fpu_div_exp_dp.
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//
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///////////////////////////////////////////////////////////////////////////////
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wire [12:0] div_exp1; // divide exponent- intermediate value
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wire [12:12] div_expadd2; // divide exponent- 2nd adder output
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wire [12:0] div_exp_out; // divide exponent output- fpu_div
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wire [10:0] div_exp_outa; // divide exponent output
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///////////////////////////////////////////////////////////////////////////////
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//
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// Outputs of fpu_div_frac_dp.
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//
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///////////////////////////////////////////////////////////////////////////////
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wire [5:0] div_shl_cnt; // divide left shift amount
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wire d6stg_frac_0; // divide fraction[0]- intermediate val
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wire d6stg_frac_1; // divide fraction[1]- intermediate val
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wire d6stg_frac_2; // divide fraction[2]- intermediate val
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wire d6stg_frac_29; // divide fraction[29]- intermediate val
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wire d6stg_frac_30; // divide fraction[30]- intermediate val
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wire d6stg_frac_31; // divide fraction[31]- intermediate val
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wire div_frac_add_in1_neq_0; // div_frac_add_in1 != 0
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wire div_frac_add_52_inv; // div_frac_add bit[52] inverted
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wire div_frac_add_52_inva; // div_frac_add bit[52] inverted copy
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wire [54:53] div_frac_out; // divide fraction output- fpu_div
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wire [51:0] div_frac_outa; // divide fraction output
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///////////////////////////////////////////////////////////////////////////////
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//
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// Instantiations.
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//
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///////////////////////////////////////////////////////////////////////////////
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fpu_div_ctl fpu_div_ctl (
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.inq_in1_51 (inq_in1[51]),
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.inq_in1_54 (inq_in1[54]),
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.inq_in1_53_0_neq_0 (inq_in1_53_0_neq_0),
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.inq_in1_50_0_neq_0 (inq_in1_50_0_neq_0),
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.inq_in1_53_32_neq_0 (inq_in1_53_32_neq_0),
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.inq_in1_exp_eq_0 (inq_in1_exp_eq_0),
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.inq_in1_exp_neq_ffs (inq_in1_exp_neq_ffs),
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.inq_in2_51 (inq_in2[51]),
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.inq_in2_54 (inq_in2[54]),
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.inq_in2_53_0_neq_0 (inq_in2_53_0_neq_0),
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.inq_in2_50_0_neq_0 (inq_in2_50_0_neq_0),
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| 233 |
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.inq_in2_53_32_neq_0 (inq_in2_53_32_neq_0),
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| 234 |
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.inq_in2_exp_eq_0 (inq_in2_exp_eq_0),
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| 235 |
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.inq_in2_exp_neq_ffs (inq_in2_exp_neq_ffs),
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.inq_op (inq_op[7:0]),
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| 237 |
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.div_exp1 (div_exp1[12:0]),
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| 238 |
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.div_dest_rdy (div_dest_rdy),
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| 239 |
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.inq_rnd_mode (inq_rnd_mode[1:0]),
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| 240 |
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.inq_id (inq_id[4:0]),
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| 241 |
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.inq_in1_63 (inq_in1[63]),
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| 242 |
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.inq_in2_63 (inq_in2[63]),
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| 243 |
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.inq_div (inq_div),
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| 244 |
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.div_exp_out (div_exp_out[12:0]),
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| 245 |
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.div_frac_add_52_inva (div_frac_add_52_inva),
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| 246 |
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.div_frac_add_in1_neq_0 (div_frac_add_in1_neq_0),
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| 247 |
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.div_frac_out_54 (div_frac_out[54]),
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| 248 |
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.d6stg_frac_0 (d6stg_frac_0),
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| 249 |
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.d6stg_frac_1 (d6stg_frac_1),
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| 250 |
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.d6stg_frac_2 (d6stg_frac_2),
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| 251 |
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.d6stg_frac_29 (d6stg_frac_29),
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| 252 |
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.d6stg_frac_30 (d6stg_frac_30),
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| 253 |
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.d6stg_frac_31 (d6stg_frac_31),
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| 254 |
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.div_frac_out_53 (div_frac_out[53]),
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| 255 |
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.div_expadd2_12 (div_expadd2[12]),
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| 256 |
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.arst_l (arst_l),
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| 257 |
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.grst_l (grst_l),
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| 258 |
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.rclk (rclk),
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| 259 |
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| 260 |
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.div_pipe_active (div_pipe_active),
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| 261 |
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.d1stg_snan_sng_in1 (d1stg_snan_sng_in1),
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| 262 |
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.d1stg_snan_dbl_in1 (d1stg_snan_dbl_in1),
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| 263 |
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.d1stg_snan_sng_in2 (d1stg_snan_sng_in2),
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| 264 |
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.d1stg_snan_dbl_in2 (d1stg_snan_dbl_in2),
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| 265 |
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.d1stg_step (d1stg_step),
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| 266 |
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.d1stg_dblop (d1stg_dblop),
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| 267 |
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.d234stg_fdiv (d234stg_fdiv),
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| 268 |
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.d3stg_fdiv (d3stg_fdiv),
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| 269 |
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.d4stg_fdiv (d4stg_fdiv),
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| 270 |
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.d5stg_fdiva (d5stg_fdiva),
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| 271 |
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.d5stg_fdivb (d5stg_fdivb),
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| 272 |
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.d5stg_fdivs (d5stg_fdivs),
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| 273 |
|
|
.d5stg_fdivd (d5stg_fdivd),
|
| 274 |
|
|
.d6stg_fdiv (d6stg_fdiv),
|
| 275 |
|
|
.d6stg_fdivs (d6stg_fdivs),
|
| 276 |
|
|
.d6stg_fdivd (d6stg_fdivd),
|
| 277 |
|
|
.d7stg_fdiv (d7stg_fdiv),
|
| 278 |
|
|
.d7stg_fdivd (d7stg_fdivd),
|
| 279 |
|
|
.d8stg_fdiv_in (d8stg_fdiv_in),
|
| 280 |
|
|
.d8stg_fdivs (d8stg_fdivs),
|
| 281 |
|
|
.d8stg_fdivd (d8stg_fdivd),
|
| 282 |
|
|
.div_id_out_in (div_id_out_in[9:0]),
|
| 283 |
|
|
.div_sign_out (div_sign_out),
|
| 284 |
|
|
.div_exc_out (div_exc_out[4:0]),
|
| 285 |
|
|
.div_norm_frac_in1_dbl_norm (div_norm_frac_in1_dbl_norm),
|
| 286 |
|
|
.div_norm_frac_in1_dbl_dnrm (div_norm_frac_in1_dbl_dnrm),
|
| 287 |
|
|
.div_norm_frac_in1_sng_norm (div_norm_frac_in1_sng_norm),
|
| 288 |
|
|
.div_norm_frac_in1_sng_dnrm (div_norm_frac_in1_sng_dnrm),
|
| 289 |
|
|
.div_norm_frac_in2_dbl_norm (div_norm_frac_in2_dbl_norm),
|
| 290 |
|
|
.div_norm_frac_in2_dbl_dnrm (div_norm_frac_in2_dbl_dnrm),
|
| 291 |
|
|
.div_norm_frac_in2_sng_norm (div_norm_frac_in2_sng_norm),
|
| 292 |
|
|
.div_norm_frac_in2_sng_dnrm (div_norm_frac_in2_sng_dnrm),
|
| 293 |
|
|
.div_norm_inf (div_norm_inf),
|
| 294 |
|
|
.div_norm_qnan (div_norm_qnan),
|
| 295 |
|
|
.div_norm_zero (div_norm_zero),
|
| 296 |
|
|
.div_frac_add_in2_load (div_frac_add_in2_load),
|
| 297 |
|
|
.d6stg_frac_out_shl1 (d6stg_frac_out_shl1),
|
| 298 |
|
|
.d6stg_frac_out_nosh (d6stg_frac_out_nosh),
|
| 299 |
|
|
.div_frac_add_in1_add (div_frac_add_in1_add),
|
| 300 |
|
|
.div_frac_add_in1_load (div_frac_add_in1_load),
|
| 301 |
|
|
.d7stg_rndup_inv (d7stg_rndup_inv),
|
| 302 |
|
|
.d7stg_to_0 (d7stg_to_0),
|
| 303 |
|
|
.d7stg_to_0_inv (d7stg_to_0_inv),
|
| 304 |
|
|
.div_frac_out_add_in1 (div_frac_out_add_in1),
|
| 305 |
|
|
.div_frac_out_add (div_frac_out_add),
|
| 306 |
|
|
.div_frac_out_shl1_dbl (div_frac_out_shl1_dbl),
|
| 307 |
|
|
.div_frac_out_shl1_sng (div_frac_out_shl1_sng),
|
| 308 |
|
|
.div_frac_out_of (div_frac_out_of),
|
| 309 |
|
|
.div_frac_out_load (div_frac_out_load),
|
| 310 |
|
|
.div_expadd1_in1_dbl (div_expadd1_in1_dbl),
|
| 311 |
|
|
.div_expadd1_in1_sng (div_expadd1_in1_sng),
|
| 312 |
|
|
.div_expadd1_in2_exp_in2_dbl (div_expadd1_in2_exp_in2_dbl),
|
| 313 |
|
|
.div_expadd1_in2_exp_in2_sng (div_expadd1_in2_exp_in2_sng),
|
| 314 |
|
|
.div_exp1_expadd1 (div_exp1_expadd1),
|
| 315 |
|
|
.div_exp1_0835 (div_exp1_0835),
|
| 316 |
|
|
.div_exp1_0118 (div_exp1_0118),
|
| 317 |
|
|
.div_exp1_zero (div_exp1_zero),
|
| 318 |
|
|
.div_exp1_load (div_exp1_load),
|
| 319 |
|
|
.div_expadd2_in1_exp_out (div_expadd2_in1_exp_out),
|
| 320 |
|
|
.div_expadd2_no_decr_inv (div_expadd2_no_decr_inv),
|
| 321 |
|
|
.div_expadd2_cin (div_expadd2_cin),
|
| 322 |
|
|
.div_exp_out_expadd22_inv (div_exp_out_expadd22_inv),
|
| 323 |
|
|
.div_exp_out_expadd2 (div_exp_out_expadd2),
|
| 324 |
|
|
.div_exp_out_of (div_exp_out_of),
|
| 325 |
|
|
.div_exp_out_exp_out (div_exp_out_exp_out),
|
| 326 |
|
|
.div_exp_out_load (div_exp_out_load),
|
| 327 |
|
|
|
| 328 |
|
|
.se (se),
|
| 329 |
|
|
.si (si),
|
| 330 |
|
|
.so (scan_out_fpu_div_ctl)
|
| 331 |
|
|
);
|
| 332 |
|
|
|
| 333 |
|
|
|
| 334 |
|
|
fpu_div_exp_dp fpu_div_exp_dp (
|
| 335 |
|
|
.inq_in1 (inq_in1[62:52]),
|
| 336 |
|
|
.inq_in2 (inq_in2[62:52]),
|
| 337 |
|
|
.d1stg_step (d1stg_step),
|
| 338 |
|
|
.d234stg_fdiv (d234stg_fdiv),
|
| 339 |
|
|
.div_expadd1_in1_dbl (div_expadd1_in1_dbl),
|
| 340 |
|
|
.div_expadd1_in1_sng (div_expadd1_in1_sng),
|
| 341 |
|
|
.div_expadd1_in2_exp_in2_dbl (div_expadd1_in2_exp_in2_dbl),
|
| 342 |
|
|
.div_expadd1_in2_exp_in2_sng (div_expadd1_in2_exp_in2_sng),
|
| 343 |
|
|
.d3stg_fdiv (d3stg_fdiv),
|
| 344 |
|
|
.d4stg_fdiv (d4stg_fdiv),
|
| 345 |
|
|
.div_shl_cnt (div_shl_cnt[5:0]),
|
| 346 |
|
|
.div_exp1_expadd1 (div_exp1_expadd1),
|
| 347 |
|
|
.div_exp1_0835 (div_exp1_0835),
|
| 348 |
|
|
.div_exp1_0118 (div_exp1_0118),
|
| 349 |
|
|
.div_exp1_zero (div_exp1_zero),
|
| 350 |
|
|
.div_exp1_load (div_exp1_load),
|
| 351 |
|
|
.div_expadd2_in1_exp_out (div_expadd2_in1_exp_out),
|
| 352 |
|
|
.d5stg_fdiva (d5stg_fdiva),
|
| 353 |
|
|
.d5stg_fdivd (d5stg_fdivd),
|
| 354 |
|
|
.d5stg_fdivs (d5stg_fdivs),
|
| 355 |
|
|
.d6stg_fdiv (d6stg_fdiv),
|
| 356 |
|
|
.d7stg_fdiv (d7stg_fdiv),
|
| 357 |
|
|
.div_expadd2_no_decr_inv (div_expadd2_no_decr_inv),
|
| 358 |
|
|
.div_expadd2_cin (div_expadd2_cin),
|
| 359 |
|
|
.div_exp_out_expadd2 (div_exp_out_expadd2),
|
| 360 |
|
|
.div_exp_out_expadd22_inv (div_exp_out_expadd22_inv),
|
| 361 |
|
|
.div_exp_out_of (div_exp_out_of),
|
| 362 |
|
|
.d7stg_to_0_inv (d7stg_to_0_inv),
|
| 363 |
|
|
.d7stg_fdivd (d7stg_fdivd),
|
| 364 |
|
|
.div_exp_out_exp_out (div_exp_out_exp_out),
|
| 365 |
|
|
.d7stg_rndup_inv (d7stg_rndup_inv),
|
| 366 |
|
|
.div_frac_add_52_inv (div_frac_add_52_inv),
|
| 367 |
|
|
.div_exp_out_load (div_exp_out_load),
|
| 368 |
|
|
.fdiv_clken_l (fdiv_clken_l_div_exp_buf1),
|
| 369 |
|
|
.rclk (rclk),
|
| 370 |
|
|
|
| 371 |
|
|
.div_exp1 (div_exp1[12:0]),
|
| 372 |
|
|
.div_expadd2_12 (div_expadd2[12]),
|
| 373 |
|
|
.div_exp_out (div_exp_out[12:0]),
|
| 374 |
|
|
.div_exp_outa (div_exp_outa[10:0]),
|
| 375 |
|
|
|
| 376 |
|
|
.se (se),
|
| 377 |
|
|
.si (scan_out_fpu_div_ctl),
|
| 378 |
|
|
.so (scan_out_fpu_div_exp_dp)
|
| 379 |
|
|
);
|
| 380 |
|
|
|
| 381 |
|
|
|
| 382 |
|
|
fpu_div_frac_dp fpu_div_frac_dp (
|
| 383 |
|
|
.inq_in1 (inq_in1[54:0]),
|
| 384 |
|
|
.inq_in2 (inq_in2[54:0]),
|
| 385 |
|
|
.d1stg_step (d1stg_step),
|
| 386 |
|
|
.div_norm_frac_in1_dbl_norm (div_norm_frac_in1_dbl_norm),
|
| 387 |
|
|
.div_norm_frac_in1_dbl_dnrm (div_norm_frac_in1_dbl_dnrm),
|
| 388 |
|
|
.div_norm_frac_in1_sng_norm (div_norm_frac_in1_sng_norm),
|
| 389 |
|
|
.div_norm_frac_in1_sng_dnrm (div_norm_frac_in1_sng_dnrm),
|
| 390 |
|
|
.div_norm_frac_in2_dbl_norm (div_norm_frac_in2_dbl_norm),
|
| 391 |
|
|
.div_norm_frac_in2_dbl_dnrm (div_norm_frac_in2_dbl_dnrm),
|
| 392 |
|
|
.div_norm_frac_in2_sng_norm (div_norm_frac_in2_sng_norm),
|
| 393 |
|
|
.div_norm_frac_in2_sng_dnrm (div_norm_frac_in2_sng_dnrm),
|
| 394 |
|
|
.div_norm_inf (div_norm_inf),
|
| 395 |
|
|
.div_norm_qnan (div_norm_qnan),
|
| 396 |
|
|
.d1stg_dblop (d1stg_dblop),
|
| 397 |
|
|
.div_norm_zero (div_norm_zero),
|
| 398 |
|
|
.d1stg_snan_dbl_in1 (d1stg_snan_dbl_in1),
|
| 399 |
|
|
.d1stg_snan_sng_in1 (d1stg_snan_sng_in1),
|
| 400 |
|
|
.d1stg_snan_dbl_in2 (d1stg_snan_dbl_in2),
|
| 401 |
|
|
.d1stg_snan_sng_in2 (d1stg_snan_sng_in2),
|
| 402 |
|
|
.d3stg_fdiv (d3stg_fdiv),
|
| 403 |
|
|
.d6stg_fdiv (d6stg_fdiv),
|
| 404 |
|
|
.d6stg_fdivd (d6stg_fdivd),
|
| 405 |
|
|
.d6stg_fdivs (d6stg_fdivs),
|
| 406 |
|
|
.div_frac_add_in2_load (div_frac_add_in2_load),
|
| 407 |
|
|
.d6stg_frac_out_shl1 (d6stg_frac_out_shl1),
|
| 408 |
|
|
.d6stg_frac_out_nosh (d6stg_frac_out_nosh),
|
| 409 |
|
|
.d4stg_fdiv (d4stg_fdiv),
|
| 410 |
|
|
.div_frac_add_in1_add (div_frac_add_in1_add),
|
| 411 |
|
|
.div_frac_add_in1_load (div_frac_add_in1_load),
|
| 412 |
|
|
.d5stg_fdivb (d5stg_fdivb),
|
| 413 |
|
|
.div_frac_out_add_in1 (div_frac_out_add_in1),
|
| 414 |
|
|
.div_frac_out_add (div_frac_out_add),
|
| 415 |
|
|
.div_frac_out_shl1_dbl (div_frac_out_shl1_dbl),
|
| 416 |
|
|
.div_frac_out_shl1_sng (div_frac_out_shl1_sng),
|
| 417 |
|
|
.div_frac_out_of (div_frac_out_of),
|
| 418 |
|
|
.d7stg_to_0 (d7stg_to_0),
|
| 419 |
|
|
.div_frac_out_load (div_frac_out_load),
|
| 420 |
|
|
.fdiv_clken_l (fdiv_clken_l),
|
| 421 |
|
|
.rclk (rclk),
|
| 422 |
|
|
|
| 423 |
|
|
.div_shl_cnt (div_shl_cnt[5:0]),
|
| 424 |
|
|
.d6stg_frac_0 (d6stg_frac_0),
|
| 425 |
|
|
.d6stg_frac_1 (d6stg_frac_1),
|
| 426 |
|
|
.d6stg_frac_2 (d6stg_frac_2),
|
| 427 |
|
|
.d6stg_frac_29 (d6stg_frac_29),
|
| 428 |
|
|
.d6stg_frac_30 (d6stg_frac_30),
|
| 429 |
|
|
.d6stg_frac_31 (d6stg_frac_31),
|
| 430 |
|
|
.div_frac_add_in1_neq_0 (div_frac_add_in1_neq_0),
|
| 431 |
|
|
.div_frac_add_52_inv (div_frac_add_52_inv),
|
| 432 |
|
|
.div_frac_add_52_inva (div_frac_add_52_inva),
|
| 433 |
|
|
.div_frac_out_54_53 (div_frac_out[54:53]),
|
| 434 |
|
|
.div_frac_outa (div_frac_outa[51:0]),
|
| 435 |
|
|
|
| 436 |
|
|
.se (se),
|
| 437 |
|
|
.si (scan_out_fpu_div_exp_dp),
|
| 438 |
|
|
.so (so)
|
| 439 |
|
|
);
|
| 440 |
|
|
|
| 441 |
|
|
|
| 442 |
|
|
endmodule
|
| 443 |
|
|
|
| 444 |
|
|
|
