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[/] [sparc64soc/] [trunk/] [T1-FPU/] [fpu_div_ctl.v] - Blame information for rev 3

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1 2 dmitryr 
// ========== Copyright Header Begin ==========================================
2 
//
3 
// OpenSPARC T1 Processor File: fpu_div_ctl.v
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// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
8 
// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
10 
//
11 
// The above named program is distributed in the hope that it will be
12 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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// General Public License for more details.
15 
//
16 
// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
18 
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
21 
///////////////////////////////////////////////////////////////////////////////
22 
//
23 
//      Divide pipeline synthesizable logic
24 
//              - special input cases
25 
//              - opcode pipeline
26 
//              - sign logic
27 
//              - exception logic
28 
//              - datapath control- select lines and control logic
29 
//
30 
///////////////////////////////////////////////////////////////////////////////
31 
 
32 
module fpu_div_ctl (
33 
        inq_in1_51,
34 
        inq_in1_54,
35 
        inq_in1_53_0_neq_0,
36 
        inq_in1_50_0_neq_0,
37 
        inq_in1_53_32_neq_0,
38 
        inq_in1_exp_eq_0,
39 
        inq_in1_exp_neq_ffs,
40 
        inq_in2_51,
41 
        inq_in2_54,
42 
        inq_in2_53_0_neq_0,
43 
        inq_in2_50_0_neq_0,
44 
        inq_in2_53_32_neq_0,
45 
        inq_in2_exp_eq_0,
46 
        inq_in2_exp_neq_ffs,
47 
        inq_op,
48 
        div_exp1,
49 
        div_dest_rdy,
50 
        inq_rnd_mode,
51 
        inq_id,
52 
        inq_in1_63,
53 
        inq_in2_63,
54 
        inq_div,
55 
        div_exp_out,
56 
        div_frac_add_52_inva,
57 
        div_frac_add_in1_neq_0,
58 
        div_frac_out_54,
59 
        d6stg_frac_0,
60 
        d6stg_frac_1,
61 
        d6stg_frac_2,
62 
        d6stg_frac_29,
63 
        d6stg_frac_30,
64 
        d6stg_frac_31,
65 
        div_frac_out_53,
66 
        div_expadd2_12,
67 
        arst_l,
68 
        grst_l,
69 
        rclk,
70 
 
71 
        div_pipe_active,
72 
        d1stg_snan_sng_in1,
73 
        d1stg_snan_dbl_in1,
74 
        d1stg_snan_sng_in2,
75 
        d1stg_snan_dbl_in2,
76 
        d1stg_step,
77 
        d1stg_dblop,
78 
        d234stg_fdiv,
79 
        d3stg_fdiv,
80 
        d4stg_fdiv,
81 
        d5stg_fdiva,
82 
        d5stg_fdivb,
83 
        d5stg_fdivs,
84 
        d5stg_fdivd,
85 
        d6stg_fdiv,
86 
        d6stg_fdivs,
87 
        d6stg_fdivd,
88 
        d7stg_fdiv,
89 
        d7stg_fdivd,
90 
        d8stg_fdiv_in,
91 
        d8stg_fdivs,
92 
        d8stg_fdivd,
93 
        div_id_out_in,
94 
        div_sign_out,
95 
        div_exc_out,
96 
        div_norm_frac_in1_dbl_norm,
97 
        div_norm_frac_in1_dbl_dnrm,
98 
        div_norm_frac_in1_sng_norm,
99 
        div_norm_frac_in1_sng_dnrm,
100 
        div_norm_frac_in2_dbl_norm,
101 
        div_norm_frac_in2_dbl_dnrm,
102 
        div_norm_frac_in2_sng_norm,
103 
        div_norm_frac_in2_sng_dnrm,
104 
        div_norm_inf,
105 
        div_norm_qnan,
106 
        div_norm_zero,
107 
        div_frac_add_in2_load,
108 
        d6stg_frac_out_shl1,
109 
        d6stg_frac_out_nosh,
110 
        div_frac_add_in1_add,
111 
        div_frac_add_in1_load,
112 
        d7stg_rndup_inv,
113 
        d7stg_to_0,
114 
        d7stg_to_0_inv,
115 
        div_frac_out_add_in1,
116 
        div_frac_out_add,
117 
        div_frac_out_shl1_dbl,
118 
        div_frac_out_shl1_sng,
119 
        div_frac_out_of,
120 
        div_frac_out_load,
121 
        div_expadd1_in1_dbl,
122 
        div_expadd1_in1_sng,
123 
        div_expadd1_in2_exp_in2_dbl,
124 
        div_expadd1_in2_exp_in2_sng,
125 
        div_exp1_expadd1,
126 
        div_exp1_0835,
127 
        div_exp1_0118,
128 
        div_exp1_zero,
129 
        div_exp1_load,
130 
        div_expadd2_in1_exp_out,
131 
        div_expadd2_no_decr_inv,
132 
        div_expadd2_cin,
133 
        div_exp_out_expadd22_inv,
134 
        div_exp_out_expadd2,
135 
        div_exp_out_of,
136 
        div_exp_out_exp_out,
137 
        div_exp_out_load,
138 
 
139 
        se,
140 
        si,
141 
        so
142 
);
143 
 
144 
 
145 
parameter
146 
                FDIVS=  8'h4d,
147 
                FDIVD=  8'h4e;
148 
 
149 
 
150 
input           inq_in1_51;             // request operand 1[51]
151 
input           inq_in1_54;             // request operand 1[54]
152 
input           inq_in1_53_0_neq_0;     // request operand 1[53:0]!=0
153 
input           inq_in1_50_0_neq_0;     // request operand 1[50:0]!=0
154 
input           inq_in1_53_32_neq_0;    // request operand 1[53:32]!=0
155 
input           inq_in1_exp_eq_0;       // request operand 1[62:52]==0
156 
input           inq_in1_exp_neq_ffs;    // request operand 1[62:52]!=0x7ff
157 
input           inq_in2_51;             // request operand 2[51]
158 
input           inq_in2_54;             // request operand 2[54]
159 
input           inq_in2_53_0_neq_0;     // request operand 2[53:0]!=0
160 
input           inq_in2_50_0_neq_0;     // request operand 2[50:0]!=0
161 
input           inq_in2_53_32_neq_0;    // request operand 2[53:32]!=0
162 
input           inq_in2_exp_eq_0;       // request operand 2[62:52]==0
163 
input           inq_in2_exp_neq_ffs;    // request operand 2[62:52]!=0x7ff
164 
input [7:0]      inq_op;                 // request opcode to op pipes
165 
input [12:0]     div_exp1;               // divide exponent- intermediate value
166 
input           div_dest_rdy;           // divide result req accepted for CPX
167 
input [1:0]      inq_rnd_mode;           // request rounding mode to op pipes
168 
input [4:0]      inq_id;                 // request ID to the operation pipes
169 
input           inq_in1_63;             // request operand 1 to op pipes- sign
170 
input           inq_in2_63;             // request operand 2 to op pipes- sign
171 
input           inq_div;                // divide pipe request
172 
input [12:0]     div_exp_out;            // divide exponent output
173 
input           div_frac_add_52_inva;   // div_frac_add bit[52] inverted
174 
input           div_frac_add_in1_neq_0; // div_frac_add_in1 != 0
175 
input           div_frac_out_54;        // div_frac_out bit[54]
176 
input           d6stg_frac_0;           // divide fraction[0]- intermediate val
177 
input           d6stg_frac_1;           // divide fraction[1]- intermediate val
178 
input           d6stg_frac_2;           // divide fraction[2]- intermediate val
179 
input           d6stg_frac_29;          // divide fraction[29]- intermediate val
180 
input           d6stg_frac_30;          // divide fraction[30]- intermediate val
181 
input           d6stg_frac_31;          // divide fraction[31]- intermediate val
182 
input           div_frac_out_53;        // div_frac_out bit[53]
183 
input           div_expadd2_12;         // div_expadd2 bit[12]
184 
input           arst_l;                 // global async. reset- asserted low
185 
input           grst_l;                 // global sync. reset- asserted low
186 
input           rclk;           // global clock
187 
 
188 
output          div_pipe_active;        // div pipe is executing a valid instr
189 
output          d1stg_snan_sng_in1;     // operand 1 is single signalling NaN
190 
output          d1stg_snan_dbl_in1;     // operand 1 is double signalling NaN
191 
output          d1stg_snan_sng_in2;     // operand 2 is single signalling NaN
192 
output          d1stg_snan_dbl_in2;     // operand 2 is double signalling NaN
193 
output          d1stg_step;             // divide pipe load
194 
output          d1stg_dblop;            // double precision operation- d1 stg
195 
output          d234stg_fdiv;           // select line to div_expadd1
196 
output          d3stg_fdiv;             // divide operation- divide stage 3
197 
output          d4stg_fdiv;             // divide operation- divide stage 4
198 
output          d5stg_fdiva;            // divide operation- divide stage 5
199 
output          d5stg_fdivb;            // divide operation- divide stage 5
200 
output          d5stg_fdivs;            // divide single- divide stage 5
201 
output          d5stg_fdivd;            // divide double- divide stage 5
202 
output          d6stg_fdiv;             // divide operation- divide stage 6
203 
output          d6stg_fdivs;            // divide single- divide stage 6
204 
output          d6stg_fdivd;            // divide double- divide stage 6
205 
output          d7stg_fdiv;             // divide operation- divide stage 7
206 
output          d7stg_fdivd;            // divide double- divide stage 7
207 
output          d8stg_fdiv_in;          // div pipe output request next cycle
208 
output          d8stg_fdivs;            // divide single- divide stage 8
209 
output          d8stg_fdivd;            // divide double- divide stage 8
210 
output [9:0]     div_id_out_in;          // div pipe output ID next cycle
211 
output          div_sign_out;           // divide sign output
212 
output [4:0]     div_exc_out;            // divide pipe result- exception flags
213 
output          div_norm_frac_in1_dbl_norm; // select line to div_norm
214 
output          div_norm_frac_in1_dbl_dnrm; // select line to div_norm
215 
output          div_norm_frac_in1_sng_norm; // select line to div_norm
216 
output          div_norm_frac_in1_sng_dnrm; // select line to div_norm
217 
output          div_norm_frac_in2_dbl_norm; // select line to div_norm
218 
output          div_norm_frac_in2_dbl_dnrm; // select line to div_norm
219 
output          div_norm_frac_in2_sng_norm; // select line to div_norm
220 
output          div_norm_frac_in2_sng_dnrm; // select line to div_norm
221 
output          div_norm_inf;           // select line to div_norm
222 
output          div_norm_qnan;          // select line to div_norm
223 
output          div_norm_zero;          // select line to div_norm
224 
output          div_frac_add_in2_load;  // load enable to div_frac_add_in2
225 
output          d6stg_frac_out_shl1;    // select line to d6stg_frac
226 
output          d6stg_frac_out_nosh;    // select line to d6stg_frac
227 
output          div_frac_add_in1_add;   // select line to div_frac_add_in1
228 
output          div_frac_add_in1_load;  // load enable to div_frac_add_in1
229 
output          d7stg_rndup_inv;        // no rounding increment
230 
output          d7stg_to_0;             // result to max finite on overflow
231 
output          d7stg_to_0_inv;         // result to infinity on overflow
232 
output          div_frac_out_add_in1;   // select line to div_frac_out
233 
output          div_frac_out_add;       // select line to div_frac_out
234 
output          div_frac_out_shl1_dbl;  // select line to div_frac_out
235 
output          div_frac_out_shl1_sng;  // select line to div_frac_out
236 
output          div_frac_out_of;        // select line to div_frac_out
237 
output          div_frac_out_load;      // load enable to div_frac_out
238 
output          div_expadd1_in1_dbl;    // select line to div_expadd1
239 
output          div_expadd1_in1_sng;    // select line to div_expadd1
240 
output          div_expadd1_in2_exp_in2_dbl; // select line to div_expadd1
241 
output          div_expadd1_in2_exp_in2_sng; //select line to div_expadd1
242 
output          div_exp1_expadd1;       // select line to div_exp1
243 
output          div_exp1_0835;          // select line to div_exp1
244 
output          div_exp1_0118;          // select line to div_exp1
245 
output          div_exp1_zero;          // select line to div_exp1
246 
output          div_exp1_load;          // load enable to div_exp1
247 
output          div_expadd2_in1_exp_out; // select line to div_expadd2
248 
output          div_expadd2_no_decr_inv; // no exponent decrement
249 
output          div_expadd2_cin;        // carry in to 2nd exponent adder
250 
output          div_exp_out_expadd22_inv; // select line to div_exp_out
251 
output          div_exp_out_expadd2;    // select line to div_exp_out
252 
output          div_exp_out_of;         // overflow to exponent output
253 
output          div_exp_out_exp_out;    // select line to div_exp_out
254 
output          div_exp_out_load;       // load enable to div_exp_out
255 
 
256 
input           se;                     // scan_enable
257 
input           si;                     // scan in
258 
output          so;                     // scan out
259 
 
260 
 
261 
wire            reset;
262 
wire            div_frac_in1_51;
263 
wire            div_frac_in1_54;
264 
wire            div_frac_in1_53_0_neq_0;
265 
wire            div_frac_in1_50_0_neq_0;
266 
wire            div_frac_in1_53_32_neq_0;
267 
wire            div_exp_in1_exp_eq_0;
268 
wire            div_exp_in1_exp_neq_ffs;
269 
wire            div_frac_in2_51;
270 
wire            div_frac_in2_54;
271 
wire            div_frac_in2_53_0_neq_0;
272 
wire            div_frac_in2_50_0_neq_0;
273 
wire            div_frac_in2_53_32_neq_0;
274 
wire            div_exp_in2_exp_eq_0;
275 
wire            div_exp_in2_exp_neq_ffs;
276 
wire            d1stg_denorm_sng_in1;
277 
wire            d1stg_denorm_dbl_in1;
278 
wire            d1stg_denorm_sng_in2;
279 
wire            d1stg_denorm_dbl_in2;
280 
wire            d2stg_denorm_sng_in2;
281 
wire            d2stg_denorm_dbl_in2;
282 
wire            d1stg_norm_sng_in1;
283 
wire            d1stg_norm_dbl_in1;
284 
wire            d1stg_norm_sng_in2;
285 
wire            d1stg_norm_dbl_in2;
286 
wire            d2stg_norm_sng_in2;
287 
wire            d2stg_norm_dbl_in2;
288 
wire            d1stg_snan_sng_in1;
289 
wire            d1stg_snan_dbl_in1;
290 
wire            d1stg_snan_sng_in2;
291 
wire            d1stg_snan_dbl_in2;
292 
wire            d1stg_qnan_sng_in1;
293 
wire            d1stg_qnan_dbl_in1;
294 
wire            d1stg_qnan_sng_in2;
295 
wire            d1stg_qnan_dbl_in2;
296 
wire            d1stg_snan_in1;
297 
wire            d1stg_snan_in2;
298 
wire            d1stg_qnan_in1;
299 
wire            d1stg_qnan_in2;
300 
wire            d1stg_nan_sng_in1;
301 
wire            d1stg_nan_dbl_in1;
302 
wire            d1stg_nan_sng_in2;
303 
wire            d1stg_nan_dbl_in2;
304 
wire            d1stg_nan_in1;
305 
wire            d1stg_nan_in2;
306 
wire            d1stg_nan_in;
307 
wire            d2stg_snan_in1;
308 
wire            d2stg_snan_in2;
309 
wire            d2stg_qnan_in1;
310 
wire            d2stg_qnan_in2;
311 
wire            d2stg_nan_in2;
312 
wire            d2stg_nan_in;
313 
wire            d1stg_inf_sng_in1;
314 
wire            d1stg_inf_dbl_in1;
315 
wire            d1stg_inf_sng_in2;
316 
wire            d1stg_inf_dbl_in2;
317 
wire            d1stg_inf_in1;
318 
wire            d1stg_inf_in2;
319 
wire            d1stg_inf_in;
320 
wire            d1stg_2inf_in;
321 
wire            d2stg_inf_in1;
322 
wire            d2stg_inf_in2;
323 
wire            d2stg_2inf_in;
324 
wire            d1stg_infnan_sng_in1;
325 
wire            d1stg_infnan_dbl_in1;
326 
wire            d1stg_infnan_sng_in2;
327 
wire            d1stg_infnan_dbl_in2;
328 
wire            d1stg_infnan_in1;
329 
wire            d1stg_infnan_in2;
330 
wire            d1stg_infnan_in;
331 
wire            d2stg_infnan_in1;
332 
wire            d2stg_infnan_in2;
333 
wire            d2stg_infnan_in;
334 
wire            d1stg_zero_in1;
335 
wire            d1stg_zero_in2;
336 
wire            d1stg_zero_in;
337 
wire            d1stg_2zero_in;
338 
wire            d2stg_zero_in1;
339 
wire            d2stg_zero_in2;
340 
wire            d2stg_zero_in;
341 
wire            d2stg_2zero_in;
342 
wire            d1stg_hold;
343 
wire            d1stg_holda;
344 
wire            d1stg_step;
345 
wire            d1stg_stepa;
346 
wire [7:0]       d1stg_op_in;
347 
wire [7:0]       d1stg_op;
348 
wire            d1stg_div_in;
349 
wire            d1stg_div;
350 
wire [4:0]       d1stg_sngopa;
351 
wire            d1stg_dblop;
352 
wire [4:0]       d1stg_dblopa;
353 
wire            d1stg_fdiv;
354 
wire            d1stg_fdivs;
355 
wire            d1stg_fdivd;
356 
wire [2:0]       d1stg_opdec;
357 
wire            d234stg_fdiv_in;
358 
wire [2:0]       d2stg_opdec;
359 
wire            d234stg_fdiv;
360 
wire            d2stg_fdiv;
361 
wire            d2stg_fdivs;
362 
wire            d2stg_fdivd;
363 
wire [2:0]       d3stg_opdec;
364 
wire            d3stg_fdiv;
365 
wire [2:0]       d4stg_opdec;
366 
wire            d4stg_fdiv;
367 
wire            d4stg_fdivs;
368 
wire            d4stg_fdivd;
369 
wire            d5stg_step;
370 
wire [2:0]       d5stg_opdec;
371 
wire            d5stg_fdiva;
372 
wire            d5stg_fdivb_in;
373 
wire            d5stg_fdivb;
374 
wire            d5stg_fdiv;
375 
wire            d5stg_fdivs;
376 
wire            d5stg_fdivd;
377 
wire            d6stg_step;
378 
wire [2:0]       d6stg_opdec_in;
379 
wire [2:0]       d6stg_opdec;
380 
wire            d6stg_fdiv;
381 
wire            d6stg_fdivs;
382 
wire            d6stg_fdivd;
383 
wire [2:0]       d7stg_opdec;
384 
wire            d7stg_fdiv;
385 
wire            d7stg_fdivs;
386 
wire            d7stg_fdivd;
387 
wire            d8stg_fdiv_in;
388 
wire [2:0]       d8stg_opdec;
389 
wire            d8stg_fdiv;
390 
wire            d8stg_fdivs;
391 
wire            d8stg_fdivd;
392 
wire            d8stg_hold;
393 
wire            d8stg_step;
394 
wire [1:0]       d1stg_rnd_mode;
395 
wire [4:0]       d1stg_id;
396 
wire            d1stg_sign1;
397 
wire            d1stg_sign2;
398 
wire            d1stg_sign;
399 
wire            div_bkend_step;
400 
wire [1:0]       div_rnd_mode;
401 
wire [9:0]       div_id_out_in;
402 
wire [9:0]       div_id_out;
403 
wire            div_sign_out;
404 
wire [5:0]       div_cnt_plus1;
405 
wire [5:0]       div_cnt_in;
406 
wire            div_cnt_step;
407 
wire [5:0]       div_cnt;
408 
wire            div_cnt_lt_step;
409 
wire            divs_cnt_lt_23_in;
410 
wire            divs_cnt_lt_23;
411 
wire            divs_cnt_lt_23a;
412 
wire            divd_cnt_lt_52_in;
413 
wire            divd_cnt_lt_52;
414 
wire            divd_cnt_lt_52a;
415 
wire            div_exc_step;
416 
wire            div_of_mask_in;
417 
wire            div_of_mask;
418 
wire            div_nv_out_in;
419 
wire            div_nv_out;
420 
wire            div_dz_out_in;
421 
wire            div_dz_out;
422 
wire            d7stg_in_of;
423 
wire            div_of_out_tmp1_in;
424 
wire            div_of_out_tmp1;
425 
wire            div_of_out_tmp2;
426 
wire            div_out_52_inv;
427 
wire            div_of_out;
428 
wire            div_uf_out_in;
429 
wire            div_uf_out;
430 
wire            div_nx_out_in;
431 
wire            div_nx_out;
432 
wire [4:0]       div_exc_out;
433 
wire            d1stg_spc_rslt;
434 
wire            div_norm_frac_in1_dbl_norm;
435 
wire            div_norm_frac_in1_dbl_dnrm;
436 
wire            div_norm_frac_in1_sng_norm;
437 
wire            div_norm_frac_in1_sng_dnrm;
438 
wire            div_norm_frac_in2_dbl_norm;
439 
wire            div_norm_frac_in2_dbl_dnrm;
440 
wire            div_norm_frac_in2_sng_norm;
441 
wire            div_norm_frac_in2_sng_dnrm;
442 
wire            div_norm_inf;
443 
wire            div_norm_qnan;
444 
wire            div_norm_zero;
445 
wire            div_frac_add_in2_load;
446 
wire            d6stg_frac_out_shl1;
447 
wire            d6stg_frac_out_nosh;
448 
wire            div_frac_add_in1_add;
449 
wire            div_frac_add_in1_load;
450 
wire            d7stg_lsb_in;
451 
wire            d7stg_grd_in;
452 
wire            d7stg_stk_in;
453 
wire            d7stg_lsb;
454 
wire            d7stg_grd;
455 
wire            d7stg_stk;
456 
wire            d7stg_rndup;
457 
wire            d7stg_rndup_inv;
458 
wire            d7stg_to_0;
459 
wire            d7stg_to_0_inv;
460 
wire            div_frac_out_add_in1;
461 
wire            div_frac_out_add;
462 
wire            div_frac_out_shl1_dbl;
463 
wire            div_frac_out_shl1_sng;
464 
wire            div_frac_out_of;
465 
wire            div_frac_out_load;
466 
wire            div_expadd1_in1_dbl_in;
467 
wire            div_expadd1_in1_dbl;
468 
wire            div_expadd1_in1_sng_in;
469 
wire            div_expadd1_in1_sng;
470 
wire            div_expadd1_in2_exp_in2_dbl;
471 
wire            div_expadd1_in2_exp_in2_sng;
472 
wire            div_exp1_expadd1;
473 
wire            div_exp1_0835;
474 
wire            div_exp1_0118;
475 
wire            div_exp1_zero;
476 
wire            d2stg_max_exp;
477 
wire            d2stg_zero_exp;
478 
wire            div_exp1_load;
479 
wire            div_expadd2_in1_exp_out_in;
480 
wire            div_expadd2_in1_exp_out;
481 
wire            div_expadd2_no_decr_inv_in;
482 
wire            div_expadd2_no_decr_load;
483 
wire            div_expadd2_no_decr_inv;
484 
wire            div_expadd2_cin;
485 
wire            div_exp_out_zero;
486 
wire            div_exp_out_expadd22_inv;
487 
wire            div_exp_out_expadd2;
488 
wire            div_exp_out_of;
489 
wire            div_exp_out_exp_out;
490 
wire            div_exp_out_load;
491 
wire            div_pipe_active_in;
492 
wire            div_pipe_active;
493 
 
494 
 
495 
dffrl_async #(1)  dffrl_div_ctl (
496 
  .din  (grst_l),
497 
  .clk  (rclk),
498 
  .rst_l(arst_l),
499 
  .q    (div_ctl_rst_l),
500 
        .se (se),
501 
        .si (),
502 
        .so ()
503 
  );
504 
 
505 
assign reset= (!div_ctl_rst_l);
506 
 
507 
///////////////////////////////////////////////////////////////////////////////
508 
//
509 
//      Divide pipeline special input cases.
510 
//
511 
///////////////////////////////////////////////////////////////////////////////
512 
 
513 
dffe_s #(1) i_div_frac_in1_51 (
514 
        .din    (inq_in1_51),
515 
        .en     (d1stg_step),
516 
        .clk    (rclk),
517 
 
518 
        .q      (div_frac_in1_51),
519 
 
520 
        .se     (se),
521 
        .si     (),
522 
        .so     ()
523 
);
524 
 
525 
dffe_s #(1) i_div_frac_in1_54 (
526 
        .din    (inq_in1_54),
527 
        .en     (d1stg_step),
528 
        .clk    (rclk),
529 
 
530 
        .q      (div_frac_in1_54),
531 
 
532 
        .se     (se),
533 
        .si     (),
534 
        .so     ()
535 
);
536 
 
537 
dffe_s #(1) i_div_frac_in1_53_0_neq_0 (
538 
        .din    (inq_in1_53_0_neq_0),
539 
        .en     (d1stg_step),
540 
        .clk    (rclk),
541 
 
542 
        .q      (div_frac_in1_53_0_neq_0),
543 
 
544 
        .se     (se),
545 
        .si     (),
546 
        .so     ()
547 
);
548 
 
549 
dffe_s #(1) i_div_frac_in1_50_0_neq_0 (
550 
        .din    (inq_in1_50_0_neq_0),
551 
        .en     (d1stg_step),
552 
        .clk    (rclk),
553 
 
554 
        .q      (div_frac_in1_50_0_neq_0),
555 
 
556 
        .se     (se),
557 
        .si     (),
558 
        .so     ()
559 
);
560 
 
561 
dffe_s #(1) i_div_frac_in1_53_32_neq_0 (
562 
        .din    (inq_in1_53_32_neq_0),
563 
        .en     (d1stg_step),
564 
        .clk    (rclk),
565 
 
566 
        .q      (div_frac_in1_53_32_neq_0),
567 
 
568 
        .se     (se),
569 
        .si     (),
570 
        .so     ()
571 
);
572 
 
573 
dffe_s #(1) i_div_exp_in1_exp_eq_0 (
574 
        .din    (inq_in1_exp_eq_0),
575 
        .en     (d1stg_step),
576 
        .clk    (rclk),
577 
 
578 
        .q      (div_exp_in1_exp_eq_0),
579 
 
580 
        .se     (se),
581 
        .si     (),
582 
        .so     ()
583 
);
584 
 
585 
dffe_s #(1) i_div_exp_in1_exp_neq_ffs (
586 
        .din    (inq_in1_exp_neq_ffs),
587 
        .en     (d1stg_step),
588 
        .clk    (rclk),
589 
 
590 
        .q      (div_exp_in1_exp_neq_ffs),
591 
 
592 
        .se     (se),
593 
        .si     (),
594 
        .so     ()
595 
);
596 
 
597 
dffe_s #(1) i_div_frac_in2_51 (
598 
        .din    (inq_in2_51),
599 
        .en     (d1stg_step),
600 
        .clk    (rclk),
601 
 
602 
        .q      (div_frac_in2_51),
603 
 
604 
        .se     (se),
605 
        .si     (),
606 
        .so     ()
607 
);
608 
 
609 
dffe_s #(1) i_div_frac_in2_54 (
610 
        .din    (inq_in2_54),
611 
        .en     (d1stg_step),
612 
        .clk    (rclk),
613 
 
614 
        .q      (div_frac_in2_54),
615 
 
616 
        .se     (se),
617 
        .si     (),
618 
        .so     ()
619 
);
620 
 
621 
dffe_s #(1) i_div_frac_in2_53_0_neq_0 (
622 
        .din    (inq_in2_53_0_neq_0),
623 
        .en     (d1stg_step),
624 
        .clk    (rclk),
625 
 
626 
        .q      (div_frac_in2_53_0_neq_0),
627 
 
628 
        .se     (se),
629 
        .si     (),
630 
        .so     ()
631 
);
632 
 
633 
dffe_s #(1) i_div_frac_in2_50_0_neq_0 (
634 
        .din    (inq_in2_50_0_neq_0),
635 
        .en     (d1stg_step),
636 
        .clk    (rclk),
637 
 
638 
        .q      (div_frac_in2_50_0_neq_0),
639 
 
640 
        .se     (se),
641 
        .si     (),
642 
        .so     ()
643 
);
644 
 
645 
dffe_s #(1) i_div_frac_in2_53_32_neq_0 (
646 
        .din    (inq_in2_53_32_neq_0),
647 
        .en     (d1stg_step),
648 
        .clk    (rclk),
649 
 
650 
        .q      (div_frac_in2_53_32_neq_0),
651 
 
652 
        .se     (se),
653 
        .si     (),
654 
        .so     ()
655 
);
656 
 
657 
dffe_s #(1) i_div_exp_in2_exp_eq_0 (
658 
        .din    (inq_in2_exp_eq_0),
659 
         .en    (d1stg_step),
660 
        .clk    (rclk),
661 
 
662 
        .q      (div_exp_in2_exp_eq_0),
663 
 
664 
        .se     (se),
665 
        .si     (),
666 
        .so     ()
667 
);
668 
 
669 
dffe_s #(1) i_div_exp_in2_exp_neq_ffs (
670 
        .din    (inq_in2_exp_neq_ffs),
671 
        .en     (d1stg_step),
672 
        .clk    (rclk),
673 
 
674 
        .q      (div_exp_in2_exp_neq_ffs),
675 
 
676 
        .se     (se),
677 
        .si     (),
678 
        .so     ()
679 
);
680 
 
681 
 
682 
///////////////////////////////////////////////////////////////////////////////
683 
//
684 
//      Denorm divide inputs.
685 
//
686 
///////////////////////////////////////////////////////////////////////////////
687 
 
688 
assign d1stg_denorm_sng_in1= div_exp_in1_exp_eq_0 && d1stg_sngopa[0];
689 
 
690 
assign d1stg_denorm_dbl_in1= div_exp_in1_exp_eq_0 && d1stg_dblopa[0];
691 
 
692 
assign d1stg_denorm_sng_in2= div_exp_in2_exp_eq_0 && d1stg_sngopa[0];
693 
 
694 
assign d1stg_denorm_dbl_in2= div_exp_in2_exp_eq_0 && d1stg_dblopa[0];
695 
 
696 
dff_s #(1) i_d2stg_denorm_sng_in2 (
697 
        .din    (d1stg_denorm_sng_in2),
698 
        .clk    (rclk),
699 
 
700 
        .q      (d2stg_denorm_sng_in2),
701 
 
702 
        .se     (se),
703 
        .si     (),
704 
        .so     ()
705 
);
706 
 
707 
dff_s #(1) i_d2stg_denorm_dbl_in2 (
708 
        .din    (d1stg_denorm_dbl_in2),
709 
        .clk    (rclk),
710 
 
711 
        .q      (d2stg_denorm_dbl_in2),
712 
 
713 
        .se     (se),
714 
        .si     (),
715 
        .so     ()
716 
);
717 
 
718 
 
719 
///////////////////////////////////////////////////////////////////////////////
720 
//
721 
//      Non-denorm divide inputs.
722 
//
723 
///////////////////////////////////////////////////////////////////////////////
724 
 
725 
assign d1stg_norm_sng_in1= (!div_exp_in1_exp_eq_0) && d1stg_sngopa[0];
726 
 
727 
assign d1stg_norm_dbl_in1= (!div_exp_in1_exp_eq_0) && d1stg_dblopa[0];
728 
 
729 
assign d1stg_norm_sng_in2= (!div_exp_in2_exp_eq_0) && d1stg_sngopa[0];
730 
 
731 
assign d1stg_norm_dbl_in2= (!div_exp_in2_exp_eq_0) && d1stg_dblopa[0];
732 
 
733 
dff_s #(1) i_d2stg_norm_sng_in2 (
734 
        .din    (d1stg_norm_sng_in2),
735 
        .clk    (rclk),
736 
 
737 
        .q      (d2stg_norm_sng_in2),
738 
 
739 
        .se     (se),
740 
        .si     (),
741 
        .so     ()
742 
);
743 
 
744 
dff_s #(1) i_d2stg_norm_dbl_in2 (
745 
        .din    (d1stg_norm_dbl_in2),
746 
        .clk    (rclk),
747 
 
748 
        .q      (d2stg_norm_dbl_in2),
749 
 
750 
        .se     (se),
751 
        .si     (),
752 
        .so     ()
753 
);
754 
 
755 
 
756 
///////////////////////////////////////////////////////////////////////////////
757 
//
758 
//      Nan divide inputs.
759 
//
760 
///////////////////////////////////////////////////////////////////////////////
761 
 
762 
assign d1stg_snan_sng_in1= (!div_exp_in1_exp_neq_ffs) && (!div_frac_in1_54)
763 
                && div_frac_in1_53_32_neq_0 && d1stg_sngopa[1];
764 
 
765 
assign d1stg_snan_dbl_in1= (!div_exp_in1_exp_neq_ffs) && (!div_frac_in1_51)
766 
                && div_frac_in1_50_0_neq_0 && d1stg_dblopa[1];
767 
 
768 
assign d1stg_snan_sng_in2= (!div_exp_in2_exp_neq_ffs) && (!div_frac_in2_54)
769 
                && div_frac_in2_53_32_neq_0 && d1stg_sngopa[1];
770 
 
771 
assign d1stg_snan_dbl_in2= (!div_exp_in2_exp_neq_ffs) && (!div_frac_in2_51)
772 
                && div_frac_in2_50_0_neq_0 && d1stg_dblopa[1];
773 
 
774 
assign d1stg_qnan_sng_in1= (!div_exp_in1_exp_neq_ffs) && div_frac_in1_54
775 
                && d1stg_sngopa[1];
776 
 
777 
assign d1stg_qnan_dbl_in1= (!div_exp_in1_exp_neq_ffs) && div_frac_in1_51
778 
                && d1stg_dblopa[1];
779 
 
780 
assign d1stg_qnan_sng_in2= (!div_exp_in2_exp_neq_ffs) && div_frac_in2_54
781 
                && d1stg_sngopa[1];
782 
 
783 
assign d1stg_qnan_dbl_in2= (!div_exp_in2_exp_neq_ffs) && div_frac_in2_51
784 
                && d1stg_dblopa[1];
785 
 
786 
assign d1stg_snan_in1= d1stg_snan_sng_in1 || d1stg_snan_dbl_in1;
787 
 
788 
assign d1stg_snan_in2= d1stg_snan_sng_in2 || d1stg_snan_dbl_in2;
789 
 
790 
assign d1stg_qnan_in1= d1stg_qnan_sng_in1 || d1stg_qnan_dbl_in1;
791 
 
792 
assign d1stg_qnan_in2= d1stg_qnan_sng_in2 || d1stg_qnan_dbl_in2;
793 
 
794 
assign d1stg_nan_sng_in1= (!div_exp_in1_exp_neq_ffs)
795 
                && (div_frac_in1_54 || div_frac_in1_53_32_neq_0)
796 
                && d1stg_sngopa[2];
797 
 
798 
assign d1stg_nan_dbl_in1= (!div_exp_in1_exp_neq_ffs)
799 
                && (div_frac_in1_51 || div_frac_in1_50_0_neq_0)
800 
                && d1stg_dblopa[2];
801 
 
802 
assign d1stg_nan_sng_in2= (!div_exp_in2_exp_neq_ffs)
803 
                && (div_frac_in2_54 || div_frac_in2_53_32_neq_0)
804 
                && d1stg_sngopa[2];
805 
 
806 
assign d1stg_nan_dbl_in2= (!div_exp_in2_exp_neq_ffs)
807 
                && (div_frac_in2_51 || div_frac_in2_50_0_neq_0)
808 
                && d1stg_dblopa[2];
809 
 
810 
assign d1stg_nan_in1= d1stg_nan_sng_in1 || d1stg_nan_dbl_in1;
811 
 
812 
assign d1stg_nan_in2= d1stg_nan_sng_in2 || d1stg_nan_dbl_in2;
813 
 
814 
assign d1stg_nan_in= d1stg_nan_in1 || d1stg_nan_in2;
815 
 
816 
dff_s #(1) i_d2stg_snan_in1 (
817 
        .din    (d1stg_snan_in1),
818 
        .clk    (rclk),
819 
 
820 
        .q      (d2stg_snan_in1),
821 
 
822 
        .se     (se),
823 
        .si     (),
824 
        .so     ()
825 
);
826 
 
827 
dff_s #(1) i_d2stg_snan_in2 (
828 
        .din    (d1stg_snan_in2),
829 
        .clk    (rclk),
830 
 
831 
        .q      (d2stg_snan_in2),
832 
 
833 
        .se     (se),
834 
        .si     (),
835 
        .so     ()
836 
);
837 
 
838 
dff_s #(1) i_d2stg_qnan_in1 (
839 
        .din    (d1stg_qnan_in1),
840 
        .clk    (rclk),
841 
 
842 
        .q      (d2stg_qnan_in1),
843 
 
844 
        .se     (se),
845 
        .si     (),
846 
        .so     ()
847 
);
848 
 
849 
dff_s #(1) i_d2stg_qnan_in2 (
850 
        .din    (d1stg_qnan_in2),
851 
        .clk    (rclk),
852 
 
853 
        .q      (d2stg_qnan_in2),
854 
 
855 
        .se     (se),
856 
        .si     (),
857 
        .so     ()
858 
);
859 
 
860 
dff_s #(1) i_d2stg_nan_in2 (
861 
        .din    (d1stg_nan_in2),
862 
        .clk    (rclk),
863 
 
864 
        .q      (d2stg_nan_in2),
865 
 
866 
        .se     (se),
867 
        .si     (),
868 
        .so     ()
869 
);
870 
 
871 
dff_s #(1) i_d2stg_nan_in (
872 
        .din    (d1stg_nan_in),
873 
        .clk    (rclk),
874 
 
875 
        .q      (d2stg_nan_in),
876 
 
877 
        .se     (se),
878 
        .si     (),
879 
        .so     ()
880 
);
881 
 
882 
 
883 
///////////////////////////////////////////////////////////////////////////////
884 
//
885 
//      Infinity divide inputs.
886 
//
887 
///////////////////////////////////////////////////////////////////////////////
888 
 
889 
assign d1stg_inf_sng_in1= (!div_exp_in1_exp_neq_ffs)
890 
                && (!div_frac_in1_54) && (!div_frac_in1_53_32_neq_0)
891 
                && d1stg_sngopa[2];
892 
 
893 
assign d1stg_inf_dbl_in1= (!div_exp_in1_exp_neq_ffs)
894 
                && (!div_frac_in1_51) && (!div_frac_in1_50_0_neq_0)
895 
                && d1stg_dblopa[2];
896 
 
897 
assign d1stg_inf_sng_in2= (!div_exp_in2_exp_neq_ffs)
898 
                && (!div_frac_in2_54) && (!div_frac_in2_53_32_neq_0)
899 
                && d1stg_sngopa[2];
900 
 
901 
assign d1stg_inf_dbl_in2= (!div_exp_in2_exp_neq_ffs)
902 
                && (!div_frac_in2_51) && (!div_frac_in2_50_0_neq_0)
903 
                && d1stg_dblopa[2];
904 
 
905 
assign d1stg_inf_in1= d1stg_inf_sng_in1 || d1stg_inf_dbl_in1;
906 
 
907 
assign d1stg_inf_in2= d1stg_inf_sng_in2 || d1stg_inf_dbl_in2;
908 
 
909 
assign d1stg_inf_in= d1stg_inf_in1 || d1stg_inf_in2;
910 
 
911 
assign d1stg_2inf_in= d1stg_inf_in1 && d1stg_inf_in2;
912 
 
913 
dff_s #(1) i_d2stg_inf_in1 (
914 
        .din    (d1stg_inf_in1),
915 
        .clk    (rclk),
916 
 
917 
        .q      (d2stg_inf_in1),
918 
 
919 
        .se     (se),
920 
        .si     (),
921 
        .so     ()
922 
);
923 
 
924 
dff_s #(1) i_d2stg_inf_in2 (
925 
        .din    (d1stg_inf_in2),
926 
        .clk    (rclk),
927 
 
928 
        .q      (d2stg_inf_in2),
929 
 
930 
        .se     (se),
931 
        .si     (),
932 
        .so     ()
933 
);
934 
 
935 
dff_s #(1) i_d2stg_2inf_in (
936 
        .din    (d1stg_2inf_in),
937 
        .clk    (rclk),
938 
 
939 
        .q      (d2stg_2inf_in),
940 
 
941 
        .se     (se),
942 
        .si     (),
943 
        .so     ()
944 
);
945 
 
946 
 
947 
///////////////////////////////////////////////////////////////////////////////
948 
//
949 
//      Infinity/Nan divide inputs.
950 
//
951 
///////////////////////////////////////////////////////////////////////////////
952 
 
953 
assign d1stg_infnan_sng_in1= (!div_exp_in1_exp_neq_ffs) && d1stg_sngopa[3];
954 
 
955 
assign d1stg_infnan_dbl_in1= (!div_exp_in1_exp_neq_ffs) && d1stg_dblopa[3];
956 
 
957 
assign d1stg_infnan_sng_in2= (!div_exp_in2_exp_neq_ffs) && d1stg_sngopa[3];
958 
 
959 
assign d1stg_infnan_dbl_in2= (!div_exp_in2_exp_neq_ffs) && d1stg_dblopa[3];
960 
 
961 
assign d1stg_infnan_in1= d1stg_infnan_sng_in1 || d1stg_infnan_dbl_in1;
962 
 
963 
assign d1stg_infnan_in2= d1stg_infnan_sng_in2 || d1stg_infnan_dbl_in2;
964 
 
965 
assign d1stg_infnan_in= d1stg_infnan_in1 || d1stg_infnan_in2;
966 
 
967 
dff_s #(1) i_d2stg_infnan_in1 (
968 
        .din    (d1stg_infnan_in1),
969 
        .clk    (rclk),
970 
 
971 
        .q      (d2stg_infnan_in1),
972 
 
973 
        .se     (se),
974 
        .si     (),
975 
        .so     ()
976 
);
977 
 
978 
dff_s #(1) i_d2stg_infnan_in2 (
979 
        .din    (d1stg_infnan_in2),
980 
        .clk    (rclk),
981 
 
982 
        .q      (d2stg_infnan_in2),
983 
 
984 
        .se     (se),
985 
        .si     (),
986 
        .so     ()
987 
);
988 
 
989 
dff_s #(1) i_d2stg_infnan_in (
990 
        .din    (d1stg_infnan_in),
991 
        .clk    (rclk),
992 
 
993 
        .q      (d2stg_infnan_in),
994 
 
995 
        .se     (se),
996 
        .si     (),
997 
        .so     ()
998 
);
999 
 
1000 
 
1001 
///////////////////////////////////////////////////////////////////////////////
1002 
//
1003 
//      Zero divide inputs.
1004 
//
1005 
///////////////////////////////////////////////////////////////////////////////
1006 
 
1007 
assign d1stg_zero_in1= div_exp_in1_exp_eq_0
1008 
                && (!div_frac_in1_53_0_neq_0) && (!div_frac_in1_54);
1009 
 
1010 
assign d1stg_zero_in2= div_exp_in2_exp_eq_0
1011 
                && (!div_frac_in2_53_0_neq_0) && (!div_frac_in2_54);
1012 
 
1013 
assign d1stg_zero_in= d1stg_zero_in1 || d1stg_zero_in2;
1014 
 
1015 
assign d1stg_2zero_in= d1stg_zero_in1 && d1stg_zero_in2;
1016 
 
1017 
dff_s #(1) i_d2stg_zero_in1 (
1018 
        .din    (d1stg_zero_in1),
1019 
        .clk    (rclk),
1020 
 
1021 
        .q      (d2stg_zero_in1),
1022 
 
1023 
        .se     (se),
1024 
        .si     (),
1025 
        .so     ()
1026 
);
1027 
 
1028 
dff_s #(1) i_d2stg_zero_in2 (
1029 
        .din    (d1stg_zero_in2),
1030 
        .clk    (rclk),
1031 
 
1032 
        .q      (d2stg_zero_in2),
1033 
 
1034 
        .se     (se),
1035 
        .si     (),
1036 
        .so     ()
1037 
);
1038 
 
1039 
dff_s #(1) i_d2stg_zero_in (
1040 
        .din    (d1stg_zero_in),
1041 
        .clk    (rclk),
1042 
 
1043 
        .q      (d2stg_zero_in),
1044 
 
1045 
        .se     (se),
1046 
        .si     (),
1047 
        .so     ()
1048 
);
1049 
 
1050 
dff_s #(1) i_d2stg_2zero_in (
1051 
        .din    (d1stg_2zero_in),
1052 
        .clk    (rclk),
1053 
 
1054 
        .q      (d2stg_2zero_in),
1055 
 
1056 
        .se     (se),
1057 
        .si     (),
1058 
        .so     ()
1059 
);
1060 
 
1061 
 
1062 
///////////////////////////////////////////////////////////////////////////////
1063 
//
1064 
//      Floating point divide control pipeline.
1065 
//
1066 
///////////////////////////////////////////////////////////////////////////////
1067 
 
1068 
///////////////////////////////////////////////////////////////////////////////
1069 
//
1070 
//      Opcode pipeline- divide pipeline input.
1071 
//
1072 
///////////////////////////////////////////////////////////////////////////////
1073 
 
1074 
assign d1stg_hold= d1stg_div
1075 
                || d234stg_fdiv
1076 
                || divs_cnt_lt_23
1077 
                || divd_cnt_lt_52;
1078 
 
1079 
assign d1stg_holda= d1stg_div
1080 
                || d234stg_fdiv
1081 
                || divs_cnt_lt_23a
1082 
                || divd_cnt_lt_52a;
1083 
 
1084 
assign d1stg_step= (!d1stg_hold);
1085 
 
1086 
assign d1stg_stepa= (!d1stg_holda);
1087 
 
1088 
 
1089 
assign d1stg_op_in[7:0]= ({8{d1stg_stepa}}
1090 
                            & (inq_op[7:0] & {8{inq_div}}));
1091 
 
1092 
dffr_s #(8) i_d1stg_op (
1093 
        .din    (d1stg_op_in[7:0]),
1094 
        .rst    (reset),
1095 
        .clk    (rclk),
1096 
 
1097 
        .q      (d1stg_op[7:0]),
1098 
 
1099 
        .se     (se),
1100 
        .si     (),
1101 
        .so     ()
1102 
);
1103 
 
1104 
assign d1stg_div_in= inq_div && d1stg_stepa;
1105 
 
1106 
dffr_s #(1) i_d1stg_div (
1107 
        .din    (d1stg_div_in),
1108 
        .rst    (reset),
1109 
        .clk    (rclk),
1110 
 
1111 
        .q      (d1stg_div),
1112 
 
1113 
        .se     (se),
1114 
        .si     (),
1115 
        .so     ()
1116 
);
1117 
 
1118 
dffe_s #(5) i_d1stg_sngopa (
1119 
        .din    ({5{inq_op[0]}}),
1120 
        .en     (d1stg_stepa),
1121 
        .clk    (rclk),
1122 
 
1123 
        .q      (d1stg_sngopa[4:0]),
1124 
 
1125 
        .se     (se),
1126 
        .si     (),
1127 
        .so     ()
1128 
);
1129 
 
1130 
dffe_s #(1) i_d1stg_dblop (
1131 
        .din    (inq_op[1]),
1132 
        .en     (d1stg_stepa),
1133 
        .clk    (rclk),
1134 
 
1135 
        .q      (d1stg_dblop),
1136 
 
1137 
        .se     (se),
1138 
        .si     (),
1139 
        .so     ()
1140 
);
1141 
 
1142 
dffe_s #(5) i_d1stg_dblopa (
1143 
        .din    ({5{inq_op[1]}}),
1144 
        .en     (d1stg_stepa),
1145 
        .clk    (rclk),
1146 
 
1147 
        .q      (d1stg_dblopa[4:0]),
1148 
 
1149 
        .se     (se),
1150 
        .si     (),
1151 
        .so     ()
1152 
);
1153 
 
1154 
 
1155 
///////////////////////////////////////////////////////////////////////////////
1156 
//
1157 
//      Opcode decode- divide stage 1.
1158 
//
1159 
///////////////////////////////////////////////////////////////////////////////
1160 
 
1161 
assign d1stg_fdiv= (d1stg_op[7:0]==FDIVS) || (d1stg_op[7:0]==FDIVD);
1162 
 
1163 
assign d1stg_fdivs= (d1stg_op[7:0]==FDIVS);
1164 
 
1165 
assign d1stg_fdivd= (d1stg_op[7:0]==FDIVD);
1166 
 
1167 
assign d1stg_opdec[2:0]= {d1stg_fdiv,
1168 
                        d1stg_fdivs,
1169 
                        d1stg_fdivd};
1170 
 
1171 
assign d234stg_fdiv_in= d1stg_fdiv || d2stg_fdiv || d3stg_fdiv;
1172 
 
1173 
dffr_s #(3) i_d2stg_opdec (
1174 
        .din    (d1stg_opdec[2:0]),
1175 
        .rst    (reset),
1176 
        .clk    (rclk),
1177 
 
1178 
        .q      (d2stg_opdec[2:0]),
1179 
 
1180 
        .se     (se),
1181 
        .si     (),
1182 
        .so     ()
1183 
);
1184 
 
1185 
dffr_s #(1) i_d234stg_fdiv (
1186 
        .din    (d234stg_fdiv_in),
1187 
        .rst    (reset),
1188 
        .clk    (rclk),
1189 
 
1190 
        .q      (d234stg_fdiv),
1191 
 
1192 
        .se     (se),
1193 
        .si     (),
1194 
        .so     ()
1195 
);
1196 
 
1197 
 
1198 
///////////////////////////////////////////////////////////////////////////////
1199 
//
1200 
//      Opcode pipeline- divide stage 2.
1201 
//
1202 
///////////////////////////////////////////////////////////////////////////////
1203 
 
1204 
assign d2stg_fdiv= d2stg_opdec[2];
1205 
assign d2stg_fdivs= d2stg_opdec[1];
1206 
assign d2stg_fdivd= d2stg_opdec[0];
1207 
 
1208 
dffr_s #(3) i_d3stg_opdec (
1209 
        .din    (d2stg_opdec[2:0]),
1210 
        .rst    (reset),
1211 
        .clk    (rclk),
1212 
 
1213 
        .q      (d3stg_opdec[2:0]),
1214 
 
1215 
        .se     (se),
1216 
        .si     (),
1217 
        .so     ()
1218 
);
1219 
 
1220 
 
1221 
///////////////////////////////////////////////////////////////////////////////
1222 
//
1223 
//      Opcode pipeline- divide stage 3.
1224 
//
1225 
///////////////////////////////////////////////////////////////////////////////
1226 
 
1227 
assign d3stg_fdiv= d3stg_opdec[2];
1228 
//assign d3stg_fdivs= d3stg_opdec[1];
1229 
//assign d3stg_fdivd= d3stg_opdec[0];
1230 
 
1231 
dffr_s #(3) i_d4stg_opdec (
1232 
        .din    (d3stg_opdec[2:0]),
1233 
        .rst    (reset),
1234 
        .clk    (rclk),
1235 
 
1236 
        .q      (d4stg_opdec[2:0]),
1237 
 
1238 
        .se     (se),
1239 
        .si     (),
1240 
        .so     ()
1241 
);
1242 
 
1243 
 
1244 
///////////////////////////////////////////////////////////////////////////////
1245 
//
1246 
//      Opcode pipeline- divide stage 4.
1247 
//
1248 
///////////////////////////////////////////////////////////////////////////////
1249 
 
1250 
assign d4stg_fdiv= d4stg_opdec[2];
1251 
assign d4stg_fdivs= d4stg_opdec[1];
1252 
assign d4stg_fdivd= d4stg_opdec[0];
1253 
 
1254 
assign d5stg_step= (!d5stg_fdiv) || d6stg_step;
1255 
 
1256 
dffre_s #(3) i_d5stg_opdec (
1257 
        .din    (d4stg_opdec[2:0]),
1258 
        .en     (d5stg_step),
1259 
        .rst    (reset),
1260 
        .clk    (rclk),
1261 
 
1262 
        .q      (d5stg_opdec[2:0]),
1263 
 
1264 
        .se     (se),
1265 
        .si     (),
1266 
        .so     ()
1267 
);
1268 
 
1269 
dffre_s #(1) i_d5stg_fdiva (
1270 
        .din    (d4stg_fdiv),
1271 
        .en     (d5stg_step),
1272 
        .rst    (reset),
1273 
        .clk    (rclk),
1274 
 
1275 
        .q      (d5stg_fdiva),
1276 
 
1277 
        .se     (se),
1278 
        .si     (),
1279 
        .so     ()
1280 
);
1281 
 
1282 
assign d5stg_fdivb_in= ((d5stg_step && d4stg_fdiv)
1283 
                        || ((!d5stg_step) && d5stg_fdiv))
1284 
                && (!reset);
1285 
 
1286 
dff_s #(1) i_d5stg_fdivb (
1287 
        .din    (d5stg_fdivb_in),
1288 
        .clk    (rclk),
1289 
 
1290 
        .q      (d5stg_fdivb),
1291 
 
1292 
        .se     (se),
1293 
        .si     (),
1294 
        .so     ()
1295 
);
1296 
 
1297 
 
1298 
///////////////////////////////////////////////////////////////////////////////
1299 
//
1300 
//      Opcode pipeline- divide stage 5.
1301 
//
1302 
///////////////////////////////////////////////////////////////////////////////
1303 
 
1304 
assign d5stg_fdiv= d5stg_opdec[2];
1305 
assign d5stg_fdivs= d5stg_opdec[1];
1306 
assign d5stg_fdivd= d5stg_opdec[0];
1307 
 
1308 
assign d6stg_step= (d5stg_fdivd && (div_cnt[5:0]==6'h36))
1309 
                || (d5stg_fdivs && (div_cnt[5:0]==6'h19))
1310 
                || (d5stg_fdiv && ((({7'b0, div_cnt[5:0]}==div_exp1[12:0])
1311 
                                        && (div_exp1[12:0]!=13'b0))
1312 
                                || (({7'b0, div_cnt[5:0]}==div_exp1[12:0])
1313 
                                        && (div_exp1[12:0]==13'b0)
1314 
                                        && d8stg_step)
1315 
                                || (div_exp1[12] && d8stg_step)));
1316 
 
1317 
assign d6stg_opdec_in[2:0]= ({3{d6stg_step}}
1318 
                            & d5stg_opdec[2:0]);
1319 
 
1320 
dffr_s #(3) i_d6stg_opdec (
1321 
        .din    (d6stg_opdec_in[2:0]),
1322 
        .rst    (reset),
1323 
        .clk    (rclk),
1324 
 
1325 
        .q      (d6stg_opdec[2:0]),
1326 
 
1327 
        .se     (se),
1328 
        .si     (),
1329 
        .so     ()
1330 
);
1331 
 
1332 
 
1333 
///////////////////////////////////////////////////////////////////////////////
1334 
//
1335 
//      Opcode pipeline- divide stage 6.
1336 
//
1337 
///////////////////////////////////////////////////////////////////////////////
1338 
 
1339 
assign d6stg_fdiv= d6stg_opdec[2];
1340 
assign d6stg_fdivs= d6stg_opdec[1];
1341 
assign d6stg_fdivd= d6stg_opdec[0];
1342 
 
1343 
dffr_s #(3) i_d7stg_opdec (
1344 
        .din    (d6stg_opdec[2:0]),
1345 
        .rst    (reset),
1346 
        .clk    (rclk),
1347 
 
1348 
        .q      (d7stg_opdec[2:0]),
1349 
 
1350 
        .se     (se),
1351 
        .si     (),
1352 
        .so     ()
1353 
);
1354 
 
1355 
 
1356 
///////////////////////////////////////////////////////////////////////////////
1357 
//
1358 
//      Opcode pipeline- divide stage 7.
1359 
//
1360 
///////////////////////////////////////////////////////////////////////////////
1361 
 
1362 
assign d7stg_fdiv= d7stg_opdec[2];
1363 
assign d7stg_fdivs= d7stg_opdec[1];
1364 
assign d7stg_fdivd= d7stg_opdec[0];
1365 
 
1366 
assign d8stg_fdiv_in= (d8stg_step && (!reset) && d7stg_fdiv)
1367 
                || ((!d8stg_step) && (!reset) && d8stg_fdiv);
1368 
 
1369 
dffre_s #(3) i_d8stg_opdec (
1370 
        .din    (d7stg_opdec[2:0]),
1371 
        .en     (d8stg_step),
1372 
        .rst    (reset),
1373 
        .clk    (rclk),
1374 
 
1375 
        .q      (d8stg_opdec[2:0]),
1376 
 
1377 
        .se     (se),
1378 
        .si     (),
1379 
        .so     ()
1380 
);
1381 
 
1382 
 
1383 
///////////////////////////////////////////////////////////////////////////////
1384 
//
1385 
//      Opcode pipeline- divide pipeline output.
1386 
//
1387 
///////////////////////////////////////////////////////////////////////////////
1388 
 
1389 
assign d8stg_fdiv= d8stg_opdec[2];
1390 
assign d8stg_fdivs= d8stg_opdec[1];
1391 
assign d8stg_fdivd= d8stg_opdec[0];
1392 
 
1393 
assign d8stg_hold= d8stg_fdiv && (!div_dest_rdy);
1394 
 
1395 
assign d8stg_step= (!d8stg_hold);
1396 
 
1397 
// Austin update
1398 
// Power management update
1399 
 
1400 
assign div_pipe_active_in =  // div pipe is executing a valid instr
1401 
   d1stg_fdiv || d2stg_fdiv || d3stg_fdiv || d4stg_fdiv |
1402 
   d5stg_fdiv || d6stg_fdiv || d7stg_fdiv || d8stg_fdiv ;
1403 
 
1404 
dffre_s #(1) i_div_pipe_active (
1405 
        .din    (div_pipe_active_in),
1406 
        .en     (1'b1),
1407 
        .rst    (reset),
1408 
        .clk    (rclk),
1409 
 
1410 
        .q      (div_pipe_active),
1411 
 
1412 
        .se     (se),
1413 
        .si     (),
1414 
        .so     ()
1415 
);
1416 
 
1417 
 
1418 
///////////////////////////////////////////////////////////////////////////////
1419 
//
1420 
//      Divide information pipeline
1421 
//              - rounding mode
1422 
//              - ID
1423 
//              - sign logic
1424 
//      Front end of the pipeline.
1425 
//
1426 
///////////////////////////////////////////////////////////////////////////////
1427 
 
1428 
dffe_s #(2) i_d1stg_rnd_mode (
1429 
        .din    (inq_rnd_mode[1:0]),
1430 
        .en     (d1stg_stepa),
1431 
        .clk    (rclk),
1432 
 
1433 
        .q      (d1stg_rnd_mode[1:0]),
1434 
 
1435 
        .se     (se),
1436 
        .si     (),
1437 
        .so     ()
1438 
);
1439 
 
1440 
dffe_s #(5) i_d1stg_id (
1441 
        .din    (inq_id[4:0]),
1442 
        .en     (d1stg_stepa),
1443 
        .clk    (rclk),
1444 
 
1445 
        .q      (d1stg_id[4:0]),
1446 
 
1447 
        .se     (se),
1448 
        .si     (),
1449 
        .so     ()
1450 
);
1451 
 
1452 
dffe_s #(1) i_d1stg_sign1 (
1453 
        .din    (inq_in1_63),
1454 
        .en     (d1stg_stepa),
1455 
        .clk    (rclk),
1456 
 
1457 
        .q      (d1stg_sign1),
1458 
 
1459 
        .se     (se),
1460 
        .si     (),
1461 
        .so     ()
1462 
);
1463 
 
1464 
dffe_s #(1) i_d1stg_sign2 (
1465 
        .din    (inq_in2_63),
1466 
        .en     (d1stg_stepa),
1467 
        .clk    (rclk),
1468 
 
1469 
        .q      (d1stg_sign2),
1470 
 
1471 
        .se     (se),
1472 
        .si     (),
1473 
        .so     ()
1474 
);
1475 
 
1476 
 
1477 
///////////////////////////////////////////////////////////////////////////////
1478 
//
1479 
//      Divide information pipeline
1480 
//              - rounding mode
1481 
//              - ID
1482 
//              - sign logic
1483 
//      Back end of the pipeline.
1484 
//
1485 
///////////////////////////////////////////////////////////////////////////////
1486 
 
1487 
assign d1stg_sign= ((d1stg_sign1
1488 
                                && (!d2stg_snan_in2)
1489 
                                && (!(d2stg_qnan_in2 && (!d2stg_snan_in1))))
1490 
                        ^ (d1stg_sign2
1491 
                                && (!(d2stg_snan_in1 && (!d2stg_snan_in2)))
1492 
                                && (!(d2stg_qnan_in1 && (!d2stg_nan_in2)))))
1493 
                && (!(d2stg_2inf_in || d2stg_2zero_in));
1494 
 
1495 
assign div_bkend_step= (d5stg_fdiv && (div_cnt[5:0]==6'b0) && d8stg_step);
1496 
 
1497 
dffe_s #(2) i_div_rnd_mode (
1498 
        .din    (d1stg_rnd_mode[1:0]),
1499 
        .en     (div_bkend_step),
1500 
        .clk    (rclk),
1501 
 
1502 
        .q      (div_rnd_mode[1:0]),
1503 
 
1504 
        .se     (se),
1505 
        .si     (),
1506 
        .so     ()
1507 
);
1508 
 
1509 
assign div_id_out_in[9:0]= ({10{div_bkend_step}}
1510 
                            & {(d1stg_id[4:2]==3'o7),
1511 
                                (d1stg_id[4:2]==3'o6),
1512 
                                (d1stg_id[4:2]==3'o5),
1513 
                                (d1stg_id[4:2]==3'o4),
1514 
                                (d1stg_id[4:2]==3'o3),
1515 
                                (d1stg_id[4:2]==3'o2),
1516 
                                (d1stg_id[4:2]==3'o1),
1517 
                                (d1stg_id[4:2]==3'o0),
1518 
                                d1stg_id[1:0]})
1519 
                | ({10{(!div_bkend_step)}}
1520 
                            & div_id_out[9:0]);
1521 
 
1522 
dff_s #(10) i_div_id_out (
1523 
        .din    (div_id_out_in[9:0]),
1524 
        .clk    (rclk),
1525 
 
1526 
        .q      (div_id_out[9:0]),
1527 
 
1528 
        .se     (se),
1529 
        .si     (),
1530 
        .so     ()
1531 
);
1532 
 
1533 
dffe_s #(1) i_div_sign_out (
1534 
        .din    (d1stg_sign),
1535 
        .en     (div_bkend_step),
1536 
        .clk    (rclk),
1537 
 
1538 
        .q      (div_sign_out),
1539 
 
1540 
        .se     (se),
1541 
        .si     (),
1542 
        .so     ()
1543 
);
1544 
 
1545 
 
1546 
///////////////////////////////////////////////////////////////////////////////
1547 
//
1548 
//      Divide counter.
1549 
//
1550 
//      Tracks the number of subtraction iterations.
1551 
//
1552 
///////////////////////////////////////////////////////////////////////////////
1553 
 
1554 
assign div_cnt_plus1[5:0]= (div_cnt[5:0] + 6'h01);
1555 
 
1556 
assign div_cnt_in[5:0]= ({6{(d5stg_fdiv && d8stg_step)}}
1557 
                            & div_cnt_plus1[5:0])
1558 
                | ({6{d4stg_fdiv}}
1559 
                            & 6'b0);
1560 
 
1561 
assign div_cnt_step= (d5stg_fdiv && d8stg_step)
1562 
                || d4stg_fdiv;
1563 
 
1564 
dffre_s #(6) i_div_cnt (
1565 
        .din    (div_cnt_in[5:0]),
1566 
        .en     (div_cnt_step),
1567 
        .rst    (reset),
1568 
        .clk    (rclk),
1569 
 
1570 
        .q      (div_cnt[5:0]),
1571 
 
1572 
        .se     (se),
1573 
        .si     (),
1574 
        .so     ()
1575 
);
1576 
 
1577 
assign div_cnt_lt_step= (!d5stg_fdiv) || d6stg_step || d8stg_step;
1578 
 
1579 
assign divs_cnt_lt_23_in= d4stg_fdivs
1580 
                || (d5stg_fdivs && (!d6stg_step) && (div_cnt_plus1[5:0]<6'h17));
1581 
 
1582 
dffre_s #(1) i_divs_cnt_lt_23 (
1583 
        .din    (divs_cnt_lt_23_in),
1584 
        .en     (div_cnt_lt_step),
1585 
        .rst    (reset),
1586 
        .clk    (rclk),
1587 
 
1588 
        .q      (divs_cnt_lt_23),
1589 
 
1590 
        .se     (se),
1591 
        .si     (),
1592 
        .so     ()
1593 
);
1594 
 
1595 
dffre_s #(1) i_divs_cnt_lt_23a (
1596 
        .din    (divs_cnt_lt_23_in),
1597 
        .en     (div_cnt_lt_step),
1598 
        .rst    (reset),
1599 
        .clk    (rclk),
1600 
 
1601 
        .q      (divs_cnt_lt_23a),
1602 
 
1603 
        .se     (se),
1604 
        .si     (),
1605 
        .so     ()
1606 
);
1607 
 
1608 
assign divd_cnt_lt_52_in= d4stg_fdivd
1609 
                || (d5stg_fdivd && (!d6stg_step) && (div_cnt_plus1[5:0]<6'h34));
1610 
 
1611 
dffre_s #(1) i_divd_cnt_lt_52 (
1612 
        .din    (divd_cnt_lt_52_in),
1613 
        .en     (div_cnt_lt_step),
1614 
        .rst    (reset),
1615 
        .clk    (rclk),
1616 
 
1617 
        .q      (divd_cnt_lt_52),
1618 
 
1619 
        .se     (se),
1620 
        .si     (),
1621 
        .so     ()
1622 
);
1623 
 
1624 
dffre_s #(1) i_divd_cnt_lt_52a (
1625 
        .din    (divd_cnt_lt_52_in),
1626 
        .en     (div_cnt_lt_step),
1627 
        .rst    (reset),
1628 
        .clk    (rclk),
1629 
 
1630 
        .q      (divd_cnt_lt_52a),
1631 
 
1632 
        .se     (se),
1633 
        .si     (),
1634 
        .so     ()
1635 
);
1636 
 
1637 
 
1638 
///////////////////////////////////////////////////////////////////////////////
1639 
//
1640 
//      Divide exception logic.
1641 
//
1642 
///////////////////////////////////////////////////////////////////////////////
1643 
 
1644 
///////////////////////////////////////////////////////////////////////////////
1645 
//
1646 
//      Divide overflow exception enabled.
1647 
//
1648 
///////////////////////////////////////////////////////////////////////////////
1649 
 
1650 
assign div_exc_step= d5stg_fdiv && (div_cnt[5:0]==6'b0) && d8stg_step;
1651 
 
1652 
assign div_of_mask_in= (!(d1stg_infnan_in || d1stg_zero_in));
1653 
 
1654 
dffe_s #(1) i_div_of_mask (
1655 
        .din    (div_of_mask_in),
1656 
        .en     (div_exc_step),
1657 
        .clk    (rclk),
1658 
 
1659 
        .q      (div_of_mask),
1660 
 
1661 
        .se     (se),
1662 
        .si     (),
1663 
        .so     ()
1664 
);
1665 
 
1666 
 
1667 
///////////////////////////////////////////////////////////////////////////////
1668 
//
1669 
//      Divide invalid exception.
1670 
//
1671 
///////////////////////////////////////////////////////////////////////////////
1672 
 
1673 
assign div_nv_out_in= d1stg_snan_in1 || d1stg_snan_in2 || d1stg_2inf_in
1674 
                || d1stg_2zero_in;
1675 
 
1676 
dffe_s #(1) i_div_nv_out (
1677 
        .din    (div_nv_out_in),
1678 
        .en     (div_exc_step),
1679 
        .clk    (rclk),
1680 
 
1681 
        .q      (div_nv_out),
1682 
 
1683 
        .se     (se),
1684 
        .si     (),
1685 
        .so     ()
1686 
);
1687 
 
1688 
///////////////////////////////////////////////////////////////////////////////
1689 
//
1690 
//      Divide by zero exception.
1691 
//
1692 
///////////////////////////////////////////////////////////////////////////////
1693 
 
1694 
assign div_dz_out_in= d1stg_zero_in2 && (!d1stg_zero_in1)
1695 
                && (!d1stg_infnan_in1);
1696 
 
1697 
dffe_s #(1) i_div_dz_out (
1698 
        .din    (div_dz_out_in),
1699 
        .en     (div_exc_step),
1700 
        .clk    (rclk),
1701 
 
1702 
        .q      (div_dz_out),
1703 
 
1704 
        .se     (se),
1705 
        .si     (),
1706 
        .so     ()
1707 
);
1708 
 
1709 
 
1710 
///////////////////////////////////////////////////////////////////////////////
1711 
//
1712 
//      Divide overflow exception.
1713 
//
1714 
///////////////////////////////////////////////////////////////////////////////
1715 
 
1716 
assign d7stg_in_of= ((!div_exp_out[12])
1717 
                        && d7stg_fdivd
1718 
                        && (div_exp_out[11] || (&div_exp_out[10:0]))
1719 
                        && div_of_mask)
1720 
                || ((!div_exp_out[12])
1721 
                        && d7stg_fdivs
1722 
                        && ((|div_exp_out[11:8]) || (&div_exp_out[7:0]))
1723 
                        && div_of_mask);
1724 
 
1725 
assign div_of_out_tmp1_in= ((!div_exp_out[12])
1726 
                        && d7stg_fdivd
1727 
                        && (&div_exp_out[10:1])
1728 
                        && d7stg_rndup
1729 
                        && div_of_mask)
1730 
                || ((!div_exp_out[12])
1731 
                        && d7stg_fdivs
1732 
                        && (&div_exp_out[7:1])
1733 
                        && d7stg_rndup
1734 
                        && div_of_mask);
1735 
 
1736 
dffe_s #(1) i_div_of_out_tmp1 (
1737 
        .din    (div_of_out_tmp1_in),
1738 
        .en     (d7stg_fdiv),
1739 
        .clk    (rclk),
1740 
 
1741 
        .q      (div_of_out_tmp1),
1742 
 
1743 
        .se     (se),
1744 
        .si     (),
1745 
        .so     ()
1746 
);
1747 
 
1748 
dffe_s #(1) i_div_of_out_tmp2 (
1749 
        .din    (d7stg_in_of),
1750 
        .en     (d7stg_fdiv),
1751 
        .clk    (rclk),
1752 
 
1753 
        .q      (div_of_out_tmp2),
1754 
 
1755 
        .se     (se),
1756 
        .si     (),
1757 
        .so     ()
1758 
);
1759 
 
1760 
dffe_s #(1) i_div_out_52_inv (
1761 
        .din    (div_frac_add_52_inva),
1762 
        .en     (d7stg_fdiv),
1763 
        .clk    (rclk),
1764 
 
1765 
        .q      (div_out_52_inv),
1766 
 
1767 
// Austin update
1768 
// include se pin
1769 
        .se     (se),
1770 
        .si     (),
1771 
        .so     ()
1772 
);
1773 
 
1774 
assign div_of_out= div_of_out_tmp2
1775 
                || (div_of_out_tmp1 && (!div_out_52_inv));
1776 
 
1777 
 
1778 
///////////////////////////////////////////////////////////////////////////////
1779 
//
1780 
//      Divide underflow exception.
1781 
//
1782 
///////////////////////////////////////////////////////////////////////////////
1783 
 
1784 
assign div_uf_out_in= ((!(|div_exp_out[11:0]))
1785 
                        && (div_frac_add_in1_neq_0
1786 
                                || d7stg_grd
1787 
                                || d7stg_stk)
1788 
                        && div_of_mask)
1789 
                || (div_exp_out[12]
1790 
                        && div_of_mask);
1791 
 
1792 
dffe_s #(1) i_div_uf_out (
1793 
        .din    (div_uf_out_in),
1794 
        .en     (d7stg_fdiv),
1795 
        .clk    (rclk),
1796 
 
1797 
        .q      (div_uf_out),
1798 
 
1799 
        .se     (se),
1800 
        .si     (),
1801 
        .so     ()
1802 
);
1803 
 
1804 
 
1805 
///////////////////////////////////////////////////////////////////////////////
1806 
//
1807 
//      Divide inexact exception.
1808 
//
1809 
///////////////////////////////////////////////////////////////////////////////
1810 
 
1811 
assign div_nx_out_in= d7stg_grd || d7stg_stk;
1812 
 
1813 
dffe_s #(1) i_div_nx_out (
1814 
        .din    (div_nx_out_in),
1815 
        .en     (d7stg_fdiv),
1816 
        .clk    (rclk),
1817 
 
1818 
        .q      (div_nx_out),
1819 
 
1820 
        .se     (se),
1821 
        .si     (),
1822 
        .so     ()
1823 
);
1824 
 
1825 
 
1826 
///////////////////////////////////////////////////////////////////////////////
1827 
//
1828 
//      Divide exception output.
1829 
//
1830 
///////////////////////////////////////////////////////////////////////////////
1831 
 
1832 
// Austin update
1833 
// Overflow is always accompanied by inexact.
1834 
// Previously this was handled within the FFU.
1835 
 
1836 
// assign div_exc_out[4:0]= {div_nv_out, div_of_out, div_uf_out, div_dz_out,
1837 
//                              div_nx_out};
1838 
 
1839 
assign div_exc_out[4:0] =
1840 
  {div_nv_out,
1841 
   div_of_out,
1842 
   div_uf_out,
1843 
   div_dz_out,
1844 
   (div_nx_out || div_of_out)};  // Overflow is always accompanied by inexact
1845 
 
1846 
 
1847 
///////////////////////////////////////////////////////////////////////////////
1848 
//
1849 
//      Divide pipeline control logic.
1850 
//
1851 
///////////////////////////////////////////////////////////////////////////////
1852 
 
1853 
///////////////////////////////////////////////////////////////////////////////
1854 
//
1855 
//      Select lines- divide normalization and special input injection.
1856 
//
1857 
///////////////////////////////////////////////////////////////////////////////
1858 
 
1859 
assign d1stg_spc_rslt= (d1stg_inf_in || d1stg_zero_in) && (!d1stg_nan_in);
1860 
 
1861 
assign div_norm_frac_in1_dbl_norm= d1stg_fdiv && d1stg_norm_dbl_in1
1862 
                && (!d1stg_snan_dbl_in2)
1863 
                && ((!d1stg_qnan_dbl_in2) || d1stg_snan_dbl_in1)
1864 
                && (!d1stg_spc_rslt);
1865 
 
1866 
assign div_norm_frac_in1_dbl_dnrm= d1stg_fdiv && d1stg_denorm_dbl_in1
1867 
                && (!d1stg_snan_dbl_in2)
1868 
                && (!d1stg_qnan_dbl_in2)
1869 
                && (!d1stg_spc_rslt);
1870 
 
1871 
assign div_norm_frac_in1_sng_norm= d1stg_fdiv && d1stg_norm_sng_in1
1872 
                && (!d1stg_snan_sng_in2)
1873 
                && ((!d1stg_qnan_sng_in2) || d1stg_snan_sng_in1)
1874 
                && (!d1stg_spc_rslt);
1875 
 
1876 
assign div_norm_frac_in1_sng_dnrm= d1stg_fdiv && d1stg_denorm_sng_in1
1877 
                && (!d1stg_snan_sng_in2)
1878 
                && (!d1stg_qnan_sng_in2)
1879 
                && (!d1stg_spc_rslt);
1880 
 
1881 
assign div_norm_frac_in2_dbl_norm= (d2stg_fdiv && d2stg_norm_dbl_in2
1882 
                        && (!d2stg_infnan_in) && (!d2stg_zero_in))
1883 
                || (d1stg_fdiv && d1stg_snan_dbl_in2)
1884 
                || (d1stg_fdiv && d1stg_qnan_dbl_in2 && (!d1stg_snan_dbl_in1));
1885 
 
1886 
assign div_norm_frac_in2_dbl_dnrm= d2stg_fdiv && d2stg_denorm_dbl_in2
1887 
                        && (!d2stg_infnan_in) && (!d2stg_zero_in);
1888 
 
1889 
assign div_norm_frac_in2_sng_norm= (d2stg_fdiv && d2stg_norm_sng_in2
1890 
                        && (!d2stg_infnan_in) && (!d2stg_zero_in))
1891 
                || (d1stg_fdiv && d1stg_snan_sng_in2)
1892 
                || (d1stg_fdiv && d1stg_qnan_sng_in2 && (!d1stg_snan_sng_in1));
1893 
 
1894 
assign div_norm_frac_in2_sng_dnrm= d2stg_fdiv && d2stg_denorm_sng_in2
1895 
                        && (!d2stg_infnan_in) && (!d2stg_zero_in);
1896 
 
1897 
assign div_norm_inf= (d2stg_fdiv && (d2stg_infnan_in || d2stg_zero_in))
1898 
                || (d1stg_fdiv && ((d1stg_inf_in1 && (!d1stg_infnan_in2))
1899 
                                || (d1stg_zero_in2 && (!d1stg_infnan_in1)
1900 
                                        && (!d1stg_zero_in1))));
1901 
 
1902 
assign div_norm_qnan= d1stg_fdiv && (d1stg_2inf_in || d1stg_2zero_in);
1903 
 
1904 
assign div_norm_zero= d1stg_fdiv
1905 
                && ((d1stg_inf_in2 && (!d1stg_infnan_in1))
1906 
                        || (d1stg_zero_in1 && (!d1stg_infnan_in2)
1907 
                                && (!d1stg_zero_in2)));
1908 
 
1909 
 
1910 
///////////////////////////////////////////////////////////////////////////////
1911 
//
1912 
//      Select lines- divide left shift.
1913 
//
1914 
///////////////////////////////////////////////////////////////////////////////
1915 
 
1916 
assign div_frac_add_in2_load= d4stg_fdiv || d6stg_fdiv;
1917 
 
1918 
 
1919 
///////////////////////////////////////////////////////////////////////////////
1920 
//
1921 
//      Select lines- divide adder/subtractor 2nd input.
1922 
//
1923 
///////////////////////////////////////////////////////////////////////////////
1924 
 
1925 
assign d6stg_frac_out_shl1= (!div_frac_out_54) && (!div_exp_out[12])
1926 
                && (div_exp_out[11:1]!=11'b0);
1927 
 
1928 
assign d6stg_frac_out_nosh= (!d6stg_frac_out_shl1);
1929 
 
1930 
assign div_frac_add_in1_add= d5stg_fdiv && (!div_exp1[12]) && d8stg_step;
1931 
 
1932 
assign div_frac_add_in1_load= d4stg_fdiv
1933 
                || (d5stg_fdiv && (!div_exp1[12]) && d8stg_step)
1934 
                || d6stg_fdiv;
1935 
 
1936 
 
1937 
///////////////////////////////////////////////////////////////////////////////
1938 
//
1939 
//      Divide rounding bits.
1940 
//
1941 
///////////////////////////////////////////////////////////////////////////////
1942 
 
1943 
assign d7stg_lsb_in= (d6stg_fdivd && d6stg_frac_2)
1944 
                || ((!d6stg_fdivd) && d6stg_frac_31);
1945 
 
1946 
assign d7stg_grd_in= (d6stg_fdivd && d6stg_frac_1)
1947 
                || ((!d6stg_fdivd) && d6stg_frac_30);
1948 
 
1949 
assign d7stg_stk_in= (d6stg_fdivd && d6stg_frac_0)
1950 
                || ((!d6stg_fdivd) && d6stg_frac_29)
1951 
                || div_frac_add_in1_neq_0;
1952 
 
1953 
dffe_s #(1) i_d7stg_lsb (
1954 
        .din    (d7stg_lsb_in),
1955 
        .en     (d6stg_fdiv),
1956 
        .clk    (rclk),
1957 
 
1958 
        .q      (d7stg_lsb),
1959 
 
1960 
        .se     (se),
1961 
        .si     (),
1962 
        .so     ()
1963 
);
1964 
 
1965 
dffe_s #(1) i_d7stg_grd (
1966 
        .din    (d7stg_grd_in),
1967 
        .en     (d6stg_fdiv),
1968 
        .clk    (rclk),
1969 
 
1970 
        .q      (d7stg_grd),
1971 
 
1972 
        .se     (se),
1973 
        .si     (),
1974 
        .so     ()
1975 
);
1976 
 
1977 
dffe_s #(1) i_d7stg_stk (
1978 
        .din    (d7stg_stk_in),
1979 
        .en     (d6stg_fdiv),
1980 
        .clk    (rclk),
1981 
 
1982 
        .q      (d7stg_stk),
1983 
 
1984 
        .se     (se),
1985 
        .si     (),
1986 
        .so     ()
1987 
);
1988 
 
1989 
 
1990 
///////////////////////////////////////////////////////////////////////////////
1991 
//
1992 
//      Select lines- divide adder/subtractor and fraction output register.
1993 
//
1994 
///////////////////////////////////////////////////////////////////////////////
1995 
 
1996 
assign d7stg_rndup= ((div_rnd_mode[1:0]==2'b10) && (!div_sign_out)
1997 
                        && (d7stg_grd || d7stg_stk))
1998 
                || ((div_rnd_mode[1:0]==2'b11) && div_sign_out
1999 
                        && (d7stg_grd || d7stg_stk))
2000 
                || ((div_rnd_mode[1:0]==2'b00)
2001 
                        && ((d7stg_grd && d7stg_stk)
2002 
                                || (d7stg_grd && (!d7stg_stk) && d7stg_lsb)));
2003 
 
2004 
assign d7stg_rndup_inv= (!d7stg_rndup);
2005 
 
2006 
assign d7stg_to_0= (div_rnd_mode[1:0]==2'b01)
2007 
                || ((div_rnd_mode[1:0]==2'b10) && div_sign_out)
2008 
                || ((div_rnd_mode[1:0]==2'b11) && (!div_sign_out));
2009 
 
2010 
assign d7stg_to_0_inv= (!d7stg_to_0);
2011 
 
2012 
assign div_frac_out_add_in1= d7stg_fdiv && (!d7stg_rndup) && (!d7stg_in_of);
2013 
 
2014 
assign div_frac_out_add= d7stg_fdiv && d7stg_rndup && (!d7stg_in_of);
2015 
 
2016 
assign div_frac_out_shl1_dbl= d5stg_fdivd && (!div_exp1[12]) && d8stg_step;
2017 
 
2018 
assign div_frac_out_shl1_sng= d5stg_fdivs && (!div_exp1[12]) && d8stg_step;
2019 
 
2020 
assign div_frac_out_of= d7stg_fdiv && d7stg_in_of;
2021 
 
2022 
assign div_frac_out_load= d4stg_fdiv
2023 
                || d7stg_fdiv
2024 
                || div_frac_out_shl1_dbl
2025 
                || div_frac_out_shl1_sng;
2026 
 
2027 
 
2028 
///////////////////////////////////////////////////////////////////////////////
2029 
//
2030 
//      Select lines- divide exponent adder in the front end of the divide pipe.
2031 
//
2032 
///////////////////////////////////////////////////////////////////////////////
2033 
 
2034 
assign div_expadd1_in1_dbl_in= ((d1stg_stepa && inq_op[1])
2035 
                        || ((!d1stg_stepa) && d1stg_dblopa[4]))
2036 
                && (!((d1stg_fdiv || d2stg_fdiv || d3stg_fdiv) && (!reset)));
2037 
 
2038 
dff_s #(1) i_div_expadd1_in1_dbl (
2039 
        .din    (div_expadd1_in1_dbl_in),
2040 
        .clk    (rclk),
2041 
 
2042 
        .q      (div_expadd1_in1_dbl),
2043 
 
2044 
        .se     (se),
2045 
        .si     (),
2046 
        .so     ()
2047 
);
2048 
 
2049 
assign div_expadd1_in1_sng_in= ((d1stg_stepa && inq_op[0])
2050 
                        || ((!d1stg_stepa) && d1stg_sngopa[4]))
2051 
                && (!((d1stg_fdiv || d2stg_fdiv || d3stg_fdiv) && (!reset)));
2052 
 
2053 
dff_s #(1) i_div_expadd1_in1_sng (
2054 
        .din    (div_expadd1_in1_sng_in),
2055 
        .clk    (rclk),
2056 
 
2057 
        .q      (div_expadd1_in1_sng),
2058 
 
2059 
        .se     (se),
2060 
        .si     (),
2061 
        .so     ()
2062 
);
2063 
 
2064 
assign div_expadd1_in2_exp_in2_dbl= d2stg_fdivd;
2065 
 
2066 
assign div_expadd1_in2_exp_in2_sng= d2stg_fdivs;
2067 
 
2068 
assign div_exp1_expadd1= d1stg_fdiv
2069 
                || (d2stg_fdiv && (!d2stg_infnan_in) && (!d2stg_zero_in))
2070 
                || d3stg_fdiv
2071 
                || d4stg_fdiv;
2072 
 
2073 
assign div_exp1_0835= d2stg_fdivd && d2stg_max_exp;
2074 
 
2075 
assign div_exp1_0118= d2stg_fdivs && d2stg_max_exp;
2076 
 
2077 
assign div_exp1_zero= d2stg_fdiv && d2stg_zero_exp;
2078 
 
2079 
assign d2stg_max_exp= d2stg_nan_in || d2stg_inf_in1 || d2stg_zero_in2;
2080 
 
2081 
assign d2stg_zero_exp= (d2stg_inf_in2 && (!d2stg_infnan_in1))
2082 
                || (d2stg_zero_in1 && (!d2stg_infnan_in2) && (!d2stg_zero_in2));
2083 
 
2084 
assign div_exp1_load= d1stg_fdiv || d2stg_fdiv || d3stg_fdiv || d4stg_fdiv;
2085 
 
2086 
 
2087 
///////////////////////////////////////////////////////////////////////////////
2088 
//
2089 
//      Select lines- divide exponent adder in the back end of the divide pipe.
2090 
//
2091 
///////////////////////////////////////////////////////////////////////////////
2092 
 
2093 
assign div_expadd2_in1_exp_out_in= d6stg_opdec_in[2] || d6stg_fdiv;
2094 
 
2095 
dffr_s #(1) i_div_expadd2_in1_exp_out (
2096 
        .din    (div_expadd2_in1_exp_out_in),
2097 
        .rst    (reset),
2098 
        .clk    (rclk),
2099 
 
2100 
        .q      (div_expadd2_in1_exp_out),
2101 
 
2102 
        .se     (se),
2103 
        .si     (),
2104 
        .so     ()
2105 
);
2106 
 
2107 
assign div_expadd2_no_decr_inv_in= (!(div_frac_out_53
2108 
                || (div_exp1[11:0]==(({12{(!d5stg_fdivs)}} & 12'h035)
2109 
                                        | ({12{d5stg_fdivs}} & 12'h018)))
2110 
                || div_expadd2_12));
2111 
 
2112 
assign div_expadd2_no_decr_load= d5stg_fdiv && d8stg_step;
2113 
 
2114 
dffe_s #(1) i_div_expadd2_no_decr_inv (
2115 
        .din    (div_expadd2_no_decr_inv_in),
2116 
        .en     (div_expadd2_no_decr_load),
2117 
        .clk    (rclk),
2118 
 
2119 
        .q      (div_expadd2_no_decr_inv),
2120 
 
2121 
        .se     (se),
2122 
        .si     (),
2123 
        .so     ()
2124 
);
2125 
 
2126 
assign div_expadd2_cin= d5stg_fdiv || d7stg_fdiv;
2127 
 
2128 
assign div_exp_out_zero= d7stg_fdiv && div_exp_out[12];
2129 
 
2130 
assign div_exp_out_expadd22_inv= (!(d6stg_fdiv
2131 
                        || (d5stg_fdiv && (div_cnt[5:0]==6'b0) && d8stg_step)));
2132 
 
2133 
assign div_exp_out_expadd2= ((d7stg_fdiv && d7stg_rndup && (!d7stg_in_of))
2134 
                        || (d5stg_fdiv && (div_cnt[5:0]==6'b0) && d8stg_step)
2135 
                        || d6stg_fdiv)
2136 
                && (!div_exp_out_zero);
2137 
 
2138 
assign div_exp_out_of= d7stg_fdiv && d7stg_in_of;
2139 
 
2140 
assign div_exp_out_exp_out= d7stg_fdiv
2141 
                && (!d7stg_in_of)
2142 
                && (!div_exp_out_zero);
2143 
 
2144 
assign div_exp_out_load= (d5stg_fdiv && (div_cnt[5:0]==6'b0) && d8stg_step)
2145 
                || d6stg_fdiv
2146 
                || d7stg_fdiv;
2147 
 
2148 
 
2149 
endmodule
2150 
 
2151 
 

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