1 |
2 |
dmitryr |
// ========== Copyright Header Begin ==========================================
|
2 |
|
|
//
|
3 |
|
|
// OpenSPARC T1 Processor File: fpu_in2_gt_in1_3to1.v
|
4 |
|
|
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
|
5 |
|
|
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
|
6 |
|
|
//
|
7 |
|
|
// The above named program is free software; you can redistribute it and/or
|
8 |
|
|
// modify it under the terms of the GNU General Public
|
9 |
|
|
// License version 2 as published by the Free Software Foundation.
|
10 |
|
|
//
|
11 |
|
|
// The above named program is distributed in the hope that it will be
|
12 |
|
|
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 |
|
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 |
|
|
// General Public License for more details.
|
15 |
|
|
//
|
16 |
|
|
// You should have received a copy of the GNU General Public
|
17 |
|
|
// License along with this work; if not, write to the Free Software
|
18 |
|
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
19 |
|
|
//
|
20 |
|
|
// ========== Copyright Header End ============================================
|
21 |
|
|
///////////////////////////////////////////////////////////////////////////////
|
22 |
|
|
//
|
23 |
|
|
// Reduce three fpu_in2_gt_in1_*b results to one set of results.
|
24 |
|
|
//
|
25 |
|
|
///////////////////////////////////////////////////////////////////////////////
|
26 |
|
|
|
27 |
|
|
module fpu_in2_gt_in1_3to1 (
|
28 |
|
|
din2_neq_din1_hi,
|
29 |
|
|
din2_gt_din1_hi,
|
30 |
|
|
din2_neq_din1_mid,
|
31 |
|
|
din2_gt_din1_mid,
|
32 |
|
|
din2_neq_din1_lo,
|
33 |
|
|
din2_gt_din1_lo,
|
34 |
|
|
|
35 |
|
|
din2_neq_din1,
|
36 |
|
|
din2_gt_din1
|
37 |
|
|
);
|
38 |
|
|
|
39 |
|
|
|
40 |
|
|
input din2_neq_din1_hi; // input 2 != input 1- high 3 bits
|
41 |
|
|
input din2_gt_din1_hi; // input 2 > input 1- high 3 bits
|
42 |
|
|
input din2_neq_din1_mid; // input 2 != input 1- middle 3 bits
|
43 |
|
|
input din2_gt_din1_mid; // input 2 > input 1- middle 3 bits
|
44 |
|
|
input din2_neq_din1_lo; // input 2 != input 1- low 3 bits
|
45 |
|
|
input din2_gt_din1_lo; // input 2 > input 1- low 3 bits
|
46 |
|
|
|
47 |
|
|
output din2_neq_din1; // input 2 doesn't equal input 1
|
48 |
|
|
output din2_gt_din1; // input 2 is greater than input 1
|
49 |
|
|
|
50 |
|
|
|
51 |
|
|
wire din2_neq_din1;
|
52 |
|
|
wire din2_gt_din1;
|
53 |
|
|
|
54 |
|
|
|
55 |
|
|
assign din2_neq_din1= din2_neq_din1_hi || din2_neq_din1_mid || din2_neq_din1_lo;
|
56 |
|
|
|
57 |
|
|
assign din2_gt_din1= (din2_neq_din1_hi && din2_gt_din1_hi)
|
58 |
|
|
|| ((!din2_neq_din1_hi) && din2_neq_din1_mid
|
59 |
|
|
&& din2_gt_din1_mid)
|
60 |
|
|
|| ((!din2_neq_din1_hi) && (!din2_neq_din1_mid)
|
61 |
|
|
&& din2_gt_din1_lo);
|
62 |
|
|
|
63 |
|
|
|
64 |
|
|
endmodule
|
65 |
|
|
|
66 |
|
|
|