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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: fpu_in2_gt_in1_frac.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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///////////////////////////////////////////////////////////////////////////////
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//
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// Fraction comparison of two inputs that can have any value.
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//
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///////////////////////////////////////////////////////////////////////////////
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module fpu_in2_gt_in1_frac (
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din1,
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din2,
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sngop,
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expadd11,
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expeq,
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din2_neq_din1,
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din2_gt_din1,
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din2_gt1_din1
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);
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input [54:0] din1; // input 1- fraction
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input [54:0] din2; // input 2- fraction
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input sngop; // single precision inputs
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input expadd11; // exponent sign bit
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input expeq; // exponent are equal
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output din2_neq_din1; // input 2 != input 1- fraction
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output din2_gt_din1; // input 2 > input 1- fraction
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output din2_gt1_din1; // input 2 > input 1
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wire din2_neq_din1_54_52;
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wire din2_gt_din1_54_52;
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wire din2_neq_din1_51_50;
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wire din2_gt_din1_51_50;
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wire din2_neq_din1_49_48;
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wire din2_gt_din1_49_48;
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wire din2_neq_din1_47_45;
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wire din2_gt_din1_47_45;
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wire din2_neq_din1_44_42;
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wire din2_gt_din1_44_42;
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wire din2_neq_din1_41_39;
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wire din2_gt_din1_41_39;
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wire din2_neq_din1_38_36;
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wire din2_gt_din1_38_36;
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wire din2_neq_din1_35_33;
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wire din2_gt_din1_35_33;
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wire din2_neq_din1_32_30;
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wire din2_gt_din1_32_30;
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wire din2_neq_din1_29_27;
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wire din2_gt_din1_29_27;
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wire din2_neq_din1_26_24;
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wire din2_gt_din1_26_24;
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wire din2_neq_din1_23_21;
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wire din2_gt_din1_23_21;
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wire din2_neq_din1_20_18;
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wire din2_gt_din1_20_18;
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wire din2_neq_din1_17_15;
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wire din2_gt_din1_17_15;
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wire din2_neq_din1_14_12;
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wire din2_gt_din1_14_12;
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wire din2_neq_din1_11_9;
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wire din2_gt_din1_11_9;
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wire din2_neq_din1_8_6;
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wire din2_gt_din1_8_6;
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wire din2_neq_din1_5_3;
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wire din2_gt_din1_5_3;
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wire din2_neq_din1_2_0;
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wire din2_gt_din1_2_0;
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wire din2_neq_din1_51_45;
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wire din2_gt_din1_51_45;
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wire din2_neq_din1_44_36;
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wire din2_gt_din1_44_36;
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wire din2_neq_din1_35_27;
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wire din2_gt_din1_35_27;
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wire din2_neq_din1_26_18;
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wire din2_gt_din1_26_18;
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wire din2_neq_din1_17_9;
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wire din2_gt_din1_17_9;
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wire din2_neq_din1_8_0;
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wire din2_gt_din1_8_0;
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wire din2_neq_din1_51_27;
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wire din2_gt_din1_51_27;
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wire din2_neq_din1_26_0;
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wire din2_gt_din1_26_0;
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wire din2_neq_din1;
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wire din2_gt_din1;
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wire din2_gt1_din1;
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fpu_in2_gt_in1_3b fpu_in2_gt_in1_54_52 (
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.din1 (din1[54:52]),
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.din2 (din2[54:52]),
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.din2_neq_din1 (din2_neq_din1_54_52),
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.din2_gt_din1 (din2_gt_din1_54_52)
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);
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fpu_in2_gt_in1_2b fpu_in2_gt_in1_51_50 (
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.din1 (din1[51:50]),
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.din2 (din2[51:50]),
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.din2_neq_din1 (din2_neq_din1_51_50),
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.din2_gt_din1 (din2_gt_din1_51_50)
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);
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fpu_in2_gt_in1_2b fpu_in2_gt_in1_49_48 (
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.din1 (din1[49:48]),
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.din2 (din2[49:48]),
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.din2_neq_din1 (din2_neq_din1_49_48),
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.din2_gt_din1 (din2_gt_din1_49_48)
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);
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fpu_in2_gt_in1_3b fpu_in2_gt_in1_47_45 (
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.din1 (din1[47:45]),
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.din2 (din2[47:45]),
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.din2_neq_din1 (din2_neq_din1_47_45),
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.din2_gt_din1 (din2_gt_din1_47_45)
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);
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fpu_in2_gt_in1_3b fpu_in2_gt_in1_44_42 (
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.din1 (din1[44:42]),
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.din2 (din2[44:42]),
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.din2_neq_din1 (din2_neq_din1_44_42),
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.din2_gt_din1 (din2_gt_din1_44_42)
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);
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fpu_in2_gt_in1_3b fpu_in2_gt_in1_41_39 (
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.din1 (din1[41:39]),
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.din2 (din2[41:39]),
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.din2_neq_din1 (din2_neq_din1_41_39),
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.din2_gt_din1 (din2_gt_din1_41_39)
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);
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fpu_in2_gt_in1_3b fpu_in2_gt_in1_38_36 (
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.din1 (din1[38:36]),
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.din2 (din2[38:36]),
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.din2_neq_din1 (din2_neq_din1_38_36),
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.din2_gt_din1 (din2_gt_din1_38_36)
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);
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fpu_in2_gt_in1_3b fpu_in2_gt_in1_35_33 (
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.din1 (din1[35:33]),
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.din2 (din2[35:33]),
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.din2_neq_din1 (din2_neq_din1_35_33),
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.din2_gt_din1 (din2_gt_din1_35_33)
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);
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fpu_in2_gt_in1_3b fpu_in2_gt_in1_32_30 (
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.din1 (din1[32:30]),
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.din2 (din2[32:30]),
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.din2_neq_din1 (din2_neq_din1_32_30),
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.din2_gt_din1 (din2_gt_din1_32_30)
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);
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fpu_in2_gt_in1_3b fpu_in2_gt_in1_29_27 (
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.din1 (din1[29:27]),
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.din2 (din2[29:27]),
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.din2_neq_din1 (din2_neq_din1_29_27),
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.din2_gt_din1 (din2_gt_din1_29_27)
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);
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fpu_in2_gt_in1_3b fpu_in2_gt_in1_26_24 (
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.din1 (din1[26:24]),
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.din2 (din2[26:24]),
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.din2_neq_din1 (din2_neq_din1_26_24),
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.din2_gt_din1 (din2_gt_din1_26_24)
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);
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fpu_in2_gt_in1_3b fpu_in2_gt_in1_23_21 (
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.din1 (din1[23:21]),
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.din2 (din2[23:21]),
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.din2_neq_din1 (din2_neq_din1_23_21),
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.din2_gt_din1 (din2_gt_din1_23_21)
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);
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fpu_in2_gt_in1_3b fpu_in2_gt_in1_20_18 (
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.din1 (din1[20:18]),
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.din2 (din2[20:18]),
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.din2_neq_din1 (din2_neq_din1_20_18),
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.din2_gt_din1 (din2_gt_din1_20_18)
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);
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fpu_in2_gt_in1_3b fpu_in2_gt_in1_17_15 (
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.din1 (din1[17:15]),
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.din2 (din2[17:15]),
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.din2_neq_din1 (din2_neq_din1_17_15),
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.din2_gt_din1 (din2_gt_din1_17_15)
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);
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fpu_in2_gt_in1_3b fpu_in2_gt_in1_14_12 (
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.din1 (din1[14:12]),
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.din2 (din2[14:12]),
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.din2_neq_din1 (din2_neq_din1_14_12),
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.din2_gt_din1 (din2_gt_din1_14_12)
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);
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fpu_in2_gt_in1_3b fpu_in2_gt_in1_11_9 (
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.din1 (din1[11:9]),
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.din2 (din2[11:9]),
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.din2_neq_din1 (din2_neq_din1_11_9),
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.din2_gt_din1 (din2_gt_din1_11_9)
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);
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fpu_in2_gt_in1_3b fpu_in2_gt_in1_8_6 (
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.din1 (din1[8:6]),
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.din2 (din2[8:6]),
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.din2_neq_din1 (din2_neq_din1_8_6),
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.din2_gt_din1 (din2_gt_din1_8_6)
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);
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fpu_in2_gt_in1_3b fpu_in2_gt_in1_5_3 (
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.din1 (din1[5:3]),
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.din2 (din2[5:3]),
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.din2_neq_din1 (din2_neq_din1_5_3),
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.din2_gt_din1 (din2_gt_din1_5_3)
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);
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fpu_in2_gt_in1_3b fpu_in2_gt_in1_2_0 (
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.din1 (din1[2:0]),
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| 256 |
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.din2 (din2[2:0]),
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.din2_neq_din1 (din2_neq_din1_2_0),
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| 259 |
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.din2_gt_din1 (din2_gt_din1_2_0)
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);
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fpu_in2_gt_in1_3to1 fpu_in2_gt_in1_51_45 (
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| 264 |
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.din2_neq_din1_hi (din2_neq_din1_51_50),
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| 265 |
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.din2_gt_din1_hi (din2_gt_din1_51_50),
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| 266 |
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.din2_neq_din1_mid (din2_neq_din1_49_48),
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| 267 |
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.din2_gt_din1_mid (din2_gt_din1_49_48),
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| 268 |
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.din2_neq_din1_lo (din2_neq_din1_47_45),
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| 269 |
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.din2_gt_din1_lo (din2_gt_din1_47_45),
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| 270 |
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| 271 |
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.din2_neq_din1 (din2_neq_din1_51_45),
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| 272 |
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.din2_gt_din1 (din2_gt_din1_51_45)
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| 273 |
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);
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| 274 |
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| 275 |
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fpu_in2_gt_in1_3to1 fpu_in2_gt_in1_44_36 (
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| 276 |
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.din2_neq_din1_hi (din2_neq_din1_44_42),
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| 277 |
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.din2_gt_din1_hi (din2_gt_din1_44_42),
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| 278 |
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.din2_neq_din1_mid (din2_neq_din1_41_39),
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| 279 |
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.din2_gt_din1_mid (din2_gt_din1_41_39),
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| 280 |
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.din2_neq_din1_lo (din2_neq_din1_38_36),
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| 281 |
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.din2_gt_din1_lo (din2_gt_din1_38_36),
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| 282 |
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| 283 |
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.din2_neq_din1 (din2_neq_din1_44_36),
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| 284 |
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.din2_gt_din1 (din2_gt_din1_44_36)
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| 285 |
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);
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| 286 |
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| 287 |
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fpu_in2_gt_in1_3to1 fpu_in2_gt_in1_35_27 (
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| 288 |
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.din2_neq_din1_hi (din2_neq_din1_35_33),
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| 289 |
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.din2_gt_din1_hi (din2_gt_din1_35_33),
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| 290 |
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.din2_neq_din1_mid (din2_neq_din1_32_30),
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| 291 |
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.din2_gt_din1_mid (din2_gt_din1_32_30),
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| 292 |
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.din2_neq_din1_lo (din2_neq_din1_29_27),
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| 293 |
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.din2_gt_din1_lo (din2_gt_din1_29_27),
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| 294 |
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| 295 |
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.din2_neq_din1 (din2_neq_din1_35_27),
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| 296 |
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.din2_gt_din1 (din2_gt_din1_35_27)
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| 297 |
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);
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| 298 |
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|
|
| 299 |
|
|
fpu_in2_gt_in1_3to1 fpu_in2_gt_in1_26_18 (
|
| 300 |
|
|
.din2_neq_din1_hi (din2_neq_din1_26_24),
|
| 301 |
|
|
.din2_gt_din1_hi (din2_gt_din1_26_24),
|
| 302 |
|
|
.din2_neq_din1_mid (din2_neq_din1_23_21),
|
| 303 |
|
|
.din2_gt_din1_mid (din2_gt_din1_23_21),
|
| 304 |
|
|
.din2_neq_din1_lo (din2_neq_din1_20_18),
|
| 305 |
|
|
.din2_gt_din1_lo (din2_gt_din1_20_18),
|
| 306 |
|
|
|
| 307 |
|
|
.din2_neq_din1 (din2_neq_din1_26_18),
|
| 308 |
|
|
.din2_gt_din1 (din2_gt_din1_26_18)
|
| 309 |
|
|
);
|
| 310 |
|
|
|
| 311 |
|
|
fpu_in2_gt_in1_3to1 fpu_in2_gt_in1_17_9 (
|
| 312 |
|
|
.din2_neq_din1_hi (din2_neq_din1_17_15),
|
| 313 |
|
|
.din2_gt_din1_hi (din2_gt_din1_17_15),
|
| 314 |
|
|
.din2_neq_din1_mid (din2_neq_din1_14_12),
|
| 315 |
|
|
.din2_gt_din1_mid (din2_gt_din1_14_12),
|
| 316 |
|
|
.din2_neq_din1_lo (din2_neq_din1_11_9),
|
| 317 |
|
|
.din2_gt_din1_lo (din2_gt_din1_11_9),
|
| 318 |
|
|
|
| 319 |
|
|
.din2_neq_din1 (din2_neq_din1_17_9),
|
| 320 |
|
|
.din2_gt_din1 (din2_gt_din1_17_9)
|
| 321 |
|
|
);
|
| 322 |
|
|
|
| 323 |
|
|
fpu_in2_gt_in1_3to1 fpu_in2_gt_in1_8_0 (
|
| 324 |
|
|
.din2_neq_din1_hi (din2_neq_din1_8_6),
|
| 325 |
|
|
.din2_gt_din1_hi (din2_gt_din1_8_6),
|
| 326 |
|
|
.din2_neq_din1_mid (din2_neq_din1_5_3),
|
| 327 |
|
|
.din2_gt_din1_mid (din2_gt_din1_5_3),
|
| 328 |
|
|
.din2_neq_din1_lo (din2_neq_din1_2_0),
|
| 329 |
|
|
.din2_gt_din1_lo (din2_gt_din1_2_0),
|
| 330 |
|
|
|
| 331 |
|
|
.din2_neq_din1 (din2_neq_din1_8_0),
|
| 332 |
|
|
.din2_gt_din1 (din2_gt_din1_8_0)
|
| 333 |
|
|
);
|
| 334 |
|
|
|
| 335 |
|
|
|
| 336 |
|
|
fpu_in2_gt_in1_3to1 fpu_in2_gt_in1_51_27 (
|
| 337 |
|
|
.din2_neq_din1_hi (din2_neq_din1_51_45),
|
| 338 |
|
|
.din2_gt_din1_hi (din2_gt_din1_51_45),
|
| 339 |
|
|
.din2_neq_din1_mid (din2_neq_din1_44_36),
|
| 340 |
|
|
.din2_gt_din1_mid (din2_gt_din1_44_36),
|
| 341 |
|
|
.din2_neq_din1_lo (din2_neq_din1_35_27),
|
| 342 |
|
|
.din2_gt_din1_lo (din2_gt_din1_35_27),
|
| 343 |
|
|
|
| 344 |
|
|
.din2_neq_din1 (din2_neq_din1_51_27),
|
| 345 |
|
|
.din2_gt_din1 (din2_gt_din1_51_27)
|
| 346 |
|
|
);
|
| 347 |
|
|
|
| 348 |
|
|
fpu_in2_gt_in1_3to1 fpu_in2_gt_in1_26_0 (
|
| 349 |
|
|
.din2_neq_din1_hi (din2_neq_din1_26_18),
|
| 350 |
|
|
.din2_gt_din1_hi (din2_gt_din1_26_18),
|
| 351 |
|
|
.din2_neq_din1_mid (din2_neq_din1_17_9),
|
| 352 |
|
|
.din2_gt_din1_mid (din2_gt_din1_17_9),
|
| 353 |
|
|
.din2_neq_din1_lo (din2_neq_din1_8_0),
|
| 354 |
|
|
.din2_gt_din1_lo (din2_gt_din1_8_0),
|
| 355 |
|
|
|
| 356 |
|
|
.din2_neq_din1 (din2_neq_din1_26_0),
|
| 357 |
|
|
.din2_gt_din1 (din2_gt_din1_26_0)
|
| 358 |
|
|
);
|
| 359 |
|
|
|
| 360 |
|
|
|
| 361 |
|
|
assign din2_neq_din1= din2_neq_din1_51_27
|
| 362 |
|
|
|| din2_neq_din1_26_0
|
| 363 |
|
|
|| (din2_neq_din1_54_52 && sngop);
|
| 364 |
|
|
|
| 365 |
|
|
assign din2_gt_din1= (din2_neq_din1_54_52 && din2_gt_din1_54_52
|
| 366 |
|
|
&& sngop)
|
| 367 |
|
|
|| ((!(din2_neq_din1_54_52 && sngop))
|
| 368 |
|
|
&& din2_neq_din1_51_27 && din2_gt_din1_51_27)
|
| 369 |
|
|
|| ((!(din2_neq_din1_54_52 && sngop))
|
| 370 |
|
|
&& (!din2_neq_din1_51_27)
|
| 371 |
|
|
&& din2_gt_din1_26_0);
|
| 372 |
|
|
|
| 373 |
|
|
assign din2_gt1_din1= expadd11
|
| 374 |
|
|
|| (din2_gt_din1 && expeq);
|
| 375 |
|
|
|
| 376 |
|
|
|
| 377 |
|
|
endmodule
|
| 378 |
|
|
|
| 379 |
|
|
|
