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[/] [sparc64soc/] [trunk/] [T1-FPU/] [fpu_in_ctl.v] - Blame information for rev 5

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1 2 dmitryr
// ========== Copyright Header Begin ==========================================
2
// 
3
// OpenSPARC T1 Processor File: fpu_in_ctl.v
4
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
5
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6
// 
7
// The above named program is free software; you can redistribute it and/or
8
// modify it under the terms of the GNU General Public
9
// License version 2 as published by the Free Software Foundation.
10
// 
11
// The above named program is distributed in the hope that it will be 
12
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
// General Public License for more details.
15
// 
16
// You should have received a copy of the GNU General Public
17
// License along with this work; if not, write to the Free Software
18
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19
// 
20
// ========== Copyright Header End ============================================
21
///////////////////////////////////////////////////////////////////////////////
22
//
23
//      FPU input control logic.
24
//
25
///////////////////////////////////////////////////////////////////////////////
26
 
27
module fpu_in_ctl (
28
        pcx_fpio_data_rdy_px2,
29
        pcx_fpio_data_px2,
30
        fp_op_in,
31
        fp_op_in_7in,
32
        a1stg_step,
33
        m1stg_step,
34
        d1stg_step,
35
        add_pipe_active,
36
        mul_pipe_active,
37
        div_pipe_active,
38
        sehold,
39
        arst_l,
40
        grst_l,
41
        rclk,
42
 
43
        fp_data_rdy,
44
        fadd_clken_l,
45
        fmul_clken_l,
46
        fdiv_clken_l,
47
 
48
        inq_we,
49
        inq_wraddr,
50
        inq_read_en,
51
        inq_rdaddr,
52
        inq_bp,
53
        inq_bp_inv,
54
        inq_fwrd,
55
        inq_fwrd_inv,
56
        inq_add,
57
        inq_mul,
58
        inq_div,
59
 
60
        se,
61
        si,
62
        so
63
);
64
 
65
 
66
input           pcx_fpio_data_rdy_px2;  // FPU request ready from PCX
67
input [123:118] pcx_fpio_data_px2;      // FPU request data from PCX
68
input [3:2]     fp_op_in;               // request opcode
69
input           fp_op_in_7in;           // request opcode
70
input           a1stg_step;             // add pipe load
71
input           m1stg_step;             // multiply pipe load
72
input           d1stg_step;             // divide pipe load
73
input           add_pipe_active;        // add pipe is executing a valid instr
74
input           mul_pipe_active;        // mul pipe is executing a valid instr
75
input           div_pipe_active;        // div pipe is executing a valid instr
76
input sehold; // hold sram output MUX (for inq_data[155:0] in fpu_in_dp) for macrotest
77
input           arst_l;                 // global asynchronous reset- asserted low
78
input           grst_l;                 // global synchronous reset- asserted low
79
input           rclk;           // global clock
80
 
81
output          fp_data_rdy;
82
 
83
output          fadd_clken_l;           // add      pipe clk enable - asserted low
84
output          fmul_clken_l;           // multiply pipe clk enable - asserted low
85
output          fdiv_clken_l;           // divide   pipe clk enable - asserted low
86
 
87
output          inq_we;                 // input Q write enable
88
output [3:0]     inq_wraddr;             // input Q write address
89
output          inq_read_en;            // input Q read enable
90
output [3:0]     inq_rdaddr;             // input Q read address
91
output          inq_bp;                 // bypass the input Q SRAM
92
output          inq_bp_inv;             // don't bypass the input Q SRAM
93
output          inq_fwrd;               // input Q is empty
94
output          inq_fwrd_inv;           // input Q is not empty
95
output          inq_add;                // add pipe request
96
output          inq_mul;                // multiply pipe request
97
output          inq_div;                // divide pipe request
98
 
99
input           se;                     // scan_enable
100
input           si;                     // scan in
101
output          so;                     // scan out
102
 
103
 
104
wire            reset;
105
wire            fp_data_rdy;
106
wire            fp_vld_in;
107
wire [4:0]       fp_type_in;
108
wire            fadd_clken_l;
109
wire            fmul_clken_l;
110
wire            fdiv_clken_l;
111
wire            fp_op_in_7;
112
wire            fp_op_in_7_inv;
113
wire            inq_we;
114
wire            inq_read_en;
115
wire [3:0]       inq_wrptr_plus1;
116
wire            inq_wrptr_step;
117
wire [3:0]       inq_wrptr;
118
wire [3:0]       inq_div_wrptr_plus1;
119
wire            inq_div_wrptr_step;
120
wire [3:0]       inq_div_wrptr;
121
wire [3:0]       inq_wraddr;
122
wire [3:0]       inq_wraddr_del;
123
wire            inq_re;
124
wire [3:0]       inq_rdptr_plus1;
125
wire [3:0]       inq_rdptr_in;
126
wire [3:0]       inq_rdptr;
127
wire            inq_div_re;
128
wire [3:0]       inq_div_rdptr_plus1;
129
wire [3:0]       inq_div_rdptr_in;
130
wire [3:0]       inq_div_rdptr;
131
wire            inq_div_rd_in;
132
wire            inq_div_rd;
133
wire [3:0]       inq_rdaddr;
134
wire [3:0]       inq_rdaddr_del;
135
wire            inq_bp;
136
wire            inq_bp_inv;
137
wire            inq_empty;
138
wire            inq_div_empty;
139
wire            inq_fwrd;
140
wire            inq_fwrd_inv;
141
wire            fp_add_in;
142
wire            fp_mul_in;
143
wire            fp_div_in;
144
wire [7:0]       inq_rdptr_dec_in;
145
wire [7:0]       inq_rdptr_dec;
146
wire [7:0]       inq_div_rdptr_dec_in;
147
wire [7:0]       inq_div_rdptr_dec;
148
wire [15:0]      inq_rdaddr_del_dec_in;
149
wire [15:0]      inq_rdaddr_del_dec;
150
wire            inq_pipe0_we;
151
wire            inq_pipe1_we;
152
wire            inq_pipe2_we;
153
wire            inq_pipe3_we;
154
wire            inq_pipe4_we;
155
wire            inq_pipe5_we;
156
wire            inq_pipe6_we;
157
wire            inq_pipe7_we;
158
wire            inq_pipe8_we;
159
wire            inq_pipe9_we;
160
wire            inq_pipe10_we;
161
wire            inq_pipe11_we;
162
wire            inq_pipe12_we;
163
wire            inq_pipe13_we;
164
wire            inq_pipe14_we;
165
wire            inq_pipe15_we;
166
wire [2:0]       inq_pipe0;
167
wire [2:0]       inq_pipe1;
168
wire [2:0]       inq_pipe2;
169
wire [2:0]       inq_pipe3;
170
wire [2:0]       inq_pipe4;
171
wire [2:0]       inq_pipe5;
172
wire [2:0]       inq_pipe6;
173
wire [2:0]       inq_pipe7;
174
wire [2:0]       inq_pipe8;
175
wire [2:0]       inq_pipe9;
176
wire [2:0]       inq_pipe10;
177
wire [2:0]       inq_pipe11;
178
wire [2:0]       inq_pipe12;
179
wire [2:0]       inq_pipe13;
180
wire [2:0]       inq_pipe14;
181
wire [2:0]       inq_pipe15;
182
wire [2:0]       inq_pipe;
183
wire            inq_div;
184
wire            inq_diva;
185
wire            inq_diva_dly;
186
wire            d1stg_step_dly;
187
wire            inq_mul;
188
wire            inq_mula;
189
wire            inq_add;
190
wire            inq_adda;
191
wire            valid_packet;
192
wire            valid_packet_dly;
193
wire            tag_sel;
194
wire sehold_inv;
195
 
196
 
197
dffrl_async #(1)  dffrl_in_ctl (
198
  .din  (grst_l),
199
  .clk  (rclk),
200
  .rst_l(arst_l),
201
  .q    (in_ctl_rst_l),
202
        .se (se),
203
        .si (),
204
        .so ()
205
  );
206
 
207
assign reset= (!in_ctl_rst_l);
208
 
209
 
210
///////////////////////////////////////////////////////////////////////////////
211
//
212
//      Capture request and input control information.
213
//
214
///////////////////////////////////////////////////////////////////////////////
215
 
216
dffr_s #(1) i_fp_data_rdy (
217
        .din    (pcx_fpio_data_rdy_px2),
218
        .rst    (reset),
219
        .clk    (rclk),
220
 
221
        .q      (fp_data_rdy),
222
 
223
        .se     (se),
224
        .si     (),
225
        .so     ()
226
);
227
 
228
dff_s #(1) i_fp_vld_in (
229
        .din    (pcx_fpio_data_px2[123]),
230
        .clk    (rclk),
231
 
232
        .q      (fp_vld_in),
233
 
234
        .se     (se),
235
        .si     (),
236
        .so     ()
237
);
238
 
239
dff_s #(5) i_fp_type_in (
240
        .din    (pcx_fpio_data_px2[122:118]),
241
        .clk    (rclk),
242
 
243
        .q      (fp_type_in[4:0]),
244
 
245
        .se     (se),
246
        .si     (),
247
        .so     ()
248
);
249
 
250
 
251
///////////////////////////////////////////////////////////////////////////////
252
//
253
//      Select lines- extract the two operands.
254
//
255
///////////////////////////////////////////////////////////////////////////////
256
 
257
assign fp_op_in_7= fp_op_in_7in;
258
 
259
assign fp_op_in_7_inv= (!fp_op_in_7);
260
 
261
 
262
///////////////////////////////////////////////////////////////////////////////
263
//
264
//      Input queue control logic
265
//              - write enables
266
//              - write pointers
267
//              - read enables
268
//              - read pointers
269
//              - write address
270
//              - read address
271
//
272
///////////////////////////////////////////////////////////////////////////////
273
 
274
assign inq_we= fp_data_rdy && fp_vld_in
275
                && (((fp_type_in[4:0]==5'h0a) && fp_op_in_7)
276
                        || ((fp_type_in[4:0]==5'h0b) && fp_op_in_7_inv));
277
 
278
assign inq_wrptr_plus1[3:0]= inq_wrptr[3:0] + 4'h1;
279
 
280
assign inq_wrptr_step= inq_we && (!fp_div_in);
281
 
282
dffre_s #(4) i_inq_wrptr (
283
        .din    (inq_wrptr_plus1[3:0]),
284
        .en     (inq_wrptr_step),
285
        .rst    (reset),
286
        .clk    (rclk),
287
 
288
        .q      (inq_wrptr[3:0]),
289
 
290
        .se     (se),
291
        .si     (),
292
        .so     ()
293
);
294
 
295
assign inq_div_wrptr_plus1[3:0]= inq_div_wrptr[3:0] + 4'h1;
296
 
297
assign inq_div_wrptr_step= inq_we && fp_div_in;
298
 
299
dffre_s #(4) i_inq_div_wrptr (
300
        .din    (inq_div_wrptr_plus1[3:0]),
301
        .en     (inq_div_wrptr_step),
302
        .rst    (reset),
303
        .clk    (rclk),
304
 
305
        .q      (inq_div_wrptr[3:0]),
306
 
307
        .se     (se),
308
        .si     (),
309
        .so     ()
310
);
311
 
312
assign inq_wraddr[3:0]= {fp_div_in,
313
                (({3{fp_div_in}}
314
                            & inq_div_wrptr[2:0])
315
                    | ({3{(!fp_div_in)}}
316
                            & inq_wrptr[2:0]))};
317
 
318
dff_s #(4) i_inq_wraddr_del (
319
        .din    (inq_wraddr[3:0]),
320
        .clk    (rclk),
321
 
322
        .q      (inq_wraddr_del[3:0]),
323
 
324
        .se     (se),
325
        .si     (),
326
        .so     ()
327
);
328
 
329
assign inq_read_en = ~inq_empty | ~inq_div_empty;
330
 
331
assign inq_re= (inq_adda && a1stg_step)
332
                || (inq_mula && m1stg_step);
333
 
334
assign inq_rdptr_plus1[3:0]= inq_rdptr[3:0] + 4'h1;
335
 
336
assign inq_rdptr_in[3:0]= ({4{(inq_re && (!reset))}}
337
                            & inq_rdptr_plus1[3:0])
338
                | ({4{((!inq_re) && (!reset))}}
339
                            & inq_rdptr[3:0]);
340
 
341
dff_s #(4) i_inq_rdptr (
342
        .din    (inq_rdptr_in[3:0]),
343
        .clk    (rclk),
344
 
345
        .q      (inq_rdptr[3:0]),
346
 
347
        .se     (se),
348
        .si     (),
349
        .so     ()
350
);
351
 
352
assign inq_div_re= (inq_diva && d1stg_step);
353
 
354
assign inq_div_rdptr_plus1[3:0]= inq_div_rdptr[3:0] + 4'h1;
355
 
356
assign inq_div_rdptr_in[3:0]= ({4{(inq_div_re && (!reset))}}
357
                            & inq_div_rdptr_plus1[3:0])
358
                | ({4{((!inq_div_re) && (!reset))}}
359
                            & inq_div_rdptr[3:0]);
360
 
361
dff_s #(4) i_inq_div_rdptr (
362
        .din    (inq_div_rdptr_in[3:0]),
363
        .clk    (rclk),
364
 
365
        .q      (inq_div_rdptr[3:0]),
366
 
367
        .se     (se),
368
        .si     (),
369
        .so     ()
370
);
371
 
372
assign inq_div_rd_in= (!inq_div_empty) && d1stg_step && (!inq_diva);
373
 
374
dff_s #(1) i_inq_div_rd (
375
        .din    (inq_div_rd_in),
376
        .clk    (rclk),
377
 
378
        .q      (inq_div_rd),
379
 
380
        .se     (se),
381
        .si     (),
382
        .so     ()
383
);
384
 
385
assign inq_rdaddr[3:0]= {inq_div_rd_in,
386
                (({3{inq_div_rd_in}}
387
                            & (inq_div_rdptr[2:0] & {3{(!reset)}}))
388
                    | ({3{(!inq_div_rd_in)}}
389
                            & inq_rdptr_in[2:0]))};
390
 
391
dff_s #(4) i_inq_rdaddr_del (
392
        .din    (inq_rdaddr[3:0]),
393
        .clk    (rclk),
394
 
395
        .q      (inq_rdaddr_del[3:0]),
396
 
397
        .se     (se),
398
        .si     (),
399
        .so     ()
400
);
401
 
402
 
403
///////////////////////////////////////////////////////////////////////////////
404
//
405
//      Input queue empty and bypass signals.
406
//
407
///////////////////////////////////////////////////////////////////////////////
408
 
409
// Power management update
410
 
411
assign valid_packet = fp_data_rdy && fp_vld_in &&
412
                      ((fp_type_in[4:0]==5'h0a) || (fp_type_in[4:0]==5'h0b));
413
 
414
dffre_s #(1) i_valid_packet_dly (
415
        .din    (valid_packet),
416
        .en     (1'b1),
417
        .rst    (reset),
418
        .clk    (rclk),
419
 
420
        .q      (valid_packet_dly),
421
 
422
        .se     (se),
423
        .si     (),
424
        .so     ()
425
);
426
 
427
// Never bypass/forward invalid packets to the execution pipes
428
// assign inq_bp= (inq_wraddr_del[3:0]==inq_rdaddr_del[3:0]);
429
 
430
// 11/11/03: macrotest (AND with sehold_inv) 
431
assign sehold_inv = ~sehold;
432
 
433
assign inq_bp= (inq_wraddr_del[3:0]==inq_rdaddr_del[3:0]) && valid_packet_dly && sehold_inv;
434
 
435
assign inq_bp_inv= (!inq_bp);
436
 
437
assign inq_empty= (inq_wrptr[3:0]==inq_rdptr[3:0]);
438
 
439
assign inq_div_empty= (inq_div_wrptr[3:0]==inq_div_rdptr[3:0]);
440
 
441
// Power management update
442
// Never bypass/forward invalid packets to the execution pipes
443
// assign inq_fwrd= (inq_empty && (!inq_div_rd))
444
//              || (inq_div_empty && fp_div_in && fp_data_rdy && fp_vld_in
445
//                      && d1stg_step);
446
 
447
// 11/11/03: macrotest change (AND with sehold_inv) 
448
assign inq_fwrd= ((inq_empty && (!inq_div_rd))
449
                || (inq_div_empty && fp_div_in
450
                        && d1stg_step)) && valid_packet && sehold_inv;
451
 
452
assign inq_fwrd_inv= (!inq_fwrd);
453
 
454
 
455
///////////////////////////////////////////////////////////////////////////////
456
//
457
//      FPU pipe selection flags.
458
//
459
///////////////////////////////////////////////////////////////////////////////
460
 
461
assign fp_add_in= fp_data_rdy && fp_vld_in && (fp_type_in[4:1]==4'h5)
462
                && ((fp_op_in_7 && (!fp_type_in[0]))
463
                        || (fp_op_in_7_inv && (!fp_op_in[3]) && fp_type_in[0]));
464
 
465
assign fp_mul_in= fp_data_rdy && fp_vld_in && (fp_type_in[4:0]==5'h0b)
466
                && fp_op_in_7_inv && (fp_op_in[3:2]==2'b10);
467
 
468
assign fp_div_in= fp_data_rdy && fp_vld_in && (fp_type_in[4:0]==5'h0b)
469
                && fp_op_in_7_inv && (fp_op_in[3:2]==2'b11);
470
 
471
assign inq_rdptr_dec_in[7:0]= ({8{reset}}
472
                            & 8'h01)
473
                | ({8{(inq_re && (!reset))}}
474
                            & {inq_rdptr_dec[6:0], inq_rdptr_dec[7]})
475
                | ({8{((!inq_re) && (!reset))}}
476
                            & inq_rdptr_dec[7:0]);
477
 
478
dff_s #(8) i_inq_rdptr_dec (
479
        .din    (inq_rdptr_dec_in[7:0]),
480
        .clk    (rclk),
481
 
482
        .q      (inq_rdptr_dec[7:0]),
483
 
484
        .se     (se),
485
        .si     (),
486
        .so     ()
487
);
488
 
489
assign inq_div_rdptr_dec_in[7:0]= ({8{reset}}
490
                            & 8'h01)
491
                | ({8{(inq_div_re && (!reset))}}
492
                            & {inq_div_rdptr_dec[6:0], inq_div_rdptr_dec[7]})
493
                | ({8{((!inq_div_re) && (!reset))}}
494
                            & inq_div_rdptr_dec[7:0]);
495
 
496
dff_s #(8) i_inq_div_rdptr_dec (
497
        .din    (inq_div_rdptr_dec_in[7:0]),
498
        .clk    (rclk),
499
 
500
        .q      (inq_div_rdptr_dec[7:0]),
501
 
502
        .se     (se),
503
        .si     (),
504
        .so     ()
505
);
506
 
507
assign inq_rdaddr_del_dec_in[15:0]= ({16{((!inq_div_empty) && d1stg_step
508
                                        && (!inq_diva))}}
509
                            & {(inq_div_rdptr_dec[7:1] & {7{(!reset)}}),
510
                                (inq_div_rdptr_dec[0] || reset), 8'b0})
511
                | ({16{(!((!inq_div_empty) && d1stg_step && (!inq_diva)))}}
512
                            & {8'b0, inq_rdptr_dec_in[7:0]});
513
 
514
dff_s #16 i_inq_rdaddr_del_dec (
515
        .din    (inq_rdaddr_del_dec_in[15:0]),
516
        .clk    (rclk),
517
 
518
        .q      (inq_rdaddr_del_dec[15:0]),
519
 
520
        .se     (se),
521
        .si     (),
522
        .so     ()
523
);
524
 
525
assign inq_pipe0_we= inq_we && (!fp_div_in) && (inq_wrptr[2:0]==3'h0);
526
assign inq_pipe1_we= inq_we && (!fp_div_in) && (inq_wrptr[2:0]==3'h1);
527
assign inq_pipe2_we= inq_we && (!fp_div_in) && (inq_wrptr[2:0]==3'h2);
528
assign inq_pipe3_we= inq_we && (!fp_div_in) && (inq_wrptr[2:0]==3'h3);
529
assign inq_pipe4_we= inq_we && (!fp_div_in) && (inq_wrptr[2:0]==3'h4);
530
assign inq_pipe5_we= inq_we && (!fp_div_in) && (inq_wrptr[2:0]==3'h5);
531
assign inq_pipe6_we= inq_we && (!fp_div_in) && (inq_wrptr[2:0]==3'h6);
532
assign inq_pipe7_we= inq_we && (!fp_div_in) && (inq_wrptr[2:0]==3'h7);
533
 
534
assign inq_pipe8_we= inq_we && fp_div_in && (inq_div_wrptr[2:0]==3'h0);
535
assign inq_pipe9_we= inq_we && fp_div_in && (inq_div_wrptr[2:0]==3'h1);
536
assign inq_pipe10_we= inq_we && fp_div_in && (inq_div_wrptr[2:0]==3'h2);
537
assign inq_pipe11_we= inq_we && fp_div_in && (inq_div_wrptr[2:0]==3'h3);
538
assign inq_pipe12_we= inq_we && fp_div_in && (inq_div_wrptr[2:0]==3'h4);
539
assign inq_pipe13_we= inq_we && fp_div_in && (inq_div_wrptr[2:0]==3'h5);
540
assign inq_pipe14_we= inq_we && fp_div_in && (inq_div_wrptr[2:0]==3'h6);
541
assign inq_pipe15_we= inq_we && fp_div_in && (inq_div_wrptr[2:0]==3'h7);
542
 
543
dffre_s #(3) i_inq_pipe0 (
544
        .din    ({fp_div_in, fp_mul_in, fp_add_in}),
545
        .en     (inq_pipe0_we),
546
        .rst    (reset),
547
        .clk    (rclk),
548
 
549
        .q      (inq_pipe0[2:0]),
550
 
551
        .se     (se),
552
        .si     (),
553
        .so     ()
554
);
555
 
556
dffre_s #(3) i_inq_pipe1 (
557
        .din    ({fp_div_in, fp_mul_in, fp_add_in}),
558
        .en     (inq_pipe1_we),
559
        .rst    (reset),
560
        .clk    (rclk),
561
 
562
        .q      (inq_pipe1[2:0]),
563
 
564
        .se     (se),
565
        .si     (),
566
        .so     ()
567
);
568
 
569
dffre_s #(3) i_inq_pipe2 (
570
        .din    ({fp_div_in, fp_mul_in, fp_add_in}),
571
        .en     (inq_pipe2_we),
572
        .rst    (reset),
573
        .clk    (rclk),
574
 
575
        .q      (inq_pipe2[2:0]),
576
 
577
        .se     (se),
578
        .si     (),
579
        .so     ()
580
);
581
 
582
dffre_s #(3) i_inq_pipe3 (
583
        .din    ({fp_div_in, fp_mul_in, fp_add_in}),
584
        .en     (inq_pipe3_we),
585
        .rst    (reset),
586
        .clk    (rclk),
587
 
588
        .q      (inq_pipe3[2:0]),
589
 
590
        .se     (se),
591
        .si     (),
592
        .so     ()
593
);
594
 
595
dffre_s #(3) i_inq_pipe4 (
596
        .din    ({fp_div_in, fp_mul_in, fp_add_in}),
597
        .en     (inq_pipe4_we),
598
        .rst    (reset),
599
        .clk    (rclk),
600
 
601
        .q      (inq_pipe4[2:0]),
602
 
603
        .se     (se),
604
        .si     (),
605
        .so     ()
606
);
607
 
608
dffre_s #(3) i_inq_pipe5 (
609
        .din    ({fp_div_in, fp_mul_in, fp_add_in}),
610
        .en     (inq_pipe5_we),
611
        .rst    (reset),
612
        .clk    (rclk),
613
 
614
        .q      (inq_pipe5[2:0]),
615
 
616
        .se     (se),
617
        .si     (),
618
        .so     ()
619
);
620
 
621
dffre_s #(3) i_inq_pipe6 (
622
        .din    ({fp_div_in, fp_mul_in, fp_add_in}),
623
        .en     (inq_pipe6_we),
624
        .rst    (reset),
625
        .clk    (rclk),
626
 
627
        .q      (inq_pipe6[2:0]),
628
 
629
        .se     (se),
630
        .si     (),
631
        .so     ()
632
);
633
 
634
dffre_s #(3) i_inq_pipe7 (
635
        .din    ({fp_div_in, fp_mul_in, fp_add_in}),
636
        .en     (inq_pipe7_we),
637
        .rst    (reset),
638
        .clk    (rclk),
639
 
640
        .q      (inq_pipe7[2:0]),
641
 
642
        .se     (se),
643
        .si     (),
644
        .so     ()
645
);
646
 
647
dffre_s #(3) i_inq_pipe8 (
648
        .din    ({fp_div_in, fp_mul_in, fp_add_in}),
649
        .en     (inq_pipe8_we),
650
        .rst    (reset),
651
        .clk    (rclk),
652
 
653
        .q      (inq_pipe8[2:0]),
654
 
655
        .se     (se),
656
        .si     (),
657
        .so     ()
658
);
659
 
660
dffre_s #(3) i_inq_pipe9 (
661
        .din    ({fp_div_in, fp_mul_in, fp_add_in}),
662
        .en     (inq_pipe9_we),
663
        .rst    (reset),
664
        .clk    (rclk),
665
 
666
        .q      (inq_pipe9[2:0]),
667
 
668
        .se     (se),
669
        .si     (),
670
        .so     ()
671
);
672
 
673
dffre_s #(3) i_inq_pipe10 (
674
        .din    ({fp_div_in, fp_mul_in, fp_add_in}),
675
        .en     (inq_pipe10_we),
676
        .rst    (reset),
677
        .clk    (rclk),
678
 
679
        .q      (inq_pipe10[2:0]),
680
 
681
        .se     (se),
682
        .si     (),
683
        .so     ()
684
);
685
 
686
dffre_s #(3) i_inq_pipe11 (
687
        .din    ({fp_div_in, fp_mul_in, fp_add_in}),
688
        .en     (inq_pipe11_we),
689
        .rst    (reset),
690
        .clk    (rclk),
691
 
692
        .q      (inq_pipe11[2:0]),
693
 
694
        .se     (se),
695
        .si     (),
696
        .so     ()
697
);
698
 
699
dffre_s #(3) i_inq_pipe12 (
700
        .din    ({fp_div_in, fp_mul_in, fp_add_in}),
701
        .en     (inq_pipe12_we),
702
        .rst    (reset),
703
        .clk    (rclk),
704
 
705
        .q      (inq_pipe12[2:0]),
706
 
707
        .se     (se),
708
        .si     (),
709
        .so     ()
710
);
711
 
712
dffre_s #(3) i_inq_pipe13 (
713
        .din    ({fp_div_in, fp_mul_in, fp_add_in}),
714
        .en     (inq_pipe13_we),
715
        .rst    (reset),
716
        .clk    (rclk),
717
 
718
        .q      (inq_pipe13[2:0]),
719
 
720
        .se     (se),
721
        .si     (),
722
        .so     ()
723
);
724
 
725
dffre_s #(3) i_inq_pipe14 (
726
        .din    ({fp_div_in, fp_mul_in, fp_add_in}),
727
        .en     (inq_pipe14_we),
728
        .rst    (reset),
729
        .clk    (rclk),
730
 
731
        .q      (inq_pipe14[2:0]),
732
 
733
        .se     (se),
734
        .si     (),
735
        .so     ()
736
);
737
 
738
dffre_s #(3) i_inq_pipe15 (
739
        .din    ({fp_div_in, fp_mul_in, fp_add_in}),
740
        .en     (inq_pipe15_we),
741
        .rst    (reset),
742
        .clk    (rclk),
743
 
744
        .q      (inq_pipe15[2:0]),
745
 
746
        .se     (se),
747
        .si     (),
748
        .so     ()
749
);
750
 
751
// Power management update
752
// 3-bit fifo pipe tags (div,mul,add) are not cleared after use.
753
// Now that inq_fwrd is qualified by valid_packet, inq_fwrd can't be
754
// used for inq_pipe[2:0] selection.
755
 
756
assign tag_sel = (inq_empty && (!inq_div_rd))
757
                || (inq_div_empty && fp_div_in && fp_data_rdy && fp_vld_in
758
                        && d1stg_step);
759
 
760
assign inq_pipe[2:0]= ({3{tag_sel}}
761
                                // Austin update
762
                                // performance change: allow div to bypass FIFO (2 cyc latency reduction)
763
                            & {(inq_div_empty && fp_div_in && fp_data_rdy && fp_vld_in
764
                                && d1stg_step
765
                                && d1stg_step_dly && (!inq_diva_dly)),
766
                                fp_mul_in,
767
                                fp_add_in})
768
                | ({3{(!tag_sel)}}
769
                            & (({3{inq_rdaddr_del_dec[0]}}
770
                                        & inq_pipe0[2:0])
771
                                | ({3{inq_rdaddr_del_dec[1]}}
772
                                        & inq_pipe1[2:0])
773
                                | ({3{inq_rdaddr_del_dec[2]}}
774
                                        & inq_pipe2[2:0])
775
                                | ({3{inq_rdaddr_del_dec[3]}}
776
                                        & inq_pipe3[2:0])
777
                                | ({3{inq_rdaddr_del_dec[4]}}
778
                                        & inq_pipe4[2:0])
779
                                | ({3{inq_rdaddr_del_dec[5]}}
780
                                        & inq_pipe5[2:0])
781
                                | ({3{inq_rdaddr_del_dec[6]}}
782
                                        & inq_pipe6[2:0])
783
                                | ({3{inq_rdaddr_del_dec[7]}}
784
                                        & inq_pipe7[2:0])
785
                                | ({3{inq_rdaddr_del_dec[8]}}
786
                                        & inq_pipe8[2:0])
787
                                | ({3{inq_rdaddr_del_dec[9]}}
788
                                        & inq_pipe9[2:0])
789
                                | ({3{inq_rdaddr_del_dec[10]}}
790
                                        & inq_pipe10[2:0])
791
                                | ({3{inq_rdaddr_del_dec[11]}}
792
                                        & inq_pipe11[2:0])
793
                                | ({3{inq_rdaddr_del_dec[12]}}
794
                                        & inq_pipe12[2:0])
795
                                | ({3{inq_rdaddr_del_dec[13]}}
796
                                        & inq_pipe13[2:0])
797
                                | ({3{inq_rdaddr_del_dec[14]}}
798
                                        & inq_pipe14[2:0])
799
                                | ({3{inq_rdaddr_del_dec[15]}}
800
                                        & inq_pipe15[2:0])));
801
 
802
assign inq_div= inq_pipe[2];
803
assign inq_diva= inq_pipe[2];
804
assign inq_mul= inq_pipe[1];
805
assign inq_mula= inq_pipe[1];
806
assign inq_add= inq_pipe[0];
807
assign inq_adda= inq_pipe[0];
808
 
809
 
810
// Power management update
811
// Gate the clocks on a per pipe basis (add, mul, div independently)
812
// when a given pipe is not in use
813
 
814
dffre_s #(1) i_inq_adda_dly (
815
        .din    (inq_adda),
816
        .en     (1'b1),
817
        .rst    (reset),
818
        .clk    (rclk),
819
 
820
        .q      (inq_adda_dly),
821
 
822
        .se     (se),
823
        .si     (),
824
        .so     ()
825
);
826
 
827
dffre_s #(1) i_inq_mula_dly (
828
        .din    (inq_mula),
829
        .en     (1'b1),
830
        .rst    (reset),
831
        .clk    (rclk),
832
 
833
        .q      (inq_mula_dly),
834
 
835
        .se     (se),
836
        .si     (),
837
        .so     ()
838
);
839
 
840
dffre_s #(1) i_inq_diva_dly (
841
        .din    (inq_diva),
842
        .en     (1'b1),
843
        .rst    (reset),
844
        .clk    (rclk),
845
 
846
        .q      (inq_diva_dly),
847
 
848
        .se     (se),
849
        .si     (),
850
        .so     ()
851
);
852
 
853
dffre_s #(1) i_d1stg_step_dly (
854
        .din    (d1stg_step),
855
        .en     (1'b1),
856
        .rst    (reset),
857
        .clk    (rclk),
858
 
859
        .q      (d1stg_step_dly),
860
 
861
        .se     (se),
862
        .si     (),
863
        .so     ()
864
);
865
 
866
assign fadd_clken_l = !(add_pipe_active || inq_adda || inq_adda_dly || reset);
867
assign fmul_clken_l = !(mul_pipe_active || inq_mula || inq_mula_dly || reset);
868
assign fdiv_clken_l = !(div_pipe_active || inq_diva || inq_diva_dly || reset);
869
 
870
 
871
endmodule
872
 
873
 

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