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[/] [sparc64soc/] [trunk/] [T1-FPU/] [fpu_in_dp.v] - Blame information for rev 2

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1 2 dmitryr
// ========== Copyright Header Begin ==========================================
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// 
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// OpenSPARC T1 Processor File: fpu_in_dp.v
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// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// 
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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// 
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// The above named program is distributed in the hope that it will be 
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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// General Public License for more details.
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// 
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// 
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// ========== Copyright Header End ============================================
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///////////////////////////////////////////////////////////////////////////////
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//
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//      FPU input datapath.
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//
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///////////////////////////////////////////////////////////////////////////////
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module fpu_in_dp (
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        fp_data_rdy,
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        fpio_data_px2_116_112,
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        fpio_data_px2_79_72,
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        fpio_data_px2_67_0,
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        inq_fwrd,
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        inq_fwrd_inv,
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        inq_bp,
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        inq_bp_inv,
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        inq_dout,
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        rclk,
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        fp_op_in_7in,
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        inq_id,
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        inq_rnd_mode,
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        inq_fcc,
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        inq_op,
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        inq_in1_exp_neq_ffs,
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        inq_in1_exp_eq_0,
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        inq_in1_53_0_neq_0,
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        inq_in1_50_0_neq_0,
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        inq_in1_53_32_neq_0,
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        inq_in1,
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        inq_in2_exp_neq_ffs,
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        inq_in2_exp_eq_0,
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        inq_in2_53_0_neq_0,
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        inq_in2_50_0_neq_0,
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        inq_in2_53_32_neq_0,
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        inq_in2,
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        fp_id_in,
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        fp_rnd_mode_in,
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        fp_fcc_in,
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        fp_op_in,
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        fp_src1_in,
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        fp_src2_in,
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64
        se,
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        si,
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        so
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);
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69
 
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input           fp_data_rdy;
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input [116:112] fpio_data_px2_116_112;  // FPU request data from PCX
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input [79:72]   fpio_data_px2_79_72;    // FPU request data from PCX
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input [67:0]    fpio_data_px2_67_0;     // FPU request data from PCX
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input           inq_fwrd;               // input Q is empty
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input           inq_fwrd_inv;           // input Q is not empty
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input           inq_bp;                 // bypass the input Q SRAM
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input           inq_bp_inv;             // don't bypass the input Q SRAM
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input [154:0] inq_dout; // data read out from input Q SRAM
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input           rclk;           // global clock
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81
output          fp_op_in_7in;           // request opcode
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output [4:0]     inq_id;                 // request ID to the operation pipes
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output [1:0]     inq_rnd_mode;           // request rounding mode to op pipes
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output [1:0]     inq_fcc;                // request cc ID to op pipes
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output [7:0]     inq_op;                 // request opcode to op pipes
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output          inq_in1_exp_neq_ffs;    // request operand 1 exp!=ff's
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output          inq_in1_exp_eq_0;       // request operand 1 exp==0
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output          inq_in1_53_0_neq_0;     // request operand 1[53:0]!=0
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output          inq_in1_50_0_neq_0;     // request operand 1[50:0]!=0
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output          inq_in1_53_32_neq_0;    // request operand 1[53:32]!=0
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output [63:0]    inq_in1;                // request operand 1 to op pipes
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output          inq_in2_exp_neq_ffs;    // request operand 2 exp!=ff's
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output          inq_in2_exp_eq_0;       // request operand 2 exp==0
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output          inq_in2_53_0_neq_0;     // request operand 2[53:0]!=0
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output          inq_in2_50_0_neq_0;     // request operand 2[50:0]!=0
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output          inq_in2_53_32_neq_0;    // request operand 2[53:32]!=0
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output [63:0]    inq_in2;                // request operand 2 to op pipes
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// 6/20/03: New outputs to drive fpu-level i_fpu_inq_sram inputs 
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output [4:0] fp_id_in; // id to be written into inq_sram
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output [1:0] fp_rnd_mode_in; // rnd_mode to be written into inq_sram
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output [1:0] fp_fcc_in; // fcc to be written into inq_sram
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output [7:0] fp_op_in; // request opcode
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output [68:0] fp_src1_in; // operand1 and its pre-computed bits portion
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output [68:0] fp_src2_in; // operand2, includes pre-computed bits
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input           se;                     // scan_enable
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input           si;                     // scan in
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output          so;                     // scan out
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111
 
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wire [154:0]     inq_dout;
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wire [4:0]       fp_id_in;
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wire [7:0]       fp_op_in;
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wire            fp_op_in_7;             // request opcode bit[7]
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wire            fp_op_in_7_inv;         // inverted request opcode bit[7]
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wire            fp_op_in_7in;
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wire [1:0]       fp_fcc_in;
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wire [1:0]       fp_rnd_mode_in;
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wire [63:0]      fp_srca_in;
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wire            fp_srca_53_0_neq_0;
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wire            fp_srca_50_0_neq_0;
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wire            fp_srca_53_32_neq_0;
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wire            fp_srca_exp_eq_0;
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wire            fp_srca_exp_neq_ffs;
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wire [68:0]      fp_srcb_in;
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wire [68:0]      fp_src1_in;
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wire [68:0]      fp_src2_in;
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wire [154:0]     inq_din_d1;
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wire [154:0]     inq_data;
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wire [4:0]       inq_id;
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wire [1:0]       inq_rnd_mode;
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wire [1:0]       inq_fcc;
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wire [7:0]       inq_op;
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wire            inq_in1_exp_neq_ffs;
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wire            inq_in1_exp_eq_0;
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wire            inq_in1_53_0_neq_0;
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wire            inq_in1_50_0_neq_0;
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wire            inq_in1_53_32_neq_0;
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wire [63:0]      inq_in1;
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wire            inq_in2_exp_neq_ffs;
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wire            inq_in2_exp_eq_0;
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wire            inq_in2_53_0_neq_0;
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wire            inq_in2_50_0_neq_0;
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wire            inq_in2_53_32_neq_0;
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wire [63:0]      inq_in2;
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148
wire clk;
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150
wire se_l;
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152
// 6/23/03: Replaced tm_l with se_l 
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assign se_l = ~se;
154
 
155
clken_buf  ckbuf_in_dp (
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  .clk(clk),
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  .rclk(rclk),
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  .enb_l(1'b0),
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  .tmb_l(se_l)
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  );
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162
///////////////////////////////////////////////////////////////////////////////
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//
164
//      Capture input information.
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//
166
///////////////////////////////////////////////////////////////////////////////
167
 
168
dff_s #(5) i_fp_id_in (
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        .din    (fpio_data_px2_116_112[116:112]),
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        .clk    (clk),
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172
        .q      (fp_id_in[4:0]),
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        .se     (se),
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        .si     (),
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        .so     ()
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);
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dff_s #(8) i_fp_op_in (
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        .din    (fpio_data_px2_79_72[79:72]),
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        .clk    (clk),
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        .q      (fp_op_in[7:0]),
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        .se     (se),
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        .si     (),
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        .so     ()
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);
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assign fp_op_in_7in = fp_op_in[7];
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assign fp_op_in_7 = fp_op_in[7];
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assign fp_op_in_7_inv = ~fp_op_in[7];
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dff_s #(2) i_fp_fcc_in (
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        .din    (fpio_data_px2_67_0[67:66]),
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        .clk    (clk),
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        .q      (fp_fcc_in[1:0]),
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200
        .se     (se),
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        .si     (),
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        .so     ()
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);
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dff_s #(2) i_fp_rnd_mode_in (
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        .din    (fpio_data_px2_67_0[65:64]),
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        .clk    (clk),
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        .q      (fp_rnd_mode_in[1:0]),
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        .se     (se),
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        .si     (),
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        .so     ()
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);
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dff_s #(64) i_fp_srca_in (
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        .din    (fpio_data_px2_67_0[63:0]),
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        .clk    (clk),
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        .q      (fp_srca_in[63:0]),
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        .se     (se),
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        .si     (),
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        .so     ()
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);
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assign fp_srca_53_0_neq_0= (|fp_srca_in[53:0]);
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229
assign fp_srca_50_0_neq_0= (|fp_srca_in[50:0]);
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231
assign fp_srca_53_32_neq_0= (|fp_srca_in[53:32]);
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assign fp_srca_exp_eq_0= (!((|fp_srca_in[62:55])
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                || (fp_op_in[1] && (|fp_srca_in[54:52]))));
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assign fp_srca_exp_neq_ffs= (!((&fp_srca_in[62:55])
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                && (fp_op_in[0] || (&fp_srca_in[54:52]))));
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240
///////////////////////////////////////////////////////////////////////////////
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//
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//      Extract the two operands.
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//
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///////////////////////////////////////////////////////////////////////////////
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dffe_s #(69) i_fp_srcb_in (
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        .din    ({fp_srca_exp_neq_ffs, fp_srca_exp_eq_0, fp_srca_53_0_neq_0,
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                        fp_srca_50_0_neq_0, fp_srca_53_32_neq_0,
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                        fp_srca_in[63:0]}),
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        .en     (fp_data_rdy),
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        .clk    (clk),
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        .q      (fp_srcb_in[68:0]),
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255
        .se     (se),
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        .si     (),
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        .so     ()
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);
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assign fp_src1_in[68:0]= ({69{fp_op_in_7_inv}}
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                            & {fp_srca_exp_neq_ffs, fp_srca_exp_eq_0,
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                                fp_srca_53_0_neq_0, fp_srca_50_0_neq_0,
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                                fp_srca_53_32_neq_0, fp_srca_in[63:0]})
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                | ({69{fp_op_in_7}}
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                            & 69'h180000000000000000);
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assign fp_src2_in[68:0]= ({69{fp_op_in_7_inv}}
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                            & fp_srcb_in[68:0])
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                | ({69{fp_op_in_7}}
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                            & {fp_srca_exp_neq_ffs, fp_srca_exp_eq_0,
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                                fp_srca_53_0_neq_0, fp_srca_50_0_neq_0,
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                                fp_srca_53_32_neq_0, fp_srca_in[63:0]});
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///////////////////////////////////////////////////////////////////////////////
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//
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//      Input queue FIFO bypass and output.
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//
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///////////////////////////////////////////////////////////////////////////////
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dff_s #(155) i_inq_din_d1 (
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        .din    ({fp_id_in[4:0], fp_rnd_mode_in[1:0], fp_fcc_in[1:0],
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                        fp_op_in[7:0], fp_src1_in[68:0], fp_src2_in[68:0]}),
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        .clk    (clk),
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        .q      (inq_din_d1[154:0]),
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        .se     (se),
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        .si     (),
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        .so     ()
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);
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assign inq_data[154:0]= ({155{inq_fwrd}}
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                            & {fp_id_in[4:0], fp_rnd_mode_in[1:0],
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                                fp_fcc_in[1:0], fp_op_in[7:0],
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                                fp_src1_in[68:0], fp_src2_in[68:0]})
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                | ({155{inq_fwrd_inv}}
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                            & (({155{inq_bp}}
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                                        & inq_din_d1[154:0])
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                                | ({155{inq_bp_inv}}
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                                        & inq_dout[154:0])));
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304
assign inq_id[4:0]= inq_data[154:150];
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assign inq_rnd_mode[1:0]= inq_data[149:148];
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assign inq_fcc[1:0]= inq_data[147:146];
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assign inq_op[7:0]= inq_data[145:138];
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assign inq_in1_exp_neq_ffs= inq_data[137];
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assign inq_in1_exp_eq_0= inq_data[136];
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assign inq_in1_53_0_neq_0= inq_data[135];
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assign inq_in1_50_0_neq_0= inq_data[134];
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assign inq_in1_53_32_neq_0= inq_data[133];
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assign inq_in1[63:0]= inq_data[132:69];
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assign inq_in2_exp_neq_ffs= inq_data[68];
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assign inq_in2_exp_eq_0= inq_data[67];
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assign inq_in2_53_0_neq_0= inq_data[66];
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assign inq_in2_50_0_neq_0= inq_data[65];
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assign inq_in2_53_32_neq_0= inq_data[64];
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assign inq_in2[63:0]= inq_data[63:0];
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321
 
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endmodule
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