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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: fpu_mul.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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///////////////////////////////////////////////////////////////////////////////
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//
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// FPU multiply pipe.
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//
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///////////////////////////////////////////////////////////////////////////////
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module fpu_mul (
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inq_op,
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inq_rnd_mode,
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inq_id,
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inq_in1,
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inq_in1_53_0_neq_0,
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inq_in1_50_0_neq_0,
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inq_in1_53_32_neq_0,
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inq_in1_exp_eq_0,
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inq_in1_exp_neq_ffs,
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inq_in2,
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inq_in2_53_0_neq_0,
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inq_in2_50_0_neq_0,
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inq_in2_53_32_neq_0,
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inq_in2_exp_eq_0,
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inq_in2_exp_neq_ffs,
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inq_mul,
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mul_dest_rdy,
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mul_dest_rdya,
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fmul_clken_l,
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fmul_clken_l_buf1,
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arst_l,
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grst_l,
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rclk,
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mul_pipe_active,
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m1stg_step,
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m6stg_fmul_in,
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m6stg_id_in,
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mul_exc_out,
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m6stg_fmul_dbl_dst,
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m6stg_fmuls,
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mul_sign_out,
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mul_exp_out,
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mul_frac_out,
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se_mul,
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se_mul64,
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si,
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so
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);
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input [7:0] inq_op; // request opcode to op pipes
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input [1:0] inq_rnd_mode; // request rounding mode to op pipes
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input [4:0] inq_id; // request ID to the operation pipes
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input [63:0] inq_in1; // request operand 1 to op pipes
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input inq_in1_53_0_neq_0; // request operand 1[53:0]!=0
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input inq_in1_50_0_neq_0; // request operand 1[50:0]!=0
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input inq_in1_53_32_neq_0; // request operand 1[53:32]!=0
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input inq_in1_exp_eq_0; // request operand 1 exp==0
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input inq_in1_exp_neq_ffs; // request operand 1 exp!=0xff's
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input [63:0] inq_in2; // request operand 2 to op pipes
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input inq_in2_53_0_neq_0; // request operand 2[53:0]!=0
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input inq_in2_50_0_neq_0; // request operand 2[50:0]!=0
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input inq_in2_53_32_neq_0; // request operand 2[53:32]!=0
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input inq_in2_exp_eq_0; // request operand 2 exp==0
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input inq_in2_exp_neq_ffs; // request operand 2 exp!=0xff's
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input inq_mul; // multiply pipe request
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input mul_dest_rdy; // multiply result req accepted for CPX
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input mul_dest_rdya; // multiply result req accepted for CPX
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input fmul_clken_l; // fmul clock enable for mul_frac_dp
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input fmul_clken_l_buf1; // fmul clock enable for mul_exp_dp
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input arst_l; // global asynch. reset- asserted low
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input grst_l; // global synch. reset- asserted low
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input rclk; // global clock
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output mul_pipe_active; // mul pipe is executing a valid instr
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output m1stg_step; // multiply pipe load
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output m6stg_fmul_in; // mul pipe output request next cycle
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output [9:0] m6stg_id_in; // mul pipe output ID next cycle
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output [4:0] mul_exc_out; // multiply pipe result- exception flags
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output m6stg_fmul_dbl_dst; // double precision multiply result
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output m6stg_fmuls; // fmuls- multiply 6 stage
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output mul_sign_out; // multiply sign output
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output [10:0] mul_exp_out; // multiply exponent output
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output [51:0] mul_frac_out; // multiply fraction output
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input se_mul; // scan_enable for mul_frac_dp, mul_ctl, mul_exp_dp
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input se_mul64; // scan_enable for mul64
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input si; // scan in
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output so; // scan out
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///////////////////////////////////////////////////////////////////////////////
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//
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// Outputs of fpu_mul_ctl.
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//
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///////////////////////////////////////////////////////////////////////////////
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wire m1stg_snan_sng_in1; // operand 1 is single signalling NaN
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wire m1stg_snan_dbl_in1; // operand 1 is double signalling NaN
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wire m1stg_snan_sng_in2; // operand 2 is single signalling NaN
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wire m1stg_snan_dbl_in2; // operand 2 is double signalling NaN
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wire m1stg_step; // multiply pipe load
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wire m1stg_sngop; // single precision operation- mul 1 stg
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wire m1stg_dblop; // double precision operation- mul 1 stg
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wire m1stg_dblop_inv; // single or int operation- mul 1 stg
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wire m1stg_fmul; // multiply operation- mul 1 stage
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wire m1stg_fsmuld; // fsmuld- multiply 1 stage
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wire m2stg_fmuls; // fmuls- multiply 2 stage
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wire m2stg_fmuld; // fmuld- multiply 2 stage
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wire m2stg_fsmuld; // fsmuld- multiply 2 stage
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wire m5stg_fmuls; // fmuls- multiply 5 stage
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wire m5stg_fmuld; // fmuld- multiply 5 stage
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wire m5stg_fmulda; // fmuld- multiply 5 stage copy
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wire m6stg_fmul_in; // mul pipe output request next cycle
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wire [9:0] m6stg_id_in; // mul pipe output ID next cycle
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wire m6stg_fmul_dbl_dst; // double precision multiply result
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wire m6stg_fmuls; // fmuls- multiply 6 stage
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wire m6stg_step; // advance the multiply pipe
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wire mul_sign_out; // multiply sign output
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wire m5stg_in_of; // multiply overflow- select exp out
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wire [4:0] mul_exc_out; // multiply pipe result- exception flags
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wire m2stg_frac1_dbl_norm; // select line to m2stg_frac1
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wire m2stg_frac1_dbl_dnrm; // select line to m2stg_frac1
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wire m2stg_frac1_sng_norm; // select line to m2stg_frac1
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wire m2stg_frac1_sng_dnrm; // select line to m2stg_frac1
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wire m2stg_frac1_inf; // select line to m2stg_frac1
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wire m2stg_frac2_dbl_norm; // select line to m2stg_frac2
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wire m2stg_frac2_dbl_dnrm; // select line to m2stg_frac2
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wire m2stg_frac2_sng_norm; // select line to m2stg_frac2
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wire m2stg_frac2_sng_dnrm; // select line to m2stg_frac2
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wire m2stg_frac2_inf; // select line to m2stg_frac2
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wire m1stg_inf_zero_in; // 1 operand is infinity; other is 0
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wire m1stg_inf_zero_in_dbl; // 1 opnd is infinity; other is 0- dbl
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wire m2stg_exp_expadd; // select line to m2stg_exp
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wire m2stg_exp_0bff; // select line to m2stg_exp
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wire m2stg_exp_017f; // select line to m2stg_exp
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wire m2stg_exp_04ff; // select line to m2stg_exp
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wire m2stg_exp_zero; // select line to m2stg_exp
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wire [6:0] m3bstg_ld0_inv; // leading 0's in multiply operands
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wire [5:0] m4stg_sh_cnt_in; // multiply normalization shift count
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wire m4stg_inc_exp_54; // select line to m5stg_exp
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wire m4stg_inc_exp_55; // select line to m5stg_exp
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wire m4stg_inc_exp_105; // select line to m5stg_exp
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wire m4stg_left_shift_step; // select line to m5stg_frac
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wire m4stg_right_shift_step; // select line to m5stg_frac
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wire m5stg_to_0; // result to max finite on overflow
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wire m5stg_to_0_inv; // result to infinity on overflow
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wire mul_frac_out_fracadd; // select line to mul_frac_out
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wire mul_frac_out_frac; // select line to mul_frac_out
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wire mul_exp_out_exp_plus1; // select line to mul_exp_out
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wire mul_exp_out_exp; // select line to mul_exp_out
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wire mul_pipe_active; // mul pipe is executing a valid instr
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// 3/14/03: output of dffrl_async is an input to mul64
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wire mul_rst_l; // reset (active low) signal for mul64
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///////////////////////////////////////////////////////////////////////////////
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//
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// Outputs of fpu_mul_exp_dp.
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//
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///////////////////////////////////////////////////////////////////////////////
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wire [12:0] m3stg_exp; // exponent input- multiply 3 stage
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wire m3stg_expadd_eq_0; // mul stage 3 exponent adder sum == 0
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wire m3stg_expadd_lte_0_inv; // mul stage 3 exponent adder sum <= 0
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wire [12:0] m4stg_exp; // exponent input- multiply 4 stage
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wire [12:0] m5stg_exp; // exponent input- multiply 5 stage
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wire [10:0] mul_exp_out; // multiply exponent output
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///////////////////////////////////////////////////////////////////////////////
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//
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// Outputs of fpu_mul_frac_dp.
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//
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///////////////////////////////////////////////////////////////////////////////
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wire [52:0] m2stg_frac1_array_in; // multiply array input 1
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wire [52:0] m2stg_frac2_array_in; // multiply array input 2
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wire [5:0] m1stg_ld0_1; // denorm operand 1 leading 0's
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wire [5:0] m1stg_ld0_2; // denorm operand 2 leading 0's
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wire m4stg_frac_105; // multiply stage 4a fraction input[105]
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wire [6:0] m3stg_ld0_inv; // leading 0's in multiply operands
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wire m4stg_shl_54; // multiply shift left output bit[54]
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wire m4stg_shl_55; // multiply shift left output bit[55]
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wire [32:0] m5stg_frac_32_0; // multiply stage 5 fraction input
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wire m5stg_frac_dbl_nx; // double precision inexact result
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wire m5stg_frac_sng_nx; // single precision inexact result
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wire m5stg_frac_neq_0; // fraction input to mul 5 stage != 0
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wire m5stg_fracadd_cout; // fraction rounding adder carry out
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wire [51:0] mul_frac_out; // multiply fraction output
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///////////////////////////////////////////////////////////////////////////////
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//
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// Outputs of mul64
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//
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///////////////////////////////////////////////////////////////////////////////
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wire [105:0] m4stg_frac; // multiply array output
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wire [29:0] m4stg_frac_unused; // unused upper 30 bits (135:106) of the mul64 output
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///////////////////////////////////////////////////////////////////////////////
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//
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// Instantiations.
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//
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///////////////////////////////////////////////////////////////////////////////
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fpu_mul_ctl fpu_mul_ctl (
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.inq_in1_51 (inq_in1[51]),
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.inq_in1_54 (inq_in1[54]),
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.inq_in1_53_0_neq_0 (inq_in1_53_0_neq_0),
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.inq_in1_50_0_neq_0 (inq_in1_50_0_neq_0),
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.inq_in1_53_32_neq_0 (inq_in1_53_32_neq_0),
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.inq_in1_exp_eq_0 (inq_in1_exp_eq_0),
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.inq_in1_exp_neq_ffs (inq_in1_exp_neq_ffs),
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.inq_in2_51 (inq_in2[51]),
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.inq_in2_54 (inq_in2[54]),
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| 240 |
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.inq_in2_53_0_neq_0 (inq_in2_53_0_neq_0),
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| 241 |
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.inq_in2_50_0_neq_0 (inq_in2_50_0_neq_0),
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| 242 |
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.inq_in2_53_32_neq_0 (inq_in2_53_32_neq_0),
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| 243 |
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.inq_in2_exp_eq_0 (inq_in2_exp_eq_0),
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| 244 |
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.inq_in2_exp_neq_ffs (inq_in2_exp_neq_ffs),
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| 245 |
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.inq_op (inq_op[7:0]),
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| 246 |
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.inq_mul (inq_mul),
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| 247 |
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.inq_rnd_mode (inq_rnd_mode[1:0]),
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| 248 |
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.inq_id (inq_id[4:0]),
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| 249 |
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.inq_in1_63 (inq_in1[63]),
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| 250 |
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.inq_in2_63 (inq_in2[63]),
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| 251 |
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.mul_dest_rdy (mul_dest_rdy),
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| 252 |
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.mul_dest_rdya (mul_dest_rdya),
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| 253 |
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.m5stg_exp (m5stg_exp[12:0]),
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| 254 |
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.m5stg_fracadd_cout (m5stg_fracadd_cout),
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| 255 |
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.m5stg_frac_neq_0 (m5stg_frac_neq_0),
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| 256 |
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.m5stg_frac_dbl_nx (m5stg_frac_dbl_nx),
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| 257 |
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.m5stg_frac_sng_nx (m5stg_frac_sng_nx),
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| 258 |
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.m1stg_ld0_1 (m1stg_ld0_1[5:0]),
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| 259 |
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.m1stg_ld0_2 (m1stg_ld0_2[5:0]),
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| 260 |
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.m3stg_exp (m3stg_exp[12:0]),
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| 261 |
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.m3stg_expadd_eq_0 (m3stg_expadd_eq_0),
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| 262 |
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.m3stg_expadd_lte_0_inv (m3stg_expadd_lte_0_inv),
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| 263 |
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.m3stg_ld0_inv (m3stg_ld0_inv[5:0]),
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| 264 |
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.m4stg_exp (m4stg_exp[12:0]),
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| 265 |
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.m4stg_frac_105 (m4stg_frac_105),
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| 266 |
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.m5stg_frac (m5stg_frac_32_0[32:0]),
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| 267 |
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.arst_l (arst_l),
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| 268 |
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.grst_l (grst_l),
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| 269 |
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.mula_rst_l (mul_rst_l),
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| 270 |
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.rclk (rclk),
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| 271 |
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| 272 |
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.mul_pipe_active (mul_pipe_active),
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| 273 |
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.m1stg_snan_sng_in1 (m1stg_snan_sng_in1),
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| 274 |
|
|
.m1stg_snan_dbl_in1 (m1stg_snan_dbl_in1),
|
| 275 |
|
|
.m1stg_snan_sng_in2 (m1stg_snan_sng_in2),
|
| 276 |
|
|
.m1stg_snan_dbl_in2 (m1stg_snan_dbl_in2),
|
| 277 |
|
|
.m1stg_step (m1stg_step),
|
| 278 |
|
|
.m1stg_sngop (m1stg_sngop),
|
| 279 |
|
|
.m1stg_dblop (m1stg_dblop),
|
| 280 |
|
|
.m1stg_dblop_inv (m1stg_dblop_inv),
|
| 281 |
|
|
.m1stg_fmul (m1stg_fmul),
|
| 282 |
|
|
.m1stg_fsmuld (m1stg_fsmuld),
|
| 283 |
|
|
.m2stg_fmuls (m2stg_fmuls),
|
| 284 |
|
|
.m2stg_fmuld (m2stg_fmuld),
|
| 285 |
|
|
.m2stg_fsmuld (m2stg_fsmuld),
|
| 286 |
|
|
.m5stg_fmuls (m5stg_fmuls),
|
| 287 |
|
|
.m5stg_fmuld (m5stg_fmuld),
|
| 288 |
|
|
.m5stg_fmulda (m5stg_fmulda),
|
| 289 |
|
|
.m6stg_fmul_in (m6stg_fmul_in),
|
| 290 |
|
|
.m6stg_id_in (m6stg_id_in[9:0]),
|
| 291 |
|
|
.m6stg_fmul_dbl_dst (m6stg_fmul_dbl_dst),
|
| 292 |
|
|
.m6stg_fmuls (m6stg_fmuls),
|
| 293 |
|
|
.m6stg_step (m6stg_step),
|
| 294 |
|
|
.mul_sign_out (mul_sign_out),
|
| 295 |
|
|
.m5stg_in_of (m5stg_in_of),
|
| 296 |
|
|
.mul_exc_out (mul_exc_out[4:0]),
|
| 297 |
|
|
.m2stg_frac1_dbl_norm (m2stg_frac1_dbl_norm),
|
| 298 |
|
|
.m2stg_frac1_dbl_dnrm (m2stg_frac1_dbl_dnrm),
|
| 299 |
|
|
.m2stg_frac1_sng_norm (m2stg_frac1_sng_norm),
|
| 300 |
|
|
.m2stg_frac1_sng_dnrm (m2stg_frac1_sng_dnrm),
|
| 301 |
|
|
.m2stg_frac1_inf (m2stg_frac1_inf),
|
| 302 |
|
|
.m2stg_frac2_dbl_norm (m2stg_frac2_dbl_norm),
|
| 303 |
|
|
.m2stg_frac2_dbl_dnrm (m2stg_frac2_dbl_dnrm),
|
| 304 |
|
|
.m2stg_frac2_sng_norm (m2stg_frac2_sng_norm),
|
| 305 |
|
|
.m2stg_frac2_sng_dnrm (m2stg_frac2_sng_dnrm),
|
| 306 |
|
|
.m2stg_frac2_inf (m2stg_frac2_inf),
|
| 307 |
|
|
.m1stg_inf_zero_in (m1stg_inf_zero_in),
|
| 308 |
|
|
.m1stg_inf_zero_in_dbl (m1stg_inf_zero_in_dbl),
|
| 309 |
|
|
.m2stg_exp_expadd (m2stg_exp_expadd),
|
| 310 |
|
|
.m2stg_exp_0bff (m2stg_exp_0bff),
|
| 311 |
|
|
.m2stg_exp_017f (m2stg_exp_017f),
|
| 312 |
|
|
.m2stg_exp_04ff (m2stg_exp_04ff),
|
| 313 |
|
|
.m2stg_exp_zero (m2stg_exp_zero),
|
| 314 |
|
|
.m3bstg_ld0_inv (m3bstg_ld0_inv[6:0]),
|
| 315 |
|
|
.m4stg_sh_cnt_in (m4stg_sh_cnt_in[5:0]),
|
| 316 |
|
|
.m4stg_inc_exp_54 (m4stg_inc_exp_54),
|
| 317 |
|
|
.m4stg_inc_exp_55 (m4stg_inc_exp_55),
|
| 318 |
|
|
.m4stg_inc_exp_105 (m4stg_inc_exp_105),
|
| 319 |
|
|
.m4stg_left_shift_step (m4stg_left_shift_step),
|
| 320 |
|
|
.m4stg_right_shift_step (m4stg_right_shift_step),
|
| 321 |
|
|
.m5stg_to_0 (m5stg_to_0),
|
| 322 |
|
|
.m5stg_to_0_inv (m5stg_to_0_inv),
|
| 323 |
|
|
.mul_frac_out_fracadd (mul_frac_out_fracadd),
|
| 324 |
|
|
.mul_frac_out_frac (mul_frac_out_frac),
|
| 325 |
|
|
.mul_exp_out_exp_plus1 (mul_exp_out_exp_plus1),
|
| 326 |
|
|
.mul_exp_out_exp (mul_exp_out_exp),
|
| 327 |
|
|
|
| 328 |
|
|
.se (se_mul),
|
| 329 |
|
|
.si (si),
|
| 330 |
|
|
.so (scan_out_fpu_mul_ctl)
|
| 331 |
|
|
);
|
| 332 |
|
|
|
| 333 |
|
|
|
| 334 |
|
|
fpu_mul_exp_dp fpu_mul_exp_dp (
|
| 335 |
|
|
.inq_in1 (inq_in1[62:52]),
|
| 336 |
|
|
.inq_in2 (inq_in2[62:52]),
|
| 337 |
|
|
.m6stg_step (m6stg_step),
|
| 338 |
|
|
.m1stg_dblop (m1stg_dblop),
|
| 339 |
|
|
.m1stg_sngop (m1stg_sngop),
|
| 340 |
|
|
.m2stg_exp_expadd (m2stg_exp_expadd),
|
| 341 |
|
|
.m2stg_exp_0bff (m2stg_exp_0bff),
|
| 342 |
|
|
.m2stg_exp_017f (m2stg_exp_017f),
|
| 343 |
|
|
.m2stg_exp_04ff (m2stg_exp_04ff),
|
| 344 |
|
|
.m2stg_exp_zero (m2stg_exp_zero),
|
| 345 |
|
|
.m1stg_fsmuld (m1stg_fsmuld),
|
| 346 |
|
|
.m2stg_fmuld (m2stg_fmuld),
|
| 347 |
|
|
.m2stg_fmuls (m2stg_fmuls),
|
| 348 |
|
|
.m2stg_fsmuld (m2stg_fsmuld),
|
| 349 |
|
|
.m3stg_ld0_inv (m3stg_ld0_inv[6:0]),
|
| 350 |
|
|
.m4stg_inc_exp_54 (m4stg_inc_exp_54),
|
| 351 |
|
|
.m4stg_inc_exp_55 (m4stg_inc_exp_55),
|
| 352 |
|
|
.m4stg_inc_exp_105 (m4stg_inc_exp_105),
|
| 353 |
|
|
.m5stg_fracadd_cout (m5stg_fracadd_cout),
|
| 354 |
|
|
.mul_exp_out_exp_plus1 (mul_exp_out_exp_plus1),
|
| 355 |
|
|
.mul_exp_out_exp (mul_exp_out_exp),
|
| 356 |
|
|
.m5stg_in_of (m5stg_in_of),
|
| 357 |
|
|
.m5stg_fmuld (m5stg_fmuld),
|
| 358 |
|
|
.m5stg_to_0_inv (m5stg_to_0_inv),
|
| 359 |
|
|
.m4stg_shl_54 (m4stg_shl_54),
|
| 360 |
|
|
.m4stg_shl_55 (m4stg_shl_55),
|
| 361 |
|
|
.fmul_clken_l (fmul_clken_l_buf1),
|
| 362 |
|
|
.rclk (rclk),
|
| 363 |
|
|
|
| 364 |
|
|
.m3stg_exp (m3stg_exp[12:0]),
|
| 365 |
|
|
.m3stg_expadd_eq_0 (m3stg_expadd_eq_0),
|
| 366 |
|
|
.m3stg_expadd_lte_0_inv (m3stg_expadd_lte_0_inv),
|
| 367 |
|
|
.m4stg_exp (m4stg_exp[12:0]),
|
| 368 |
|
|
.m5stg_exp (m5stg_exp[12:0]),
|
| 369 |
|
|
.mul_exp_out (mul_exp_out[10:0]),
|
| 370 |
|
|
|
| 371 |
|
|
.se (se_mul),
|
| 372 |
|
|
.si (scan_out_fpu_mul_ctl),
|
| 373 |
|
|
.so (scan_out_fpu_mul_exp_dp)
|
| 374 |
|
|
);
|
| 375 |
|
|
|
| 376 |
|
|
|
| 377 |
|
|
fpu_mul_frac_dp fpu_mul_frac_dp (
|
| 378 |
|
|
.inq_in1 (inq_in1[54:0]),
|
| 379 |
|
|
.inq_in2 (inq_in2[54:0]),
|
| 380 |
|
|
.m6stg_step (m6stg_step),
|
| 381 |
|
|
.m2stg_frac1_dbl_norm (m2stg_frac1_dbl_norm),
|
| 382 |
|
|
.m2stg_frac1_dbl_dnrm (m2stg_frac1_dbl_dnrm),
|
| 383 |
|
|
.m2stg_frac1_sng_norm (m2stg_frac1_sng_norm),
|
| 384 |
|
|
.m2stg_frac1_sng_dnrm (m2stg_frac1_sng_dnrm),
|
| 385 |
|
|
.m2stg_frac1_inf (m2stg_frac1_inf),
|
| 386 |
|
|
.m1stg_snan_dbl_in1 (m1stg_snan_dbl_in1),
|
| 387 |
|
|
.m1stg_snan_sng_in1 (m1stg_snan_sng_in1),
|
| 388 |
|
|
.m2stg_frac2_dbl_norm (m2stg_frac2_dbl_norm),
|
| 389 |
|
|
.m2stg_frac2_dbl_dnrm (m2stg_frac2_dbl_dnrm),
|
| 390 |
|
|
.m2stg_frac2_sng_norm (m2stg_frac2_sng_norm),
|
| 391 |
|
|
.m2stg_frac2_sng_dnrm (m2stg_frac2_sng_dnrm),
|
| 392 |
|
|
.m2stg_frac2_inf (m2stg_frac2_inf),
|
| 393 |
|
|
.m1stg_snan_dbl_in2 (m1stg_snan_dbl_in2),
|
| 394 |
|
|
.m1stg_snan_sng_in2 (m1stg_snan_sng_in2),
|
| 395 |
|
|
.m1stg_inf_zero_in (m1stg_inf_zero_in),
|
| 396 |
|
|
.m1stg_inf_zero_in_dbl (m1stg_inf_zero_in_dbl),
|
| 397 |
|
|
.m1stg_dblop (m1stg_dblop),
|
| 398 |
|
|
.m1stg_dblop_inv (m1stg_dblop_inv),
|
| 399 |
|
|
.m4stg_frac (m4stg_frac),
|
| 400 |
|
|
.m4stg_sh_cnt_in (m4stg_sh_cnt_in[5:0]),
|
| 401 |
|
|
.m3bstg_ld0_inv (m3bstg_ld0_inv[6:0]),
|
| 402 |
|
|
.m4stg_left_shift_step (m4stg_left_shift_step),
|
| 403 |
|
|
.m4stg_right_shift_step (m4stg_right_shift_step),
|
| 404 |
|
|
.m5stg_fmuls (m5stg_fmuls),
|
| 405 |
|
|
.m5stg_fmulda (m5stg_fmulda),
|
| 406 |
|
|
.mul_frac_out_fracadd (mul_frac_out_fracadd),
|
| 407 |
|
|
.mul_frac_out_frac (mul_frac_out_frac),
|
| 408 |
|
|
.m5stg_in_of (m5stg_in_of),
|
| 409 |
|
|
.m5stg_to_0 (m5stg_to_0),
|
| 410 |
|
|
.fmul_clken_l (fmul_clken_l),
|
| 411 |
|
|
.rclk (rclk),
|
| 412 |
|
|
|
| 413 |
|
|
.m2stg_frac1_array_in (m2stg_frac1_array_in),
|
| 414 |
|
|
.m2stg_frac2_array_in (m2stg_frac2_array_in),
|
| 415 |
|
|
.m1stg_ld0_1 (m1stg_ld0_1),
|
| 416 |
|
|
.m1stg_ld0_2 (m1stg_ld0_2),
|
| 417 |
|
|
.m4stg_frac_105 (m4stg_frac_105),
|
| 418 |
|
|
.m3stg_ld0_inv (m3stg_ld0_inv[6:0]),
|
| 419 |
|
|
.m4stg_shl_54 (m4stg_shl_54),
|
| 420 |
|
|
.m4stg_shl_55 (m4stg_shl_55),
|
| 421 |
|
|
.m5stg_frac_32_0 (m5stg_frac_32_0[32:0]),
|
| 422 |
|
|
.m5stg_frac_dbl_nx (m5stg_frac_dbl_nx),
|
| 423 |
|
|
.m5stg_frac_sng_nx (m5stg_frac_sng_nx),
|
| 424 |
|
|
.m5stg_frac_neq_0 (m5stg_frac_neq_0),
|
| 425 |
|
|
.m5stg_fracadd_cout (m5stg_fracadd_cout),
|
| 426 |
|
|
.mul_frac_out (mul_frac_out[51:0]),
|
| 427 |
|
|
|
| 428 |
|
|
.se (se_mul),
|
| 429 |
|
|
.si (scan_out_fpu_mul_exp_dp),
|
| 430 |
|
|
.so (scan_out_fpu_mul_frac_dp)
|
| 431 |
|
|
);
|
| 432 |
|
|
|
| 433 |
|
|
|
| 434 |
|
|
// 3/14/03: Promoted mul64 to unit level. Got rid of fpu_mul_array. Same representation for RTL and gates. Also, now agreed that mul64 will not have dffrl_async inside, so the staged signal mul_rst_l is sent from fpu_mul_ctl. mul64 port step has been renamed to mul_step to avoid conflicts with DEF keyword STEP in some backend flows (WARP).
|
| 435 |
|
|
mul64 i_m4stg_frac (
|
| 436 |
|
|
.rs1_l ({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1,
|
| 437 |
|
|
1'b1, 1'b1, 1'b1, m2stg_frac1_array_in[52:0]}),
|
| 438 |
|
|
.rs2 ({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
|
| 439 |
|
|
1'b0, 1'b0, 1'b0, m2stg_frac2_array_in[52:0]}),
|
| 440 |
|
|
.valid(m1stg_fmul),
|
| 441 |
|
|
.areg ({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
|
| 442 |
|
|
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
|
| 443 |
|
|
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
|
| 444 |
|
|
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
|
| 445 |
|
|
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
|
| 446 |
|
|
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
|
| 447 |
|
|
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
|
| 448 |
|
|
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
|
| 449 |
|
|
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
|
| 450 |
|
|
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
|
| 451 |
|
|
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
|
| 452 |
|
|
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
|
| 453 |
|
|
1'b0}),
|
| 454 |
|
|
.accreg ({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
|
| 455 |
|
|
.x2 (1'b0),
|
| 456 |
|
|
.rclk (rclk),
|
| 457 |
|
|
.si (scan_out_fpu_mul_frac_dp),
|
| 458 |
|
|
.se (se_mul64),
|
| 459 |
|
|
.mul_rst_l (mul_rst_l),
|
| 460 |
|
|
.mul_step (m6stg_step),
|
| 461 |
|
|
.so (so),
|
| 462 |
|
|
.out ({m4stg_frac_unused[29:0], m4stg_frac[105:0]})
|
| 463 |
|
|
);
|
| 464 |
|
|
|
| 465 |
|
|
endmodule
|
| 466 |
|
|
|
| 467 |
|
|
|
