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1 2 dmitryr
// ========== Copyright Header Begin ==========================================
2
// 
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// OpenSPARC T1 Processor File: fpu_mul_ctl.v
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// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// 
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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// 
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// The above named program is distributed in the hope that it will be 
12
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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// General Public License for more details.
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// 
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// 
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// ========== Copyright Header End ============================================
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///////////////////////////////////////////////////////////////////////////////
22
//
23
//      Multiply pipeline synthesizable logic
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//              - special input cases
25
//              - opcode pipeline
26
//              - sign logic
27
//              - exception logic
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//              - datapath control- select lines and control logic
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//
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///////////////////////////////////////////////////////////////////////////////
31
 
32
 
33
module fpu_mul_ctl (
34
        inq_in1_51,
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        inq_in1_54,
36
        inq_in1_53_0_neq_0,
37
        inq_in1_50_0_neq_0,
38
        inq_in1_53_32_neq_0,
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        inq_in1_exp_eq_0,
40
        inq_in1_exp_neq_ffs,
41
        inq_in2_51,
42
        inq_in2_54,
43
        inq_in2_53_0_neq_0,
44
        inq_in2_50_0_neq_0,
45
        inq_in2_53_32_neq_0,
46
        inq_in2_exp_eq_0,
47
        inq_in2_exp_neq_ffs,
48
        inq_op,
49
        inq_mul,
50
        inq_rnd_mode,
51
        inq_id,
52
        inq_in1_63,
53
        inq_in2_63,
54
        mul_dest_rdy,
55
        mul_dest_rdya,
56
        m5stg_exp,
57
        m5stg_fracadd_cout,
58
        m5stg_frac_neq_0,
59
        m5stg_frac_dbl_nx,
60
        m5stg_frac_sng_nx,
61
        m1stg_ld0_1,
62
        m1stg_ld0_2,
63
        m3stg_exp,
64
        m3stg_expadd_eq_0,
65
        m3stg_expadd_lte_0_inv,
66
        m3stg_ld0_inv,
67
        m4stg_exp,
68
        m4stg_frac_105,
69
        m5stg_frac,
70
        arst_l,
71
        grst_l,
72
        rclk,
73
 
74
        mul_pipe_active,
75
        m1stg_snan_sng_in1,
76
        m1stg_snan_dbl_in1,
77
        m1stg_snan_sng_in2,
78
        m1stg_snan_dbl_in2,
79
        m1stg_step,
80
        m1stg_sngop,
81
        m1stg_dblop,
82
        m1stg_dblop_inv,
83
        m1stg_fmul,
84
        m1stg_fsmuld,
85
        m2stg_fmuls,
86
        m2stg_fmuld,
87
        m2stg_fsmuld,
88
        m5stg_fmuls,
89
        m5stg_fmuld,
90
        m5stg_fmulda,
91
        m6stg_fmul_in,
92
        m6stg_id_in,
93
        m6stg_fmul_dbl_dst,
94
        m6stg_fmuls,
95
        m6stg_step,
96
        mul_sign_out,
97
        m5stg_in_of,
98
        mul_exc_out,
99
        m2stg_frac1_dbl_norm,
100
        m2stg_frac1_dbl_dnrm,
101
        m2stg_frac1_sng_norm,
102
        m2stg_frac1_sng_dnrm,
103
        m2stg_frac1_inf,
104
        m2stg_frac2_dbl_norm,
105
        m2stg_frac2_dbl_dnrm,
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        m2stg_frac2_sng_norm,
107
        m2stg_frac2_sng_dnrm,
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        m2stg_frac2_inf,
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        m1stg_inf_zero_in,
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        m1stg_inf_zero_in_dbl,
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        m2stg_exp_expadd,
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        m2stg_exp_0bff,
113
        m2stg_exp_017f,
114
        m2stg_exp_04ff,
115
        m2stg_exp_zero,
116
        m3bstg_ld0_inv,
117
        m4stg_sh_cnt_in,
118
        m4stg_inc_exp_54,
119
        m4stg_inc_exp_55,
120
        m4stg_inc_exp_105,
121
        m4stg_left_shift_step,
122
        m4stg_right_shift_step,
123
        m5stg_to_0,
124
        m5stg_to_0_inv,
125
        mul_frac_out_fracadd,
126
        mul_frac_out_frac,
127
        mul_exp_out_exp_plus1,
128
        mul_exp_out_exp,
129
        mula_rst_l,
130
 
131
        se,
132
        si,
133
        so
134
);
135
 
136
 
137
parameter
138
                FMULS=  8'h49,
139
                FMULD=  8'h4a,
140
                FSMULD= 8'h69;
141
 
142
 
143
input           inq_in1_51;             // request operand 1[51]
144
input           inq_in1_54;             // request operand 1[54]
145
input           inq_in1_53_0_neq_0;     // request operand 1[53:0]!=0
146
input           inq_in1_50_0_neq_0;     // request operand 1[50:0]!=0
147
input           inq_in1_53_32_neq_0;    // request operand 1[53:32]!=0
148
input           inq_in1_exp_eq_0;       // request operand 1[62:52]==0
149
input           inq_in1_exp_neq_ffs;    // request operand 1[62:52]!=0x7ff
150
input           inq_in2_51;             // request operand 2[51]
151
input           inq_in2_54;             // request operand 2[54]
152
input           inq_in2_53_0_neq_0;     // request operand 2[53:0]!=0
153
input           inq_in2_50_0_neq_0;     // request operand 2[50:0]!=0
154
input           inq_in2_53_32_neq_0;    // request operand 2[53:32]!=0
155
input           inq_in2_exp_eq_0;       // request operand 2[62:52]==0
156
input           inq_in2_exp_neq_ffs;    // request operand 2[62:52]!=0x7ff
157
input [7:0]      inq_op;                 // request opcode to op pipes
158
input           inq_mul;                // multiply pipe request
159
input [1:0]      inq_rnd_mode;           // request rounding mode to op pipes
160
input [4:0]      inq_id;                 // request ID to the operation pipes
161
input           inq_in1_63;             // request[63] operand 1 to op pipes
162
input           inq_in2_63;             // request[63] operand 2 to op pipes
163
input           mul_dest_rdy;           // multiply result req accepted for CPX
164
input           mul_dest_rdya;          // multiply result req accepted for CPX
165
input [12:0]     m5stg_exp;              // exponent input- multiply 5 stage
166
input           m5stg_fracadd_cout;     // fraction rounding adder carry out
167
input           m5stg_frac_neq_0;       // fraction input to mul 5 stage != 0
168
input           m5stg_frac_dbl_nx;      // double precision inexact result
169
input           m5stg_frac_sng_nx;      // single precision inexact result
170
input [5:0]      m1stg_ld0_1;            // denorm operand 1 leading 0's
171
input [5:0]      m1stg_ld0_2;            // denorm operand 2 leading 0's
172
input [12:0]     m3stg_exp;              // exponent input- multiply 3 stage
173
input           m3stg_expadd_eq_0;      // mul stage 3 exponent adder sum == 0
174
input           m3stg_expadd_lte_0_inv; // mul stage 3 exponent adder sum <= 0
175
input [5:0]      m3stg_ld0_inv;          // leading 0's in multiply operands
176
input [12:0]     m4stg_exp;              // exponent input- multiply 4 stage
177
input           m4stg_frac_105; // multiply stage 4a fraction input[105]
178
input [32:0]     m5stg_frac;             // multiply stage 5 fraction input
179
input           arst_l;                 // asynchronous global reset- asserted low
180
input           grst_l;                 // synchronous global reset- asserted low
181
input           rclk;           // global clock
182
 
183
output          mul_pipe_active;        // mul pipe is executing a valid instr
184
output          m1stg_snan_sng_in1;     // operand 1 is single signalling NaN
185
output          m1stg_snan_dbl_in1;     // operand 1 is double signalling NaN
186
output          m1stg_snan_sng_in2;     // operand 2 is single signalling NaN
187
output          m1stg_snan_dbl_in2;     // operand 2 is double signalling NaN
188
output          m1stg_step;             // multiply pipe load
189
output          m1stg_sngop;            // single precision operation- mul 1 stg
190
output          m1stg_dblop;            // double precision operation- mul 1 stg
191
output          m1stg_dblop_inv;        // single or int operation- mul 1 stg
192
output          m1stg_fmul;             // multiply operation- mul 1 stage
193
output          m1stg_fsmuld;           // fsmuld- multiply 1 stage
194
output          m2stg_fmuls;            // fmuls- multiply 2 stage
195
output          m2stg_fmuld;            // fmuld- multiply 2 stage
196
output          m2stg_fsmuld;           // fsmuld- multiply 2 stage
197
output          m5stg_fmuls;            // fmuls- multiply 5 stage
198
output          m5stg_fmuld;            // fmuld- multiply 5 stage
199
output          m5stg_fmulda;           // fmuld- multiply 5 stage copy
200
output          m6stg_fmul_in;          // mul pipe output request next cycle
201
output [9:0]     m6stg_id_in;            // mul pipe output ID next cycle
202
output          m6stg_fmul_dbl_dst;     // double precision multiply result
203
output          m6stg_fmuls;            // fmuls- multiply 6 stage
204
output          m6stg_step;             // advance the multiply pipe
205
output          mul_sign_out;           // multiply sign output
206
output          m5stg_in_of;            // multiply overflow- select exp out
207
output [4:0]     mul_exc_out;            // multiply pipe result- exception flags
208
output          m2stg_frac1_dbl_norm;   // select line to m2stg_frac1
209
output          m2stg_frac1_dbl_dnrm;   // select line to m2stg_frac1
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output          m2stg_frac1_sng_norm;   // select line to m2stg_frac1
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output          m2stg_frac1_sng_dnrm;   // select line to m2stg_frac1
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output          m2stg_frac1_inf;        // select line to m2stg_frac1
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output          m2stg_frac2_dbl_norm;   // select line to m2stg_frac2
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output          m2stg_frac2_dbl_dnrm;   // select line to m2stg_frac2
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output          m2stg_frac2_sng_norm;   // select line to m2stg_frac2
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output          m2stg_frac2_sng_dnrm;   // select line to m2stg_frac2
217
output          m2stg_frac2_inf;        // select line to m2stg_frac2
218
output          m1stg_inf_zero_in;      // 1 operand is infinity; other is 0
219
output          m1stg_inf_zero_in_dbl;  // 1 opnd is infinity; other is 0- dbl
220
output          m2stg_exp_expadd;       // select line to m2stg_exp
221
output          m2stg_exp_0bff;         // select line to m2stg_exp
222
output          m2stg_exp_017f;         // select line to m2stg_exp
223
output          m2stg_exp_04ff;         // select line to m2stg_exp
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output          m2stg_exp_zero;         // select line to m2stg_exp
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output [6:0]     m3bstg_ld0_inv;         // leading 0's in multiply operands
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output [5:0]     m4stg_sh_cnt_in;        // multiply normalization shift count
227
output          m4stg_inc_exp_54;       // select line to m5stg_exp
228
output          m4stg_inc_exp_55;       // select line to m5stg_exp
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output          m4stg_inc_exp_105;      // select line to m5stg_exp
230
output          m4stg_left_shift_step;  // select line to m5stg_frac
231
output          m4stg_right_shift_step; // select line to m5stg_frac
232
output          m5stg_to_0;             // result to max finite on overflow
233
output          m5stg_to_0_inv;         // result to infinity on overflow
234
output          mul_frac_out_fracadd;   // select line to mul_frac_out
235
output          mul_frac_out_frac;      // select line to mul_frac_out
236
output          mul_exp_out_exp_plus1;  // select line to mul_exp_out
237
output          mul_exp_out_exp;        // select line to mul_exp_out
238
output    mula_rst_l; // reset for mul64
239
 
240
input           se;                     // scan_enable
241
input           si;                     // scan in
242
output          so;                     // scan out
243
 
244
 
245
wire            reset;
246
wire            mul_frac_in1_51;
247
wire            mul_frac_in1_54;
248
wire            mul_frac_in1_53_0_neq_0;
249
wire            mul_frac_in1_50_0_neq_0;
250
wire            mul_frac_in1_53_32_neq_0;
251
wire            mul_exp_in1_exp_eq_0;
252
wire            mul_exp_in1_exp_neq_ffs;
253
wire            mul_frac_in2_51;
254
wire            mul_frac_in2_54;
255
wire            mul_frac_in2_53_0_neq_0;
256
wire            mul_frac_in2_50_0_neq_0;
257
wire            mul_frac_in2_53_32_neq_0;
258
wire            mul_exp_in2_exp_eq_0;
259
wire            mul_exp_in2_exp_neq_ffs;
260
wire            m1stg_denorm_sng_in1;
261
wire            m1stg_denorm_dbl_in1;
262
wire            m1stg_denorm_sng_in2;
263
wire            m1stg_denorm_dbl_in2;
264
wire            m1stg_denorm_in1;
265
wire            m1stg_denorm_in2;
266
wire            m1stg_norm_sng_in1;
267
wire            m1stg_norm_dbl_in1;
268
wire            m1stg_norm_sng_in2;
269
wire            m1stg_norm_dbl_in2;
270
wire            m1stg_snan_sng_in1;
271
wire            m1stg_snan_dbl_in1;
272
wire            m1stg_snan_sng_in2;
273
wire            m1stg_snan_dbl_in2;
274
wire            m1stg_qnan_sng_in1;
275
wire            m1stg_qnan_dbl_in1;
276
wire            m1stg_qnan_sng_in2;
277
wire            m1stg_qnan_dbl_in2;
278
wire            m1stg_snan_in1;
279
wire            m1stg_snan_in2;
280
wire            m1stg_qnan_in1;
281
wire            m1stg_qnan_in2;
282
wire            m2stg_snan_in1;
283
wire            m2stg_snan_in2;
284
wire            m2stg_qnan_in1;
285
wire            m2stg_qnan_in2;
286
wire            m1stg_nan_sng_in1;
287
wire            m1stg_nan_dbl_in1;
288
wire            m1stg_nan_sng_in2;
289
wire            m1stg_nan_dbl_in2;
290
wire            m1stg_nan_in1;
291
wire            m1stg_nan_in2;
292
wire            m2stg_nan_in2;
293
wire            m1stg_inf_sng_in1;
294
wire            m1stg_inf_dbl_in1;
295
wire            m1stg_inf_sng_in2;
296
wire            m1stg_inf_dbl_in2;
297
wire            m1stg_inf_in1;
298
wire            m1stg_inf_in2;
299
wire            m1stg_inf_in;
300
wire            m2stg_inf_in1;
301
wire            m2stg_inf_in2;
302
wire            m2stg_inf_in;
303
wire            m1stg_infnan_sng_in1;
304
wire            m1stg_infnan_dbl_in1;
305
wire            m1stg_infnan_sng_in2;
306
wire            m1stg_infnan_dbl_in2;
307
wire            m1stg_infnan_in1;
308
wire            m1stg_infnan_in2;
309
wire            m1stg_infnan_in;
310
wire            m1stg_zero_in1;
311
wire            m1stg_zero_in2;
312
wire            m1stg_zero_in;
313
wire            m2stg_zero_in1;
314
wire            m2stg_zero_in2;
315
wire            m2stg_zero_in;
316
wire            m1stg_step;
317
wire [7:0]       m1stg_op_in;
318
wire [7:0]       m1stg_op;
319
wire            m1stg_mul_in;
320
wire            m1stg_mul;
321
wire            m1stg_sngop;
322
wire [3:0]       m1stg_sngopa;
323
wire            m1stg_dblop;
324
wire [3:0]       m1stg_dblopa;
325
wire            m1stg_dblop_inv_in;
326
wire            m1stg_dblop_inv;
327
wire [1:0]       m1stg_rnd_mode;
328
wire [4:0]       m1stg_id;
329
wire            m1stg_fmul;
330
wire            m1stg_fmul_dbl_dst;
331
wire            m1stg_fmuls;
332
wire            m1stg_fmuld;
333
wire            m1stg_fsmuld;
334
wire [4:0]       m1stg_opdec;
335
wire [4:0]       m2stg_opdec;
336
wire [1:0]       m2stg_rnd_mode;
337
wire [4:0]       m2stg_id;
338
wire            m2stg_fmul;
339
wire            m2stg_fmuls;
340
wire            m2stg_fmuld;
341
wire            m2stg_fsmuld;
342
wire [4:1]      m3astg_opdec;
343
wire [1:0]       m3astg_rnd_mode;
344
wire [4:0]       m3astg_id;
345
wire [4:1]      m3bstg_opdec;
346
wire [1:0]       m3bstg_rnd_mode;
347
wire [4:0]       m3bstg_id;
348
wire [4:1]      m3stg_opdec;
349
wire [1:0]       m3stg_rnd_mode;
350
wire [4:0]       m3stg_id;
351
wire            m3stg_fmul;
352
wire [4:1]      m4stg_opdec;
353
wire [1:0]       m4stg_rnd_mode;
354
wire [4:0]       m4stg_id;
355
wire            m4stg_fmul;
356
wire            m4stg_fmuld;
357
wire [4:1]      m5stg_opdec;
358
wire [1:0]       m5stg_rnd_mode;
359
wire [4:0]       m5stg_id;
360
wire            m5stg_fmul;
361
wire            m5stg_fmuls;
362
wire            m5stg_fmuld;
363
wire            m5stg_fmulda;
364
wire            m6stg_fmul_in;
365
wire [4:2]      m6stg_opdec;
366
wire [9:0]       m6stg_id_in;
367
wire [9:0]       m6stg_id;
368
wire            m6stg_fmul;
369
wire            m6stg_fmul_dbl_dst;
370
wire            m6stg_fmuls;
371
wire            m6stg_hold;
372
wire            m6stg_holda;
373
wire            m6stg_step;
374
wire            m6stg_stepa;
375
wire            m1stg_sign1;
376
wire            m1stg_sign2;
377
wire            m2stg_sign1;
378
wire            m2stg_sign2;
379
wire            m1stg_of_mask;
380
wire            m2stg_of_mask;
381
wire            m2stg_sign;
382
wire            m3astg_sign;
383
wire            m2stg_nv;
384
wire            m3astg_nv;
385
wire            m3astg_of_mask;
386
wire            m3bstg_sign;
387
wire            m3bstg_nv;
388
wire            m3stg_sign;
389
wire            m3stg_nv;
390
wire            m3stg_of_mask;
391
wire            m4stg_sign;
392
wire            m4stg_nv;
393
wire            m4stg_of_mask;
394
wire            m5stg_sign;
395
wire            m5stg_nv;
396
wire            m5stg_of_mask;
397
wire            mul_sign_out;
398
wire            mul_nv_out;
399
wire            m5stg_in_of;
400
wire            mul_of_out_tmp1_in;
401
wire            mul_of_out_tmp1;
402
wire            mul_of_out_tmp2;
403
wire            mul_of_out_cout;
404
wire            mul_of_out;
405
wire            mul_uf_out_in;
406
wire            mul_uf_out;
407
wire            mul_nx_out_in;
408
wire            mul_nx_out;
409
wire [4:0]       mul_exc_out;
410
wire            m2stg_frac1_dbl_norm;
411
wire            m2stg_frac1_dbl_dnrm;
412
wire            m2stg_frac1_sng_norm;
413
wire            m2stg_frac1_sng_dnrm;
414
wire            m2stg_frac1_inf;
415
wire            m2stg_frac2_dbl_norm;
416
wire            m2stg_frac2_dbl_dnrm;
417
wire            m2stg_frac2_sng_norm;
418
wire            m2stg_frac2_sng_dnrm;
419
wire            m2stg_frac2_inf;
420
wire            m1stg_inf_zero_in;
421
wire            m1stg_inf_zero_in_dbl;
422
wire [5:0]       m2stg_ld0_1_in;
423
wire [5:0]       m2stg_ld0_1;
424
wire [5:0]       m2stg_ld0_2_in;
425
wire [5:0]       m2stg_ld0_2;
426
wire            m2stg_exp_expadd;
427
wire            m2stg_exp_0bff;
428
wire            m2stg_exp_017f;
429
wire            m2stg_exp_04ff;
430
wire            m2stg_exp_zero;
431
wire [6:0]       m2stg_ld0;
432
wire [6:0]       m2stg_ld0_inv;
433
wire [6:0]       m3astg_ld0_inv;
434
wire [6:0]       m3bstg_ld0_inv;
435
wire            m4stg_expadd_eq_0;
436
wire            m3stg_exp_lte_0;
437
wire            m4stg_right_shift_in;
438
wire            m4stg_right_shift;
439
wire [5:0]       m3stg_exp_minus1;
440
wire [5:0]       m3stg_exp_inv_plus2;
441
wire            m3stg_exp_lt_neg57;
442
wire [5:0]       m4stg_sh_cnt_in;
443
wire            m4stg_left_shift_step;
444
wire            m4stg_right_shift_step;
445
wire            m4stg_inc_exp_54;
446
wire            m4stg_inc_exp_55;
447
wire            m4stg_inc_exp_105;
448
wire            m5stg_rndup;
449
wire            m5stg_to_0;
450
wire            m5stg_to_0_inv;
451
wire            mul_frac_out_fracadd;
452
wire            mul_frac_out_frac;
453
wire            mul_exp_out_exp_plus1;
454
wire            mul_exp_out_exp;
455
wire            mul_pipe_active_in;
456
wire            mul_pipe_active;
457
wire    mula_rst_l;
458
 
459
 
460
dffrl_async #(1)  dffrl_mul_ctl (
461
  .din  (grst_l),
462
  .clk  (rclk),
463
  .rst_l(arst_l),
464
  .q    (mul_ctl_rst_l),
465
        .se (se),
466
        .si (),
467
        .so ()
468
  );
469
 
470
assign reset= (!mul_ctl_rst_l);
471
 
472
// 3/14/03 reset signal for mul64
473
assign mula_rst_l = mul_ctl_rst_l;
474
 
475
 
476
///////////////////////////////////////////////////////////////////////////////
477
//
478
//      Multiply pipeline special input cases.
479
//
480
///////////////////////////////////////////////////////////////////////////////
481
 
482
dffe_s #(1) i_mul_frac_in1_51 (
483
        .din    (inq_in1_51),
484
        .en     (m6stg_step),
485
        .clk    (rclk),
486
 
487
        .q      (mul_frac_in1_51),
488
 
489
        .se     (se),
490
        .si     (),
491
        .so     ()
492
);
493
 
494
dffe_s #(1) i_mul_frac_in1_54 (
495
        .din    (inq_in1_54),
496
        .en     (m6stg_step),
497
        .clk    (rclk),
498
 
499
        .q      (mul_frac_in1_54),
500
 
501
        .se     (se),
502
        .si     (),
503
        .so     ()
504
);
505
 
506
dffe_s #(1) i_mul_frac_in1_53_0_neq_0 (
507
        .din    (inq_in1_53_0_neq_0),
508
        .en     (m6stg_step),
509
        .clk    (rclk),
510
 
511
        .q      (mul_frac_in1_53_0_neq_0),
512
 
513
        .se     (se),
514
        .si     (),
515
        .so     ()
516
);
517
 
518
dffe_s #(1) i_mul_frac_in1_50_0_neq_0 (
519
        .din    (inq_in1_50_0_neq_0),
520
        .en     (m6stg_step),
521
        .clk    (rclk),
522
 
523
        .q      (mul_frac_in1_50_0_neq_0),
524
 
525
        .se     (se),
526
        .si     (),
527
        .so     ()
528
);
529
 
530
dffe_s #(1) i_mul_frac_in1_53_32_neq_0 (
531
        .din    (inq_in1_53_32_neq_0),
532
        .en     (m6stg_step),
533
        .clk    (rclk),
534
 
535
        .q      (mul_frac_in1_53_32_neq_0),
536
 
537
        .se     (se),
538
        .si     (),
539
        .so     ()
540
);
541
 
542
dffe_s #(1) i_mul_exp_in1_exp_eq_0 (
543
        .din    (inq_in1_exp_eq_0),
544
        .en     (m6stg_step),
545
        .clk    (rclk),
546
 
547
        .q      (mul_exp_in1_exp_eq_0),
548
 
549
        .se     (se),
550
        .si     (),
551
        .so     ()
552
);
553
 
554
dffe_s #(1) i_mul_exp_in1_exp_neq_ffs (
555
        .din    (inq_in1_exp_neq_ffs),
556
        .en     (m6stg_step),
557
        .clk    (rclk),
558
 
559
        .q      (mul_exp_in1_exp_neq_ffs),
560
 
561
        .se     (se),
562
        .si     (),
563
        .so     ()
564
);
565
 
566
dffe_s #(1) i_mul_frac_in2_51 (
567
        .din    (inq_in2_51),
568
        .en     (m6stg_step),
569
        .clk    (rclk),
570
 
571
        .q      (mul_frac_in2_51),
572
 
573
        .se     (se),
574
        .si     (),
575
        .so     ()
576
);
577
 
578
dffe_s #(1) i_mul_frac_in2_54 (
579
        .din    (inq_in2_54),
580
        .en     (m6stg_step),
581
        .clk    (rclk),
582
 
583
        .q      (mul_frac_in2_54),
584
 
585
        .se     (se),
586
        .si     (),
587
        .so     ()
588
);
589
 
590
dffe_s #(1) i_mul_frac_in2_53_0_neq_0 (
591
        .din    (inq_in2_53_0_neq_0),
592
        .en     (m6stg_step),
593
        .clk    (rclk),
594
 
595
        .q      (mul_frac_in2_53_0_neq_0),
596
 
597
        .se     (se),
598
        .si     (),
599
        .so     ()
600
);
601
 
602
dffe_s #(1) i_mul_frac_in2_50_0_neq_0 (
603
        .din    (inq_in2_50_0_neq_0),
604
        .en     (m6stg_step),
605
        .clk    (rclk),
606
 
607
        .q      (mul_frac_in2_50_0_neq_0),
608
 
609
        .se     (se),
610
        .si     (),
611
        .so     ()
612
);
613
 
614
dffe_s #(1) i_mul_frac_in2_53_32_neq_0 (
615
        .din    (inq_in2_53_32_neq_0),
616
        .en     (m6stg_step),
617
        .clk    (rclk),
618
 
619
        .q      (mul_frac_in2_53_32_neq_0),
620
 
621
        .se     (se),
622
        .si     (),
623
        .so     ()
624
);
625
 
626
dffe_s #(1) i_mul_exp_in2_exp_eq_0 (
627
        .din    (inq_in2_exp_eq_0),
628
         .en    (m6stg_step),
629
        .clk    (rclk),
630
 
631
        .q      (mul_exp_in2_exp_eq_0),
632
 
633
        .se     (se),
634
        .si     (),
635
        .so     ()
636
);
637
 
638
dffe_s #(1) i_mul_exp_in2_exp_neq_ffs (
639
        .din    (inq_in2_exp_neq_ffs),
640
        .en     (m6stg_step),
641
        .clk    (rclk),
642
 
643
        .q      (mul_exp_in2_exp_neq_ffs),
644
 
645
        .se     (se),
646
        .si     (),
647
        .so     ()
648
);
649
 
650
 
651
///////////////////////////////////////////////////////////////////////////////
652
//
653
//      Denorm multiply inputs.
654
//
655
///////////////////////////////////////////////////////////////////////////////
656
 
657
assign m1stg_denorm_sng_in1= mul_exp_in1_exp_eq_0 && m1stg_sngopa[0];
658
 
659
assign m1stg_denorm_dbl_in1= mul_exp_in1_exp_eq_0 && m1stg_dblopa[0];
660
 
661
assign m1stg_denorm_sng_in2= mul_exp_in2_exp_eq_0 && m1stg_sngopa[0];
662
 
663
assign m1stg_denorm_dbl_in2= mul_exp_in2_exp_eq_0 && m1stg_dblopa[0];
664
 
665
assign m1stg_denorm_in1= m1stg_denorm_sng_in1 || m1stg_denorm_dbl_in1;
666
 
667
assign m1stg_denorm_in2= m1stg_denorm_sng_in2 || m1stg_denorm_dbl_in2;
668
 
669
 
670
///////////////////////////////////////////////////////////////////////////////
671
//
672
//      Non-denorm multiply inputs.
673
//
674
///////////////////////////////////////////////////////////////////////////////
675
 
676
assign m1stg_norm_sng_in1= (!mul_exp_in1_exp_eq_0) && m1stg_sngopa[0];
677
 
678
assign m1stg_norm_dbl_in1= (!mul_exp_in1_exp_eq_0) && m1stg_dblopa[0];
679
 
680
assign m1stg_norm_sng_in2= (!mul_exp_in2_exp_eq_0) && m1stg_sngopa[0];
681
 
682
assign m1stg_norm_dbl_in2= (!mul_exp_in2_exp_eq_0) && m1stg_dblopa[0];
683
 
684
 
685
///////////////////////////////////////////////////////////////////////////////
686
//
687
//      Nan multiply inputs.
688
//
689
///////////////////////////////////////////////////////////////////////////////
690
 
691
assign m1stg_snan_sng_in1= (!mul_exp_in1_exp_neq_ffs) && (!mul_frac_in1_54)
692
                && (mul_frac_in1_53_32_neq_0) && m1stg_sngopa[1];
693
 
694
assign m1stg_snan_dbl_in1= (!mul_exp_in1_exp_neq_ffs)
695
                && (!mul_frac_in1_51) && mul_frac_in1_50_0_neq_0
696
                && m1stg_dblopa[1];
697
 
698
assign m1stg_snan_sng_in2= (!mul_exp_in2_exp_neq_ffs) && (!mul_frac_in2_54)
699
                && (mul_frac_in2_53_32_neq_0) && m1stg_sngopa[1];
700
 
701
assign m1stg_snan_dbl_in2= (!mul_exp_in2_exp_neq_ffs)
702
                && (!mul_frac_in2_51) && mul_frac_in2_50_0_neq_0
703
                && m1stg_dblopa[1];
704
 
705
assign m1stg_qnan_sng_in1= (!mul_exp_in1_exp_neq_ffs) && mul_frac_in1_54
706
                && m1stg_sngopa[1];
707
 
708
assign m1stg_qnan_dbl_in1= (!mul_exp_in1_exp_neq_ffs) && mul_frac_in1_51
709
                && m1stg_dblopa[1];
710
 
711
assign m1stg_qnan_sng_in2= (!mul_exp_in2_exp_neq_ffs) && mul_frac_in2_54
712
                && m1stg_sngopa[1];
713
 
714
assign m1stg_qnan_dbl_in2= (!mul_exp_in2_exp_neq_ffs) && mul_frac_in2_51
715
                && m1stg_dblopa[1];
716
 
717
assign m1stg_snan_in1= m1stg_snan_sng_in1 || m1stg_snan_dbl_in1;
718
 
719
assign m1stg_snan_in2= m1stg_snan_sng_in2 || m1stg_snan_dbl_in2;
720
 
721
assign m1stg_qnan_in1= m1stg_qnan_sng_in1 || m1stg_qnan_dbl_in1;
722
 
723
assign m1stg_qnan_in2= m1stg_qnan_sng_in2 || m1stg_qnan_dbl_in2;
724
 
725
dffe_s #(1) i_m2stg_snan_in1 (
726
        .din    (m1stg_snan_in1),
727
        .en     (m6stg_step),
728
        .clk    (rclk),
729
 
730
        .q      (m2stg_snan_in1),
731
 
732
        .se     (se),
733
        .si     (),
734
        .so     ()
735
);
736
 
737
dffe_s #(1) i_m2stg_snan_in2 (
738
        .din    (m1stg_snan_in2),
739
        .en     (m6stg_step),
740
        .clk    (rclk),
741
 
742
        .q      (m2stg_snan_in2),
743
 
744
        .se     (se),
745
        .si     (),
746
        .so     ()
747
);
748
 
749
dffe_s #(1) i_m2stg_qnan_in1 (
750
        .din    (m1stg_qnan_in1),
751
        .en     (m6stg_step),
752
        .clk    (rclk),
753
 
754
        .q      (m2stg_qnan_in1),
755
 
756
        .se     (se),
757
        .si     (),
758
        .so     ()
759
);
760
 
761
dffe_s #(1) i_m2stg_qnan_in2 (
762
        .din    (m1stg_qnan_in2),
763
        .en     (m6stg_step),
764
        .clk    (rclk),
765
 
766
        .q      (m2stg_qnan_in2),
767
 
768
        .se     (se),
769
        .si     (),
770
        .so     ()
771
);
772
 
773
assign m1stg_nan_sng_in1= (!mul_exp_in1_exp_neq_ffs)
774
                && (mul_frac_in1_54 || mul_frac_in1_53_32_neq_0)
775
                && m1stg_sngopa[2];
776
 
777
assign m1stg_nan_dbl_in1= (!mul_exp_in1_exp_neq_ffs)
778
                && (mul_frac_in1_51 || mul_frac_in1_50_0_neq_0)
779
                && m1stg_dblopa[2];
780
 
781
assign m1stg_nan_sng_in2= (!mul_exp_in2_exp_neq_ffs)
782
                && (mul_frac_in2_54 || mul_frac_in2_53_32_neq_0)
783
                && m1stg_sngopa[2];
784
 
785
assign m1stg_nan_dbl_in2= (!mul_exp_in2_exp_neq_ffs)
786
                && (mul_frac_in2_51 || mul_frac_in2_50_0_neq_0)
787
                && m1stg_dblopa[2];
788
 
789
assign m1stg_nan_in1= m1stg_nan_sng_in1 || m1stg_nan_dbl_in1;
790
 
791
assign m1stg_nan_in2= m1stg_nan_sng_in2 || m1stg_nan_dbl_in2;
792
 
793
dffe_s #(1) i_m2stg_nan_in2 (
794
        .din    (m1stg_nan_in2),
795
        .en     (m6stg_step),
796
        .clk    (rclk),
797
 
798
        .q      (m2stg_nan_in2),
799
 
800
        .se     (se),
801
        .si     (),
802
        .so     ()
803
);
804
 
805
 
806
///////////////////////////////////////////////////////////////////////////////
807
//
808
//      Infinity multiply inputs.
809
//
810
///////////////////////////////////////////////////////////////////////////////
811
 
812
assign m1stg_inf_sng_in1= (!mul_exp_in1_exp_neq_ffs)
813
                && (!mul_frac_in1_54) && (!mul_frac_in1_53_32_neq_0)
814
                && m1stg_sngopa[2];
815
 
816
assign m1stg_inf_dbl_in1= (!mul_exp_in1_exp_neq_ffs)
817
                && (!mul_frac_in1_51) && (!mul_frac_in1_50_0_neq_0)
818
                && m1stg_dblopa[2];
819
 
820
assign m1stg_inf_sng_in2= (!mul_exp_in2_exp_neq_ffs)
821
                && (!mul_frac_in2_54) && (!mul_frac_in2_53_32_neq_0)
822
                && m1stg_sngopa[2];
823
 
824
assign m1stg_inf_dbl_in2= (!mul_exp_in2_exp_neq_ffs)
825
                && (!mul_frac_in2_51) && (!mul_frac_in2_50_0_neq_0)
826
                && m1stg_dblopa[2];
827
 
828
assign m1stg_inf_in1= m1stg_inf_sng_in1 || m1stg_inf_dbl_in1;
829
 
830
assign m1stg_inf_in2= m1stg_inf_sng_in2 || m1stg_inf_dbl_in2;
831
 
832
assign m1stg_inf_in= m1stg_inf_in1 || m1stg_inf_in2;
833
 
834
dffe_s #(1) i_m2stg_inf_in1 (
835
        .din    (m1stg_inf_in1),
836
        .en     (m6stg_step),
837
        .clk    (rclk),
838
 
839
        .q      (m2stg_inf_in1),
840
 
841
        .se     (se),
842
        .si     (),
843
        .so     ()
844
);
845
 
846
dffe_s #(1) i_m2stg_inf_in2 (
847
        .din    (m1stg_inf_in2),
848
        .en     (m6stg_step),
849
        .clk    (rclk),
850
 
851
        .q      (m2stg_inf_in2),
852
 
853
        .se     (se),
854
        .si     (),
855
        .so     ()
856
);
857
 
858
dffe_s #(1) i_m2stg_inf_in (
859
        .din    (m1stg_inf_in),
860
        .en     (m6stg_step),
861
        .clk    (rclk),
862
 
863
        .q      (m2stg_inf_in),
864
 
865
        .se     (se),
866
        .si     (),
867
        .so     ()
868
);
869
 
870
 
871
///////////////////////////////////////////////////////////////////////////////
872
//
873
//      Infinity/Nan multiply inputs.
874
//
875
///////////////////////////////////////////////////////////////////////////////
876
 
877
assign m1stg_infnan_sng_in1= (!mul_exp_in1_exp_neq_ffs) && m1stg_sngopa[3];
878
 
879
assign m1stg_infnan_dbl_in1= (!mul_exp_in1_exp_neq_ffs) && m1stg_dblopa[3];
880
 
881
assign m1stg_infnan_sng_in2= (!mul_exp_in2_exp_neq_ffs) && m1stg_sngopa[3];
882
 
883
assign m1stg_infnan_dbl_in2= (!mul_exp_in2_exp_neq_ffs) && m1stg_dblopa[3];
884
 
885
assign m1stg_infnan_in1= m1stg_infnan_sng_in1 || m1stg_infnan_dbl_in1;
886
 
887
assign m1stg_infnan_in2= m1stg_infnan_sng_in2 || m1stg_infnan_dbl_in2;
888
 
889
assign m1stg_infnan_in= m1stg_infnan_in1 || m1stg_infnan_in2;
890
 
891
 
892
///////////////////////////////////////////////////////////////////////////////
893
//
894
//      Zero multiply inputs.
895
//
896
///////////////////////////////////////////////////////////////////////////////
897
 
898
assign m1stg_zero_in1= mul_exp_in1_exp_eq_0
899
                && (!mul_frac_in1_53_0_neq_0) && (!mul_frac_in1_54);
900
 
901
assign m1stg_zero_in2= mul_exp_in2_exp_eq_0
902
                && (!mul_frac_in2_53_0_neq_0) && (!mul_frac_in2_54);
903
 
904
assign m1stg_zero_in= m1stg_zero_in1 || m1stg_zero_in2;
905
 
906
dffe_s #(1) i_m2stg_zero_in1 (
907
        .din    (m1stg_zero_in1),
908
        .en     (m6stg_step),
909
        .clk    (rclk),
910
 
911
        .q      (m2stg_zero_in1),
912
 
913
        .se     (se),
914
        .si     (),
915
        .so     ()
916
);
917
 
918
dffe_s #(1) i_m2stg_zero_in2 (
919
        .din    (m1stg_zero_in2),
920
        .en     (m6stg_step),
921
        .clk    (rclk),
922
 
923
        .q      (m2stg_zero_in2),
924
 
925
        .se     (se),
926
        .si     (),
927
        .so     ()
928
);
929
 
930
dffe_s #(1) i_m2stg_zero_in (
931
        .din    (m1stg_zero_in),
932
        .en     (m6stg_step),
933
        .clk    (rclk),
934
 
935
        .q      (m2stg_zero_in),
936
 
937
        .se     (se),
938
        .si     (),
939
        .so     ()
940
);
941
 
942
 
943
///////////////////////////////////////////////////////////////////////////////
944
//
945
//      Floating point multiply control pipeline.
946
//
947
///////////////////////////////////////////////////////////////////////////////
948
 
949
///////////////////////////////////////////////////////////////////////////////
950
//
951
//      Opcode pipeline- multiply input stage.
952
//
953
///////////////////////////////////////////////////////////////////////////////
954
 
955
assign m1stg_step= m6stg_stepa && (!m1stg_mul);
956
 
957
assign m1stg_op_in[7:0]= ({8{(m1stg_step && (!reset))}}
958
                            & (inq_op[7:0] & {8{inq_mul}}))
959
                | ({8{((!m6stg_step) && (!reset))}}
960
                            & m1stg_op[7:0]);
961
 
962
dff_s #(8) i_m1stg_op (
963
        .din    (m1stg_op_in[7:0]),
964
        .clk    (rclk),
965
 
966
        .q      (m1stg_op[7:0]),
967
 
968
        .se     (se),
969
        .si     (),
970
        .so     ()
971
);
972
 
973
assign m1stg_mul_in= (m1stg_step && (!reset) && inq_mul)
974
                || ((!m6stg_step) && (!reset) && m1stg_mul);
975
 
976
dff_s #(1) i_m1stg_mul (
977
        .din    (m1stg_mul_in),
978
        .clk    (rclk),
979
 
980
        .q      (m1stg_mul),
981
 
982
        .se     (se),
983
        .si     (),
984
        .so     ()
985
);
986
 
987
dffe_s #(1) i_m1stg_sngop (
988
        .din    (inq_op[0]),
989
        .en     (m6stg_step),
990
        .clk    (rclk),
991
 
992
        .q      (m1stg_sngop),
993
 
994
        .se     (se),
995
        .si     (),
996
        .so     ()
997
);
998
 
999
dffe_s #(4) i_m1stg_sngopa (
1000
        .din    ({4{inq_op[0]}}),
1001
        .en     (m6stg_step),
1002
        .clk    (rclk),
1003
 
1004
        .q      (m1stg_sngopa[3:0]),
1005
 
1006
        .se     (se),
1007
        .si     (),
1008
        .so     ()
1009
);
1010
 
1011
dffe_s #(1) i_m1stg_dblop (
1012
        .din    (inq_op[1]),
1013
        .en     (m6stg_step),
1014
        .clk    (rclk),
1015
 
1016
        .q      (m1stg_dblop),
1017
 
1018
        .se     (se),
1019
        .si     (),
1020
        .so     ()
1021
);
1022
 
1023
dffe_s #(4) i_m1stg_dblopa (
1024
        .din    ({4{inq_op[1]}}),
1025
        .en     (m6stg_step),
1026
        .clk    (rclk),
1027
 
1028
         .q     (m1stg_dblopa[3:0]),
1029
 
1030
        .se     (se),
1031
        .si     (),
1032
        .so     ()
1033
);
1034
 
1035
assign m1stg_dblop_inv_in= (!inq_op[1]);
1036
 
1037
dffe_s #(1) i_m1stg_dblop_inv (
1038
        .din    (m1stg_dblop_inv_in),
1039
        .en     (m6stg_step),
1040
        .clk    (rclk),
1041
 
1042
        .q      (m1stg_dblop_inv),
1043
 
1044
        .se     (se),
1045
        .si     (),
1046
        .so     ()
1047
);
1048
 
1049
dffe_s #(2) i_m1stg_rnd_mode (
1050
        .din    (inq_rnd_mode[1:0]),
1051
        .en     (m6stg_step),
1052
        .clk    (rclk),
1053
 
1054
        .q      (m1stg_rnd_mode[1:0]),
1055
 
1056
        .se     (se),
1057
        .si     (),
1058
        .so     ()
1059
);
1060
 
1061
dffe_s #(5) i_m1stg_id (
1062
        .din    (inq_id[4:0]),
1063
        .en     (m6stg_step),
1064
        .clk    (rclk),
1065
 
1066
        .q      (m1stg_id[4:0]),
1067
 
1068
        .se     (se),
1069
        .si     (),
1070
        .so     ()
1071
);
1072
 
1073
 
1074
///////////////////////////////////////////////////////////////////////////////
1075
//
1076
//      Opcode decode- multiply stage 1.
1077
//
1078
///////////////////////////////////////////////////////////////////////////////
1079
 
1080
assign m1stg_fmul= (m1stg_op[7:0]==FMULS) || (m1stg_op[7:0]==FMULD)
1081
                || (m1stg_op[7:0]==FSMULD);
1082
 
1083
assign m1stg_fmul_dbl_dst= (m1stg_op[7:0]==FMULD) || (m1stg_op[7:0]==FSMULD);
1084
 
1085
assign m1stg_fmuls= (m1stg_op[7:0]==FMULS);
1086
 
1087
assign m1stg_fmuld= (m1stg_op[7:0]==FMULD);
1088
 
1089
assign m1stg_fsmuld= (m1stg_op[7:0]==FSMULD);
1090
 
1091
assign m1stg_opdec[4:0]= {m1stg_fmul,
1092
                        m1stg_fmul_dbl_dst,
1093
                        m1stg_fmuls,
1094
                        m1stg_fmuld,
1095
                        m1stg_fsmuld};
1096
 
1097
dffre_s #(5) i_m2stg_opdec (
1098
        .din    (m1stg_opdec[4:0]),
1099
        .en     (m6stg_step),
1100
        .rst    (reset),
1101
        .clk    (rclk),
1102
 
1103
        .q      (m2stg_opdec[4:0]),
1104
 
1105
        .se     (se),
1106
        .si     (),
1107
        .so     ()
1108
);
1109
 
1110
dffe_s #(2) i_m2stg_rnd_mode (
1111
        .din    (m1stg_rnd_mode[1:0]),
1112
        .en     (m6stg_step),
1113
        .clk    (rclk),
1114
 
1115
        .q      (m2stg_rnd_mode[1:0]),
1116
 
1117
        .se     (se),
1118
        .si     (),
1119
        .so     ()
1120
);
1121
 
1122
dffe_s #(5) i_m2stg_id (
1123
        .din    (m1stg_id[4:0]),
1124
        .en     (m6stg_step),
1125
        .clk    (rclk),
1126
 
1127
        .q      (m2stg_id[4:0]),
1128
 
1129
        .se     (se),
1130
        .si     (),
1131
        .so     ()
1132
);
1133
 
1134
 
1135
///////////////////////////////////////////////////////////////////////////////
1136
//
1137
//      Opcode pipeline- multiply stage 2.
1138
//
1139
///////////////////////////////////////////////////////////////////////////////
1140
 
1141
assign m2stg_fmul= m2stg_opdec[4];
1142
assign m2stg_fmuls= m2stg_opdec[2];
1143
assign m2stg_fmuld= m2stg_opdec[1];
1144
assign m2stg_fsmuld= m2stg_opdec[0];
1145
 
1146
dffre_s #(4) i_m3astg_opdec (
1147
        .din    (m2stg_opdec[4:1]),
1148
        .en     (m6stg_step),
1149
        .rst    (reset),
1150
        .clk    (rclk),
1151
 
1152
        .q      (m3astg_opdec[4:1]),
1153
 
1154
        .se     (se),
1155
        .si     (),
1156
        .so     ()
1157
);
1158
 
1159
dffe_s #(2) i_m3astg_rnd_mode (
1160
        .din    (m2stg_rnd_mode[1:0]),
1161
        .en     (m6stg_step),
1162
        .clk    (rclk),
1163
 
1164
        .q      (m3astg_rnd_mode[1:0]),
1165
 
1166
        .se     (se),
1167
        .si     (),
1168
        .so     ()
1169
);
1170
 
1171
dffe_s #(5) i_m3astg_id (
1172
        .din    (m2stg_id[4:0]),
1173
        .en     (m6stg_step),
1174
        .clk    (rclk),
1175
 
1176
        .q      (m3astg_id[4:0]),
1177
 
1178
        .se     (se),
1179
        .si     (),
1180
        .so     ()
1181
);
1182
 
1183
 
1184
///////////////////////////////////////////////////////////////////////////////
1185
//
1186
//      Opcode pipeline- multiply stage 3a.
1187
//
1188
///////////////////////////////////////////////////////////////////////////////
1189
 
1190
dffre_s #(4) i_m3bstg_opdec (
1191
        .din    (m3astg_opdec[4:1]),
1192
        .en     (m6stg_step),
1193
        .rst    (reset),
1194
        .clk    (rclk),
1195
 
1196
        .q      (m3bstg_opdec[4:1]),
1197
 
1198
        .se     (se),
1199
        .si     (),
1200
        .so     ()
1201
);
1202
 
1203
dffe_s #(2) i_m3bstg_rnd_mode (
1204
        .din    (m3astg_rnd_mode[1:0]),
1205
        .en     (m6stg_step),
1206
        .clk    (rclk),
1207
 
1208
        .q      (m3bstg_rnd_mode[1:0]),
1209
 
1210
        .se     (se),
1211
        .si     (),
1212
        .so     ()
1213
);
1214
 
1215
dffe_s #(5) i_m3bstg_id (
1216
        .din    (m3astg_id[4:0]),
1217
        .en     (m6stg_step),
1218
        .clk    (rclk),
1219
 
1220
        .q      (m3bstg_id[4:0]),
1221
 
1222
        .se     (se),
1223
        .si     (),
1224
        .so     ()
1225
);
1226
 
1227
 
1228
///////////////////////////////////////////////////////////////////////////////
1229
//
1230
//      Opcode pipeline- multiply stage 3b.
1231
//
1232
///////////////////////////////////////////////////////////////////////////////
1233
 
1234
dffre_s #(4) i_m3stg_opdec (
1235
        .din    (m3bstg_opdec[4:1]),
1236
        .en     (m6stg_step),
1237
        .rst    (reset),
1238
        .clk    (rclk),
1239
 
1240
        .q      (m3stg_opdec[4:1]),
1241
 
1242
        .se     (se),
1243
        .si     (),
1244
        .so     ()
1245
);
1246
 
1247
dffe_s #(2) i_m3stg_rnd_mode (
1248
        .din    (m3bstg_rnd_mode[1:0]),
1249
        .en     (m6stg_step),
1250
        .clk    (rclk),
1251
 
1252
        .q      (m3stg_rnd_mode[1:0]),
1253
 
1254
        .se     (se),
1255
        .si     (),
1256
        .so     ()
1257
);
1258
 
1259
dffe_s #(5) i_m3stg_id (
1260
        .din    (m3bstg_id[4:0]),
1261
        .en     (m6stg_step),
1262
        .clk    (rclk),
1263
 
1264
        .q      (m3stg_id[4:0]),
1265
 
1266
        .se     (se),
1267
        .si     (),
1268
        .so     ()
1269
);
1270
 
1271
 
1272
///////////////////////////////////////////////////////////////////////////////
1273
//
1274
//      Opcode pipeline- multiply stage 3.
1275
//
1276
///////////////////////////////////////////////////////////////////////////////
1277
 
1278
assign m3stg_fmul= m3stg_opdec[4];
1279
 
1280
dffre_s #(4) i_m4stg_opdec (
1281
        .din    (m3stg_opdec[4:1]),
1282
        .en     (m6stg_step),
1283
        .rst    (reset),
1284
        .clk    (rclk),
1285
 
1286
        .q      (m4stg_opdec[4:1]),
1287
 
1288
        .se     (se),
1289
        .si     (),
1290
        .so     ()
1291
);
1292
 
1293
dffe_s #(2) i_m4stg_rnd_mode (
1294
        .din    (m3stg_rnd_mode[1:0]),
1295
        .en     (m6stg_step),
1296
        .clk    (rclk),
1297
 
1298
        .q      (m4stg_rnd_mode[1:0]),
1299
 
1300
        .se     (se),
1301
        .si     (),
1302
        .so     ()
1303
);
1304
 
1305
dffe_s #(5) i_m4stg_id (
1306
        .din    (m3stg_id[4:0]),
1307
        .en     (m6stg_step),
1308
        .clk    (rclk),
1309
 
1310
        .q      (m4stg_id[4:0]),
1311
 
1312
        .se     (se),
1313
        .si     (),
1314
        .so     ()
1315
);
1316
 
1317
 
1318
///////////////////////////////////////////////////////////////////////////////
1319
//
1320
//      Opcode pipeline- multiply stage 4.
1321
//
1322
///////////////////////////////////////////////////////////////////////////////
1323
 
1324
assign m4stg_fmul= m4stg_opdec[4];
1325
assign m4stg_fmuld= m4stg_opdec[1];
1326
 
1327
dffre_s #(4) i_m5stg_opdec (
1328
        .din    (m4stg_opdec[4:1]),
1329
        .en     (m6stg_step),
1330
        .rst    (reset),
1331
        .clk    (rclk),
1332
 
1333
        .q      (m5stg_opdec[4:1]),
1334
 
1335
        .se     (se),
1336
        .si     (),
1337
        .so     ()
1338
);
1339
 
1340
dffe_s #(2) i_m5stg_rnd_mode (
1341
        .din    (m4stg_rnd_mode[1:0]),
1342
        .en     (m6stg_step),
1343
        .clk    (rclk),
1344
 
1345
        .q      (m5stg_rnd_mode[1:0]),
1346
 
1347
        .se     (se),
1348
        .si     (),
1349
        .so     ()
1350
);
1351
 
1352
dffe_s #(5) i_m5stg_id (
1353
        .din    (m4stg_id[4:0]),
1354
        .en     (m6stg_step),
1355
        .clk    (rclk),
1356
 
1357
        .q      (m5stg_id[4:0]),
1358
 
1359
        .se     (se),
1360
        .si     (),
1361
        .so     ()
1362
);
1363
 
1364
dffre_s #(1) i_m5stg_fmulda (
1365
        .din    (m4stg_fmuld),
1366
        .en     (m6stg_step),
1367
        .rst    (reset),
1368
        .clk    (rclk),
1369
 
1370
        .q      (m5stg_fmulda),
1371
 
1372
        .se     (se),
1373
        .si     (),
1374
        .so     ()
1375
);
1376
 
1377
 
1378
///////////////////////////////////////////////////////////////////////////////
1379
//
1380
//      Opcode pipeline- multiply stage 5.
1381
//
1382
///////////////////////////////////////////////////////////////////////////////
1383
 
1384
assign m5stg_fmul= m5stg_opdec[4];
1385
assign m5stg_fmuls= m5stg_opdec[2];
1386
assign m5stg_fmuld= m5stg_opdec[1];
1387
 
1388
assign m6stg_fmul_in= (m6stg_stepa && (!reset)
1389
                        && m5stg_fmul)
1390
                || ((!m6stg_stepa) && (!reset)
1391
                        && m6stg_fmul);
1392
 
1393
dffre_s #(3) i_m6stg_opdec (
1394
        .din    (m5stg_opdec[4:2]),
1395
        .en     (m6stg_step),
1396
        .rst    (reset),
1397
        .clk    (rclk),
1398
 
1399
        .q      (m6stg_opdec[4:2]),
1400
 
1401
        .se     (se),
1402
        .si     (),
1403
        .so     ()
1404
);
1405
 
1406
assign m6stg_id_in[9:0]= ({10{m6stg_stepa}}
1407
                            & {(m5stg_id[4:2]==3'o7),
1408
                                (m5stg_id[4:2]==3'o6),
1409
                                (m5stg_id[4:2]==3'o5),
1410
                                (m5stg_id[4:2]==3'o4),
1411
                                (m5stg_id[4:2]==3'o3),
1412
                                (m5stg_id[4:2]==3'o2),
1413
                                (m5stg_id[4:2]==3'o1),
1414
                                (m5stg_id[4:2]==3'o0),
1415
                                m5stg_id[1:0]})
1416
                | ({10{(!m6stg_stepa)}}
1417
                            & m6stg_id[9:0]);
1418
 
1419
dffe_s #(10) i_m6stg_id (
1420
        .din    (m6stg_id_in[9:0]),
1421
        .en     (m6stg_step),
1422
        .clk    (rclk),
1423
 
1424
        .q      (m6stg_id[9:0]),
1425
 
1426
        .se     (se),
1427
        .si     (),
1428
        .so     ()
1429
);
1430
 
1431
 
1432
///////////////////////////////////////////////////////////////////////////////
1433
//
1434
//      Opcode pipeline- multiply pipeline output.
1435
//
1436
///////////////////////////////////////////////////////////////////////////////
1437
 
1438
assign m6stg_fmul= m6stg_opdec[4];
1439
assign m6stg_fmul_dbl_dst= m6stg_opdec[3];
1440
assign m6stg_fmuls= m6stg_opdec[2];
1441
 
1442
assign m6stg_hold= m6stg_fmul && (!mul_dest_rdy);
1443
assign m6stg_holda= m6stg_fmul && (!mul_dest_rdya);
1444
 
1445
assign m6stg_step= (!m6stg_hold);
1446
assign m6stg_stepa= (!m6stg_holda);
1447
 
1448
// Austin update
1449
// Power management update
1450
 
1451
assign mul_pipe_active_in =  // mul pipe is executing a valid instr
1452
   m1stg_fmul || m2stg_fmul || m3astg_opdec[4] || m3bstg_opdec[4] ||
1453
   m3stg_fmul || m4stg_fmul || m5stg_fmul      || m6stg_fmul;
1454
 
1455
dffre_s #(1) i_mul_pipe_active (
1456
        .din    (mul_pipe_active_in),
1457
        .en     (1'b1),
1458
        .rst    (reset),
1459
        .clk    (rclk),
1460
 
1461
        .q      (mul_pipe_active),
1462
 
1463
        .se     (se),
1464
        .si     (),
1465
        .so     ()
1466
);
1467
 
1468
 
1469
///////////////////////////////////////////////////////////////////////////////
1470
//
1471
//      Multiply sign and exception logic.
1472
//
1473
///////////////////////////////////////////////////////////////////////////////
1474
 
1475
///////////////////////////////////////////////////////////////////////////////
1476
//
1477
//      Multiply sign inputs.
1478
//
1479
///////////////////////////////////////////////////////////////////////////////
1480
 
1481
dffe_s #(1) i_m1stg_sign1 (
1482
        .din    (inq_in1_63),
1483
        .en     (m6stg_step),
1484
        .clk    (rclk),
1485
 
1486
        .q      (m1stg_sign1),
1487
 
1488
        .se     (se),
1489
        .si     (),
1490
        .so     ()
1491
);
1492
 
1493
dffe_s #(1) i_m1stg_sign2 (
1494
        .din    (inq_in2_63),
1495
        .en     (m6stg_step),
1496
        .clk    (rclk),
1497
 
1498
        .q      (m1stg_sign2),
1499
 
1500
        .se     (se),
1501
        .si     (),
1502
        .so     ()
1503
);
1504
 
1505
 
1506
///////////////////////////////////////////////////////////////////////////////
1507
//
1508
//      Multiply sign and exceptions.
1509
//
1510
//      Multiply stage 1.
1511
//
1512
///////////////////////////////////////////////////////////////////////////////
1513
 
1514
dffe_s #(1) i_m2stg_sign1 (
1515
        .din    (m1stg_sign1),
1516
        .en     (m6stg_step),
1517
        .clk    (rclk),
1518
 
1519
        .q      (m2stg_sign1),
1520
 
1521
        .se     (se),
1522
        .si     (),
1523
        .so     ()
1524
);
1525
 
1526
dffe_s #(1) i_m2stg_sign2 (
1527
        .din    (m1stg_sign2),
1528
        .en     (m6stg_step),
1529
        .clk    (rclk),
1530
 
1531
        .q      (m2stg_sign2),
1532
 
1533
        .se     (se),
1534
        .si     (),
1535
        .so     ()
1536
);
1537
 
1538
assign m1stg_of_mask= (!m1stg_infnan_in);
1539
 
1540
dffe_s #(1) i_m2stg_of_mask (
1541
        .din    (m1stg_of_mask),
1542
        .en     (m6stg_step),
1543
        .clk    (rclk),
1544
 
1545
        .q      (m2stg_of_mask),
1546
 
1547
        .se     (se),
1548
        .si     (),
1549
        .so     ()
1550
);
1551
 
1552
 
1553
///////////////////////////////////////////////////////////////////////////////
1554
//
1555
//      Multiply sign and exceptions.
1556
//
1557
//      Multiply stage 2.
1558
//
1559
///////////////////////////////////////////////////////////////////////////////
1560
 
1561
assign m2stg_sign= ((m2stg_sign1
1562
                                && (!m2stg_snan_in2)
1563
                                && (!(m2stg_qnan_in2 && (!m2stg_snan_in1))))
1564
                        ^ (m2stg_sign2
1565
                                && (!(m2stg_snan_in1 && (!m2stg_snan_in2)))
1566
                                && (!(m2stg_qnan_in1 && (!m2stg_nan_in2)))))
1567
                && (!(m2stg_inf_in && m2stg_zero_in));
1568
 
1569
dffe_s #(1) i_m3astg_sign (
1570
        .din    (m2stg_sign),
1571
        .en     (m6stg_step),
1572
        .clk    (rclk),
1573
 
1574
        .q      (m3astg_sign),
1575
 
1576
        .se     (se),
1577
        .si     (),
1578
        .so     ()
1579
);
1580
 
1581
assign m2stg_nv= m2stg_snan_in1
1582
                || m2stg_snan_in2
1583
                || (m2stg_zero_in1 && m2stg_inf_in2)
1584
                || (m2stg_inf_in1 && m2stg_zero_in2);
1585
 
1586
dffe_s #(1) i_m3astg_nv (
1587
        .din    (m2stg_nv),
1588
        .en     (m6stg_step),
1589
        .clk    (rclk),
1590
 
1591
        .q      (m3astg_nv),
1592
 
1593
        .se     (se),
1594
        .si     (),
1595
        .so     ()
1596
);
1597
 
1598
dffe_s #(1) i_m3astg_of_mask (
1599
        .din    (m2stg_of_mask),
1600
        .en     (m6stg_step),
1601
        .clk    (rclk),
1602
 
1603
        .q      (m3astg_of_mask),
1604
 
1605
        .se     (se),
1606
        .si     (),
1607
        .so     ()
1608
);
1609
 
1610
 
1611
///////////////////////////////////////////////////////////////////////////////
1612
//
1613
//      Multiply sign and exceptions.
1614
//
1615
//      Multiply stage 3a.
1616
//
1617
///////////////////////////////////////////////////////////////////////////////
1618
 
1619
dffe_s #(1) i_m3bstg_sign (
1620
        .din    (m3astg_sign),
1621
        .en     (m6stg_step),
1622
        .clk    (rclk),
1623
 
1624
        .q      (m3bstg_sign),
1625
 
1626
        .se     (se),
1627
        .si     (),
1628
        .so     ()
1629
);
1630
 
1631
dffe_s #(1) i_m3bstg_nv (
1632
        .din    (m3astg_nv),
1633
        .en     (m6stg_step),
1634
        .clk    (rclk),
1635
 
1636
        .q      (m3bstg_nv),
1637
 
1638
        .se     (se),
1639
        .si     (),
1640
        .so     ()
1641
);
1642
 
1643
dffe_s #(1) i_m3bstg_of_mask (
1644
        .din    (m3astg_of_mask),
1645
        .en     (m6stg_step),
1646
        .clk    (rclk),
1647
 
1648
        .q      (m3bstg_of_mask),
1649
 
1650
        .se     (se),
1651
        .si     (),
1652
        .so     ()
1653
);
1654
 
1655
 
1656
///////////////////////////////////////////////////////////////////////////////
1657
//
1658
//      Multiply sign and exceptions.
1659
//
1660
//      Multiply stage 3b.
1661
//
1662
///////////////////////////////////////////////////////////////////////////////
1663
 
1664
dffe_s #(1) i_m3stg_sign (
1665
        .din    (m3bstg_sign),
1666
        .en     (m6stg_step),
1667
        .clk    (rclk),
1668
 
1669
        .q      (m3stg_sign),
1670
 
1671
        .se     (se),
1672
        .si     (),
1673
        .so     ()
1674
);
1675
 
1676
dffe_s #(1) i_m3stg_nv (
1677
        .din    (m3bstg_nv),
1678
        .en     (m6stg_step),
1679
        .clk    (rclk),
1680
 
1681
        .q      (m3stg_nv),
1682
 
1683
        .se     (se),
1684
        .si     (),
1685
        .so     ()
1686
);
1687
 
1688
dffe_s #(1) i_m3stg_of_mask (
1689
        .din    (m3bstg_of_mask),
1690
        .en     (m6stg_step),
1691
        .clk    (rclk),
1692
 
1693
        .q      (m3stg_of_mask),
1694
 
1695
        .se     (se),
1696
        .si     (),
1697
        .so     ()
1698
);
1699
 
1700
 
1701
///////////////////////////////////////////////////////////////////////////////
1702
//
1703
//      Multiply sign and exceptions.
1704
//
1705
//      Multiply stage 3.
1706
//
1707
///////////////////////////////////////////////////////////////////////////////
1708
 
1709
dffe_s #(1) i_m4stg_sign (
1710
        .din    (m3stg_sign),
1711
        .en     (m6stg_step),
1712
        .clk    (rclk),
1713
 
1714
        .q      (m4stg_sign),
1715
 
1716
        .se     (se),
1717
        .si     (),
1718
        .so     ()
1719
);
1720
 
1721
dffe_s #(1) i_m4stg_nv (
1722
        .din    (m3stg_nv),
1723
        .en     (m6stg_step),
1724
        .clk    (rclk),
1725
 
1726
        .q      (m4stg_nv),
1727
 
1728
        .se     (se),
1729
        .si     (),
1730
        .so     ()
1731
);
1732
 
1733
dffe_s #(1) i_m4stg_of_mask (
1734
        .din    (m3stg_of_mask),
1735
        .en     (m6stg_step),
1736
        .clk    (rclk),
1737
 
1738
        .q      (m4stg_of_mask),
1739
 
1740
        .se     (se),
1741
        .si     (),
1742
        .so     ()
1743
);
1744
 
1745
 
1746
///////////////////////////////////////////////////////////////////////////////
1747
//
1748
//      Multiply sign and exceptions.
1749
//
1750
//      Multiply stage 4.
1751
//
1752
///////////////////////////////////////////////////////////////////////////////
1753
 
1754
dffe_s #(1) i_m5stg_sign (
1755
        .din    (m4stg_sign),
1756
        .en     (m6stg_step),
1757
        .clk    (rclk),
1758
 
1759
        .q      (m5stg_sign),
1760
 
1761
        .se     (se),
1762
        .si     (),
1763
        .so     ()
1764
);
1765
 
1766
dffe_s #(1) i_m5stg_nv (
1767
        .din    (m4stg_nv),
1768
        .en     (m6stg_step),
1769
        .clk    (rclk),
1770
 
1771
        .q      (m5stg_nv),
1772
 
1773
        .se     (se),
1774
        .si     (),
1775
        .so     ()
1776
);
1777
 
1778
dffe_s #(1) i_m5stg_of_mask (
1779
        .din    (m4stg_of_mask),
1780
        .en     (m6stg_step),
1781
        .clk    (rclk),
1782
 
1783
        .q      (m5stg_of_mask),
1784
 
1785
        .se     (se),
1786
        .si     (),
1787
        .so     ()
1788
);
1789
 
1790
 
1791
///////////////////////////////////////////////////////////////////////////////
1792
//
1793
//      Multiply sign and exceptions.
1794
//
1795
//      Multiply stage 5.
1796
//
1797
///////////////////////////////////////////////////////////////////////////////
1798
 
1799
dffe_s #(1) i_mul_sign_out (
1800
        .din    (m5stg_sign),
1801
        .en     (m6stg_step),
1802
        .clk    (rclk),
1803
 
1804
        .q      (mul_sign_out),
1805
 
1806
        .se     (se),
1807
        .si     (),
1808
        .so     ()
1809
);
1810
 
1811
dffe_s #(1) i_mul_nv_out (
1812
        .din    (m5stg_nv),
1813
        .en     (m6stg_step),
1814
        .clk    (rclk),
1815
 
1816
        .q      (mul_nv_out),
1817
 
1818
        .se     (se),
1819
        .si     (),
1820
        .so     ()
1821
);
1822
 
1823
assign m5stg_in_of= ((!m5stg_exp[12])
1824
                        && m5stg_fmuld
1825
                        && (m5stg_exp[11] || (&m5stg_exp[10:0]))
1826
                        && m5stg_of_mask)
1827
                || ((!m5stg_exp[12])
1828
                        && m5stg_fmuls
1829
                        && ((|m5stg_exp[11:8]) || (&m5stg_exp[7:0]))
1830
                        && m5stg_of_mask);
1831
 
1832
assign mul_of_out_tmp1_in= ((!m5stg_exp[12])
1833
                        && m5stg_fmuld
1834
                        && (&m5stg_exp[10:1])
1835
                        && m5stg_rndup
1836
                        && m5stg_of_mask)
1837
                || ((!m5stg_exp[12])
1838
                        && m5stg_fmuls
1839
                        && (&m5stg_exp[7:1])
1840
                        && m5stg_rndup
1841
                        && m5stg_of_mask);
1842
 
1843
dffe_s #(1) i_mul_of_out_tmp1 (
1844
        .din    (mul_of_out_tmp1_in),
1845
        .en     (m6stg_step),
1846
        .clk    (rclk),
1847
 
1848
        .q      (mul_of_out_tmp1),
1849
 
1850
        .se     (se),
1851
        .si     (),
1852
        .so     ()
1853
);
1854
 
1855
dffe_s #(1) i_mul_of_out_tmp2 (
1856
        .din    (m5stg_in_of),
1857
        .en     (m6stg_step),
1858
        .clk    (rclk),
1859
 
1860
        .q      (mul_of_out_tmp2),
1861
 
1862
        .se     (se),
1863
        .si     (),
1864
        .so     ()
1865
);
1866
 
1867
dffe_s #(1) i_mul_of_out_cout (
1868
        .din    (m5stg_fracadd_cout),
1869
        .en     (m6stg_step),
1870
        .clk    (rclk),
1871
 
1872
        .q      (mul_of_out_cout),
1873
 
1874
        .se     (se),
1875
        .si     (),
1876
        .so     ()
1877
);
1878
 
1879
assign mul_of_out= mul_of_out_tmp2
1880
                || (mul_of_out_tmp1 && mul_of_out_cout);
1881
 
1882
assign mul_uf_out_in= (m5stg_exp[12] || (!(|m5stg_exp[11:0])))
1883
                && m5stg_frac_neq_0;
1884
 
1885
dffe_s #(1) i_mul_uf_out (
1886
        .din    (mul_uf_out_in),
1887
        .en     (m6stg_step),
1888
        .clk    (rclk),
1889
 
1890
        .q      (mul_uf_out),
1891
 
1892
        .se     (se),
1893
        .si     (),
1894
        .so     ()
1895
);
1896
 
1897
assign mul_nx_out_in= (m5stg_fmuld && m5stg_frac_dbl_nx)
1898
                || (m5stg_fmuls && m5stg_frac_sng_nx);
1899
 
1900
dffe_s #(1) i_mul_nx_out (
1901
        .din    (mul_nx_out_in),
1902
        .en     (m6stg_step),
1903
        .clk    (rclk),
1904
 
1905
        .q      (mul_nx_out),
1906
 
1907
        .se     (se),
1908
        .si     (),
1909
        .so     ()
1910
);
1911
 
1912
 
1913
///////////////////////////////////////////////////////////////////////////////
1914
//
1915
//      Multiply exception output.
1916
//
1917
///////////////////////////////////////////////////////////////////////////////
1918
 
1919
// Austin update
1920
// Overflow is always accompanied by inexact.
1921
// Previously this was handled within the FFU.
1922
 
1923
// assign mul_exc_out[4:0]= {mul_nv_out, mul_of_out, mul_uf_out, 1'b0, mul_nx_out};
1924
 
1925
assign mul_exc_out[4:0] =
1926
  {mul_nv_out,
1927
   mul_of_out,
1928
   mul_uf_out,
1929
   1'b0,
1930
   (mul_nx_out || mul_of_out)};  // Overflow is always accompanied by inexact
1931
 
1932
 
1933
///////////////////////////////////////////////////////////////////////////////
1934
//
1935
//      Multiply pipeline control logic.
1936
//
1937
///////////////////////////////////////////////////////////////////////////////
1938
 
1939
///////////////////////////////////////////////////////////////////////////////
1940
//
1941
//      Select lines- multiply normalization and special input injection.
1942
//
1943
//      Multiply stage 1.
1944
//
1945
///////////////////////////////////////////////////////////////////////////////
1946
 
1947
assign m2stg_frac1_dbl_norm= m1stg_norm_dbl_in1
1948
                && ((!(m1stg_infnan_dbl_in1 || m1stg_infnan_dbl_in2))
1949
                        || (m1stg_snan_dbl_in1 && (!m1stg_snan_dbl_in2))
1950
                        || (m1stg_qnan_dbl_in1 && (!m1stg_nan_dbl_in2)));
1951
 
1952
assign m2stg_frac1_dbl_dnrm= m1stg_denorm_dbl_in1
1953
                && (!(m1stg_infnan_dbl_in1 || m1stg_infnan_dbl_in2));
1954
 
1955
assign m2stg_frac1_sng_norm= m1stg_norm_sng_in1
1956
                && ((!(m1stg_infnan_sng_in1 || m1stg_infnan_sng_in2))
1957
                        || (m1stg_snan_sng_in1 && (!m1stg_snan_sng_in2))
1958
                        || (m1stg_qnan_sng_in1 && (!m1stg_nan_sng_in2)));
1959
 
1960
assign m2stg_frac1_sng_dnrm= m1stg_denorm_sng_in1
1961
                && (!(m1stg_infnan_sng_in1 || m1stg_infnan_sng_in2));
1962
 
1963
assign m2stg_frac1_inf= (m1stg_inf_in && (!m1stg_nan_in1) && (!m1stg_nan_in2))
1964
                || m1stg_snan_in2
1965
                || (m1stg_qnan_in2 && (!m1stg_snan_in1));
1966
 
1967
assign m2stg_frac2_dbl_norm= m1stg_norm_dbl_in2
1968
                && ((!(m1stg_infnan_dbl_in1 || m1stg_infnan_dbl_in2))
1969
                        || m1stg_snan_dbl_in2
1970
                        || (m1stg_qnan_dbl_in2 && (!m1stg_snan_dbl_in1)));
1971
 
1972
assign m2stg_frac2_dbl_dnrm= m1stg_denorm_dbl_in2
1973
                && (!(m1stg_infnan_dbl_in1 || m1stg_infnan_dbl_in2));
1974
 
1975
assign m2stg_frac2_sng_norm= m1stg_norm_sng_in2
1976
                && ((!(m1stg_infnan_sng_in1 || m1stg_infnan_sng_in2))
1977
                        || m1stg_snan_sng_in2
1978
                        || (m1stg_qnan_sng_in2 && (!m1stg_snan_sng_in1)));
1979
 
1980
assign m2stg_frac2_sng_dnrm= m1stg_denorm_sng_in2
1981
                && (!(m1stg_infnan_sng_in1 || m1stg_infnan_sng_in2));
1982
 
1983
assign m2stg_frac2_inf= (m1stg_inf_in && (!m1stg_nan_in1) && (!m1stg_nan_in2))
1984
                || (m1stg_snan_in1 && (!m1stg_snan_in2))
1985
                || (m1stg_qnan_in1 && (!m1stg_nan_in2));
1986
 
1987
assign m1stg_inf_zero_in= (m1stg_inf_in1 && m1stg_zero_in2)
1988
                || (m1stg_zero_in1 && m1stg_inf_in2);
1989
 
1990
assign m1stg_inf_zero_in_dbl= ((m1stg_inf_in1 && m1stg_zero_in2)
1991
                        || (m1stg_zero_in1 && m1stg_inf_in2))
1992
                && m1stg_fmul_dbl_dst;
1993
 
1994
 
1995
///////////////////////////////////////////////////////////////////////////////
1996
//
1997
//      Select lines and control logic- multiply leading 0 counts.
1998
//
1999
//      Multiply stage 1.
2000
//
2001
///////////////////////////////////////////////////////////////////////////////
2002
 
2003
assign m2stg_ld0_1_in[5:0]= ({6{(m1stg_denorm_in1 && (!m1stg_infnan_in))}}
2004
                & m1stg_ld0_1[5:0]);
2005
 
2006
dffe_s #(6) i_m2stg_ld0_1 (
2007
        .din    (m2stg_ld0_1_in[5:0]),
2008
        .en     (m6stg_step),
2009
        .clk    (rclk),
2010
 
2011
        .q      (m2stg_ld0_1[5:0]),
2012
 
2013
        .se     (se),
2014
        .si     (),
2015
        .so     ()
2016
);
2017
 
2018
assign m2stg_ld0_2_in[5:0]= ({6{(m1stg_denorm_in2 && (!m1stg_infnan_in))}}
2019
                & m1stg_ld0_2[5:0]);
2020
 
2021
dffe_s #(6) i_m2stg_ld0_2 (
2022
        .din    (m2stg_ld0_2_in[5:0]),
2023
        .en     (m6stg_step),
2024
        .clk    (rclk),
2025
 
2026
        .q      (m2stg_ld0_2[5:0]),
2027
 
2028
        .se     (se),
2029
        .si     (),
2030
        .so     ()
2031
);
2032
 
2033
 
2034
///////////////////////////////////////////////////////////////////////////////
2035
//
2036
//      Select lines- multiply exponent adder.
2037
//
2038
//      Multiply stage 1.
2039
//
2040
///////////////////////////////////////////////////////////////////////////////
2041
 
2042
assign m2stg_exp_expadd= (!m1stg_infnan_in) && (!m1stg_zero_in);
2043
 
2044
assign m2stg_exp_0bff= m1stg_fmuld && m1stg_infnan_in;
2045
 
2046
assign m2stg_exp_017f= m1stg_fmuls && m1stg_infnan_in;
2047
 
2048
assign m2stg_exp_04ff= m1stg_fsmuld && m1stg_infnan_in;
2049
 
2050
assign m2stg_exp_zero= m1stg_zero_in && (!m1stg_infnan_in);
2051
 
2052
 
2053
///////////////////////////////////////////////////////////////////////////////
2054
//
2055
//      Total the leading 0's.
2056
//
2057
//      Multiply stage 2.
2058
//
2059
///////////////////////////////////////////////////////////////////////////////
2060
 
2061
assign m2stg_ld0[6:0]= {1'b0, m2stg_ld0_1[5:0]}
2062
                        + {1'b0, m2stg_ld0_2[5:0]};
2063
 
2064
assign m2stg_ld0_inv[6:0]= (~m2stg_ld0[6:0]);
2065
 
2066
dffe_s #(7) i_m3astg_ld0_inv (
2067
        .din    (m2stg_ld0_inv[6:0]),
2068
        .en     (m6stg_step),
2069
        .clk    (rclk),
2070
 
2071
        .q      (m3astg_ld0_inv[6:0]),
2072
 
2073
        .se     (se),
2074
        .si     (),
2075
        .so     ()
2076
);
2077
 
2078
 
2079
///////////////////////////////////////////////////////////////////////////////
2080
//
2081
//      Leading 0's.
2082
//
2083
//      Multiply stage 3a.
2084
//
2085
///////////////////////////////////////////////////////////////////////////////
2086
 
2087
dffe_s #(7) i_m3bstg_ld0_inv (
2088
        .din    (m3astg_ld0_inv[6:0]),
2089
        .en     (m6stg_step),
2090
        .clk    (rclk),
2091
 
2092
        .q      (m3bstg_ld0_inv[6:0]),
2093
 
2094
        .se     (se),
2095
        .si     (),
2096
        .so     ()
2097
);
2098
 
2099
 
2100
///////////////////////////////////////////////////////////////////////////////
2101
//
2102
//      Post-normalization/denormalization shift count and direction.
2103
//
2104
//      Multiply stage 3.
2105
//
2106
///////////////////////////////////////////////////////////////////////////////
2107
 
2108
dffe_s #(1) i_m4stg_expadd_eq_0 (
2109
        .din    (m3stg_expadd_eq_0),
2110
        .en     (m6stg_step),
2111
        .clk    (rclk),
2112
 
2113
        .q      (m4stg_expadd_eq_0),
2114
 
2115
        .se     (se),
2116
        .si     (),
2117
        .so     ()
2118
);
2119
 
2120
assign m3stg_exp_lte_0= (!(|m3stg_exp[11:0])) || m3stg_exp[12];
2121
 
2122
assign m4stg_right_shift_in= (!m3stg_expadd_lte_0_inv) && m3stg_exp_lte_0;
2123
 
2124
dffe_s #(1) i_m4stg_right_shift (
2125
        .din    (m4stg_right_shift_in),
2126
        .en     (m6stg_step),
2127
        .clk    (rclk),
2128
 
2129
        .q      (m4stg_right_shift),
2130
 
2131
        .se     (se),
2132
        .si     (),
2133
        .so     ()
2134
);
2135
 
2136
assign m3stg_exp_minus1[5:0]= m3stg_exp[5:0]
2137
                        + 6'h3f;
2138
 
2139
assign m3stg_exp_inv_plus2[5:0]= (~m3stg_exp[5:0])
2140
                        + 6'h02;
2141
 
2142
assign m3stg_exp_lt_neg57= ((!(&m3stg_exp[11:6]))
2143
                        || (!(|m3stg_exp[5:3])))
2144
                && m3stg_exp[12];
2145
 
2146
assign m4stg_sh_cnt_in[5:0]= ({6{((!m3stg_expadd_lte_0_inv)
2147
                                && (!m3stg_exp_lte_0))}}
2148
                            & m3stg_exp_minus1[5:0])
2149
                | ({6{((!m3stg_expadd_lte_0_inv) && m3stg_exp_lte_0
2150
                                && m3stg_exp_lt_neg57)}}
2151
                            & 6'h39)
2152
                | ({6{((!m3stg_expadd_lte_0_inv) && m3stg_exp_lte_0
2153
                                && (!m3stg_exp_lt_neg57))}}
2154
                            & m3stg_exp_inv_plus2[5:0])
2155
                | ({6{m3stg_expadd_lte_0_inv}}
2156
                            & (~m3stg_ld0_inv[5:0]));
2157
 
2158
 
2159
///////////////////////////////////////////////////////////////////////////////
2160
//
2161
//      Select lines and control logic- multiply shifts for
2162
//              post-normalization/denormalization.
2163
//
2164
//      Multiply stage 4.
2165
//
2166
///////////////////////////////////////////////////////////////////////////////
2167
 
2168
assign m4stg_left_shift_step= (!m4stg_right_shift) && m6stg_step;
2169
 
2170
assign m4stg_right_shift_step= m4stg_right_shift && m6stg_step;
2171
 
2172
// Austin update
2173
// uarch timing fix
2174
// Endpoint: fpu_mul_exp_dp/i_m5stg_exp_pre2_10
2175
 
2176
// assign m4stg_inc_exp= (((!(|m4stg_exp[12:0])) && (!m4stg_right_shift)
2177
//                              && m4stg_shl_54)
2178
//                      || (m4stg_expadd_eq_0 && m4stg_right_shift
2179
//                              && m4stg_frac_105)
2180
//                      || ((!m4stg_right_shift) && m4stg_shl_55))
2181
//              && m6stg_step;
2182
//
2183
// assign m4stg_inc_exp_inv= (!m4stg_inc_exp) && m6stg_step;
2184
 
2185
assign m4stg_inc_exp_54  = (!(|m4stg_exp[12:0])) && (!m4stg_right_shift);
2186
assign m4stg_inc_exp_55  = !m4stg_right_shift;
2187
assign m4stg_inc_exp_105 = m4stg_expadd_eq_0 && m4stg_right_shift && m4stg_frac_105;
2188
 
2189
 
2190
///////////////////////////////////////////////////////////////////////////////
2191
//
2192
//      Select lines and control logic- multiply rounding.
2193
//
2194
//      Multiply stage 5.
2195
//
2196
///////////////////////////////////////////////////////////////////////////////
2197
 
2198
assign m5stg_rndup= ((((m5stg_rnd_mode[1:0]==2'b10) && (!m5stg_sign)
2199
                                        && (m5stg_frac[2:0]!=3'b0))
2200
                                || ((m5stg_rnd_mode[1:0]==2'b11) && m5stg_sign
2201
                                        && (m5stg_frac[2:0]!=3'b0))
2202
                                || ((m5stg_rnd_mode[1:0]==2'b00)
2203
                                        && m5stg_frac[2]
2204
                                        && ((m5stg_frac[1:0]!=2'b0)
2205
                                                || m5stg_frac[3])))
2206
                        && m5stg_fmuld)
2207
                || ((((m5stg_rnd_mode[1:0]==2'b10) && (!m5stg_sign)
2208
                                        && (m5stg_frac[31:0]!=32'b0))
2209
                                || ((m5stg_rnd_mode[1:0]==2'b11) && m5stg_sign
2210
                                        && (m5stg_frac[31:0]!=32'b0))
2211
                                || ((m5stg_rnd_mode[1:0]==2'b00)
2212
                                        && m5stg_frac[31]
2213
                                        && ((m5stg_frac[30:0]!=31'b0)
2214
                                                || m5stg_frac[32])))
2215
                        && m5stg_fmuls);
2216
 
2217
assign m5stg_to_0= (m5stg_rnd_mode[1:0]==2'b01)
2218
                || ((m5stg_rnd_mode[1:0]==2'b10) && m5stg_sign)
2219
                || ((m5stg_rnd_mode[1:0]==2'b11) && (!m5stg_sign));
2220
 
2221
assign m5stg_to_0_inv= (!m5stg_to_0);
2222
 
2223
assign mul_frac_out_fracadd= m5stg_rndup && (!m5stg_in_of);
2224
 
2225
assign mul_frac_out_frac= (!m5stg_rndup) && (!m5stg_in_of);
2226
 
2227
assign mul_exp_out_exp_plus1= m5stg_rndup && (!m5stg_in_of);
2228
 
2229
assign mul_exp_out_exp= (!m5stg_rndup) && (!m5stg_in_of);
2230
 
2231
 
2232
endmodule
2233
 
2234
 

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