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[/] [sparc64soc/] [trunk/] [T1-FPU/] [fpu_out.v] - Blame information for rev 8

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1 2 dmitryr
// ========== Copyright Header Begin ==========================================
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// 
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// OpenSPARC T1 Processor File: fpu_out.v
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// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// 
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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// 
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// The above named program is distributed in the hope that it will be 
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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// General Public License for more details.
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// 
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// 
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// ========== Copyright Header End ============================================
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///////////////////////////////////////////////////////////////////////////////
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//
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//      FPU result output.
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//
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///////////////////////////////////////////////////////////////////////////////
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module fpu_out (
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        d8stg_fdiv_in,
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        m6stg_fmul_in,
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        a6stg_fadd_in,
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        div_id_out_in,
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        m6stg_id_in,
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        add_id_out_in,
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        div_exc_out,
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        d8stg_fdivd,
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        d8stg_fdivs,
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        div_sign_out,
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        div_exp_out,
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        div_frac_out,
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        mul_exc_out,
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        m6stg_fmul_dbl_dst,
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        m6stg_fmuls,
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        mul_sign_out,
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        mul_exp_out,
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        mul_frac_out,
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        add_exc_out,
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        a6stg_fcmpop,
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        add_cc_out,
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        add_fcc_out,
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        a6stg_dbl_dst,
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        a6stg_sng_dst,
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        a6stg_long_dst,
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        a6stg_int_dst,
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        add_sign_out,
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        add_exp_out,
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        add_frac_out,
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        arst_l,
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        grst_l,
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        rclk,
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        fp_cpx_req_cq,
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        add_dest_rdy,
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        mul_dest_rdy,
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        div_dest_rdy,
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        fp_cpx_data_ca,
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        se,
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        si,
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        so
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);
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input           d8stg_fdiv_in;          // div pipe output request next cycle
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input           m6stg_fmul_in;          // mul pipe output request next cycle
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input           a6stg_fadd_in;          // add pipe output request next cycle
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input [9:0]      div_id_out_in;          // div pipe output ID next cycle
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input [9:0]      m6stg_id_in;            // mul pipe output ID next cycle
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input [9:0]      add_id_out_in;          // add pipe output ID next cycle
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input [4:0]      div_exc_out;            // divide pipe result- exception flags
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input           d8stg_fdivd;            // divide double- divide stage 8
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input           d8stg_fdivs;            // divide single- divide stage 8
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input           div_sign_out;           // divide sign output
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input [10:0]     div_exp_out;            // divide exponent output
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input [51:0]     div_frac_out;           // divide fraction output
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input [4:0]      mul_exc_out;            // multiply pipe result- exception flags
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input           m6stg_fmul_dbl_dst;     // double precision multiply result
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input           m6stg_fmuls;            // fmuls- multiply 6 stage
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input           mul_sign_out;           // multiply sign output
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input [10:0]     mul_exp_out;            // multiply exponent output
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input [51:0]     mul_frac_out;           // multiply fraction output
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input [4:0]      add_exc_out;            // add pipe result- exception flags
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input           a6stg_fcmpop;           // compare- add 6 stage
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input [1:0]      add_cc_out;             // add pipe result- condition
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input [1:0]      add_fcc_out;            // add pipe input fcc passed through
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input           a6stg_dbl_dst;          // float double result- add 6 stage
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input           a6stg_sng_dst;          // float single result- add 6 stage
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input           a6stg_long_dst;         // 64bit integer result- add 6 stage
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input           a6stg_int_dst;          // 32bit integer result- add 6 stage
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input           add_sign_out;           // add sign output
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input [10:0]     add_exp_out;            // add exponent output
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input [63:0]     add_frac_out;           // add fraction output
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input           arst_l;                 // global async. reset- asserted low
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input           grst_l;                 // global sync. reset- asserted low
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input           rclk;                   // global clock
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output [7:0]     fp_cpx_req_cq;          // FPU result request to CPX
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output          add_dest_rdy;           // add pipe result request this cycle
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output          mul_dest_rdy;           // mul pipe result request this cycle
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output          div_dest_rdy;           // div pipe result request this cycle
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output [144:0]   fp_cpx_data_ca;         // FPU result to CPX
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input           se;                     // scan_enable
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input           si;                     // scan in
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output          so;                     // scan out
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///////////////////////////////////////////////////////////////////////////////
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//
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//      Outputs of fpu_out_ctl.
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//
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///////////////////////////////////////////////////////////////////////////////
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wire [7:0]       fp_cpx_req_cq;          // FPU result request to CPX
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wire [1:0]       req_thread;             // thread ID of result req this cycle
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wire [2:0]       dest_rdy;               // pipe with result request this cycle
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wire            add_dest_rdy;           // add pipe result request this cycle
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wire            mul_dest_rdy;           // mul pipe result request this cycle
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wire            div_dest_rdy;           // div pipe result request this cycle
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///////////////////////////////////////////////////////////////////////////////
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//
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//      Outputs of fpu_out_dp.
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//
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///////////////////////////////////////////////////////////////////////////////
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wire [144:0]     fp_cpx_data_ca;         // FPU result to CPX
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///////////////////////////////////////////////////////////////////////////////
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//
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//      Instantiations.
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//
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///////////////////////////////////////////////////////////////////////////////
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fpu_out_ctl fpu_out_ctl (
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        .d8stg_fdiv_in                  (d8stg_fdiv_in),
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        .m6stg_fmul_in                  (m6stg_fmul_in),
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        .a6stg_fadd_in                  (a6stg_fadd_in),
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        .div_id_out_in                  (div_id_out_in[9:0]),
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        .m6stg_id_in                    (m6stg_id_in[9:0]),
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        .add_id_out_in                  (add_id_out_in[9:0]),
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        .arst_l                         (arst_l),
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        .grst_l                         (grst_l),
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        .rclk                   (rclk),
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        .fp_cpx_req_cq                  (fp_cpx_req_cq[7:0]),
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        .req_thread                     (req_thread[1:0]),
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        .dest_rdy                       (dest_rdy[2:0]),
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        .add_dest_rdy                   (add_dest_rdy),
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        .mul_dest_rdy                   (mul_dest_rdy),
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        .div_dest_rdy                   (div_dest_rdy),
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        .se                             (se),
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        .si                             (si),
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        .so                             (scan_out_fpu_out_ctl)
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);
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fpu_out_dp fpu_out_dp (
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        .dest_rdy                       (dest_rdy[2:0]),
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        .req_thread                     (req_thread[1:0]),
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        .div_exc_out                    (div_exc_out[4:0]),
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        .d8stg_fdivd                    (d8stg_fdivd),
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        .d8stg_fdivs                    (d8stg_fdivs),
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        .div_sign_out                   (div_sign_out),
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        .div_exp_out                    (div_exp_out[10:0]),
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        .div_frac_out                   (div_frac_out[51:0]),
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        .mul_exc_out                    (mul_exc_out[4:0]),
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        .m6stg_fmul_dbl_dst             (m6stg_fmul_dbl_dst),
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        .m6stg_fmuls                    (m6stg_fmuls),
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        .mul_sign_out                   (mul_sign_out),
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        .mul_exp_out                    (mul_exp_out[10:0]),
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        .mul_frac_out                   (mul_frac_out[51:0]),
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        .add_exc_out                    (add_exc_out[4:0]),
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        .a6stg_fcmpop                   (a6stg_fcmpop),
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        .add_cc_out                     (add_cc_out[1:0]),
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        .add_fcc_out                    (add_fcc_out[1:0]),
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        .a6stg_dbl_dst                  (a6stg_dbl_dst),
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        .a6stg_sng_dst                  (a6stg_sng_dst),
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        .a6stg_long_dst                 (a6stg_long_dst),
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        .a6stg_int_dst                  (a6stg_int_dst),
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        .add_sign_out                   (add_sign_out),
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        .add_exp_out                    (add_exp_out[10:0]),
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        .add_frac_out                   (add_frac_out[63:0]),
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        .rclk                   (rclk),
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        .fp_cpx_data_ca                 (fp_cpx_data_ca[144:0]),
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        .se                             (se),
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        .si                             (scan_out_fpu_out_ctl),
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        .so                             (so)
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);
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endmodule
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