OpenCores
URL https://opencores.org/ocsvn/sparc64soc/sparc64soc/trunk

Subversion Repositories sparc64soc

[/] [sparc64soc/] [trunk/] [T1-common/] [common/] [cluster_header.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dmitryr
// ========== Copyright Header Begin ==========================================
2
// 
3
// OpenSPARC T1 Processor File: cluster_header.v
4
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
5
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6
// 
7
// The above named program is free software; you can redistribute it and/or
8
// modify it under the terms of the GNU General Public
9
// License version 2 as published by the Free Software Foundation.
10
// 
11
// The above named program is distributed in the hope that it will be 
12
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
// General Public License for more details.
15
// 
16
// You should have received a copy of the GNU General Public
17
// License along with this work; if not, write to the Free Software
18
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19
// 
20
// ========== Copyright Header End ============================================
21
// The cluster header is instatiated as a hard macro.
22
// This model is for simulation only.
23
`include "sys.h"
24
 
25
module cluster_header (/*AUTOARG*/
26
   // Outputs
27
   dbginit_l, cluster_grst_l, rclk, so,
28
   // Inputs
29
   gclk, cluster_cken, arst_l, grst_l, adbginit_l, gdbginit_l, si,
30
   se
31
   );
32
 
33
   input       gclk;
34
   input       cluster_cken;
35
   input       arst_l;
36
   input       grst_l;
37
   input       adbginit_l;
38
   input       gdbginit_l;
39
   output      dbginit_l;
40
   output      cluster_grst_l;
41
   output      rclk;
42
 
43
   input       si; // scan ports for reset flop repeaters
44
   input       se;
45
   output      so;
46
 
47
`ifdef FPGA_SYN
48
//  assign #10 rclk = gclk;
49
//  assign #10 dbginit_l = gdbginit_l;
50
//  assign #10 cluster_grst_l = grst_l; 
51
//  assign so = 1'b0;
52
 
53
reg      dbginit_l;
54
reg      cluster_grst_l;
55
 
56
assign #10 rclk = gclk;
57
 
58
always @(negedge rclk) begin
59
  dbginit_l <= gdbginit_l;
60
  cluster_grst_l <= grst_l;
61
end
62
 
63
`else
64
 
65
   wire        pre_sync_enable;
66
   wire        sync_enable;
67
   wire        cluster_grst_l;
68
   wire        dbginit_l;
69
   wire        rst_sync_so;
70
 
71
   bw_u1_syncff_4x sync_cluster_master ( // no scan hook-up
72
                                        .so(),
73
                                        .q (pre_sync_enable),
74
                                        .ck (gclk),
75
                                        .d (cluster_cken),
76
                                        .sd(1'b0),
77
                                        .se(1'b0)
78
                                        );
79
 
80
 
81
   bw_u1_scanl_2x sync_cluster_slave ( // use scan lock-up latch
82
                                      .so (sync_enable),
83
                                      .ck (gclk),
84
                                      .sd (pre_sync_enable)
85
                                      );
86
 
87
// NOTE! Pound delay in the below statement is meant to provide 10 ps
88
// delay between gclk and rclk to allow the synchronizer for rst, dbginit,
89
// and sync pulses to be modelled accurately.  gclk and rclk need to have 
90
// at least one simulator timestep separation to allow the flop->flop 
91
// synchronizer to work correctly.
92
   assign #10 rclk = gclk & sync_enable;
93
 
94
   synchronizer_asr rst_repeater (
95
                                 .sync_out(cluster_grst_l),
96
                                 .so(rst_sync_so),
97
                                 .async_in(grst_l),
98
                                 .gclk(gclk),
99
                                 .rclk(rclk),
100
                                 .arst_l(arst_l),
101
                                 .si(si),
102
                                 .se(se)
103
                                 );
104
 
105
   synchronizer_asr dbginit_repeater (
106
                                     .sync_out(dbginit_l),
107
                                     .so(so),
108
                                     .async_in(gdbginit_l),
109
                                     .gclk(gclk),
110
                                     .rclk(rclk),
111
                                     .arst_l(adbginit_l),
112
                                     .si(rst_sync_so),
113
                                     .se(se)
114
                                     );
115
`endif
116
 
117
endmodule // cluster_header

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.