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[/] [sparc64soc/] [trunk/] [T1-common/] [common/] [cmp_sram_redhdr.v] - Blame information for rev 2

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1 2 dmitryr
// ========== Copyright Header Begin ==========================================
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// 
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// OpenSPARC T1 Processor File: cmp_sram_redhdr.v
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// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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// 
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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// 
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// The above named program is distributed in the hope that it will be 
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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// General Public License for more details.
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// 
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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// 
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// ========== Copyright Header End ============================================
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//
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//    Cluster Name:  Efuse Cluster
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//    Unit Name:  cmp_redhdr (sram redundancy header)
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//    Block Name: EFC
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//
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//    This is the header used to read and write the fuse values to the
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//    RAM blocks.  It is used to drive the ICD, DCD and L2T.  It is
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//    outside the array it is driving.
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//
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//    Top level signal renaming:
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//       s/ary/<your_ary_name>/g
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//       s/xfuse/<your_ary_initial>fuse/g
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//
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//       E.g.  fuse_ary_wren -> fuse_icd_wren
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//             efc_spc_xfuse_data -> efc_spc_ifuse_data, efc_sct_fuse_data
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//
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//-----------------------------------------------------------------------------
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`include "sys.h"
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`include "iop.h"
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//FPGA_SYN enables all FPGA related modifications
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`ifdef FPGA_SYN
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`define FPGA_SYN_CLK
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`endif
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module cmp_sram_redhdr (/*AUTOARG*/
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   // Outputs
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   fuse_ary_wren, fuse_ary_rid, fuse_ary_repair_value,
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   fuse_ary_repair_en, spc_efc_xfuse_data, scanout,
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   // Inputs
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   rclk, se, scanin, arst_l, testmode_l, efc_spc_fuse_clk1,
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   efc_spc_fuse_clk2, efc_spc_xfuse_data, efc_spc_xfuse_ashift,
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   efc_spc_xfuse_dshift, ary_fuse_repair_value, ary_fuse_repair_en
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   );
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   input                rclk;
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   input                se;
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   input                scanin;                 // CMP clock, L1 phase
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   input    arst_l;
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   input    testmode_l;
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   // eFuse controller interface
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   input                efc_spc_fuse_clk1;
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   input                efc_spc_fuse_clk2;
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   input                efc_spc_xfuse_data;
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   input                efc_spc_xfuse_ashift;   // addr shift; low during rst
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   input                efc_spc_xfuse_dshift;   // data shift; low during rst
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   // interface to cache redundancy logic
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   input [7:0] ary_fuse_repair_value;  //data out for redundancy register
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   input [1:0] ary_fuse_repair_en;     //enable bits out 
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   // outputs
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   // interface to icache
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   output      fuse_ary_wren;         //redundancy reg wr enable, qualified
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   output [5:0] fuse_ary_rid;         //redundancy register id
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   output [7:0] fuse_ary_repair_value;//data in for redundancy register
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   output [1:0] fuse_ary_repair_en;   //enable bits to turn on redundancy
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   // serial rd data to controller
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   output       spc_efc_xfuse_data;
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   // normal scan out
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   output       scanout;
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`ifdef FPGA_SYN_CLK
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   assign fuse_ary_wren = 1'b0;
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   assign fuse_ary_rid = 6'b0;
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   assign fuse_ary_repair_value = 8'b0;
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   assign fuse_ary_repair_en = 2'b0;
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   assign spc_efc_xfuse_data = 1'b0;
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   assign scanout = 1'b0;
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`else
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   // local signals
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   wire         clk;
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   wire         int_clk1;
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   wire         int_clk2;
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   wire         int_scanout; // !! hook up to last flop in scan chain !!
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   wire         int_scanin;  // !! hook up to 1st flop in scan chain !!
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   wire [6:0]   addr_shft_nxt;
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   wire [6:0]   addr_shft_ff;
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   wire         addr_shft_en;
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   wire         wren_bit;
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   wire [11:0]  data_shft_nxt;
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   wire [11:0]  data_shft_ff;
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   wire         data_shft_en;
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   wire         dshift_dly1_ff;
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   wire         dshift_dly2_ff;
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   wire         ashift_dly1_ff;
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   wire         ashift_dly2_ff;
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   wire         wren_ff;
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   wire         wren_ph1;
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   wire         rden_ph1;
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   /*AUTOWIRE*/
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   // Beginning of automatic wires (for undeclared instantiated-module outputs)
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   // End of automatics
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   //
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   // Code Begins Here
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   //
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   assign       clk = rclk;
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   //  Test logic
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   assign       int_clk1 = (~testmode_l) ? rclk : efc_spc_fuse_clk1;
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   assign       int_clk2 = (~testmode_l) ? rclk : efc_spc_fuse_clk2;
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   assign       int_scanout = 1'b0;
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   // Need latch to avoid hold time problems
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   // connect int_scanout to last flop in scan chain
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   bw_u1_scanlg_2x so_lockup(.so (scanout),
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                             .sd (int_scanout),
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                             .ck (clk),  .se(se));
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   // connect int_scanin to first flop in scan chain
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   bw_u1_scanlg_2x si_lockup(.so (int_scanin),
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                             .sd (scanin),
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                             .ck (clk), .se(se));
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   //  Shift registers
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   //  Address
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   assign   addr_shft_en = efc_spc_xfuse_ashift;
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   assign   addr_shft_nxt = {addr_shft_ff[5:0], efc_spc_xfuse_data};
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   dffe_s #(7) addr_shft_reg (.din  (addr_shft_nxt),
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                                        .q    (addr_shft_ff),
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                            .en   (addr_shft_en),
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                            .clk  (int_clk1), .se(se), .si(), .so());
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   assign   fuse_ary_rid[5:0] = addr_shft_ff[6:1];
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   assign   wren_bit = addr_shft_ff[0];
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   // Data
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   assign   data_shft_en = efc_spc_xfuse_dshift | dshift_dly1_ff | rden_ph1;
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   // mux2es
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   assign   data_shft_nxt = rden_ph1
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            ? {{3{ary_fuse_repair_en[1]}},
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               ary_fuse_repair_value[7:0],
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               ary_fuse_repair_en[0]}
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            : {data_shft_ff[10:0],
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               efc_spc_xfuse_data};
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   // 10:9 is unused
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   dffe_s #(12)          data_shft_reg (.din  (data_shft_nxt),
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                                                  .q    (data_shft_ff),
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                                .en   (data_shft_en),
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                                .clk  (int_clk1), .se(se), .si(), .so());
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   assign   fuse_ary_repair_value = data_shft_ff[8:1];
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   assign   fuse_ary_repair_en    = {(data_shft_ff[11] & wren_ff),
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                                     (data_shft_ff[0] & wren_ff)};
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   // Control
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   dff_s #(1) ashift_dly1_reg (.din (efc_spc_xfuse_ashift),
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                             .q   (ashift_dly1_ff),
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                                                     .clk (int_clk1), .se(se), .si(), .so());
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   dff_s #(1) ashift_dly2_reg (.din (ashift_dly1_ff),
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                             .q   (ashift_dly2_ff),
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                                                     .clk (int_clk1), .se(se), .si(), .so());
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   dffrl_async #(1) dshift_dly1_reg (.din (efc_spc_xfuse_dshift),
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                             .q   (dshift_dly1_ff),
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                             .rst_l (arst_l),
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                                                     .clk (int_clk1), .se(se), .si(), .so());
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   dffrl_async #(1) dshift_dly2_reg (.din (dshift_dly1_ff),
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                             .q   (dshift_dly2_ff),
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                             .rst_l (arst_l),
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                                                     .clk (int_clk1), .se(se), .si(), .so());
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   assign   wren_ph1 = dshift_dly2_ff && ~dshift_dly1_ff && wren_bit;
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   assign   rden_ph1 = ashift_dly2_ff && ~ashift_dly1_ff && ~wren_bit;
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   // use phase two for wren since array writes in phase one
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   dffrl_async #(1) wren_reg (.din  (wren_ph1),
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                      .q     (wren_ff),
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                      .rst_l (arst_l),
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                                              .clk   (int_clk2), .se(se), .si(), .so());
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   // address is never shifted out
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   assign   spc_efc_xfuse_data = data_shft_ff[11];
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   assign   fuse_ary_wren = wren_ff & testmode_l;
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`endif
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endmodule // cmp_sram_redhdr
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// Local Variables:
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// verilog-library-directories:("." "../../common/rtl")
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// verilog-library-files:      ("../../common/rtl/swrvr_clib.v")
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// verilog-auto-sense-defines-constant:t
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// End:

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