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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: ucb_flow_2buf.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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////////////////////////////////////////////////////////////////////////
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/*
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// Module Name: ucb_flow_2buf
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// Description: Unit Control Block
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// - supports 64-bit or 128-bit read with flow control
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// - supports 64-bit write with flow control
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// - automactically drops non-64-bit writes
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// - supports interrupt return to IO Bridge
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// - provides 1+2 deep buffer for incoming requests
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// from the IO Bridge
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// - provides single buffer for returns going back
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// to the IO Bridge
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//
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// This module is intended for units that have
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// 64-bit (no 128-bit) registers.
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//
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// Data bus width to and from the IO Bridge is
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// configured through parameters UCB_IOB_WIDTH and
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// IOB_UCB_WIDTH. Supported widths are:
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//
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// IOB_UCB_WIDTH UCB_IOB_WIDTH
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// ----------------------------
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// 32 8
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// 16 8
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// 8 8
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// 4 4
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*/
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////////////////////////////////////////////////////////////////////////
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// Global header file includes
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////////////////////////////////////////////////////////////////////////
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`include "sys.h" // system level definition file which
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// contains the time scale definition
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`include "iop.h"
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////////////////////////////////////////////////////////////////////////
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// Local header file includes / local defines
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////////////////////////////////////////////////////////////////////////
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`define UCB_BUF_DEPTH 2
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`define UCB_BUF_WIDTH 64+(`UCB_ADDR_HI-`UCB_ADDR_LO+1)+(`UCB_SIZE_HI-`UCB_SIZE_LO+1)+(`UCB_BUF_HI-`UCB_BUF_LO+1)+(`UCB_THR_HI-`UCB_THR_LO+1)+1+1
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module ucb_flow_2buf (/*AUTOARG*/
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// Outputs
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ucb_iob_stall, rd_req_vld, wr_req_vld, thr_id_in, buf_id_in,
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size_in, addr_in, data_in, ack_busy, int_busy, ucb_iob_vld,
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ucb_iob_data,
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// Inputs
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clk, rst_l, iob_ucb_vld, iob_ucb_data, req_acpted, rd_ack_vld,
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rd_nack_vld, thr_id_out, buf_id_out, data128, data_out, int_vld,
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int_typ, int_thr_id, dev_id, int_stat, int_vec, iob_ucb_stall
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);
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// synopsys template
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parameter IOB_UCB_WIDTH = 32; // data bus width from IOB to UCB
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parameter UCB_IOB_WIDTH = 8; // data bus width from UCB to IOB
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parameter REG_WIDTH = 64; // please do not change this parameter
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// Globals
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input clk;
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input rst_l;
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// Request from IO Bridge
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input iob_ucb_vld;
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input [IOB_UCB_WIDTH-1:0] iob_ucb_data;
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output ucb_iob_stall;
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// Request to local unit
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output rd_req_vld;
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output wr_req_vld;
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output [`UCB_THR_HI-`UCB_THR_LO:0] thr_id_in;
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output [`UCB_BUF_HI-`UCB_BUF_LO:0] buf_id_in;
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output [`UCB_SIZE_HI-`UCB_SIZE_LO:0] size_in; // only pertinent to PCI
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output [`UCB_ADDR_HI-`UCB_ADDR_LO:0] addr_in;
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output [`UCB_DATA_HI-`UCB_DATA_LO:0] data_in;
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input req_acpted;
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// Ack/Nack from local unit
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input rd_ack_vld;
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input rd_nack_vld;
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input [`UCB_THR_HI-`UCB_THR_LO:0] thr_id_out;
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input [`UCB_BUF_HI-`UCB_BUF_LO:0] buf_id_out;
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input data128; // set to 1 if data returned is 128 bit
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input [REG_WIDTH-1:0] data_out;
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output ack_busy;
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// Interrupt from local unit
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input int_vld;
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input [`UCB_PKT_HI-`UCB_PKT_LO:0] int_typ; // interrupt type
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input [`UCB_THR_HI-`UCB_THR_LO:0] int_thr_id; // interrupt thread ID
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input [`UCB_INT_DEV_HI-`UCB_INT_DEV_LO:0] dev_id; // interrupt device ID
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input [`UCB_INT_STAT_HI-`UCB_INT_STAT_LO:0] int_stat; // interrupt status
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input [`UCB_INT_VEC_HI-`UCB_INT_VEC_LO:0] int_vec; // interrupt vector
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output int_busy;
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// Output to IO Bridge
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output ucb_iob_vld;
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output [UCB_IOB_WIDTH-1:0] ucb_iob_data;
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input iob_ucb_stall;
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// Local signals
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wire indata_buf_vld;
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wire [127:0] indata_buf;
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wire ucb_iob_stall_a1;
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wire read_pending;
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wire write_pending;
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wire illegal_write_size;
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wire rd_buf;
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wire [`UCB_BUF_DEPTH-1:0] buf_head_next;
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wire [`UCB_BUF_DEPTH-1:0] buf_head;
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wire wr_buf;
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wire [`UCB_BUF_DEPTH-1:0] buf_tail_next;
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wire [`UCB_BUF_DEPTH-1:0] buf_tail;
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wire buf_full_next;
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wire buf_full;
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wire buf_empty_next;
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wire buf_empty;
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wire [`UCB_BUF_WIDTH-1:0] req_in;
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wire buf0_en;
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wire [`UCB_BUF_WIDTH-1:0] buf0;
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wire buf1_en;
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wire [`UCB_BUF_WIDTH-1:0] buf1;
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wire [`UCB_BUF_WIDTH-1:0] req_out;
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wire rd_req_vld_nq;
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wire wr_req_vld_nq;
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wire ack_buf_rd;
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wire ack_buf_wr;
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wire ack_buf_vld;
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wire ack_buf_vld_next;
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wire ack_buf_is_nack;
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wire ack_buf_is_data128;
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wire [`UCB_PKT_HI-`UCB_PKT_LO:0] ack_typ_out;
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wire [REG_WIDTH+`UCB_BUF_HI-`UCB_PKT_LO:0] ack_buf_in;
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wire [REG_WIDTH+`UCB_BUF_HI-`UCB_PKT_LO:0] ack_buf;
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wire [(REG_WIDTH+64)/UCB_IOB_WIDTH-1:0] ack_buf_vec;
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wire int_buf_rd;
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wire int_buf_wr;
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wire int_buf_vld;
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wire int_buf_vld_next;
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wire [`UCB_INT_VEC_HI-`UCB_PKT_LO:0] int_buf_in;
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wire [`UCB_INT_VEC_HI-`UCB_PKT_LO:0] int_buf;
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wire [(REG_WIDTH+64)/UCB_IOB_WIDTH-1:0] int_buf_vec;
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wire int_last_rd;
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wire outdata_buf_busy;
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wire outdata_buf_wr;
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wire [REG_WIDTH+63:0] outdata_buf_in;
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wire [(REG_WIDTH+64)/UCB_IOB_WIDTH-1:0] outdata_vec_in;
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////////////////////////////////////////////////////////////////////////
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// Code starts here
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////////////////////////////////////////////////////////////////////////
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/************************************************************
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* Inbound Data
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************************************************************/
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// Register size is hardcoded to 64 bits here because all
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// units using the UCB module will only write to 64 bit registers.
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ucb_bus_in #(IOB_UCB_WIDTH,64) ucb_bus_in (.rst_l(rst_l),
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.clk(clk),
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.vld(iob_ucb_vld),
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.data(iob_ucb_data),
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.stall(ucb_iob_stall),
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.indata_buf_vld(indata_buf_vld),
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.indata_buf(indata_buf),
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.stall_a1(ucb_iob_stall_a1));
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/************************************************************
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* Decode inbound packet type
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************************************************************/
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assign read_pending = (indata_buf[`UCB_PKT_HI:`UCB_PKT_LO] ==
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`UCB_READ_REQ) &
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indata_buf_vld;
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assign write_pending = (indata_buf[`UCB_PKT_HI:`UCB_PKT_LO] ==
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`UCB_WRITE_REQ) &
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indata_buf_vld;
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// 3'b011 is the encoding for double word. All writes have to be
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// 64 bits except writes going to PCI. PCI will instantiate a
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// customized version of UCB.
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assign illegal_write_size = (indata_buf[`UCB_SIZE_HI:`UCB_SIZE_LO] !=
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3'b011);
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assign ucb_iob_stall_a1 = (read_pending | write_pending) & buf_full;
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/************************************************************
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* Inbound buffer
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************************************************************/
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// Head pointer
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assign rd_buf = req_acpted;
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assign buf_head_next = ~rst_l ? `UCB_BUF_DEPTH'b01 :
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rd_buf ? {buf_head[`UCB_BUF_DEPTH-2:0],
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buf_head[`UCB_BUF_DEPTH-1]} :
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buf_head;
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dff_ns #(`UCB_BUF_DEPTH) buf_head_ff (.din(buf_head_next),
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.clk(clk),
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.q(buf_head));
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// Tail pointer
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assign wr_buf = (read_pending |
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(write_pending & ~illegal_write_size)) &
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~buf_full;
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assign buf_tail_next = ~rst_l ? `UCB_BUF_DEPTH'b01 :
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wr_buf ? {buf_tail[`UCB_BUF_DEPTH-2:0],
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buf_tail[`UCB_BUF_DEPTH-1]} :
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buf_tail;
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dff_ns #(`UCB_BUF_DEPTH) buf_tail_ff (.din(buf_tail_next),
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.clk(clk),
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.q(buf_tail));
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// Buffer full
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assign buf_full_next = (buf_head_next == buf_tail_next) &
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wr_buf;
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dffrle_ns #(1) buf_full_ff (.din(buf_full_next),
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.rst_l(rst_l),
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.en(rd_buf|wr_buf),
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.clk(clk),
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.q(buf_full));
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// Buffer empty
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assign buf_empty_next = ((buf_head_next == buf_tail_next) &
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rd_buf) | ~rst_l;
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dffe_ns #(1) buf_empty_ff (.din(buf_empty_next),
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.en(rd_buf|wr_buf|~rst_l),
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.clk(clk),
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.q(buf_empty));
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assign req_in = {indata_buf[`UCB_DATA_HI:`UCB_DATA_LO],
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indata_buf[`UCB_ADDR_HI:`UCB_ADDR_LO],
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indata_buf[`UCB_SIZE_HI:`UCB_SIZE_LO],
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indata_buf[`UCB_BUF_HI:`UCB_BUF_LO],
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indata_buf[`UCB_THR_HI:`UCB_THR_LO],
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write_pending & ~illegal_write_size,
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read_pending};
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// Buffer 0
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assign buf0_en = buf_tail[0] & wr_buf;
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dffe_ns #(`UCB_BUF_WIDTH) buf0_ff (.din(req_in),
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.en(buf0_en),
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.clk(clk),
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.q(buf0));
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// Buffer 1
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assign buf1_en = buf_tail[1] & wr_buf;
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dffe_ns #(`UCB_BUF_WIDTH) buf1_ff (.din(req_in),
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.en(buf1_en),
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.clk(clk),
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.q(buf1));
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assign req_out = buf_head[0] ? buf0 :
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buf_head[1] ? buf1 :
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{`UCB_BUF_WIDTH{1'b0}};
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/************************************************************
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* Inbound interface to local unit
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************************************************************/
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assign {data_in,
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addr_in,
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size_in,
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buf_id_in,
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thr_id_in,
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wr_req_vld_nq,
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rd_req_vld_nq} = req_out;
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assign rd_req_vld = rd_req_vld_nq & ~buf_empty;
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assign wr_req_vld = wr_req_vld_nq & ~buf_empty;
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/************************************************************
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* Outbound Ack/Nack
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************************************************************/
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assign ack_buf_wr = rd_ack_vld | rd_nack_vld;
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assign ack_buf_vld_next = ack_buf_wr ? 1'b1 :
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ack_buf_rd ? 1'b0 :
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ack_buf_vld;
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dffrl_ns #(1) ack_buf_vld_ff (.din(ack_buf_vld_next),
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.clk(clk),
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.rst_l(rst_l),
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.q(ack_buf_vld));
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dffe_ns #(1) ack_buf_is_nack_ff (.din(rd_nack_vld),
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.en(ack_buf_wr),
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.clk(clk),
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.q(ack_buf_is_nack));
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dffe_ns #(1) ack_buf_is_data128_ff (.din(data128),
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.en(ack_buf_wr),
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.clk(clk),
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.q(ack_buf_is_data128));
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assign ack_typ_out = rd_ack_vld ? `UCB_READ_ACK:
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`UCB_READ_NACK;
|
323 |
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|
324 |
|
|
assign ack_buf_in = {data_out,
|
325 |
|
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buf_id_out,
|
326 |
|
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thr_id_out,
|
327 |
|
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ack_typ_out};
|
328 |
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|
329 |
|
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dffe_ns #(REG_WIDTH+`UCB_BUF_HI-`UCB_PKT_LO+1) ack_buf_ff (.din(ack_buf_in),
|
330 |
|
|
.en(ack_buf_wr),
|
331 |
|
|
.clk(clk),
|
332 |
|
|
.q(ack_buf));
|
333 |
|
|
|
334 |
|
|
assign ack_buf_vec = ack_buf_is_nack ? {{REG_WIDTH/UCB_IOB_WIDTH{1'b0}},
|
335 |
|
|
{64/UCB_IOB_WIDTH{1'b1}}} :
|
336 |
|
|
ack_buf_is_data128 ? {(REG_WIDTH+64)/UCB_IOB_WIDTH{1'b1}} :
|
337 |
|
|
{(64+64)/UCB_IOB_WIDTH{1'b1}};
|
338 |
|
|
|
339 |
|
|
assign ack_busy = ack_buf_vld;
|
340 |
|
|
|
341 |
|
|
|
342 |
|
|
/************************************************************
|
343 |
|
|
* Outbound Interrupt
|
344 |
|
|
************************************************************/
|
345 |
|
|
// Assertion: int_buf_wr shoudn't be asserted if int_buf_busy
|
346 |
|
|
assign int_buf_wr = int_vld;
|
347 |
|
|
|
348 |
|
|
assign int_buf_vld_next = int_buf_wr ? 1'b1 :
|
349 |
|
|
int_buf_rd ? 1'b0 :
|
350 |
|
|
int_buf_vld;
|
351 |
|
|
|
352 |
|
|
dffrl_ns #(1) int_buf_vld_ff (.din(int_buf_vld_next),
|
353 |
|
|
.clk(clk),
|
354 |
|
|
.rst_l(rst_l),
|
355 |
|
|
.q(int_buf_vld));
|
356 |
|
|
|
357 |
|
|
assign int_buf_in = {int_vec,
|
358 |
|
|
int_stat,
|
359 |
|
|
dev_id,
|
360 |
|
|
int_thr_id,
|
361 |
|
|
int_typ};
|
362 |
|
|
|
363 |
|
|
dffe_ns #(`UCB_INT_VEC_HI-`UCB_PKT_LO+1) int_buf_ff (.din(int_buf_in),
|
364 |
|
|
.en(int_buf_wr),
|
365 |
|
|
.clk(clk),
|
366 |
|
|
.q(int_buf));
|
367 |
|
|
|
368 |
|
|
assign int_buf_vec = {{REG_WIDTH/UCB_IOB_WIDTH{1'b0}},
|
369 |
|
|
{64/UCB_IOB_WIDTH{1'b1}}};
|
370 |
|
|
|
371 |
|
|
assign int_busy = int_buf_vld;
|
372 |
|
|
|
373 |
|
|
|
374 |
|
|
/************************************************************
|
375 |
|
|
* Outbound ack/interrupt Arbitration
|
376 |
|
|
************************************************************/
|
377 |
|
|
dffrle_ns #(1) int_last_rd_ff (.din(int_buf_rd),
|
378 |
|
|
.en(ack_buf_rd|int_buf_rd),
|
379 |
|
|
.rst_l(rst_l),
|
380 |
|
|
.clk(clk),
|
381 |
|
|
.q(int_last_rd));
|
382 |
|
|
|
383 |
|
|
assign ack_buf_rd = ~outdata_buf_busy & ack_buf_vld &
|
384 |
|
|
(~int_buf_vld | int_last_rd);
|
385 |
|
|
|
386 |
|
|
assign int_buf_rd = ~outdata_buf_busy & int_buf_vld &
|
387 |
|
|
(~ack_buf_vld | ~int_last_rd);
|
388 |
|
|
|
389 |
|
|
assign outdata_buf_wr = ack_buf_rd | int_buf_rd;
|
390 |
|
|
|
391 |
|
|
assign outdata_buf_in = ack_buf_rd ? {ack_buf[REG_WIDTH+`UCB_BUF_HI:`UCB_BUF_HI+1],
|
392 |
|
|
{(`UCB_RSV_HI-`UCB_RSV_LO+1){1'b0}},
|
393 |
|
|
{(`UCB_ADDR_HI-`UCB_ADDR_LO+1){1'b0}},
|
394 |
|
|
{(`UCB_SIZE_HI-`UCB_SIZE_LO+1){1'b0}},
|
395 |
|
|
ack_buf[`UCB_BUF_HI:`UCB_BUF_LO],
|
396 |
|
|
ack_buf[`UCB_THR_HI:`UCB_THR_LO],
|
397 |
|
|
ack_buf[`UCB_PKT_HI:`UCB_PKT_LO]}:
|
398 |
|
|
{{REG_WIDTH{1'b0}},
|
399 |
|
|
{(`UCB_INT_RSV_HI-`UCB_INT_RSV_LO+1){1'b0}},
|
400 |
|
|
int_buf[`UCB_INT_VEC_HI:`UCB_INT_VEC_LO],
|
401 |
|
|
int_buf[`UCB_INT_STAT_HI:`UCB_INT_STAT_LO],
|
402 |
|
|
int_buf[`UCB_INT_DEV_HI:`UCB_INT_DEV_LO],
|
403 |
|
|
int_buf[`UCB_THR_HI:`UCB_THR_LO],
|
404 |
|
|
int_buf[`UCB_PKT_HI:`UCB_PKT_LO]};
|
405 |
|
|
|
406 |
|
|
assign outdata_vec_in = ack_buf_rd ? ack_buf_vec :
|
407 |
|
|
int_buf_vec;
|
408 |
|
|
|
409 |
|
|
ucb_bus_out #(UCB_IOB_WIDTH, REG_WIDTH) ucb_bus_out (.rst_l(rst_l),
|
410 |
|
|
.clk(clk),
|
411 |
|
|
.outdata_buf_wr(outdata_buf_wr),
|
412 |
|
|
.outdata_buf_in(outdata_buf_in),
|
413 |
|
|
.outdata_vec_in(outdata_vec_in),
|
414 |
|
|
.outdata_buf_busy(outdata_buf_busy),
|
415 |
|
|
.vld(ucb_iob_vld),
|
416 |
|
|
.data(ucb_iob_data),
|
417 |
|
|
.stall(iob_ucb_stall));
|
418 |
|
|
|
419 |
|
|
|
420 |
|
|
`undef UCB_BUF_WIDTH
|
421 |
|
|
|
422 |
|
|
endmodule // ucb_flow_2buf
|
423 |
|
|
|
424 |
|
|
|
425 |
|
|
// Local Variables:
|
426 |
|
|
// verilog-library-directories:(".")
|
427 |
|
|
// End:
|
428 |
|
|
|
429 |
|
|
|
430 |
|
|
|
431 |
|
|
|
432 |
|
|
|
433 |
|
|
|
434 |
|
|
|