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[/] [sparc64soc/] [trunk/] [T1-common/] [include/] [tlu.h] - Blame information for rev 7

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/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T1 Processor File: tlu.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
// ifu trap types
`define INST_ACC_EXC    9'h008
`define INST_ACC_MMU_MS 9'h009
`define INST_ACC_ERR    9'h00a
`define ILL_INST        9'h010
`define PRIV_OPC        9'h011
`define FP_DISABLED     9'h020
`define DATA_ACC_EXC    9'h030
 
`define         MRA_TSB_PS0_HI      155
`define         MRA_TSB_PS0_LO      108
`define         MRA_TSB_PS1_HI      107
`define         MRA_TSB_PS1_LO      60
`define         MRA_TACCESS_HI  59
`define         MRA_TACCESS_LO  12
`define         MRA_CTXTCFG_HI    11
`define         MRA_CTXTCFG_LO    6
//
// modified for hypervisor support
//
`define TLU_THRD_NUM     4
`define TLU_TT_LO            0
`define TLU_TT_HI            8
`define TLU_CWP_LO           9
`define TLU_CWP_HI          11
`define TLU_PSTATE_LO   12
`define TLU_PSTATE_HI   19
`define TLU_ASI_LO          20
`define TLU_ASI_HI          27
`define TLU_CCR_LO          28
`define TLU_CCR_HI          35
`define TLU_GL_LO           36
`define TLU_GL_HI           37
`define TLU_NPC_LO          38
`define TLU_NPC_HI          84
`define TLU_PC_LO           85
`define TLU_PC_HI          131
`define TLU_HTSTATE_LO 132
`define TLU_HTSTATE_HI 135
`define TLU_RD_NPC_HI   83
`define TLU_RD_PC_LO    84
`define TLU_RD_PC_HI   129
`define TLU_RD_HTSTATE_LO 130
`define TLU_RD_HTSTATE_HI 133
//
`define TSA_PSTATE_VRANGE1_LO 12
`define TSA_PSTATE_VRANGE1_HI 15
// modified due to bug 2588
// `define      TSA_PSTATE_VRANGE2_LO 16
`define TSA_PSTATE_VRANGE2_LO 18
`define TSA_PSTATE_VRANGE2_HI 19
//
`define TLU_TSA_WIDTH     136
`define TLU_TDP_TSA_WIDTH 134
`define TSA_HTSTATE_WIDTH   4
`define TSA_GLOBAL_WIDTH    2
`define TSA_CCR_WIDTH       8
`define TSA_ASI_WIDTH       8
`define TSA_PSTATE_WIDTH    8
`define TSA_CWP_WIDTH       3
`define TSA_TTYPE_WIDTH     9
`define TLU_GLOBAL_WIDTH    4
`define TLU_HPSTATE_WIDTH   5
//
// added due to Niagara SRAMs methodology
// The following defines have been replaced due
// the memory macro replacement from:
// bw_r_rf32x144 -> 2x bw_r_rf32x80
/*
`define TSA_MEM_WIDTH     144
`define TSA_HTSTATE_HI    142 //  3 bits
`define TSA_HTSTATE_LO    140
`define TSA_TPC_HI        138 // 47 bits
`define TSA_TPC_LO         92
`define TSA_TNPC_HI        90 // 47 bits
`define TSA_TNPC_LO        44
`define TSA_TSTATE_HI      40 // 29 bits
`define TSA_TSTATE_LO      12
`define TSA_TTYPE_HI        8 //  9 bits
`define TSA_TTYPE_LO        0
`define TSA_MEM_CWP_LO     12
`define TSA_MEM_CWP_HI     14
`define TSA_MEM_PSTATE_LO  15
`define TSA_MEM_PSTATE_HI  22
`define TSA_MEM_ASI_LO     23
`define TSA_MEM_ASI_HI     30
`define TSA_MEM_CCR_LO     31
`define TSA_MEM_CCR_HI     38
`define TSA_MEM_GL_LO      39
`define TSA_MEM_GL_HI      40
*/
`define TSA_MEM_WIDTH   80
`define TSA1_HTSTATE_HI 63 //  4 bits
`define TSA1_HTSTATE_LO 60
`define TSA1_TNPC_HI    58 // 47 bits
`define TSA1_TNPC_LO    12
`define TSA1_TTYPE_HI    8 //  9 bits
`define TSA1_TTYPE_LO    0
`define TSA0_TPC_HI     78 // 47 bits
`define TSA0_TPC_LO     32
`define TSA0_TSTATE_HI  28 // 29 bits
`define TSA0_TSTATE_LO   0
//
`define TSA0_MEM_CWP_LO     0
`define TSA0_MEM_CWP_HI     2
`define TSA0_MEM_PSTATE_LO  3
`define TSA0_MEM_PSTATE_HI 10
`define TSA0_MEM_ASI_LO    11
`define TSA0_MEM_ASI_HI    18
`define TSA0_MEM_CCR_LO    19
`define TSA0_MEM_CCR_HI    26
`define TSA0_MEM_GL_LO     27
`define TSA0_MEM_GL_HI     28
 
// HPSTATE position definitions within wsr
`define WSR_HPSTATE_ENB  11
`define WSR_HPSTATE_IBE  10
`define WSR_HPSTATE_RED   5
`define WSR_HPSTATE_PRIV  2
`define WSR_HPSTATE_TLZ   0
 
// TSTATE postition definitions within wsr
`define WSR_TSTATE_GL_HI  41 // 2b
`define WSR_TSTATE_GL_LO  40
`define WSR_TSTATE_CCR_HI 39 // 8b
`define WSR_TSTATE_CCR_LO 32
`define WSR_TSTATE_ASI_HI 31 // 8b
`define WSR_TSTATE_ASI_LO 24
`define WSR_TSTATE_PS2_HI 17 // 4b
// modified due to bug 2588
`define WSR_TSTATE_PS2_LO  16
`define WSR_TSTATE_PS1_HI  12 // 4b
// added for bug 2584
`define WSR_TSTATE_PS_PRIV 10 // 4b
`define WSR_TSTATE_PS1_LO   9
`define WSR_TSTATE_CWP_HI   2 // 3b
`define WSR_TSTATE_CWP_LO   0
//
`define WSR_TSTATE_WIDTH   29
`define RDSR_TSTATE_WIDTH  48
`define RDSR_HPSTATE_WIDTH 12
`define TLU_ASR_DATA_WIDTH 64
`define TLU_ASR_ADDR_WIDTH  7
 
`define SFTINT_WIDTH     17
//
// tick_cmp and stick_cmp definitions
`define TICKCMP_RANGE_HI 60
`define TICKCMP_RANGE_LO  0
`define TICKCMP_INTDIS   63
`define SFTINT_TICK_CMP   0
`define SFTINT_STICK_CMP 16
//
// PIB WRAP
`define SFTINT_PIB_WRAP 15
`define PIB_OVERFLOW_TTYPE 7'h4f
 
// HPSTATE postition definitions
`define HPSTATE_IBE  4
`define HPSTATE_ENB  3
`define HPSTATE_RED  2
`define HPSTATE_PRIV 1
`define HPSTATE_TLZ  0
 
// HTBA definitions
`define TLU_HTBA_WIDTH  34 // supported physical width 
`define TLU_HTBA_HI     47
`define TLU_HTBA_LO     14
 
// TBA definitions
`define TLU_TBA_WIDTH  33 // supported physical width 
`define TLU_TBA_HI     47
`define TLU_TBA_LO     15
 
`define TPC              5'h0
`define TNPC     5'h1
`define TSTATE   5'h2
`define TT               5'h3
`define TICK     5'h4
`define TBA              5'h5
`define PSTATE   5'h6
`define TL               5'h7
`define PIL              5'h8
`define HPSTATE  5'h0
`define HTSTATE  5'h1
`define HINTP    5'h3
`define HTBA     5'h5
`define HTICKCMP 5'h1f
`define STICKCMP 5'h19
`define TICKCMP  5'h17
//
// added for the hypervisor support
`define PSTATE_VRANGE1_LO       1
`define PSTATE_VRANGE1_HI   4
// modified due to bug 2588
`define PSTATE_VRANGE2_LO       8
`define PSTATE_VRANGE2_HI   9
`define PSTATE_TRUE_WIDTH  12
 
`define PSTATE_AG        0
`define PSTATE_IE        1
`define PSTATE_PRIV  2
`define PSTATE_AM        3
`define PSTATE_PEF       4
`define PSTATE_RED       5
`define PSTATE_MM_LO 6
`define PSTATE_MM_HI 7
`define PSTATE_TLE       8
`define PSTATE_CLE       9
`define PSTATE_MG       10
`define PSTATE_IG       11
//
// compressed PSTATE WSR definitions
`define WSR_PSTATE_VRANGE1_LO   0
`define WSR_PSTATE_VR_PRIV      1
`define WSR_PSTATE_VRANGE1_HI   3
`define WSR_PSTATE_VRANGE2_LO   4
`define WSR_PSTATE_VRANGE2_HI   5
`define WSR_PSTATE_VR_WIDTH     6
 
`define MAXTL  3'b110
`define MAXTL_LESSONE 3'b101
`define MAXSTL 3'b010
`define MAXSTL_TL 3'b010 // Saturation point for GL and TL (supervisor) 
`define MAXSTL_GL 2'b10  // Saturation point for GL and TL (supervisor)
`define MAXGL  4'b0011   // Saturation point for GL (hypervisor)        
`define MAXGL_GL  2'b11  // Saturation point for GL (hypervisor)
//
// ASI_QUEUE for hypervisor
// Queues are: CPU_MONODO
//             DEV_MONODO
//             RESUMABLE_ERROR
//             NON_RESUMABLE_ERROR
//
`define        ASI_VA_WIDTH       48
`define        TLU_ASI_QUE_HI     13
`define        TLU_ASI_QUE_LO      6
`define        TLU_ASI_QUE_WIDTH   8
`define        TLU_ASI_VA_WIDTH   10
`define        TLU_ASI_STATE_WIDTH 8
 
// for address range checking
`define        TLU_ASI_QUE_VA_HI   9
`define        TLU_ASI_QUE_VA_LO   3
 
`define        TLU_ASI_QUE_ASI   8'h25
`define        CPU_MONDO_HEAD   10'h3c0
`define        CPU_MONDO_TAIL   10'h3c8
`define        DEV_MONDO_HEAD   10'h3d0
`define        DEV_MONDO_TAIL   10'h3d8
`define        RESUM_ERR_HEAD   10'h3e0
`define        RESUM_ERR_TAIL   10'h3e8
`define        NRESUM_ERR_HEAD  10'h3f0
`define        NRESUM_ERR_TAIL  10'h3f8
`define        CPU_MONDO_TRAP   7'h7c // only 7 bits are defined; upper two are 2'b00
`define        DEV_MONDO_TRAP   7'h7d // only 7 bits are defined; upper two are 2'b00
`define        TLZ_TRAP         7'h5f // only 7 bits are defined; upper two are 2'b00
`define        HWINT_INT        7'h60 // only 7 bits are defined; upper two are 2'b00
//
// Niagara scratch-pads
// VA address of 0x20 and 0x28 are exclusive to hypervisor
// 
`define        TLU_SCPD_DATA_WIDTH  64
`define        SCPD_RW_ADDR_WIDTH     5
`define        SCPD_ASI_VA_ADDR_WIDTH 3
 
`define        PRI_SCPD_ASI_STATE     8'h20
`define        SCPD_ASI_VA_ADDR_LO   10'h000
`define        SCPD_ASI_VA_ADDR_HI   10'h038
//
// range checking
`define        TLU_ASI_SCPD_VA_HI  5
`define        TLU_ASI_SCPD_VA_LO  3
 
`define        HPRI_SCPD_ASI_STATE    8'h4f
`define        HSCPD_ASI_VA_ADDR_LO   3'h4
`define        HSCPD_ASI_VA_ADDR_HI   3'h5
 
// PIB related definitions
// Bit definition for events
`define        PIB_INSTR_COUNT   3'bxxx
`define        PIB_SB_FULL_CNT   3'b000
`define        PIB_FP_INST_CNT   3'b001
`define        PIB_IC_MISS_CNT   3'b010
`define        PIB_DC_MISS_CNT   3'b011
`define        PIB_ITLB_MISS_CNT 3'b100
`define        PIB_DTLB_MISS_CNT 3'b101
`define        PIB_L2_IMISS_CNT  3'b110
`define        PIB_L2_DMISS_CNT  3'b111
//
// PIB related definitions
// PCR and PIC address definitions
`define        PCR_ASR_ADDR               7'b0010000
`define        PIC_ASR_PRIV_ADDR  7'b0110001
`define        PIC_ASR_NPRIV_ADDR 7'b0010001
// 
// PCR bit definitions
`define        WSR_PCR_PRIV   0 // PIC privilege 
`define        WSR_PCR_ST     1 // supervior trace 
`define        WSR_PCR_UT     2 // user trace 
`define        WSR_PCR_SL_LO  4 // PICL event mask 
`define        WSR_PCR_SL_HI  6 // 
`define        WSR_PCR_CL_OVF 8 // 
`define        WSR_PCR_CH_OVF 9 // 
//
`define        PIB_PCR_WIDTH  8
`define        PIB_PCR_PRIV   0 // PIC privilege 
`define        PIB_PCR_ST     1 // privilege event trace 
`define        PIB_PCR_UT     2 // user event trace 
`define        PIB_PCR_SL_LO  3 // PICL event encode 
`define        PIB_PCR_SL_HI  5 // 
`define        PIB_PCR_CL_OVF 6 // 
`define        PIB_PCR_CH_OVF 7 // 
 
// PIC definitions
`define        PIB_PIC_FULL_WIDTH 64
`define        PIB_PIC_CNT_WIDTH  33
`define        PIB_PIC_CNT_WRAP   32
`define        PIB_PICH_CNT_HI    63
`define        PIB_PICH_CNT_LO    32
`define        PIB_PICL_CNT_HI    31
`define        PIB_PICL_CNT_LO     0
`define        PIB_EVQ_CNT_WIDTH   3
// PIC  mask bit position definitions
`define        PICL_MASK_WIDTH     8
`define        PICL_MASK_SB_FULL   0
`define        PICL_MASK_FP_INST   1
`define        PICL_MASK_IC_MISS   2
`define        PICL_MASK_DC_MISS   3
`define        PICL_MASK_ITLB_MISS 4
`define        PICL_MASK_DTLB_MISS 5
`define        PICL_MASK_L2_IMISS  6
`define        PICL_MASK_L2_DMISS  7
 
// added define from sparc_tlu_int.v 
`define INT_THR_HI  12
`define INT_VEC_HI 5
`define INT_VEC_LO 0
`define INT_THR_HI  12
`define INT_THR_LO   8
`define INT_TYPE_HI 17
`define INT_TYPE_LO 16
`define TLU_INRR_ASI 8'h72
`define TLU_INDR_ASI 8'h73
`define TLU_INVR_ASI 8'h74
//
// shadow scan related definitions
`define TLU_SSCAN_WIDTH 63
// modified due to logic redistribution
// `define TCL_SSCAN_WIDTH 12
`define TCL_SSCAN_WIDTH 3
`define MISCTL_SSCAN_WIDTH 9
`define TDP_SSCAN_WIDTH 51
`define TDP_SSCAN_LO  0
`define TDP_SSCAN_HI 50
// `define TCL_SSCAN_LO 51
`define MISCTL_SSCAN_LO 51
`define MISCTL_SSCAN_HI 59
`define TCL_SSCAN_LO 60
`define TCL_SSCAN_HI 62
//
// position definitions - TDP
`define TDP_SSCAN_PC_LO    0
`define TDP_SSCAN_PC_HI   45
`define TDP_SSCAN_PS_IE   46
`define TDP_SSCAN_PS_PRIV 47
`define TDP_SSCAN_HPS_LO  48
`define TDP_SSCAN_HPS_HI  50
//
// position definitions - TCL
`define TCL_SSCAN_TT_LO    0
`define TCL_SSCAN_TT_HI    8
`define TCL_SSCAN_TL_LO    9
`define TCL_SSCAN_TL_HI   11
//
// To speedup POR for verification purposes
`define RSTVADDR_BASE 34'h3_ffff_c000

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[/] [sparc64soc/] [trunk/] [T1-common/] [include/] [tlu.h] - Blame information for rev 7

Line No.	Rev	Author	Line
1	2	dmitryr	`/*`
2			`* ========== Copyright Header Begin ==========================================`
3			`*`
4			`* OpenSPARC T1 Processor File: tlu.h`
5			`* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.`
6			`* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.`
7			`*`
8			`* The above named program is free software; you can redistribute it and/or`
9			`* modify it under the terms of the GNU General Public`
10			`* License version 2 as published by the Free Software Foundation.`
11			`*`
12			`* The above named program is distributed in the hope that it will be`
13			`* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
15			`* General Public License for more details.`
16			`*`
17			`* You should have received a copy of the GNU General Public`
18			`* License along with this work; if not, write to the Free Software`
19			`* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.`
20			`*`
21			`* ========== Copyright Header End ============================================`
22			`*/`
23			`// ifu trap types`
24			`define INST_ACC_EXC 9'h008
25			`define INST_ACC_MMU_MS 9'h009
26			`define INST_ACC_ERR 9'h00a
27			`define ILL_INST 9'h010
28			`define PRIV_OPC 9'h011
29			`define FP_DISABLED 9'h020
30			`define DATA_ACC_EXC 9'h030
31
32			`define MRA_TSB_PS0_HI 155
33			`define MRA_TSB_PS0_LO 108
34			`define MRA_TSB_PS1_HI 107
35			`define MRA_TSB_PS1_LO 60
36			`define MRA_TACCESS_HI 59
37			`define MRA_TACCESS_LO 12
38			`define MRA_CTXTCFG_HI 11
39			`define MRA_CTXTCFG_LO 6
40			`//`
41			`// modified for hypervisor support`
42			`//`
43			`define TLU_THRD_NUM 4
44			`define TLU_TT_LO 0
45			`define TLU_TT_HI 8
46			`define TLU_CWP_LO 9
47			`define TLU_CWP_HI 11
48			`define TLU_PSTATE_LO 12
49			`define TLU_PSTATE_HI 19
50			`define TLU_ASI_LO 20
51			`define TLU_ASI_HI 27
52			`define TLU_CCR_LO 28
53			`define TLU_CCR_HI 35
54			`define TLU_GL_LO 36
55			`define TLU_GL_HI 37
56			`define TLU_NPC_LO 38
57			`define TLU_NPC_HI 84
58			`define TLU_PC_LO 85
59			`define TLU_PC_HI 131
60			`define TLU_HTSTATE_LO 132
61			`define TLU_HTSTATE_HI 135
62			`define TLU_RD_NPC_HI 83
63			`define TLU_RD_PC_LO 84
64			`define TLU_RD_PC_HI 129
65			`define TLU_RD_HTSTATE_LO 130
66			`define TLU_RD_HTSTATE_HI 133
67			`//`
68			`define TSA_PSTATE_VRANGE1_LO 12
69			`define TSA_PSTATE_VRANGE1_HI 15
70			`// modified due to bug 2588`
71			// `define TSA_PSTATE_VRANGE2_LO 16
72			`define TSA_PSTATE_VRANGE2_LO 18
73			`define TSA_PSTATE_VRANGE2_HI 19
74			`//`
75			`define TLU_TSA_WIDTH 136
76			`define TLU_TDP_TSA_WIDTH 134
77			`define TSA_HTSTATE_WIDTH 4
78			`define TSA_GLOBAL_WIDTH 2
79			`define TSA_CCR_WIDTH 8
80			`define TSA_ASI_WIDTH 8
81			`define TSA_PSTATE_WIDTH 8
82			`define TSA_CWP_WIDTH 3
83			`define TSA_TTYPE_WIDTH 9
84			`define TLU_GLOBAL_WIDTH 4
85			`define TLU_HPSTATE_WIDTH 5
86			`//`
87			`// added due to Niagara SRAMs methodology`
88			`// The following defines have been replaced due`
89			`// the memory macro replacement from:`
90			`// bw_r_rf32x144 -> 2x bw_r_rf32x80`
91			`/*`
92			`define TSA_MEM_WIDTH 144
93			`define TSA_HTSTATE_HI 142 // 3 bits
94			`define TSA_HTSTATE_LO 140
95			`define TSA_TPC_HI 138 // 47 bits
96			`define TSA_TPC_LO 92
97			`define TSA_TNPC_HI 90 // 47 bits
98			`define TSA_TNPC_LO 44
99			`define TSA_TSTATE_HI 40 // 29 bits
100			`define TSA_TSTATE_LO 12
101			`define TSA_TTYPE_HI 8 // 9 bits
102			`define TSA_TTYPE_LO 0
103			`define TSA_MEM_CWP_LO 12
104			`define TSA_MEM_CWP_HI 14
105			`define TSA_MEM_PSTATE_LO 15
106			`define TSA_MEM_PSTATE_HI 22
107			`define TSA_MEM_ASI_LO 23
108			`define TSA_MEM_ASI_HI 30
109			`define TSA_MEM_CCR_LO 31
110			`define TSA_MEM_CCR_HI 38
111			`define TSA_MEM_GL_LO 39
112			`define TSA_MEM_GL_HI 40
113			`*/`
114			`define TSA_MEM_WIDTH 80
115			`define TSA1_HTSTATE_HI 63 // 4 bits
116			`define TSA1_HTSTATE_LO 60
117			`define TSA1_TNPC_HI 58 // 47 bits
118			`define TSA1_TNPC_LO 12
119			`define TSA1_TTYPE_HI 8 // 9 bits
120			`define TSA1_TTYPE_LO 0
121			`define TSA0_TPC_HI 78 // 47 bits
122			`define TSA0_TPC_LO 32
123			`define TSA0_TSTATE_HI 28 // 29 bits
124			`define TSA0_TSTATE_LO 0
125			`//`
126			`define TSA0_MEM_CWP_LO 0
127			`define TSA0_MEM_CWP_HI 2
128			`define TSA0_MEM_PSTATE_LO 3
129			`define TSA0_MEM_PSTATE_HI 10
130			`define TSA0_MEM_ASI_LO 11
131			`define TSA0_MEM_ASI_HI 18
132			`define TSA0_MEM_CCR_LO 19
133			`define TSA0_MEM_CCR_HI 26
134			`define TSA0_MEM_GL_LO 27
135			`define TSA0_MEM_GL_HI 28
136
137			`// HPSTATE position definitions within wsr`
138			`define WSR_HPSTATE_ENB 11
139			`define WSR_HPSTATE_IBE 10
140			`define WSR_HPSTATE_RED 5
141			`define WSR_HPSTATE_PRIV 2
142			`define WSR_HPSTATE_TLZ 0
143
144			`// TSTATE postition definitions within wsr`
145			`define WSR_TSTATE_GL_HI 41 // 2b
146			`define WSR_TSTATE_GL_LO 40
147			`define WSR_TSTATE_CCR_HI 39 // 8b
148			`define WSR_TSTATE_CCR_LO 32
149			`define WSR_TSTATE_ASI_HI 31 // 8b
150			`define WSR_TSTATE_ASI_LO 24
151			`define WSR_TSTATE_PS2_HI 17 // 4b
152			`// modified due to bug 2588`
153			`define WSR_TSTATE_PS2_LO 16
154			`define WSR_TSTATE_PS1_HI 12 // 4b
155			`// added for bug 2584`
156			`define WSR_TSTATE_PS_PRIV 10 // 4b
157			`define WSR_TSTATE_PS1_LO 9
158			`define WSR_TSTATE_CWP_HI 2 // 3b
159			`define WSR_TSTATE_CWP_LO 0
160			`//`
161			`define WSR_TSTATE_WIDTH 29
162			`define RDSR_TSTATE_WIDTH 48
163			`define RDSR_HPSTATE_WIDTH 12
164			`define TLU_ASR_DATA_WIDTH 64
165			`define TLU_ASR_ADDR_WIDTH 7
166
167			`define SFTINT_WIDTH 17
168			`//`
169			`// tick_cmp and stick_cmp definitions`
170			`define TICKCMP_RANGE_HI 60
171			`define TICKCMP_RANGE_LO 0
172			`define TICKCMP_INTDIS 63
173			`define SFTINT_TICK_CMP 0
174			`define SFTINT_STICK_CMP 16
175			`//`
176			`// PIB WRAP`
177			`define SFTINT_PIB_WRAP 15
178			`define PIB_OVERFLOW_TTYPE 7'h4f
179
180			`// HPSTATE postition definitions`
181			`define HPSTATE_IBE 4
182			`define HPSTATE_ENB 3
183			`define HPSTATE_RED 2
184			`define HPSTATE_PRIV 1
185			`define HPSTATE_TLZ 0
186
187			`// HTBA definitions`
188			`define TLU_HTBA_WIDTH 34 // supported physical width
189			`define TLU_HTBA_HI 47
190			`define TLU_HTBA_LO 14
191
192			`// TBA definitions`
193			`define TLU_TBA_WIDTH 33 // supported physical width
194			`define TLU_TBA_HI 47
195			`define TLU_TBA_LO 15
196
197			`define TPC 5'h0
198			`define TNPC 5'h1
199			`define TSTATE 5'h2
200			`define TT 5'h3
201			`define TICK 5'h4
202			`define TBA 5'h5
203			`define PSTATE 5'h6
204			`define TL 5'h7
205			`define PIL 5'h8
206			`define HPSTATE 5'h0
207			`define HTSTATE 5'h1
208			`define HINTP 5'h3
209			`define HTBA 5'h5
210			`define HTICKCMP 5'h1f
211			`define STICKCMP 5'h19
212			`define TICKCMP 5'h17
213			`//`
214			`// added for the hypervisor support`
215			`define PSTATE_VRANGE1_LO 1
216			`define PSTATE_VRANGE1_HI 4
217			`// modified due to bug 2588`
218			`define PSTATE_VRANGE2_LO 8
219			`define PSTATE_VRANGE2_HI 9
220			`define PSTATE_TRUE_WIDTH 12
221
222			`define PSTATE_AG 0
223			`define PSTATE_IE 1
224			`define PSTATE_PRIV 2
225			`define PSTATE_AM 3
226			`define PSTATE_PEF 4
227			`define PSTATE_RED 5
228			`define PSTATE_MM_LO 6
229			`define PSTATE_MM_HI 7
230			`define PSTATE_TLE 8
231			`define PSTATE_CLE 9
232			`define PSTATE_MG 10
233			`define PSTATE_IG 11
234			`//`
235			`// compressed PSTATE WSR definitions`
236			`define WSR_PSTATE_VRANGE1_LO 0
237			`define WSR_PSTATE_VR_PRIV 1
238			`define WSR_PSTATE_VRANGE1_HI 3
239			`define WSR_PSTATE_VRANGE2_LO 4
240			`define WSR_PSTATE_VRANGE2_HI 5
241			`define WSR_PSTATE_VR_WIDTH 6
242
243			`define MAXTL 3'b110
244			`define MAXTL_LESSONE 3'b101
245			`define MAXSTL 3'b010
246			`define MAXSTL_TL 3'b010 // Saturation point for GL and TL (supervisor)
247			`define MAXSTL_GL 2'b10 // Saturation point for GL and TL (supervisor)
248			`define MAXGL 4'b0011 // Saturation point for GL (hypervisor)
249			`define MAXGL_GL 2'b11 // Saturation point for GL (hypervisor)
250			`//`
251			`// ASI_QUEUE for hypervisor`
252			`// Queues are: CPU_MONODO`
253			`// DEV_MONODO`
254			`// RESUMABLE_ERROR`
255			`// NON_RESUMABLE_ERROR`
256			`//`
257			`define ASI_VA_WIDTH 48
258			`define TLU_ASI_QUE_HI 13
259			`define TLU_ASI_QUE_LO 6
260			`define TLU_ASI_QUE_WIDTH 8
261			`define TLU_ASI_VA_WIDTH 10
262			`define TLU_ASI_STATE_WIDTH 8
263
264			`// for address range checking`
265			`define TLU_ASI_QUE_VA_HI 9
266			`define TLU_ASI_QUE_VA_LO 3
267
268			`define TLU_ASI_QUE_ASI 8'h25
269			`define CPU_MONDO_HEAD 10'h3c0
270			`define CPU_MONDO_TAIL 10'h3c8
271			`define DEV_MONDO_HEAD 10'h3d0
272			`define DEV_MONDO_TAIL 10'h3d8
273			`define RESUM_ERR_HEAD 10'h3e0
274			`define RESUM_ERR_TAIL 10'h3e8
275			`define NRESUM_ERR_HEAD 10'h3f0
276			`define NRESUM_ERR_TAIL 10'h3f8
277			`define CPU_MONDO_TRAP 7'h7c // only 7 bits are defined; upper two are 2'b00
278			`define DEV_MONDO_TRAP 7'h7d // only 7 bits are defined; upper two are 2'b00
279			`define TLZ_TRAP 7'h5f // only 7 bits are defined; upper two are 2'b00
280			`define HWINT_INT 7'h60 // only 7 bits are defined; upper two are 2'b00
281			`//`
282			`// Niagara scratch-pads`
283			`// VA address of 0x20 and 0x28 are exclusive to hypervisor`
284			`//`
285			`define TLU_SCPD_DATA_WIDTH 64
286			`define SCPD_RW_ADDR_WIDTH 5
287			`define SCPD_ASI_VA_ADDR_WIDTH 3
288
289			`define PRI_SCPD_ASI_STATE 8'h20
290			`define SCPD_ASI_VA_ADDR_LO 10'h000
291			`define SCPD_ASI_VA_ADDR_HI 10'h038
292			`//`
293			`// range checking`
294			`define TLU_ASI_SCPD_VA_HI 5
295			`define TLU_ASI_SCPD_VA_LO 3
296
297			`define HPRI_SCPD_ASI_STATE 8'h4f
298			`define HSCPD_ASI_VA_ADDR_LO 3'h4
299			`define HSCPD_ASI_VA_ADDR_HI 3'h5
300
301			`// PIB related definitions`
302			`// Bit definition for events`
303			`define PIB_INSTR_COUNT 3'bxxx
304			`define PIB_SB_FULL_CNT 3'b000
305			`define PIB_FP_INST_CNT 3'b001
306			`define PIB_IC_MISS_CNT 3'b010
307			`define PIB_DC_MISS_CNT 3'b011
308			`define PIB_ITLB_MISS_CNT 3'b100
309			`define PIB_DTLB_MISS_CNT 3'b101
310			`define PIB_L2_IMISS_CNT 3'b110
311			`define PIB_L2_DMISS_CNT 3'b111
312			`//`
313			`// PIB related definitions`
314			`// PCR and PIC address definitions`
315			`define PCR_ASR_ADDR 7'b0010000
316			`define PIC_ASR_PRIV_ADDR 7'b0110001
317			`define PIC_ASR_NPRIV_ADDR 7'b0010001
318			`//`
319			`// PCR bit definitions`
320			`define WSR_PCR_PRIV 0 // PIC privilege
321			`define WSR_PCR_ST 1 // supervior trace
322			`define WSR_PCR_UT 2 // user trace
323			`define WSR_PCR_SL_LO 4 // PICL event mask
324			`define WSR_PCR_SL_HI 6 //
325			`define WSR_PCR_CL_OVF 8 //
326			`define WSR_PCR_CH_OVF 9 //
327			`//`
328			`define PIB_PCR_WIDTH 8
329			`define PIB_PCR_PRIV 0 // PIC privilege
330			`define PIB_PCR_ST 1 // privilege event trace
331			`define PIB_PCR_UT 2 // user event trace
332			`define PIB_PCR_SL_LO 3 // PICL event encode
333			`define PIB_PCR_SL_HI 5 //
334			`define PIB_PCR_CL_OVF 6 //
335			`define PIB_PCR_CH_OVF 7 //
336
337			`// PIC definitions`
338			`define PIB_PIC_FULL_WIDTH 64
339			`define PIB_PIC_CNT_WIDTH 33
340			`define PIB_PIC_CNT_WRAP 32
341			`define PIB_PICH_CNT_HI 63
342			`define PIB_PICH_CNT_LO 32
343			`define PIB_PICL_CNT_HI 31
344			`define PIB_PICL_CNT_LO 0
345			`define PIB_EVQ_CNT_WIDTH 3
346			`// PIC mask bit position definitions`
347			`define PICL_MASK_WIDTH 8
348			`define PICL_MASK_SB_FULL 0
349			`define PICL_MASK_FP_INST 1
350			`define PICL_MASK_IC_MISS 2
351			`define PICL_MASK_DC_MISS 3
352			`define PICL_MASK_ITLB_MISS 4
353			`define PICL_MASK_DTLB_MISS 5
354			`define PICL_MASK_L2_IMISS 6
355			`define PICL_MASK_L2_DMISS 7
356
357			`// added define from sparc_tlu_int.v`
358			`define INT_THR_HI 12
359			`define INT_VEC_HI 5
360			`define INT_VEC_LO 0
361			`define INT_THR_HI 12
362			`define INT_THR_LO 8
363			`define INT_TYPE_HI 17
364			`define INT_TYPE_LO 16
365			`define TLU_INRR_ASI 8'h72
366			`define TLU_INDR_ASI 8'h73
367			`define TLU_INVR_ASI 8'h74
368			`//`
369			`// shadow scan related definitions`
370			`define TLU_SSCAN_WIDTH 63
371			`// modified due to logic redistribution`
372			// `define TCL_SSCAN_WIDTH 12
373			`define TCL_SSCAN_WIDTH 3
374			`define MISCTL_SSCAN_WIDTH 9
375			`define TDP_SSCAN_WIDTH 51
376			`define TDP_SSCAN_LO 0
377			`define TDP_SSCAN_HI 50
378			// `define TCL_SSCAN_LO 51
379			`define MISCTL_SSCAN_LO 51
380			`define MISCTL_SSCAN_HI 59
381			`define TCL_SSCAN_LO 60
382			`define TCL_SSCAN_HI 62
383			`//`
384			`// position definitions - TDP`
385			`define TDP_SSCAN_PC_LO 0
386			`define TDP_SSCAN_PC_HI 45
387			`define TDP_SSCAN_PS_IE 46
388			`define TDP_SSCAN_PS_PRIV 47
389			`define TDP_SSCAN_HPS_LO 48
390			`define TDP_SSCAN_HPS_HI 50
391			`//`
392			`// position definitions - TCL`
393			`define TCL_SSCAN_TT_LO 0
394			`define TCL_SSCAN_TT_HI 8
395			`define TCL_SSCAN_TL_LO 9
396			`define TCL_SSCAN_TL_HI 11
397			`//`
398			`// To speedup POR for verification purposes`
399			`define RSTVADDR_BASE 34'h3_ffff_c000