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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: bw_r_icd.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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////////////////////////////////////////////////////////////////////////
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/*
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// Module Name: bw_r_icd
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// Description:
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// The ICD contains the icache data.
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// 32B line size.
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// Write BW: 16B
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// Read BW: 16Bx2 (fetdata and topdata), collapsed to 4Bx2
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// Associativity: 4
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// Write boundary: 34b (32b inst + parity + predec bit)
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// NOTES:
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// 1. No clock enable. Rd/Wr enable is used to trigger the
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// operation.
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// 2. 2:1 mux on address input. Selects provided externally.
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// 3. 3:1 mux on data input. Selects provided and guaranteed
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// exclusive, externally.
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//
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*/
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////////////////////////////////////////////////////////////////////////
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// Global header file includes
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////////////////////////////////////////////////////////////////////////
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//`include "sys.h" // system level definition file which contains the
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// time scale definition
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////////////////////////////////////////////////////////////////////////
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// Local header file includes / local defines
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////////////////////////////////////////////////////////////////////////
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`include "ifu.h"
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//FPGA_SYN enables all FPGA related modifications
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`ifdef FPGA_SYN
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`define FPGA_SYN_ICD
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`endif
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`ifdef FPGA_SYN_ICD
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module bw_r_icd(icd_wsel_fetdata_s1, icd_wsel_topdata_s1, icd_fuse_repair_value,
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icd_fuse_repair_en, so, rclk, se, si, reset_l, sehold, fdp_icd_index_bf,
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ifq_icd_index_bf, fcl_icd_index_sel_ifq_bf, ifq_icd_wrway_bf,
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ifq_icd_worden_bf, ifq_icd_wrdata_i2, fcl_icd_rdreq_bf,
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fcl_icd_wrreq_bf, bist_ic_data, rst_tri_en, ifq_icd_data_sel_old_i2,
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ifq_icd_data_sel_fill_i2, ifq_icd_data_sel_bist_i2, fuse_icd_wren,
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fuse_icd_rid, fuse_icd_repair_value, fuse_icd_repair_en,
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efc_spc_fuse_clk1);
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input rclk;
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input se;
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input si;
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input reset_l;
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input sehold;
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input [11:2] fdp_icd_index_bf;
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input [11:2] ifq_icd_index_bf;
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input fcl_icd_index_sel_ifq_bf;
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input [1:0] ifq_icd_wrway_bf;
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input [3:0] ifq_icd_worden_bf;
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input [135:0] ifq_icd_wrdata_i2;
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input fcl_icd_rdreq_bf;
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input fcl_icd_wrreq_bf;
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input [7:0] bist_ic_data;
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input rst_tri_en;
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input ifq_icd_data_sel_old_i2;
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input ifq_icd_data_sel_fill_i2;
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input ifq_icd_data_sel_bist_i2;
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input fuse_icd_wren;
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input [3:0] fuse_icd_rid;
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input [7:0] fuse_icd_repair_value;
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input [1:0] fuse_icd_repair_en;
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input efc_spc_fuse_clk1;
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output [135:0] icd_wsel_fetdata_s1;
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output [135:0] icd_wsel_topdata_s1;
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output [7:0] icd_fuse_repair_value;
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output [1:0] icd_fuse_repair_en;
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output so;
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reg [7:0] icd_fuse_repair_value;
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reg [1:0] icd_fuse_repair_en;
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reg [135:0] fetdata_f;
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reg [135:0] topdata_f;
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reg [135:0] fetdata_sa;
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reg [135:0] topdata_sa;
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reg [135:0] fetdata_s1;
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reg [135:0] topdata_s1;
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wire clk;
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wire [135:0] next_wrdata_bf;
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wire [135:0] wrdata_f;
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wire [135:0] bist_data_expand;
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`ifdef FPGA_SYN_ALTERA
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reg [11:2] index_bf;
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`else
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wire [11:2] index_bf;
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`endif
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reg [11:2] index_f;
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reg [11:0] wr_index0;
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reg [11:0] wr_index1;
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reg [11:0] wr_index2;
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reg [11:0] wr_index3;
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reg rdreq_f;
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reg wrreq_f;
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reg [3:0] worden_f;
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reg [1:0] wrway_f;
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`ifdef FPGA_SYN_ALTERA
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reg [33:0] icdata_ary_00_00 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
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reg [33:0] icdata_ary_00_01 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
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reg [33:0] icdata_ary_00_10 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
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reg [33:0] icdata_ary_00_11 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
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reg [33:0] icdata_ary_01_00 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
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reg [33:0] icdata_ary_01_01 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
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reg [33:0] icdata_ary_01_10 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
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reg [33:0] icdata_ary_01_11 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
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reg [33:0] icdata_ary_10_00 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
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reg [33:0] icdata_ary_10_01 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
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reg [33:0] icdata_ary_10_10 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
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reg [33:0] icdata_ary_10_11 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
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reg [33:0] icdata_ary_11_00 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
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reg [33:0] icdata_ary_11_01 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
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reg [33:0] icdata_ary_11_10 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
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reg [33:0] icdata_ary_11_11 [255:0] /* synthesis syn_ramstyle = block_ram */ ;/* syn_ramstyle = no_rw_check */
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`else
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reg [33:0] icdata_ary_00_00 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
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reg [33:0] icdata_ary_00_01 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
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reg [33:0] icdata_ary_00_10 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
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reg [33:0] icdata_ary_00_11 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
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reg [33:0] icdata_ary_01_00 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
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reg [33:0] icdata_ary_01_01 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
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reg [33:0] icdata_ary_01_10 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
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reg [33:0] icdata_ary_01_11 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
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reg [33:0] icdata_ary_10_00 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
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reg [33:0] icdata_ary_10_01 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
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reg [33:0] icdata_ary_10_10 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
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reg [33:0] icdata_ary_10_11 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
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reg [33:0] icdata_ary_11_00 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
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reg [33:0] icdata_ary_11_01 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
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reg [33:0] icdata_ary_11_10 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
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reg [33:0] icdata_ary_11_11 [255:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
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`endif
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assign clk = rclk;
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`ifdef FPGA_SYN_ALTERA
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`else
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assign index_bf = (fcl_icd_index_sel_ifq_bf ? ifq_icd_index_bf :
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fdp_icd_index_bf);
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`endif
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// assign index_bf = (fcl_icd_index_sel_ifq_bf ? ifq_icd_index_bf :
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// fdp_icd_index_bf);
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wire [11:2] top_index = {index_f[11:3] , 1'b1};
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assign bist_data_expand = 136'b0;
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assign icd_wsel_fetdata_s1 = fetdata_s1;
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assign icd_wsel_topdata_s1 = topdata_s1;
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mux3ds #(136) icden_mux(
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.dout (next_wrdata_bf),
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.in0 (wrdata_f),
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.in1 (ifq_icd_wrdata_i2),
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.in2 (bist_data_expand),
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.sel0 (ifq_icd_data_sel_old_i2),
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.sel1 (ifq_icd_data_sel_fill_i2),
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.sel2 (ifq_icd_data_sel_bist_i2));
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dffe_s #(136) wrdata_reg(
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.din (next_wrdata_bf),
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.clk (clk),
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.q (wrdata_f),
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.en ((~sehold)),
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.se (se));
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always @(posedge clk) begin
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if (~sehold) begin
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rdreq_f <= fcl_icd_rdreq_bf;
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wrreq_f <= fcl_icd_wrreq_bf;
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`ifdef FPGA_SYN_ALTERA
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`else
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index_f <= index_bf;
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`endif
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wrway_f <= ifq_icd_wrway_bf;
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worden_f <= ifq_icd_worden_bf;
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wr_index0 <= {index_bf[11:4], 2'b0, ifq_icd_wrway_bf};
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wr_index1 <= {index_bf[11:4], 2'b1, ifq_icd_wrway_bf};
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wr_index2 <= {index_bf[11:4], 2'b10, ifq_icd_wrway_bf};
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wr_index3 <= {index_bf[11:4], 2'b11, ifq_icd_wrway_bf};
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end
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fetdata_s1 <= fetdata_f;
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topdata_s1 <= topdata_f;
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end
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reg [33:0] fetch_00_00;
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reg [33:0] fetch_00_01;
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reg [33:0] fetch_00_10;
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reg [33:0] fetch_00_11;
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reg [33:0] fetch_01_00;
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reg [33:0] fetch_01_01;
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reg [33:0] fetch_01_10;
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reg [33:0] fetch_01_11;
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reg [33:0] fetch_10_00;
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reg [33:0] fetch_10_01;
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reg [33:0] fetch_10_10;
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reg [33:0] fetch_10_11;
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reg [33:0] fetch_11_00;
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reg [33:0] fetch_11_01;
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reg [33:0] fetch_11_10;
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reg [33:0] fetch_11_11;
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`ifdef FPGA_SYN_ALTERA
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reg [33:0] fetch_00_00_d;
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reg [33:0] fetch_00_01_d;
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reg [33:0] fetch_00_10_d;
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reg [33:0] fetch_00_11_d;
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reg [33:0] fetch_01_00_d;
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reg [33:0] fetch_01_01_d;
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reg [33:0] fetch_01_10_d;
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reg [33:0] fetch_01_11_d;
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reg [33:0] fetch_10_00_d;
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reg [33:0] fetch_10_01_d;
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reg [33:0] fetch_10_10_d;
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reg [33:0] fetch_10_11_d;
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reg [33:0] fetch_11_00_d;
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reg [33:0] fetch_11_01_d;
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reg [33:0] fetch_11_10_d;
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reg [33:0] fetch_11_11_d;
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reg delay_half_cycle;
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always @(negedge clk) begin // Sandeep Changed this to negedge clock from posedge clock
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// Can we push the reads to the next negedge? Delay this read!! Looks
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// like the previous write does not get through
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`else
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always @(posedge clk) begin
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`endif
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fetch_00_00 <= icdata_ary_00_00[index_bf[11:4]];
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fetch_00_01 <= icdata_ary_00_01[index_bf[11:4]];
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fetch_00_10 <= icdata_ary_00_10[index_bf[11:4]];
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fetch_00_11 <= icdata_ary_00_11[index_bf[11:4]];
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fetch_01_00 <= icdata_ary_01_00[index_bf[11:4]];
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fetch_01_01 <= icdata_ary_01_01[index_bf[11:4]];
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|
|
fetch_01_10 <= icdata_ary_01_10[index_bf[11:4]];
|
| 272 |
|
|
fetch_01_11 <= icdata_ary_01_11[index_bf[11:4]];
|
| 273 |
|
|
|
| 274 |
|
|
fetch_10_00 <= icdata_ary_10_00[index_bf[11:4]];
|
| 275 |
|
|
fetch_10_01 <= icdata_ary_10_01[index_bf[11:4]];
|
| 276 |
|
|
fetch_10_10 <= icdata_ary_10_10[index_bf[11:4]];
|
| 277 |
|
|
fetch_10_11 <= icdata_ary_10_11[index_bf[11:4]];
|
| 278 |
|
|
|
| 279 |
|
|
fetch_11_00 <= icdata_ary_11_00[index_bf[11:4]];
|
| 280 |
|
|
fetch_11_01 <= icdata_ary_11_01[index_bf[11:4]];
|
| 281 |
|
|
fetch_11_10 <= icdata_ary_11_10[index_bf[11:4]];
|
| 282 |
|
|
fetch_11_11 <= icdata_ary_11_11[index_bf[11:4]];
|
| 283 |
|
|
`ifdef FPGA_SYN_ALTERA
|
| 284 |
|
|
index_f <= index_bf; // Sandeep moved this logic 1/2 cycle forward for altera
|
| 285 |
|
|
index_bf <= (fcl_icd_index_sel_ifq_bf ? ifq_icd_index_bf : // Moved this logic from a continuous assignment to a synchronous assignment
|
| 286 |
|
|
fdp_icd_index_bf);
|
| 287 |
|
|
`endif
|
| 288 |
|
|
end
|
| 289 |
|
|
|
| 290 |
|
|
|
| 291 |
|
|
always @(index_f or rdreq_f or fetch_00_00 or fetch_01_00 or fetch_10_00 or fetch_11_00
|
| 292 |
|
|
or fetch_00_01 or fetch_01_01 or fetch_10_01 or fetch_11_01
|
| 293 |
|
|
or fetch_00_10 or fetch_01_10 or fetch_10_10 or fetch_11_10
|
| 294 |
|
|
or fetch_00_11 or fetch_01_11 or fetch_10_11 or fetch_11_11) begin
|
| 295 |
|
|
// if (rdreq_f) begin
|
| 296 |
|
|
case(index_f[3:2])
|
| 297 |
|
|
2'b00: fetdata_f[33:0] = fetch_00_00;
|
| 298 |
|
|
2'b01: fetdata_f[33:0] = fetch_01_00;
|
| 299 |
|
|
2'b10: fetdata_f[33:0] = fetch_10_00;
|
| 300 |
|
|
2'b11: fetdata_f[33:0] = fetch_11_00;
|
| 301 |
|
|
endcase
|
| 302 |
|
|
case(index_f[3:2])
|
| 303 |
|
|
2'b00: fetdata_f[67:34] = fetch_00_01;
|
| 304 |
|
|
2'b01: fetdata_f[67:34] = fetch_01_01;
|
| 305 |
|
|
2'b10: fetdata_f[67:34] = fetch_10_01;
|
| 306 |
|
|
2'b11: fetdata_f[67:34] = fetch_11_01;
|
| 307 |
|
|
endcase
|
| 308 |
|
|
case(index_f[3:2])
|
| 309 |
|
|
2'b00: fetdata_f[101:68] = fetch_00_10;
|
| 310 |
|
|
2'b01: fetdata_f[101:68] = fetch_01_10;
|
| 311 |
|
|
2'b10: fetdata_f[101:68] = fetch_10_10;
|
| 312 |
|
|
2'b11: fetdata_f[101:68] = fetch_11_10;
|
| 313 |
|
|
endcase
|
| 314 |
|
|
case(index_f[3:2])
|
| 315 |
|
|
2'b00: fetdata_f[135:102] = fetch_00_11;
|
| 316 |
|
|
2'b01: fetdata_f[135:102] = fetch_01_11;
|
| 317 |
|
|
2'b10: fetdata_f[135:102] = fetch_10_11;
|
| 318 |
|
|
2'b11: fetdata_f[135:102] = fetch_11_11;
|
| 319 |
|
|
endcase
|
| 320 |
|
|
case(index_f[3])
|
| 321 |
|
|
1'b0: topdata_f[33:0] = fetch_01_00;
|
| 322 |
|
|
1'b1: topdata_f[33:0] = fetch_11_00;
|
| 323 |
|
|
endcase
|
| 324 |
|
|
case(index_f[3])
|
| 325 |
|
|
1'b0: topdata_f[67:34] = fetch_01_01;
|
| 326 |
|
|
1'b1: topdata_f[67:34] = fetch_11_01;
|
| 327 |
|
|
endcase
|
| 328 |
|
|
case(index_f[3])
|
| 329 |
|
|
1'b0: topdata_f[101:68] = fetch_01_10;
|
| 330 |
|
|
1'b1: topdata_f[101:68] = fetch_11_10;
|
| 331 |
|
|
endcase
|
| 332 |
|
|
case(index_f[3])
|
| 333 |
|
|
1'b0: topdata_f[135:102] = fetch_01_11;
|
| 334 |
|
|
1'b1: topdata_f[135:102] = fetch_11_11;
|
| 335 |
|
|
endcase
|
| 336 |
|
|
end
|
| 337 |
|
|
// else
|
| 338 |
|
|
// begin
|
| 339 |
|
|
// fetdata_f = 136'b0;
|
| 340 |
|
|
// topdata_f = 136'b0;
|
| 341 |
|
|
// end
|
| 342 |
|
|
// end
|
| 343 |
|
|
|
| 344 |
|
|
always @(negedge clk) begin // Writes happening at the negedge
|
| 345 |
|
|
if (wrreq_f & (~rst_tri_en)) begin
|
| 346 |
|
|
if (worden_f[0]) begin
|
| 347 |
|
|
if (wr_index0[1:0] == 2'b0) begin
|
| 348 |
|
|
icdata_ary_00_00[wr_index0[11:4]] <= wrdata_f[135:102];
|
| 349 |
|
|
end
|
| 350 |
|
|
if (wr_index0[1:0] == 2'b1) begin
|
| 351 |
|
|
icdata_ary_00_01[wr_index0[11:4]] <= wrdata_f[135:102];
|
| 352 |
|
|
end
|
| 353 |
|
|
if (wr_index0[1:0] == 2'b10) begin
|
| 354 |
|
|
icdata_ary_00_10[wr_index0[11:4]] <= wrdata_f[135:102];
|
| 355 |
|
|
end
|
| 356 |
|
|
if (wr_index0[1:0] == 2'b11) begin
|
| 357 |
|
|
icdata_ary_00_11[wr_index0[11:4]] <= wrdata_f[135:102];
|
| 358 |
|
|
end
|
| 359 |
|
|
end
|
| 360 |
|
|
if (worden_f[1]) begin
|
| 361 |
|
|
if (wr_index1[1:0] == 2'b0) begin
|
| 362 |
|
|
icdata_ary_01_00[wr_index1[11:4]] <= wrdata_f[101:68];
|
| 363 |
|
|
end
|
| 364 |
|
|
if (wr_index1[1:0] == 2'b1) begin
|
| 365 |
|
|
icdata_ary_01_01[wr_index1[11:4]] <= wrdata_f[101:68];
|
| 366 |
|
|
end
|
| 367 |
|
|
if (wr_index1[1:0] == 2'b10) begin
|
| 368 |
|
|
icdata_ary_01_10[wr_index1[11:4]] <= wrdata_f[101:68];
|
| 369 |
|
|
end
|
| 370 |
|
|
if (wr_index1[1:0] == 2'b11) begin
|
| 371 |
|
|
icdata_ary_01_11[wr_index1[11:4]] <= wrdata_f[101:68];
|
| 372 |
|
|
end
|
| 373 |
|
|
end
|
| 374 |
|
|
if (worden_f[2]) begin
|
| 375 |
|
|
if (wr_index2[1:0] == 2'b0) begin
|
| 376 |
|
|
icdata_ary_10_00[wr_index2[11:4]] <= wrdata_f[67:34];
|
| 377 |
|
|
end
|
| 378 |
|
|
if (wr_index2[1:0] == 2'b1) begin
|
| 379 |
|
|
icdata_ary_10_01[wr_index2[11:4]] <= wrdata_f[67:34];
|
| 380 |
|
|
end
|
| 381 |
|
|
if (wr_index2[1:0] == 2'b10) begin
|
| 382 |
|
|
icdata_ary_10_10[wr_index2[11:4]] <= wrdata_f[67:34];
|
| 383 |
|
|
end
|
| 384 |
|
|
if (wr_index2[1:0] == 2'b11) begin
|
| 385 |
|
|
icdata_ary_10_11[wr_index2[11:4]] <= wrdata_f[67:34];
|
| 386 |
|
|
end
|
| 387 |
|
|
end
|
| 388 |
|
|
if (worden_f[3]) begin
|
| 389 |
|
|
if (wr_index3[1:0] == 2'b0) begin
|
| 390 |
|
|
icdata_ary_11_00[wr_index3[11:4]] <= wrdata_f[33:0];
|
| 391 |
|
|
end
|
| 392 |
|
|
if (wr_index3[1:0] == 2'b1) begin
|
| 393 |
|
|
icdata_ary_11_01[wr_index3[11:4]] <= wrdata_f[33:0];
|
| 394 |
|
|
end
|
| 395 |
|
|
if (wr_index3[1:0] == 2'b10) begin
|
| 396 |
|
|
icdata_ary_11_10[wr_index3[11:4]] <= wrdata_f[33:0];
|
| 397 |
|
|
end
|
| 398 |
|
|
if (wr_index3[1:0] == 2'b11) begin
|
| 399 |
|
|
icdata_ary_11_11[wr_index3[11:4]] <= wrdata_f[33:0];
|
| 400 |
|
|
end
|
| 401 |
|
|
end
|
| 402 |
|
|
end
|
| 403 |
|
|
end
|
| 404 |
|
|
endmodule
|
| 405 |
|
|
|
| 406 |
|
|
`else
|
| 407 |
|
|
|
| 408 |
|
|
module bw_r_icd(/*AUTOARG*/
|
| 409 |
|
|
// Outputs
|
| 410 |
|
|
icd_wsel_fetdata_s1, icd_wsel_topdata_s1, icd_fuse_repair_value,
|
| 411 |
|
|
icd_fuse_repair_en, so,
|
| 412 |
|
|
// Inputs
|
| 413 |
|
|
rclk, se, si, reset_l, sehold, fdp_icd_index_bf, ifq_icd_index_bf,
|
| 414 |
|
|
fcl_icd_index_sel_ifq_bf, ifq_icd_wrway_bf, ifq_icd_worden_bf,
|
| 415 |
|
|
ifq_icd_wrdata_i2, fcl_icd_rdreq_bf, fcl_icd_wrreq_bf,
|
| 416 |
|
|
bist_ic_data, rst_tri_en, ifq_icd_data_sel_old_i2,
|
| 417 |
|
|
ifq_icd_data_sel_fill_i2, ifq_icd_data_sel_bist_i2, fuse_icd_wren,
|
| 418 |
|
|
fuse_icd_rid, fuse_icd_repair_value, fuse_icd_repair_en,
|
| 419 |
|
|
efc_spc_fuse_clk1
|
| 420 |
|
|
);
|
| 421 |
|
|
|
| 422 |
|
|
input rclk,
|
| 423 |
|
|
se,
|
| 424 |
|
|
si,
|
| 425 |
|
|
reset_l;
|
| 426 |
|
|
input sehold;
|
| 427 |
|
|
|
| 428 |
|
|
input [11:2] fdp_icd_index_bf, // index to write to/read from
|
| 429 |
|
|
ifq_icd_index_bf;
|
| 430 |
|
|
input fcl_icd_index_sel_ifq_bf;
|
| 431 |
|
|
|
| 432 |
|
|
input [1:0] ifq_icd_wrway_bf; // way to write to
|
| 433 |
|
|
input [3:0] ifq_icd_worden_bf; // word to write to (ignore index 1:0)
|
| 434 |
|
|
input [135:0] ifq_icd_wrdata_i2; // 128b data, 4b sw, 4b parity
|
| 435 |
|
|
|
| 436 |
|
|
input fcl_icd_rdreq_bf,
|
| 437 |
|
|
fcl_icd_wrreq_bf;
|
| 438 |
|
|
|
| 439 |
|
|
input [7:0] bist_ic_data; // needs to be expanded
|
| 440 |
|
|
input rst_tri_en;
|
| 441 |
|
|
|
| 442 |
|
|
// datain mux selects
|
| 443 |
|
|
input ifq_icd_data_sel_old_i2,
|
| 444 |
|
|
ifq_icd_data_sel_fill_i2,
|
| 445 |
|
|
ifq_icd_data_sel_bist_i2;
|
| 446 |
|
|
|
| 447 |
|
|
// efuse values for redundancy
|
| 448 |
|
|
input fuse_icd_wren;
|
| 449 |
|
|
input [3:0] fuse_icd_rid;
|
| 450 |
|
|
input [7:0] fuse_icd_repair_value;
|
| 451 |
|
|
input [1:0] fuse_icd_repair_en;
|
| 452 |
|
|
|
| 453 |
|
|
// efuse non ovl clks
|
| 454 |
|
|
input efc_spc_fuse_clk1; // use this clk to talk to fuse hdr
|
| 455 |
|
|
// outputs
|
| 456 |
|
|
output [135:0] icd_wsel_fetdata_s1,
|
| 457 |
|
|
icd_wsel_topdata_s1;
|
| 458 |
|
|
|
| 459 |
|
|
// redundancy reg read
|
| 460 |
|
|
output [7:0] icd_fuse_repair_value;
|
| 461 |
|
|
output [1:0] icd_fuse_repair_en;
|
| 462 |
|
|
|
| 463 |
|
|
output so;
|
| 464 |
|
|
|
| 465 |
|
|
|
| 466 |
|
|
//----------------------------------------------------------------------
|
| 467 |
|
|
// Declarations
|
| 468 |
|
|
//----------------------------------------------------------------------
|
| 469 |
|
|
|
| 470 |
|
|
// local signals
|
| 471 |
|
|
`ifdef DEFINE_0IN
|
| 472 |
|
|
reg [135:0] fetdata_s1,
|
| 473 |
|
|
topdata_s1;
|
| 474 |
|
|
wire [135:0] fetdata_sa,
|
| 475 |
|
|
topdata_sa;
|
| 476 |
|
|
`else
|
| 477 |
|
|
reg [33:0] icdata_ary [4095:0];
|
| 478 |
|
|
|
| 479 |
|
|
reg [135:0] fetdata_f, // way0 is lsb, way3 is msb
|
| 480 |
|
|
topdata_f,
|
| 481 |
|
|
fetdata_sa,
|
| 482 |
|
|
topdata_sa,
|
| 483 |
|
|
fetdata_s1,
|
| 484 |
|
|
topdata_s1;
|
| 485 |
|
|
`endif
|
| 486 |
|
|
|
| 487 |
|
|
wire clk;
|
| 488 |
|
|
|
| 489 |
|
|
wire [135:0] next_wrdata_bf,
|
| 490 |
|
|
wrdata_f,
|
| 491 |
|
|
bist_data_expand;
|
| 492 |
|
|
|
| 493 |
|
|
wire [11:2] top_index,
|
| 494 |
|
|
index_bf;
|
| 495 |
|
|
|
| 496 |
|
|
reg [11:2] index_f;
|
| 497 |
|
|
|
| 498 |
|
|
wire [11:0] wr_index0,
|
| 499 |
|
|
wr_index1,
|
| 500 |
|
|
wr_index2,
|
| 501 |
|
|
wr_index3;
|
| 502 |
|
|
|
| 503 |
|
|
reg rdreq_f,
|
| 504 |
|
|
wrreq_f;
|
| 505 |
|
|
reg [3:0] worden_f;
|
| 506 |
|
|
reg [1:0] wrway_f;
|
| 507 |
|
|
|
| 508 |
|
|
|
| 509 |
|
|
// redundancy crap
|
| 510 |
|
|
reg [7:0] red0_ev_row,
|
| 511 |
|
|
red0_od_row;
|
| 512 |
|
|
reg [9:0] red0_ev_col,
|
| 513 |
|
|
red0_od_col;
|
| 514 |
|
|
reg [7:0] red1_ev_row,
|
| 515 |
|
|
red1_od_row;
|
| 516 |
|
|
reg [9:0] red1_ev_col,
|
| 517 |
|
|
red1_od_col;
|
| 518 |
|
|
reg [7:0] red2_ev_row,
|
| 519 |
|
|
red2_od_row;
|
| 520 |
|
|
reg [9:0] red2_ev_col,
|
| 521 |
|
|
red2_od_col;
|
| 522 |
|
|
reg [7:0] red3_ev_row,
|
| 523 |
|
|
red3_od_row;
|
| 524 |
|
|
reg [9:0] red3_ev_col,
|
| 525 |
|
|
red3_od_col;
|
| 526 |
|
|
|
| 527 |
|
|
reg [7:0] icd_fuse_repair_value;
|
| 528 |
|
|
reg [1:0] icd_fuse_repair_en;
|
| 529 |
|
|
|
| 530 |
|
|
|
| 531 |
|
|
//
|
| 532 |
|
|
// Code start here
|
| 533 |
|
|
//
|
| 534 |
|
|
|
| 535 |
|
|
// clk header derives clk from rclk
|
| 536 |
|
|
assign clk = rclk;
|
| 537 |
|
|
|
| 538 |
|
|
|
| 539 |
|
|
// mux merged with flop
|
| 540 |
|
|
assign index_bf = fcl_icd_index_sel_ifq_bf ? ifq_icd_index_bf :
|
| 541 |
|
|
fdp_icd_index_bf;
|
| 542 |
|
|
|
| 543 |
|
|
always @ (posedge clk)
|
| 544 |
|
|
begin
|
| 545 |
|
|
// input flops
|
| 546 |
|
|
if (~sehold)
|
| 547 |
|
|
begin
|
| 548 |
|
|
rdreq_f <= fcl_icd_rdreq_bf;
|
| 549 |
|
|
wrreq_f <= fcl_icd_wrreq_bf;
|
| 550 |
|
|
index_f <= index_bf;
|
| 551 |
|
|
wrway_f <= ifq_icd_wrway_bf;
|
| 552 |
|
|
worden_f <= ifq_icd_worden_bf;
|
| 553 |
|
|
end
|
| 554 |
|
|
// S stage flops (for rd data)
|
| 555 |
|
|
fetdata_s1 <= fetdata_sa;
|
| 556 |
|
|
topdata_s1 <= topdata_sa;
|
| 557 |
|
|
|
| 558 |
|
|
end // always @ (posedge clk)
|
| 559 |
|
|
|
| 560 |
|
|
// BIST data
|
| 561 |
|
|
assign bist_data_expand = {bist_ic_data[1:0], {4{bist_ic_data[7:0]}},
|
| 562 |
|
|
bist_ic_data[1:0], {4{bist_ic_data[7:0]}},
|
| 563 |
|
|
bist_ic_data[1:0], {4{bist_ic_data[7:0]}},
|
| 564 |
|
|
bist_ic_data[1:0], {4{bist_ic_data[7:0]}}};
|
| 565 |
|
|
|
| 566 |
|
|
|
| 567 |
|
|
// Mux + flop for write data input
|
| 568 |
|
|
// ic data enable mux
|
| 569 |
|
|
mux3ds #(136) icden_mux(.dout (next_wrdata_bf),
|
| 570 |
|
|
.in0 (wrdata_f),
|
| 571 |
|
|
.in1 (ifq_icd_wrdata_i2),
|
| 572 |
|
|
.in2 (bist_data_expand),
|
| 573 |
|
|
.sel0 (ifq_icd_data_sel_old_i2),
|
| 574 |
|
|
.sel1 (ifq_icd_data_sel_fill_i2),
|
| 575 |
|
|
.sel2 (ifq_icd_data_sel_bist_i2));
|
| 576 |
|
|
// write data regsiter
|
| 577 |
|
|
// se hold is taken care of by external logic (in ifqctl)
|
| 578 |
|
|
dffe_s #(136) wrdata_reg(.din (next_wrdata_bf),
|
| 579 |
|
|
.clk (clk),
|
| 580 |
|
|
.q (wrdata_f),
|
| 581 |
|
|
.en (~sehold),
|
| 582 |
|
|
.se (se), .si(), .so());
|
| 583 |
|
|
|
| 584 |
|
|
|
| 585 |
|
|
//----------------------------------------------------------------------
|
| 586 |
|
|
// Read Operation
|
| 587 |
|
|
//----------------------------------------------------------------------
|
| 588 |
|
|
|
| 589 |
|
|
// The index has 2 parts.
|
| 590 |
|
|
// 1. The 16B half-line index -- bits 11:4
|
| 591 |
|
|
// 2. The word offset -- bits 3:2 for reads, xx for writes
|
| 592 |
|
|
// 3. The way -- wrway_f for writes, xx for reads
|
| 593 |
|
|
// i.e. we read 1 word from each of 4 ways, but
|
| 594 |
|
|
// we write 4 words to 1 way
|
| 595 |
|
|
|
| 596 |
|
|
assign top_index = {index_f[11:3] , 1'b1};
|
| 597 |
|
|
|
| 598 |
|
|
`ifdef DEFINE_0IN
|
| 599 |
|
|
// physical implmentation: ignore this and use else portion
|
| 600 |
|
|
|
| 601 |
|
|
wire [15:0] we_wrd = ({ 3'b0,worden_f[3], 3'b0,worden_f[2],
|
| 602 |
|
|
3'b0,worden_f[1], 3'b0,worden_f[0] }) << wrway_f;
|
| 603 |
|
|
|
| 604 |
|
|
wire [543:0] we = (~wrreq_f ) ? 544'h0 :
|
| 605 |
|
|
{ {34{we_wrd[15]}}, {34{we_wrd[14]}}, {34{we_wrd[13]}}, {34{we_wrd[12]}},
|
| 606 |
|
|
{34{we_wrd[11]}}, {34{we_wrd[10]}}, {34{we_wrd[ 9]}}, {34{we_wrd[ 8]}},
|
| 607 |
|
|
{34{we_wrd[ 7]}}, {34{we_wrd[ 6]}}, {34{we_wrd[ 5]}}, {34{we_wrd[ 4]}},
|
| 608 |
|
|
{34{we_wrd[ 3]}}, {34{we_wrd[ 2]}}, {34{we_wrd[ 1]}}, {34{we_wrd[ 0]}} };
|
| 609 |
|
|
|
| 610 |
|
|
wire [543:0] din = ({ {4{wrdata_f[ 33: 0]}}, {4{wrdata_f[ 67: 34]}},
|
| 611 |
|
|
{4{wrdata_f[101:68]}}, {4{wrdata_f[135:102]}} });
|
| 612 |
|
|
wire [543:0] dout;
|
| 613 |
|
|
|
| 614 |
|
|
ic_data ic_data ( .nclk(~clk), .adr(index_f[11:4]), .we(we), .din(din), .dout(dout) );
|
| 615 |
|
|
|
| 616 |
|
|
wire [271:0] dout_l1 = index_f[3] ? dout[543:272] : dout[271:0];
|
| 617 |
|
|
|
| 618 |
|
|
assign fetdata_sa[135:0] = index_f[2] ? dout_l1[271:136] : dout_l1[135:0];
|
| 619 |
|
|
assign topdata_sa[135:0] = dout_l1[271:136];
|
| 620 |
|
|
|
| 621 |
|
|
|
| 622 |
|
|
`else
|
| 623 |
|
|
|
| 624 |
|
|
// for physical implementation use this
|
| 625 |
|
|
|
| 626 |
|
|
// read (inst[31:0] + sw bit + par bit) * 4 ways
|
| 627 |
|
|
always @(/*AUTOSENSE*/ /*memory or*/ index_f or rdreq_f
|
| 628 |
|
|
or top_index or wrreq_f)
|
| 629 |
|
|
begin
|
| 630 |
|
|
if (rdreq_f)
|
| 631 |
|
|
begin
|
| 632 |
|
|
if (wrreq_f) // rd-wr contention
|
| 633 |
|
|
begin
|
| 634 |
|
|
fetdata_f = 136'bx;
|
| 635 |
|
|
topdata_f = 136'bx;
|
| 636 |
|
|
end
|
| 637 |
|
|
else
|
| 638 |
|
|
begin // regular read
|
| 639 |
|
|
fetdata_f[33:0] = icdata_ary[{index_f,2'b00}]; // way 0
|
| 640 |
|
|
fetdata_f[67:34] = icdata_ary[{index_f,2'b01}]; // way 1
|
| 641 |
|
|
fetdata_f[101:68] = icdata_ary[{index_f,2'b10}]; // way 2
|
| 642 |
|
|
fetdata_f[135:102] = icdata_ary[{index_f,2'b11}]; // way 3
|
| 643 |
|
|
|
| 644 |
|
|
topdata_f[33:0] = icdata_ary[{top_index, 2'b00}];
|
| 645 |
|
|
topdata_f[67:34] = icdata_ary[{top_index, 2'b01}];
|
| 646 |
|
|
topdata_f[101:68] = icdata_ary[{top_index, 2'b10}];
|
| 647 |
|
|
topdata_f[135:102] = icdata_ary[{top_index, 2'b11}];
|
| 648 |
|
|
end // else: !if(wrreq_f)
|
| 649 |
|
|
end // if (rdreq_f)
|
| 650 |
|
|
|
| 651 |
|
|
else // icache disabled or rd disabled
|
| 652 |
|
|
begin
|
| 653 |
|
|
// JC modified begin
|
| 654 |
|
|
// fetdata_f = 136'bx;
|
| 655 |
|
|
// topdata_f = 136'bx;
|
| 656 |
|
|
fetdata_f = 136'b0;
|
| 657 |
|
|
topdata_f = 136'b0;
|
| 658 |
|
|
// JC modified end
|
| 659 |
|
|
end // else: !if(rdreq_f)
|
| 660 |
|
|
end // always @ (...
|
| 661 |
|
|
|
| 662 |
|
|
|
| 663 |
|
|
// SA latch -- to make 0in happy
|
| 664 |
|
|
always @ (clk or fetdata_f or topdata_f)
|
| 665 |
|
|
begin
|
| 666 |
|
|
if (~clk)
|
| 667 |
|
|
begin
|
| 668 |
|
|
fetdata_sa <= fetdata_f;
|
| 669 |
|
|
topdata_sa <= topdata_f;
|
| 670 |
|
|
end
|
| 671 |
|
|
end
|
| 672 |
|
|
`endif // !`ifdef DEFINE_0IN
|
| 673 |
|
|
|
| 674 |
|
|
// final outputs (272bits)
|
| 675 |
|
|
assign icd_wsel_fetdata_s1 = fetdata_s1;
|
| 676 |
|
|
assign icd_wsel_topdata_s1 = topdata_s1;
|
| 677 |
|
|
|
| 678 |
|
|
|
| 679 |
|
|
//----------------------------------------------------------------------
|
| 680 |
|
|
// Write Operation
|
| 681 |
|
|
//----------------------------------------------------------------------
|
| 682 |
|
|
|
| 683 |
|
|
// The index has 3 parts.
|
| 684 |
|
|
// 1. The 16B half-line index -- bits 11:4 of index_f
|
| 685 |
|
|
// 2. The word offset -- bits 3:2 for reads, xx for writes
|
| 686 |
|
|
// 3. The way -- wrway_f for writes, xx for reads
|
| 687 |
|
|
|
| 688 |
|
|
// index word way
|
| 689 |
|
|
// ----- ---- ---
|
| 690 |
|
|
assign wr_index0 = {index_f[11:4], 2'b00, wrway_f};
|
| 691 |
|
|
assign wr_index1 = {index_f[11:4], 2'b01, wrway_f};
|
| 692 |
|
|
assign wr_index2 = {index_f[11:4], 2'b10, wrway_f};
|
| 693 |
|
|
assign wr_index3 = {index_f[11:4], 2'b11, wrway_f};
|
| 694 |
|
|
|
| 695 |
|
|
`ifdef DEFINE_0IN
|
| 696 |
|
|
`else
|
| 697 |
|
|
// assume write happens @ negedge clk (i.e. phase 1)
|
| 698 |
|
|
always @ (negedge clk)
|
| 699 |
|
|
begin
|
| 700 |
|
|
if (wrreq_f & ~rst_tri_en)
|
| 701 |
|
|
begin
|
| 702 |
|
|
// instructions always Big Endian
|
| 703 |
|
|
if (worden_f[0])
|
| 704 |
|
|
icdata_ary[wr_index0] <= wrdata_f[135:102];
|
| 705 |
|
|
if (worden_f[1])
|
| 706 |
|
|
icdata_ary[wr_index1] <= wrdata_f[101:68];
|
| 707 |
|
|
if (worden_f[2])
|
| 708 |
|
|
icdata_ary[wr_index2] <= wrdata_f[67:34];
|
| 709 |
|
|
if (worden_f[3])
|
| 710 |
|
|
icdata_ary[wr_index3] <= wrdata_f[33:0];
|
| 711 |
|
|
end // if (wrreq_f)
|
| 712 |
|
|
end // always @ (...
|
| 713 |
|
|
`endif // !`ifdef DEFINE_0IN
|
| 714 |
|
|
|
| 715 |
|
|
|
| 716 |
|
|
//--------------------------------------------------------------
|
| 717 |
|
|
// Redundancy Registers
|
| 718 |
|
|
//--------------------------------------------------------------
|
| 719 |
|
|
//
|
| 720 |
|
|
// read red regs
|
| 721 |
|
|
// 16:1 mux
|
| 722 |
|
|
always @ (/*AUTOSENSE*/fuse_icd_rid or red0_ev_col or red0_ev_row
|
| 723 |
|
|
or red0_od_col or red0_od_row or red1_ev_col
|
| 724 |
|
|
or red1_ev_row or red1_od_col or red1_od_row
|
| 725 |
|
|
or red2_ev_col or red2_ev_row or red2_od_col
|
| 726 |
|
|
or red2_od_row or red3_ev_col or red3_ev_row
|
| 727 |
|
|
or red3_od_col or red3_od_row)
|
| 728 |
|
|
begin
|
| 729 |
|
|
// sub array 0
|
| 730 |
|
|
if (fuse_icd_rid[3:0] == 4'b0)
|
| 731 |
|
|
begin
|
| 732 |
|
|
icd_fuse_repair_value = {2'b0, red0_ev_row[5:0]};
|
| 733 |
|
|
icd_fuse_repair_en = red0_ev_row[7:6];
|
| 734 |
|
|
end
|
| 735 |
|
|
else if (fuse_icd_rid[3:0] == 4'b1)
|
| 736 |
|
|
begin
|
| 737 |
|
|
icd_fuse_repair_value = {2'b0, red0_od_row[5:0]};
|
| 738 |
|
|
icd_fuse_repair_en = red0_od_row[7:6];
|
| 739 |
|
|
end
|
| 740 |
|
|
else if (fuse_icd_rid[3:0] == 4'b10)
|
| 741 |
|
|
begin
|
| 742 |
|
|
icd_fuse_repair_value = red0_ev_col[7:0];
|
| 743 |
|
|
icd_fuse_repair_en = red0_ev_col[9:8];
|
| 744 |
|
|
end
|
| 745 |
|
|
else if (fuse_icd_rid[3:0] == 4'b11)
|
| 746 |
|
|
begin
|
| 747 |
|
|
icd_fuse_repair_value = red0_od_col[7:0];
|
| 748 |
|
|
icd_fuse_repair_en = red0_od_col[9:8];
|
| 749 |
|
|
end
|
| 750 |
|
|
|
| 751 |
|
|
// sub array 1
|
| 752 |
|
|
else if (fuse_icd_rid[3:0] == 4'b100)
|
| 753 |
|
|
begin
|
| 754 |
|
|
icd_fuse_repair_value = {2'b0, red1_ev_row[5:0]};
|
| 755 |
|
|
icd_fuse_repair_en = red1_ev_row[7:6];
|
| 756 |
|
|
end
|
| 757 |
|
|
else if (fuse_icd_rid[3:0] == 4'b101)
|
| 758 |
|
|
begin
|
| 759 |
|
|
icd_fuse_repair_value = {2'b0, red1_od_row[5:0]};
|
| 760 |
|
|
icd_fuse_repair_en = red1_od_row[7:6];
|
| 761 |
|
|
end
|
| 762 |
|
|
else if (fuse_icd_rid[3:0] == 4'b110)
|
| 763 |
|
|
begin
|
| 764 |
|
|
icd_fuse_repair_value = red1_ev_col[7:0];
|
| 765 |
|
|
icd_fuse_repair_en = red1_ev_col[9:8];
|
| 766 |
|
|
end
|
| 767 |
|
|
else if (fuse_icd_rid[3:0] == 4'b111)
|
| 768 |
|
|
begin
|
| 769 |
|
|
icd_fuse_repair_value = red1_od_col[7:0];
|
| 770 |
|
|
icd_fuse_repair_en = red1_od_col[9:8];
|
| 771 |
|
|
end
|
| 772 |
|
|
|
| 773 |
|
|
// sub array 2
|
| 774 |
|
|
else if (fuse_icd_rid[3:0] == 4'b1000)
|
| 775 |
|
|
begin
|
| 776 |
|
|
icd_fuse_repair_value = {2'b0, red2_ev_row[5:0]};
|
| 777 |
|
|
icd_fuse_repair_en = red2_ev_row[7:6];
|
| 778 |
|
|
end
|
| 779 |
|
|
else if (fuse_icd_rid[3:0] == 4'b1001)
|
| 780 |
|
|
begin
|
| 781 |
|
|
icd_fuse_repair_value = {2'b0, red2_od_row[5:0]};
|
| 782 |
|
|
icd_fuse_repair_en = red2_od_row[7:6];
|
| 783 |
|
|
end
|
| 784 |
|
|
else if (fuse_icd_rid[3:0] == 4'b1010)
|
| 785 |
|
|
begin
|
| 786 |
|
|
icd_fuse_repair_value = red2_ev_col[7:0];
|
| 787 |
|
|
icd_fuse_repair_en = red2_ev_col[9:8];
|
| 788 |
|
|
end
|
| 789 |
|
|
else if (fuse_icd_rid[3:0] == 4'b1011)
|
| 790 |
|
|
begin
|
| 791 |
|
|
icd_fuse_repair_value = red2_od_col[7:0];
|
| 792 |
|
|
icd_fuse_repair_en = red2_od_col[9:8];
|
| 793 |
|
|
end
|
| 794 |
|
|
|
| 795 |
|
|
// sub array 3
|
| 796 |
|
|
else if (fuse_icd_rid[3:0] == 4'b1100)
|
| 797 |
|
|
begin
|
| 798 |
|
|
icd_fuse_repair_value = {2'b0, red3_ev_row[5:0]};
|
| 799 |
|
|
icd_fuse_repair_en = red3_ev_row[7:6];
|
| 800 |
|
|
end
|
| 801 |
|
|
else if (fuse_icd_rid[3:0] == 4'b1101)
|
| 802 |
|
|
begin
|
| 803 |
|
|
icd_fuse_repair_value = {2'b0, red3_od_row[5:0]};
|
| 804 |
|
|
icd_fuse_repair_en = red3_od_row[7:6];
|
| 805 |
|
|
end
|
| 806 |
|
|
else if (fuse_icd_rid[3:0] == 4'b1110)
|
| 807 |
|
|
begin
|
| 808 |
|
|
icd_fuse_repair_value = red3_ev_col[7:0];
|
| 809 |
|
|
icd_fuse_repair_en = red3_ev_col[9:8];
|
| 810 |
|
|
end
|
| 811 |
|
|
else // if (fuse_icd_rid[3:0] == 4'b1111)
|
| 812 |
|
|
begin
|
| 813 |
|
|
icd_fuse_repair_value = red3_od_col[7:0];
|
| 814 |
|
|
icd_fuse_repair_en = red3_od_col[9:8];
|
| 815 |
|
|
end
|
| 816 |
|
|
end // always @ (...
|
| 817 |
|
|
|
| 818 |
|
|
|
| 819 |
|
|
//
|
| 820 |
|
|
// write red regs
|
| 821 |
|
|
//
|
| 822 |
|
|
// use clk1 to latch anything to/from the hdr
|
| 823 |
|
|
//
|
| 824 |
|
|
// reset_l is an asynchronous reset. Only the the repair enables [9:8]
|
| 825 |
|
|
// need to be reset. However, the actual circuit resets all the bits.
|
| 826 |
|
|
always @ (posedge efc_spc_fuse_clk1 or negedge reset_l)
|
| 827 |
|
|
begin
|
| 828 |
|
|
if (~reset_l)
|
| 829 |
|
|
begin // async reset
|
| 830 |
|
|
red0_ev_row[7:0] <= 8'b0;
|
| 831 |
|
|
red1_ev_row[7:0] <= 8'b0;
|
| 832 |
|
|
red2_ev_row[7:0] <= 8'b0;
|
| 833 |
|
|
red3_ev_row[7:0] <= 8'b0;
|
| 834 |
|
|
|
| 835 |
|
|
red0_od_row[7:0] <= 8'b0;
|
| 836 |
|
|
red1_od_row[7:0] <= 8'b0;
|
| 837 |
|
|
red2_od_row[7:0] <= 8'b0;
|
| 838 |
|
|
red3_od_row[7:0] <= 8'b0;
|
| 839 |
|
|
|
| 840 |
|
|
red0_ev_col[9:0] <= 10'b0;
|
| 841 |
|
|
red1_ev_col[9:0] <= 10'b0;
|
| 842 |
|
|
red2_ev_col[9:0] <= 10'b0;
|
| 843 |
|
|
red3_ev_col[9:0] <= 10'b0;
|
| 844 |
|
|
|
| 845 |
|
|
red0_od_col[9:0] <= 10'b0;
|
| 846 |
|
|
red1_od_col[9:0] <= 10'b0;
|
| 847 |
|
|
red2_od_col[9:0] <= 10'b0;
|
| 848 |
|
|
red3_od_col[9:0] <= 10'b0;
|
| 849 |
|
|
end // if (~reset_l)
|
| 850 |
|
|
|
| 851 |
|
|
else if (fuse_icd_wren & reset_l)
|
| 852 |
|
|
begin // 4:16 decode
|
| 853 |
|
|
if (fuse_icd_rid[3:0] == 4'b0)
|
| 854 |
|
|
begin
|
| 855 |
|
|
red0_ev_row <= {fuse_icd_repair_en[1:0],
|
| 856 |
|
|
fuse_icd_repair_value[5:0]};
|
| 857 |
|
|
end
|
| 858 |
|
|
else if (fuse_icd_rid[3:0] == 4'b1)
|
| 859 |
|
|
begin
|
| 860 |
|
|
red0_od_row <= {fuse_icd_repair_en[1:0],
|
| 861 |
|
|
fuse_icd_repair_value[5:0]};
|
| 862 |
|
|
end
|
| 863 |
|
|
else if (fuse_icd_rid[3:0] == 4'b10)
|
| 864 |
|
|
begin
|
| 865 |
|
|
red0_ev_col <= {fuse_icd_repair_en[1:0],
|
| 866 |
|
|
fuse_icd_repair_value[7:0]};
|
| 867 |
|
|
end
|
| 868 |
|
|
else if (fuse_icd_rid[3:0] == 4'b11)
|
| 869 |
|
|
begin
|
| 870 |
|
|
red0_od_col <= {fuse_icd_repair_en[1:0],
|
| 871 |
|
|
fuse_icd_repair_value[7:0]};
|
| 872 |
|
|
end
|
| 873 |
|
|
|
| 874 |
|
|
// sub array 1
|
| 875 |
|
|
else if (fuse_icd_rid[3:0] == 4'b100)
|
| 876 |
|
|
begin
|
| 877 |
|
|
red1_ev_row <= {fuse_icd_repair_en[1:0],
|
| 878 |
|
|
fuse_icd_repair_value[5:0]};
|
| 879 |
|
|
end
|
| 880 |
|
|
else if (fuse_icd_rid[3:0] == 4'b101)
|
| 881 |
|
|
begin
|
| 882 |
|
|
red1_od_row <= {fuse_icd_repair_en[1:0],
|
| 883 |
|
|
fuse_icd_repair_value[5:0]};
|
| 884 |
|
|
end
|
| 885 |
|
|
else if (fuse_icd_rid[3:0] == 4'b110)
|
| 886 |
|
|
begin
|
| 887 |
|
|
red1_ev_col <= {fuse_icd_repair_en[1:0],
|
| 888 |
|
|
fuse_icd_repair_value[7:0]};
|
| 889 |
|
|
end
|
| 890 |
|
|
else if (fuse_icd_rid[3:0] == 4'b111)
|
| 891 |
|
|
begin
|
| 892 |
|
|
red1_od_col <= {fuse_icd_repair_en[1:0],
|
| 893 |
|
|
fuse_icd_repair_value[7:0]};
|
| 894 |
|
|
end
|
| 895 |
|
|
|
| 896 |
|
|
// sub array 2
|
| 897 |
|
|
else if (fuse_icd_rid[3:0] == 4'b1000)
|
| 898 |
|
|
begin
|
| 899 |
|
|
red2_ev_row <= {fuse_icd_repair_en[1:0],
|
| 900 |
|
|
fuse_icd_repair_value[5:0]};
|
| 901 |
|
|
end
|
| 902 |
|
|
else if (fuse_icd_rid[3:0] == 4'b1001)
|
| 903 |
|
|
begin
|
| 904 |
|
|
red2_od_row <= {fuse_icd_repair_en[1:0],
|
| 905 |
|
|
fuse_icd_repair_value[5:0]};
|
| 906 |
|
|
end
|
| 907 |
|
|
else if (fuse_icd_rid[3:0] == 4'b1010)
|
| 908 |
|
|
begin
|
| 909 |
|
|
red2_ev_col <= {fuse_icd_repair_en[1:0],
|
| 910 |
|
|
fuse_icd_repair_value[7:0]};
|
| 911 |
|
|
end
|
| 912 |
|
|
else if (fuse_icd_rid[3:0] == 4'b1011)
|
| 913 |
|
|
begin
|
| 914 |
|
|
red2_od_col <= {fuse_icd_repair_en[1:0],
|
| 915 |
|
|
fuse_icd_repair_value[7:0]};
|
| 916 |
|
|
end
|
| 917 |
|
|
|
| 918 |
|
|
// sub array 2
|
| 919 |
|
|
else if (fuse_icd_rid[3:0] == 4'b1100)
|
| 920 |
|
|
begin
|
| 921 |
|
|
red3_ev_row <= {fuse_icd_repair_en[1:0],
|
| 922 |
|
|
fuse_icd_repair_value[5:0]};
|
| 923 |
|
|
end
|
| 924 |
|
|
else if (fuse_icd_rid[3:0] == 4'b1101)
|
| 925 |
|
|
begin
|
| 926 |
|
|
red3_od_row <= {fuse_icd_repair_en[1:0],
|
| 927 |
|
|
fuse_icd_repair_value[5:0]};
|
| 928 |
|
|
end
|
| 929 |
|
|
else if (fuse_icd_rid[3:0] == 4'b1110)
|
| 930 |
|
|
begin
|
| 931 |
|
|
red3_ev_col <= {fuse_icd_repair_en[1:0],
|
| 932 |
|
|
fuse_icd_repair_value[7:0]};
|
| 933 |
|
|
end
|
| 934 |
|
|
else // if (fuse_icd_rid[3:0] == 4'b1111)
|
| 935 |
|
|
begin
|
| 936 |
|
|
red3_od_col <= {fuse_icd_repair_en[1:0],
|
| 937 |
|
|
fuse_icd_repair_value[7:0]};
|
| 938 |
|
|
end
|
| 939 |
|
|
end // if (fuse_icd_wren)
|
| 940 |
|
|
end // always @ (...
|
| 941 |
|
|
|
| 942 |
|
|
endmodule // bw_r_icd
|
| 943 |
|
|
|
| 944 |
|
|
`endif
|
