OpenCores
URL https://opencores.org/ocsvn/sparc64soc/sparc64soc/trunk

Subversion Repositories sparc64soc

[/] [sparc64soc/] [trunk/] [T1-common/] [srams/] [bw_r_idct.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dmitryr
// ========== Copyright Header Begin ==========================================
2
// 
3
// OpenSPARC T1 Processor File: bw_r_idct.v
4
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
5
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6
// 
7
// The above named program is free software; you can redistribute it and/or
8
// modify it under the terms of the GNU General Public
9
// License version 2 as published by the Free Software Foundation.
10
// 
11
// The above named program is distributed in the hope that it will be 
12
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
// General Public License for more details.
15
// 
16
// You should have received a copy of the GNU General Public
17
// License along with this work; if not, write to the Free Software
18
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19
// 
20
// ========== Copyright Header End ============================================
21
////////////////////////////////////////////////////////////////////////
22
/*
23
 //  Module Name:  bw_r_idct.v
24
 //  Description:
25
 //    Contains the RTL for the icache and dcache tag blocks.
26
 //    This is a 1RW 512 entry X 33b macro, with 132b rd and 132b wr,
27
 //    broken into 4 33b segments with its own write enable.
28
 //    Address and Control inputs are available the stage before
29
 //    array access, which is referred to as "_x".  Write data is
30
 //    available in the same stage as the write to the ram, referred
31
 //    to as "_y".  Read data is also read out and available in "_y".
32
 //
33
 //            X       |      Y
34
 //     index          |  ram access
35
 //     index sel      |  write_tag
36
 //     rd/wr req      |     -> read_tag
37
 //     way enable     |
38
 */
39
 
40
 
41
////////////////////////////////////////////////////////////////////////
42
// Local header file includes / local defines
43
////////////////////////////////////////////////////////////////////////
44
 
45
//FPGA_SYN enables all FPGA related modifications
46
`ifdef FPGA_SYN
47
`define FPGA_SYN_IDCT
48
`endif
49
 
50
`ifdef FPGA_SYN_IDCT
51
 
52
module bw_r_idct(rdtag_w0_y, rdtag_w1_y, rdtag_w2_y, rdtag_w3_y, so, rclk, se,
53
        si, reset_l, sehold, rst_tri_en, index0_x, index1_x, index_sel_x,
54
        dec_wrway_x, rdreq_x, wrreq_x, wrtag_w0_y, wrtag_w1_y, wrtag_w2_y,
55
        wrtag_w3_y, adj);
56
 
57
        input                   rclk;
58
        input                   se;
59
        input                   si;
60
        input                   reset_l;
61
        input                   sehold;
62
        input                   rst_tri_en;
63
        input   [6:0]            index0_x;
64
        input   [6:0]            index1_x;
65
        input                   index_sel_x;
66
        input   [3:0]            dec_wrway_x;
67
        input                   rdreq_x;
68
        input                   wrreq_x;
69
        input   [32:0]           wrtag_w0_y;
70
        input   [32:0]           wrtag_w1_y;
71
        input   [32:0]           wrtag_w2_y;
72
        input   [32:0]           wrtag_w3_y;
73
        input   [3:0]            adj;
74
        output  [32:0]           rdtag_w0_y;
75
        output  [32:0]           rdtag_w1_y;
76
        output  [32:0]           rdtag_w2_y;
77
        output  [32:0]           rdtag_w3_y;
78
        output                  so;
79
 
80
        wire                    clk;
81
        reg     [6:0]            index_y;
82
        reg                     rdreq_y;
83
        reg                     wrreq_y;
84
        reg     [3:0]            dec_wrway_y;
85
        wire    [6:0]            index_x;
86
        wire    [3:0]            we;
87
 
88
        reg [131:0]  rdtag_sa_y; //for error_inject XMR
89
 
90
        assign clk = rclk;
91
        assign index_x = (index_sel_x ? index1_x : index0_x);
92
    assign we = ({4 {((wrreq_y & reset_l) & (~rst_tri_en))}} & dec_wrway_y);
93
 
94
        always @(posedge clk) begin
95
          if (~sehold) begin
96
            rdreq_y <= rdreq_x;
97
            wrreq_y <= wrreq_x;
98
            index_y <= index_x;
99
            dec_wrway_y <= dec_wrway_x;
100
          end
101
        end
102
 
103
        bw_r_idct_array ictag_ary_00(
104
                .we     (we[0]),
105
                .clk    (clk),
106
        .way (2'b00),
107
                .rd_data(rdtag_w0_y),
108
                .wr_data(wrtag_w0_y),
109
                .addr   (index_y),
110
        .dec_wrway_y (dec_wrway_y));
111
 
112
        bw_r_idct_array ictag_ary_01(
113
                .we     (we[1]),
114
                .clk    (clk),
115
        .way (2'b01),
116
                .rd_data(rdtag_w1_y),
117
                .wr_data(wrtag_w1_y),
118
                .addr   (index_y),
119
        .dec_wrway_y (dec_wrway_y));
120
 
121
        bw_r_idct_array ictag_ary_10(
122
                .we     (we[2]),
123
                .clk    (clk),
124
        .way(2'b10),
125
                .rd_data(rdtag_w2_y),
126
                .wr_data(wrtag_w2_y),
127
                .addr   (index_y),
128
        .dec_wrway_y (dec_wrway_y));
129
 
130
        bw_r_idct_array ictag_ary_11(
131
                .we     (we[3]),
132
                .clk    (clk),
133
        .way(2'b11),
134
                .rd_data(rdtag_w3_y),
135
                .wr_data(wrtag_w3_y),
136
                .addr   (index_y),
137
        .dec_wrway_y (dec_wrway_y));
138
 
139
endmodule
140
 
141
module bw_r_idct_array(we, clk, rd_data, wr_data, addr,dec_wrway_y,way);
142
 
143
input we;
144
input clk;
145
input [32:0] wr_data;
146
input [6:0] addr;
147
input [3:0] dec_wrway_y;
148
input [1:0] way;
149
output [32:0] rd_data;
150
reg [32:0] rd_data;
151
 
152
reg     [32:0]           array[511:0] /* synthesis syn_ramstyle = block_ram  syn_ramstyle = no_rw_check */ ;
153
integer i;
154
 
155
initial begin
156
`ifdef DO_MEM_INIT
157
    // Add the memory init file in the database
158
    $readmemb("/import/dtg-data11/sandeep/niagara/design/sys/iop/srams/rtl/mem_init_idct.txt",array);
159
`endif
160
end
161
 
162
        always @(negedge clk) begin
163
          if (we)
164
          begin
165
              array[addr] <= wr_data;
166
          end
167
          else
168
          rd_data <= array[addr];
169
        end
170
endmodule
171
 
172
`else
173
 
174
module bw_r_idct(/*AUTOARG*/
175
   // Outputs
176
   rdtag_w0_y, rdtag_w1_y, rdtag_w2_y, rdtag_w3_y, so,
177
   // Inputs
178
   rclk, se, si, reset_l, sehold, rst_tri_en, index0_x, index1_x,
179
   index_sel_x, dec_wrway_x, rdreq_x, wrreq_x, wrtag_w0_y,
180
   wrtag_w1_y, wrtag_w2_y, wrtag_w3_y, adj
181
   );
182
 
183
   input          rclk,
184
                  se,
185
                  si,
186
                  reset_l;      // active LOW reset
187
 
188
   input          sehold;
189
   input          rst_tri_en;
190
 
191
   input [6:0]    index0_x;     // read/write address0
192
   input [6:0]    index1_x;     // read/write address1
193
 
194
   input          index_sel_x;  // selects between index1 and index0
195
 
196
   input [3:0]    dec_wrway_x;  // way -- functions as a write enable
197
                                // per 33b
198
 
199
   input          rdreq_x,      // read enable
200
                              wrreq_x;      // write enable
201
 
202
   // Don't use rdreq and wrreq to gate off the clock, since these are
203
   // critical.  A separate power down signal can be supplied if
204
   // needed. 
205
 
206
   input [32:0]   wrtag_w0_y;      // write data, not flopped
207
   input [32:0]   wrtag_w1_y;      //
208
   input [32:0]   wrtag_w2_y;      //
209
   input [32:0]   wrtag_w3_y;      //
210
 
211
   input [3:0]    adj;
212
 
213
 
214
   output [32:0] rdtag_w0_y;    // read data split into 4 ports
215
   output [32:0] rdtag_w1_y;    // not flopped
216
   output [32:0] rdtag_w2_y;    // 
217
   output [32:0] rdtag_w3_y;    // 
218
 
219
   output        so;
220
 
221
 
222
   // Declarations
223
   // local signals
224
`ifdef DEFINE_0IN
225
`else
226
   reg [32:0]   ictag_ary  [511:0];
227
   reg [131:0]  rdtag_bl_y,
228
                rdtag_sa_y;
229
`endif
230
 
231
   wire         clk;
232
 
233
 
234
   reg [6:0]    index_y;
235
   reg          rdreq_y,
236
                            wrreq_y;
237
   reg [3:0]    dec_wrway_y;
238
 
239
   wire [6:0]   index_x;
240
 
241
 
242
   //----------------
243
   // Code start here 
244
   //----------------
245
 
246
   assign       clk = rclk;
247
 
248
   //-------------------------
249
   // 2:1 mux on address input
250
   //-------------------------
251
   // address inputs are critical and this mux needs to be merged with 
252
   // the receiving flop.
253
   assign index_x = index_sel_x ? index1_x :
254
                                  index0_x;
255
 
256
   //------------------------
257
   // input flops from x to y
258
   //------------------------
259
   // these need to be scannable
260
   always @ (posedge clk)
261
     begin
262
        if (~sehold)
263
          begin
264
                   rdreq_y <= rdreq_x;
265
                   wrreq_y <= wrreq_x;
266
                   index_y <= index_x;
267
                   dec_wrway_y <= dec_wrway_x;
268
          end
269
     end
270
 
271
`ifdef DEFINE_0IN
272
wire [131:0] wm = { {33{(dec_wrway_y[3])}},{33{(dec_wrway_y[2])}},{33{(dec_wrway_y[1])}},{33{(dec_wrway_y[0])}} };
273
wire         we = wrreq_y & ~se;
274
 
275
l1_tag l1_tag ( .nclk(~clk), .adr(index_y[6:0]), .we(we), .wm(wm),
276
                                              .din ({wrtag_w3_y,wrtag_w2_y,wrtag_w1_y,wrtag_w0_y}),
277
                                              .dout({rdtag_w3_y,rdtag_w2_y,rdtag_w1_y,rdtag_w0_y}) );
278
`else
279
 
280
   //----------------------------------------------------------------------
281
   // Read Operation
282
   //----------------------------------------------------------------------
283
 
284
   always @(/*AUTOSENSE*/ /*memory or*/ index_y or rdreq_y or reset_l
285
            or wrreq_y)
286
     begin
287
              if (rdreq_y & reset_l)
288
          begin
289
             if (wrreq_y)    // rd_wr conflict
290
                     begin
291
                        rdtag_bl_y = {132{1'bx}};
292
                     end
293
 
294
                   else   // no write, read only
295
                     begin
296
                  rdtag_bl_y[32:0] = ictag_ary[{index_y,2'b00}];  // way0
297
                  rdtag_bl_y[65:33] = ictag_ary[{index_y,2'b01}]; // way1
298
                  rdtag_bl_y[98:66] = ictag_ary[{index_y,2'b10}]; // way2
299
                  rdtag_bl_y[131:99] = ictag_ary[{index_y,2'b11}];// way3
300
                     end
301
          end
302
        else    // no read
303
          begin
304
             rdtag_bl_y =  {132{1'bx}};
305
          end
306
 
307
     end // always @ (...
308
 
309
 
310
   // SA latch -- to make 0in happy
311
   always @ (/*AUTOSENSE*/clk or rdreq_y or rdtag_bl_y or reset_l)
312
     begin
313
        if (rdreq_y & ~clk & reset_l)
314
          begin
315
             rdtag_sa_y <= rdtag_bl_y;
316
          end
317
     end
318
 
319
   // Output is held the same if there is no read.  This is not a
320
   // hard requirement, please let me know if the output has to
321
   // be something else for ease of implementation.
322
 
323
   // Output behavior during reset is currently not coded.
324
   // Functionally there is no preference, though it should be
325
   // unchanging to keep the power low.
326
 
327
   // Final Output
328
   assign rdtag_w0_y = rdtag_sa_y[32:0];
329
   assign rdtag_w1_y = rdtag_sa_y[65:33];
330
   assign rdtag_w2_y = rdtag_sa_y[98:66];
331
   assign rdtag_w3_y = rdtag_sa_y[131:99];
332
 
333
 
334
   //----------------------------------------------------------------------
335
   // Write Operation
336
   //----------------------------------------------------------------------
337
   // Writes should be blocked off during scan shift.
338
   always @ (negedge clk)
339
     begin
340
           if (wrreq_y & reset_l & ~rst_tri_en)
341
           begin
342
             if (dec_wrway_y[0])
343
                     ictag_ary[{index_y, 2'b00}] = wrtag_w0_y;
344
             if (dec_wrway_y[1])
345
                     ictag_ary[{index_y, 2'b01}] = wrtag_w1_y;
346
             if (dec_wrway_y[2])
347
                     ictag_ary[{index_y, 2'b10}] = wrtag_w2_y;
348
             if (dec_wrway_y[3])
349
                     ictag_ary[{index_y, 2'b11}] = wrtag_w3_y;
350
           end
351
     end
352
 
353
   // TBD: Need to model rd-wr contention
354
`endif
355
 
356
   //******************************************************
357
   // The stuff below is not part of the main functionality
358
   // and has no representation in the actual circuit.
359
   //******************************************************
360
 
361
   // synopsys translate_off
362
 
363
   //-----------------------
364
   // Contention Monitor
365
   //-----------------------
366
 `ifdef INNO_MUXEX
367
 `else
368
   always @ (negedge clk)
369
   begin
370
      if (rdreq_y & wrreq_y & reset_l)
371
        begin
372
           // 0in <fire -message "FATAL ERROR: rd and wr contention in idct"
373
           //$error("IDtag Contention", "ERROR rd and wr contention in idct");
374
        end
375
   end // always @ (negedge clk)
376
 
377
 `endif
378
 
379
 
380
   //--------------------------------
381
//   // For dump_cache.v
382
//   //--------------------------------
383
//   //fake to make dump_cache.v happy
384
//   reg [29:0] w0 [127:0];
385
//   reg [29:0] w1 [127:0];
386
//   reg [29:0] w2 [127:0];
387
//   reg [29:0] w3 [127:0];
388
//      
389
//   always @ (negedge clk)
390
//     begin
391
//            if (wrreq_y & ~se)
392
//              begin
393
//             if (rdreq_y) begin // rd/wr contention
394
//               case (dec_wrway_y)
395
//                 4'b0001 : w0[index_y[6:0]] ={30{1'bx}};
396
//                 4'b0010 : w1[index_y[6:0]] ={30{1'bx}};
397
//                 4'b0100 : w2[index_y[6:0]] ={30{1'bx}};
398
//                 4'b1000 : w3[index_y[6:0]] ={30{1'bx}};
399
//               endcase // case(wrway_y)
400
//             end
401
//             else begin 
402
//               case (dec_wrway_y)
403
//                 4'b0001 : w0[index_y[6:0]] = wrtag_w0_y[29:0];
404
//                 4'b0010 : w1[index_y[6:0]] = wrtag_w1_y[29:0];
405
//                 4'b0100 : w2[index_y[6:0]] = wrtag_w2_y[29:0];
406
//                 4'b1000 : w3[index_y[6:0]] = wrtag_w3_y[29:0];
407
//               endcase // case(wrway_y)
408
//             end
409
//              end 
410
//     end
411
 
412
   // synopsys translate_on    
413
 
414
 
415
endmodule // bw_r_idct
416
 
417
`endif
418
 
419
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.