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// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: bw_r_l2d_rep_bot.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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module bw_r_l2d_rep_bot (/*AUTOARG*/
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// Outputs
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fuse_l2d_rden_buf, fuse_l2d_wren_buf, si_buf, arst_l_buf, se_buf,
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sehold_buf, fuse_l2d_rid_buf, fuse_read_data_in_buf,
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fuse_l2d_data_in_buf, word_en_l, col_offset_l, set_l, wr_en_l,
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way_sel_l, decc_in_l, scbuf_scdata_fbdecc_top_buf,
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scbuf_scdata_fbdecc_bot_buf, sbdt_l, sbdb_l, fuse_clk1_buf,
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fuse_clk2_buf, mem_write_disable_buf,
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// Inputs
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fuse_l2d_rden, fuse_l2d_wren, si, arst_l, se, sehold,
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fuse_l2d_rid, fuse_read_data_in, fuse_l2d_data_in, word_en,
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col_offset, set, wr_en, way_sel, decc_in, fbdt_l, fbdb_l,
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scdata_scbuf_decc_top, scdata_scbuf_decc_bot,
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efc_scdata_fuse_clk1, efc_scdata_fuse_clk2, mem_write_disable
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);
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input fuse_l2d_rden;
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input [5:0] fuse_l2d_wren;
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input si;
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input arst_l;
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input se;
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input sehold;
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input [2:0] fuse_l2d_rid;
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input fuse_read_data_in;
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input fuse_l2d_data_in;
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input [3:0] word_en;
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input col_offset;
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input [9:0] set;
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input wr_en;
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input [11:0] way_sel;
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input [155:0] decc_in;
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input [155:0] fbdt_l;
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input [155:0] fbdb_l;
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input [155:0] scdata_scbuf_decc_top;
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input [155:0] scdata_scbuf_decc_bot;
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input efc_scdata_fuse_clk1;
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input efc_scdata_fuse_clk2;
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input mem_write_disable;
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output fuse_l2d_rden_buf;
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output [5:0] fuse_l2d_wren_buf;
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output si_buf;
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output arst_l_buf;
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output se_buf;
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output sehold_buf;
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output [2:0] fuse_l2d_rid_buf;
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output fuse_read_data_in_buf;
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output fuse_l2d_data_in_buf;
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output [3:0] word_en_l;
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output col_offset_l;
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output [9:0] set_l;
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output wr_en_l;
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output [11:0] way_sel_l;
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output [155:0] decc_in_l;
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output [155:0] scbuf_scdata_fbdecc_top_buf;
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output [155:0] scbuf_scdata_fbdecc_bot_buf;
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output [155:0] sbdt_l;
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output [155:0] sbdb_l;
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output fuse_clk1_buf;
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output fuse_clk2_buf;
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output mem_write_disable_buf;
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///////////////////////////////////////////////////////////////////////
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// Non-inverting Buffers
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///////////////////////////////////////////////////////////////////////
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assign fuse_l2d_rden_buf = fuse_l2d_rden;
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assign fuse_l2d_wren_buf[5:0] = fuse_l2d_wren[5:0];
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assign si_buf = si;
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assign arst_l_buf = arst_l;
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assign se_buf = se;
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assign sehold_buf = sehold;
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assign fuse_l2d_rid_buf[2:0] = fuse_l2d_rid[2:0];
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assign fuse_read_data_in_buf = fuse_read_data_in;
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assign fuse_l2d_data_in_buf = fuse_l2d_data_in;
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assign fuse_clk1_buf = efc_scdata_fuse_clk1;
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assign fuse_clk2_buf = efc_scdata_fuse_clk2;
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assign mem_write_disable_buf = mem_write_disable;
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///////////////////////////////////////////////////////////////////////
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// Inverting Buffers
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///////////////////////////////////////////////////////////////////////
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assign word_en_l[3:0] = ~word_en[3:0];
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assign col_offset_l = ~col_offset;
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assign set_l[9:0] = ~set[9:0];
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assign wr_en_l = ~wr_en;
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assign way_sel_l = ~way_sel;
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assign decc_in_l[155:0] = ~decc_in[155:0];
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assign scbuf_scdata_fbdecc_top_buf[155:0] = ~fbdt_l[155:0];
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assign scbuf_scdata_fbdecc_bot_buf[155:0] = ~fbdb_l[155:0];
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assign sbdt_l[155:0] = ~scdata_scbuf_decc_top[155:0];
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assign sbdb_l[155:0] = ~scdata_scbuf_decc_bot[155:0];
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endmodule // bw_r_l2d_rep_bot
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