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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: bw_r_rf16x128d.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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////////////////////////////////////////////////////////////////////////
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// 16 X 128 R1 W1 RF macro with decoded wordlines.
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// REad/Write ports can be accessed in PH1 only.
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////////////////////////////////////////////////////////////////////////
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module bw_r_rf16x128d(/*AUTOARG*/
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// Outputs
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dout, so,
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// Inputs
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din, rd_wl, wr_wl, read_en, wr_en, rst_tri_en, rclk, se, si,
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reset_l, sehold
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);
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input [127:0] din; // data input
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input [15:0] rd_wl; // read addr
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input [15:0] wr_wl; // write addr
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input read_en;
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input wr_en; // used in conjunction with
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// word_wen and byte_wen
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input rst_tri_en ; // gates off writes during SCAN.
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input rclk;
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input se, si ;
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input reset_l;
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input sehold; // hold scan in data.
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output [127:0] dout;
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output so;
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reg [127:0] dout;
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// memory array
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reg [127:0] inq_ary [15:0];
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// internal variable
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integer i;
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reg [127:0] temp, data_in;
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reg [3:0] rdptr_d1, wrptr_d1;
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wire [160:0] scan_out;
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reg [127:0] wrdata_d1 ;
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reg ren_d1;
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reg wr_en_d1;
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reg [15:0] rd_wl_d1, wr_wl_d1;
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reg rst_tri_en_d1;
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always @(posedge rclk ) begin
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wrdata_d1 <= ( sehold)? wrdata_d1 : din;
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wr_en_d1 <= ( sehold)? wr_en_d1 : wr_en ;
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wr_wl_d1 <= (sehold) ? wr_wl_d1 : wr_wl ;
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ren_d1 <= (sehold)? ren_d1 : read_en;
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rd_wl_d1 <= (sehold) ? rd_wl_d1 : rd_wl ;
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rst_tri_en_d1 <= rst_tri_en ; // not a real flop ( only used as a trigger ). Works only for accesses made in PH1
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end
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//////////////////////////////////////////////////////////////////////
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// Read Operation
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//////////////////////////////////////////////////////////////////////
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always @(/*AUTOSENSE*/ /*memory or*/ rd_wl_d1 or ren_d1 or reset_l
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or rst_tri_en_d1 or wr_en_d1 or wr_wl_d1)
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begin
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if (reset_l)
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begin
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// ---- \/ added the rst_tri_en qual on 11/11 \/------
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if (ren_d1)
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begin
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case(rd_wl_d1 & {16{~rst_tri_en}})
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16'b0000_0000_0000_0000: ; // do nothing.
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16'b0000_0000_0000_0001: rdptr_d1 = 4'b0000;
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16'b0000_0000_0000_0010: rdptr_d1 = 4'b0001;
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16'b0000_0000_0000_0100: rdptr_d1 = 4'b0010;
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16'b0000_0000_0000_1000: rdptr_d1 = 4'b0011;
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16'b0000_0000_0001_0000: rdptr_d1 = 4'b0100;
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16'b0000_0000_0010_0000: rdptr_d1 = 4'b0101;
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16'b0000_0000_0100_0000: rdptr_d1 = 4'b0110;
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16'b0000_0000_1000_0000: rdptr_d1 = 4'b0111;
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16'b0000_0001_0000_0000: rdptr_d1 = 4'b1000;
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16'b0000_0010_0000_0000: rdptr_d1 = 4'b1001;
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16'b0000_0100_0000_0000: rdptr_d1 = 4'b1010;
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16'b0000_1000_0000_0000: rdptr_d1 = 4'b1011;
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16'b0001_0000_0000_0000: rdptr_d1 = 4'b1100;
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16'b0010_0000_0000_0000: rdptr_d1 = 4'b1101;
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16'b0100_0000_0000_0000: rdptr_d1 = 4'b1110;
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16'b1000_0000_0000_0000: rdptr_d1 = 4'b1111;
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default: rdptr_d1 = 4'bx ;
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endcase
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`ifdef INNO_MUXEX
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`else
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// Checking for Xs on the rd pointer input when read is enabled
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if(rdptr_d1 == 4'bx) begin
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`ifdef MODELSIM
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$display("rf_error"," read pointer error %h ", rdptr_d1[3:0]);
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`else
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$error("rf_error"," read pointer error %h ", rdptr_d1[3:0]);
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`endif
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end
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`endif
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if(rst_tri_en_d1) begin // special case
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dout[127:0] = 128'hFFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF ;
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end
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// RW -conflict case and the case where all wlines are zero
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else if ((( wr_en_d1 & ~rst_tri_en ) && (rd_wl_d1 == wr_wl_d1))||
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((rd_wl_d1 & {16{~rst_tri_en}}) == 16'b0 )) begin
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dout[127:0] = 128'bx ;
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end
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else dout = inq_ary[rdptr_d1];
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end // of if rd_en
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end // if reset_l
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else dout = 128'b0 ;
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end // always @ (...
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//////////////////////////////////////////////////////////////////////
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// Write Operation
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//////////////////////////////////////////////////////////////////////
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always @ (/*AUTOSENSE*/reset_l or rst_tri_en_d1 or wr_en_d1
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or wr_wl_d1 or wrdata_d1)
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begin
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if ( reset_l) begin
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`ifdef INNO_MUXEX
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if(wr_en_d1==1'bx) begin
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// do nothing
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end
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`else
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if(wr_en_d1==1'bx) begin
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`ifdef MODELSIM
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$display("rf_error"," write enable error %b ", wr_en_d1);
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`else
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$error("rf_error"," write enable error %b ", wr_en_d1);
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`endif
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end
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`endif
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else if(wr_en_d1 & ~rst_tri_en ) begin
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case(wr_wl_d1)
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16'b0000_0000_0000_0000: ; // do nothing.
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16'b0000_0000_0000_0001: wrptr_d1 = 4'b0000;
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16'b0000_0000_0000_0010: wrptr_d1 = 4'b0001;
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16'b0000_0000_0000_0100: wrptr_d1 = 4'b0010;
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16'b0000_0000_0000_1000: wrptr_d1 = 4'b0011;
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16'b0000_0000_0001_0000: wrptr_d1 = 4'b0100;
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16'b0000_0000_0010_0000: wrptr_d1 = 4'b0101;
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16'b0000_0000_0100_0000: wrptr_d1 = 4'b0110;
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16'b0000_0000_1000_0000: wrptr_d1 = 4'b0111;
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16'b0000_0001_0000_0000: wrptr_d1 = 4'b1000;
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16'b0000_0010_0000_0000: wrptr_d1 = 4'b1001;
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16'b0000_0100_0000_0000: wrptr_d1 = 4'b1010;
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16'b0000_1000_0000_0000: wrptr_d1 = 4'b1011;
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16'b0001_0000_0000_0000: wrptr_d1 = 4'b1100;
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16'b0010_0000_0000_0000: wrptr_d1 = 4'b1101;
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16'b0100_0000_0000_0000: wrptr_d1 = 4'b1110;
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16'b1000_0000_0000_0000: wrptr_d1 = 4'b1111;
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default: wrptr_d1= 4'bx ;
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endcase
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`ifdef INNO_MUXEX
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if(wr_wl_d1!=16'b0)
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inq_ary[wrptr_d1] = wrdata_d1 ;
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`else
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if(wrptr_d1 == 4'bx) begin
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`ifdef MODELSIM
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$display("rf_error"," write pointer error %h ", wrptr_d1[3:0]);
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`else
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$error("rf_error"," write pointer error %h ", wrptr_d1[3:0]);
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`endif
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end
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else begin
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if(wr_wl_d1!=16'b0)
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inq_ary[wrptr_d1] = wrdata_d1 ;
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end
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`endif
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end
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else begin
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// do nothing
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end
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end // of if reset_l
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end // always @ (...
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endmodule // rf_16x128d
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