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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: bw_r_rf32x108.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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////////////////////////////////////////////////////////////////////////
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// 32 X 108 R1 W1 RF macro
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// REad/Write ports can be accessed in PH1 only.
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////////////////////////////////////////////////////////////////////////
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module bw_r_rf32x108(/*AUTOARG*/
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// Outputs
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dout, so,
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// Inputs
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din, rd_adr1, rd_adr2, sel_rdaddr1, wr_adr, read_en, wr_en,
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word_wen, rst_tri_en, rclk, se, si, reset_l, sehold
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);
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input [107:0] din; // data input
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input [4:0] rd_adr1; // read addr1
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input [4:0] rd_adr2; // read addr2
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input sel_rdaddr1; // sel read addr1
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input [4:0] wr_adr; // write addr
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input read_en;
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input wr_en ; // used in conjunction with
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// word_wen and byte_wen
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input [3:0] word_wen; // word enables ( if you don't use these
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// tie them to Vdd )
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input rst_tri_en ; // used to gate off write during scan.
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input rclk;
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input se, si ;
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input reset_l;
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input sehold; // hold scan in data.
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output [107:0] dout;
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output so;
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// local signals
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reg [107:0] wrdata_d1 ;
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reg [3:0] word_wen_d1;
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reg [4:0] rdptr_d1, wrptr_d1;
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reg ren_d1;
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reg wr_en_d1;
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reg rst_tri_en_d1;
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`ifdef DEFINE_0IN
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reg so;
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`else
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reg [107:0] dout;
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wire [122:0] scan_out ;
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// memory array
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reg [107:0] inq_ary [31:0];
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`endif
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// internal variable
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integer i;
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reg [107:0] temp, data_in, tmp_dout;
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`ifdef DEFINE_0IN
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wire [107:0] bit_en_d1;
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assign bit_en_d1[0] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[1] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[2] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[3] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[4] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[5] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[6] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[7] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[8] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[9] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[10] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[11] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[12] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[13] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[14] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[15] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[16] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[17] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[18] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[19] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[20] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[21] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[22] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[23] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[24] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[25] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[26] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[27] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[28] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[29] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[30] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[31] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[32] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[33] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[34] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[35] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[36] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[37] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[38] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[39] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[40] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[41] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[42] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[43] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[44] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[45] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[46] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[47] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[48] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[49] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[50] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[51] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[52] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[53] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[54] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[55] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[56] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[57] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[58] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[59] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[60] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[61] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[62] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[63] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[64] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[65] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[66] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[67] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[68] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[69] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[70] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[71] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[72] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[73] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[74] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[75] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[76] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[77] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[78] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[79] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[80] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[81] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[82] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[83] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[84] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[85] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[86] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[87] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[88] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[89] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[90] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[91] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[92] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[93] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[94] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[95] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[96] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[97] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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| 203 |
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assign bit_en_d1[98] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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| 204 |
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assign bit_en_d1[99] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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| 206 |
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assign bit_en_d1[100] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[101] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[102] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[103] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[104] = word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[105] = word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[106] = word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ;
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assign bit_en_d1[107] = word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ;
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`else
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`endif
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always @(posedge rclk ) begin
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wrdata_d1 <= (sehold)? wrdata_d1 :din;
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word_wen_d1 <= (sehold)? word_wen_d1 : word_wen ;
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wrptr_d1 <= (sehold)? wrptr_d1 :wr_adr;
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ren_d1 <= (sehold)? ren_d1 : read_en;
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wr_en_d1 <= (sehold)? wr_en_d1 : wr_en;
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rdptr_d1 <= (sehold)? rdptr_d1 : ( (sel_rdaddr1)? rd_adr1: rd_adr2 ) ;
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rst_tri_en_d1 <= rst_tri_en ; // this is a dummy flop ( only used as a trigger )
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end
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| 230 |
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| 231 |
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| 232 |
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| 233 |
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`ifdef DEFINE_0IN
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| 234 |
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rf32x108 rf32x108 ( .rclk(rclk), .radr(rdptr_d1), .wadr(wrptr_d1), .ren(ren_d1),
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| 235 |
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.we(reset_l), .wm(bit_en_d1), .din(wrdata_d1), .dout(dout) );
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| 236 |
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`else
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| 237 |
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| 238 |
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/////////////////////////////////////////////////////////////////////////////////
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| 239 |
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// Read Operation
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| 240 |
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/////////////////////////////////////////////////////////////////////////////////
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| 241 |
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| 242 |
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always @(/*AUTOSENSE*/ /*memory or*/ rdptr_d1 or ren_d1 or reset_l
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| 243 |
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or rst_tri_en_d1 or word_wen_d1 or wr_en_d1 or wrptr_d1)
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| 244 |
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begin
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| 245 |
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if (reset_l)
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| 246 |
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begin
|
| 247 |
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if (ren_d1 )
|
| 248 |
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begin
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| 249 |
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|
| 250 |
|
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// Checking for Xs on the rd pointer input when read is enabled
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| 251 |
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`ifdef INNO_MUXEX
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| 252 |
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`else
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| 253 |
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if(rdptr_d1 == 5'bx) begin
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| 254 |
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`ifdef MODELSIM
|
| 255 |
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$display("rf_error"," read pointer error %h ", rdptr_d1[4:0]);
|
| 256 |
|
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`else
|
| 257 |
|
|
$error("rf_error"," read pointer error %h ", rdptr_d1[4:0]);
|
| 258 |
|
|
`endif
|
| 259 |
|
|
end
|
| 260 |
|
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`endif
|
| 261 |
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|
| 262 |
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|
| 263 |
|
|
tmp_dout = inq_ary[rdptr_d1] ;
|
| 264 |
|
|
|
| 265 |
|
|
for(i=0; i< 108; i=i+4) begin
|
| 266 |
|
|
|
| 267 |
|
|
if((rdptr_d1 == wrptr_d1)) begin
|
| 268 |
|
|
dout[i] = ( word_wen_d1[0] & wr_en_d1 & ~rst_tri_en )?
|
| 269 |
|
|
1'bx : tmp_dout[i] ;
|
| 270 |
|
|
dout[i+1] = ( word_wen_d1[1] & wr_en_d1 & ~rst_tri_en )?
|
| 271 |
|
|
1'bx : tmp_dout[i+1] ;
|
| 272 |
|
|
dout[i+2] = ( word_wen_d1[2] & wr_en_d1 & ~rst_tri_en )?
|
| 273 |
|
|
1'bx : tmp_dout[i+2] ;
|
| 274 |
|
|
dout[i+3] = ( word_wen_d1[3] & wr_en_d1 & ~rst_tri_en )?
|
| 275 |
|
|
1'bx : tmp_dout[i+3] ;
|
| 276 |
|
|
end
|
| 277 |
|
|
else begin
|
| 278 |
|
|
dout[i] = tmp_dout[i] ;
|
| 279 |
|
|
dout[i+1] = tmp_dout[i+1] ;
|
| 280 |
|
|
dout[i+2] = tmp_dout[i+2] ;
|
| 281 |
|
|
dout[i+3] = tmp_dout[i+3] ;
|
| 282 |
|
|
end
|
| 283 |
|
|
|
| 284 |
|
|
end // of for
|
| 285 |
|
|
|
| 286 |
|
|
end
|
| 287 |
|
|
|
| 288 |
|
|
|
| 289 |
|
|
end // of if reset_l
|
| 290 |
|
|
|
| 291 |
|
|
else dout = 108'b0 ;
|
| 292 |
|
|
end
|
| 293 |
|
|
|
| 294 |
|
|
/////////////////////////////////////////////////////////////////////////////////
|
| 295 |
|
|
// Write Operation
|
| 296 |
|
|
/////////////////////////////////////////////////////////////////////////////////
|
| 297 |
|
|
|
| 298 |
|
|
always @(/*AUTOSENSE*/reset_l or rst_tri_en_d1 or word_wen_d1 or wr_en_d1
|
| 299 |
|
|
or wrdata_d1 or wrptr_d1)
|
| 300 |
|
|
begin
|
| 301 |
|
|
if ( reset_l)
|
| 302 |
|
|
begin
|
| 303 |
|
|
// Checking for Xs on bit write enables that are derived from
|
| 304 |
|
|
// the word_enables and wr enable input.
|
| 305 |
|
|
`ifdef INNO_MUXEX
|
| 306 |
|
|
`else
|
| 307 |
|
|
if((word_wen_d1 & {4{wr_en_d1 & ~rst_tri_en}}) == 4'bx ) begin
|
| 308 |
|
|
`ifdef MODELSIM
|
| 309 |
|
|
$display("rf_error"," write enable error %h ", word_wen_d1[3:0]);
|
| 310 |
|
|
`else
|
| 311 |
|
|
$error("rf_error"," write enable error %h ", word_wen_d1[3:0]);
|
| 312 |
|
|
`endif
|
| 313 |
|
|
end
|
| 314 |
|
|
`endif
|
| 315 |
|
|
|
| 316 |
|
|
if(wr_en_d1 & ~rst_tri_en) begin
|
| 317 |
|
|
|
| 318 |
|
|
`ifdef INNO_MUXEX
|
| 319 |
|
|
`else
|
| 320 |
|
|
// Checking for Xs on the wr pointer input when write is enabled
|
| 321 |
|
|
if(wrptr_d1 == 5'bx) begin
|
| 322 |
|
|
`ifdef MODELSIM
|
| 323 |
|
|
$display("rf_error"," read pointer error %h ", wrptr_d1[4:0]);
|
| 324 |
|
|
`else
|
| 325 |
|
|
$error("rf_error"," read pointer error %h ", wrptr_d1[4:0]);
|
| 326 |
|
|
`endif
|
| 327 |
|
|
end
|
| 328 |
|
|
`endif
|
| 329 |
|
|
|
| 330 |
|
|
temp = inq_ary[wrptr_d1];
|
| 331 |
|
|
for (i=0; i<108; i=i+4) begin
|
| 332 |
|
|
data_in[i] = ( word_wen_d1[0] & wr_en_d1 & ~rst_tri_en ) ?
|
| 333 |
|
|
wrdata_d1[i] : temp[i] ;
|
| 334 |
|
|
data_in[i+1] = ( word_wen_d1[1] & wr_en_d1 & ~rst_tri_en ) ?
|
| 335 |
|
|
wrdata_d1[i+1] : temp[i+1] ;
|
| 336 |
|
|
data_in[i+2] = ( word_wen_d1[2] & wr_en_d1 & ~rst_tri_en ) ?
|
| 337 |
|
|
wrdata_d1[i+2] : temp[i+2] ;
|
| 338 |
|
|
data_in[i+3] = ( word_wen_d1[3] & wr_en_d1 & ~rst_tri_en ) ?
|
| 339 |
|
|
wrdata_d1[i+3] : temp[i+3] ;
|
| 340 |
|
|
end
|
| 341 |
|
|
inq_ary[wrptr_d1] = data_in ;
|
| 342 |
|
|
|
| 343 |
|
|
end
|
| 344 |
|
|
|
| 345 |
|
|
end
|
| 346 |
|
|
end // always @ (...
|
| 347 |
|
|
|
| 348 |
|
|
`endif
|
| 349 |
|
|
|
| 350 |
|
|
|
| 351 |
|
|
endmodule // rf_32x108
|
| 352 |
|
|
|
| 353 |
|
|
|
| 354 |
|
|
|
