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// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T1 Processor File: bw_r_rf32x80.v
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
// 
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
// 
// The above named program is distributed in the hope that it will be 
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// General Public License for more details.
// 
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
// 
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
//      Description:    Trap Stack Array
//                      - Dual-Ported.
//                      - Port1 - Write Port; Used by wrpr, trap insertion.
//                      Write occurs in W Stage. (M1:M2:W).
//                      - Port2 - Read Port; Used by rdpr, done/retry.
//                      Read occurs in E Stage.
//                      - Arranged as 6(trap-levels/thread) x 4 threads = 24 entries.
//                      Trap-level and thread id used to index array.
*/
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
 
//FPGA_SYN enables all FPGA related modifications
`ifdef FPGA_SYN
`define FPGA_SYN_32x80
`endif
 
`ifdef FPGA_SYN_32x80
module bw_r_rf32x80 (/*AUTOARG*/
   // Outputs
   dout, so,
   // Inputs
   rd_en, rd_adr, wr_en, nib_wr_en, wr_adr, din,
   si, se, sehold, rclk, rst_tri_en, reset_l);
 
parameter NUM_TPL = 6 ;                 // 6 supported trap levels.
parameter NUM_ENTRIES = 32 ;    // 8 entries per thread
 
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
input [4:0]   rd_adr;      // read adr. 
input         rd_en;      // read pointer
input         wr_en;      // write pointer vld
input [19:0]  nib_wr_en;  // enable write of a byte in tsa. 
input [4:0]   wr_adr;      // write adr.
input [79:0] din;              // wr data for tsa.
input             rclk;       // clock
input         reset_l;    // active low reset
input         rst_tri_en; // reset and scan  
input         sehold;     // scan hold 
input             si;             // scan in 
input             se;             // scan enable 
 
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
output  [79:0] dout ; // rd data for tsa.
output                  so ;   // scan out write 
 
wire [79:0]    dout;
wire clk;
wire wr_vld, wr_vld_d1;
 
reg     [79:0]           tsa_rdata;
reg [79:0]     local_dout;
// reg                  so; 
 
integer i,j;
 
wire    [79:0]   write_mask;
wire    [79:0]   write_mask_d1;
//
// added for atpg support
wire [4:0]   sehold_rd_adr;         // output of sehold mux - read adr. 
wire         sehold_rd_en;         // output of sehold mux - read pointer
wire         sehold_wr_en;         // output of sehold mux - write pointer vld
wire [19:0]  sehold_nib_wr_en; // output of sehold mux - enable write of a byte in tsa. 
wire  [4:0]   sehold_wr_adr;        // output of sehold mux - write adr.
wire [79:0]  sehold_din;    // wr data for tsa.
 
reg [4:0]   rd_adr_d1;      // flopped read adr. 
wire         rd_en_d1;     // flopped read pointer
wire         wr_en_d1;     // flopped write pointer vld
wire [19:0]  nib_wr_en_d1; // flopped enable write of a byte in tsa. 
reg [4:0]   wr_adr_d1;      // flopped write adr.
wire [79:0]  din_d1;        // flopped wr data for tsa.
// wire [5:0]   local_scan1;
// wire [25:0]  local_scan2;
// wire [78:0]  local_scan3;
 
//
// creating local clock
assign clk=rclk;
// 
//=========================================================================================
//      support for atpg pattern generation
//=========================================================================================
//
// read controls
dp_mux2es #(1) mux_sehold_rd_ctrl (
    .in0  ({rd_en}),
    .in1  ({rd_en_d1}),
    .sel  (sehold),
    .dout ({sehold_rd_en})
);
//
// modified to match circuit implementataion
dff_s #(1) dff_rd_ctrl_d1(
    .din ({sehold_rd_en}),
    .q   ({rd_en_d1}),
    .clk (clk),
    .se  (se),
    .si  (),
    .so  ()
);
//
// write controls
// modified to match circuit implementataion
dp_mux2es #(21) mux_sehold_wr_ctrl (
        .in0    ({nib_wr_en[19:0], wr_en}),
        .in1    ({nib_wr_en_d1[19:0], wr_en_d1}),
        .sel    (sehold),
        .dout   ({sehold_nib_wr_en[19:0], sehold_wr_en})
);
 
// modified to match circuit implementataion
dff_s #(21) dff_wr_ctrl_d1(
    .din ({sehold_nib_wr_en[19:0], sehold_wr_en}),
    .q   ({nib_wr_en_d1[19:0], wr_en_d1}),
    .clk (clk),
    .se  (se),
    .si  (),
    .so  ()
);
//
// write data
dp_mux2es #(80) mux_sehold_din (
        .in0    (din[79:0]),
        .in1    (din_d1[79:0]),
        .sel    (sehold),
        .dout   (sehold_din[79:0])
);
 
dff_s #(80) dff_din_d1(
    .din (sehold_din[79:0]),
    .q   (din_d1[79:0]),
    .clk (clk),
    .se  (se),
    .si  (),
    .so  ()
);
 
//
// diable write to register file during reset or scan
// assign wr_vld = sehold_wr_en & ~rst_tri_en & reset_l; 
assign wr_vld = sehold_wr_en & ~rst_tri_en;
assign wr_vld_d1 = wr_en_d1 & ~rst_tri_en;
 
//    always @ (posedge clk)
//      begin
//         so <= 1'bx;
//      end
 
//=========================================================================================
//      generate wordlines
//=========================================================================================
 
// Word-Line Generation skipped. Implicit in read and write.
 
//=========================================================================================
//      write or read to/from memory
//=========================================================================================
// creating the write mask from the nibble enable controls
 
assign  write_mask[79:0] =
        {{4{sehold_nib_wr_en[19]}},
         {4{sehold_nib_wr_en[18]}},
     {4{sehold_nib_wr_en[17]}},
         {4{sehold_nib_wr_en[16]}},
         {4{sehold_nib_wr_en[15]}},
         {4{sehold_nib_wr_en[14]}},
         {4{sehold_nib_wr_en[13]}},
         {4{sehold_nib_wr_en[12]}},
         {4{sehold_nib_wr_en[11]}},
         {4{sehold_nib_wr_en[10]}},
         {4{sehold_nib_wr_en[9]}},
         {4{sehold_nib_wr_en[8]}},
         {4{sehold_nib_wr_en[7]}},
         {4{sehold_nib_wr_en[6]}},
         {4{sehold_nib_wr_en[5]}},
         {4{sehold_nib_wr_en[4]}},
         {4{sehold_nib_wr_en[3]}},
         {4{sehold_nib_wr_en[2]}},
         {4{sehold_nib_wr_en[1]}},
         {4{sehold_nib_wr_en[0]}}
        };
 
assign  write_mask_d1[79:0] =
        {{4{nib_wr_en_d1[19]}},
         {4{nib_wr_en_d1[18]}},
     {4{nib_wr_en_d1[17]}},
         {4{nib_wr_en_d1[16]}},
         {4{nib_wr_en_d1[15]}},
         {4{nib_wr_en_d1[14]}},
         {4{nib_wr_en_d1[13]}},
         {4{nib_wr_en_d1[12]}},
         {4{nib_wr_en_d1[11]}},
         {4{nib_wr_en_d1[10]}},
         {4{nib_wr_en_d1[9]}},
         {4{nib_wr_en_d1[8]}},
         {4{nib_wr_en_d1[7]}},
         {4{nib_wr_en_d1[6]}},
         {4{nib_wr_en_d1[5]}},
         {4{nib_wr_en_d1[4]}},
         {4{nib_wr_en_d1[3]}},
         {4{nib_wr_en_d1[2]}},
         {4{nib_wr_en_d1[1]}},
         {4{nib_wr_en_d1[0]}}
        };
 
reg     [79:0]   tsa_mem [NUM_ENTRIES-1:0] /* synthesis syn_ramstyle = block_ram  syn_ramstyle = no_rw_check */ ;
 
reg     [79:0]           temp_tlvl;
wire    [79:0]           temp_tlvl2;
 
 
 
always @(posedge clk) begin
  rd_adr_d1 <= sehold_rd_adr;
  wr_adr_d1 <= sehold_wr_adr;
end
 
assign sehold_wr_adr = sehold ? wr_adr_d1 : wr_adr;
assign sehold_rd_adr = sehold ? rd_adr_d1 : rd_adr;
 
assign temp_tlvl2 = tsa_mem[sehold_rd_adr[4:0]];
 
always @(posedge clk)
  if(~reset_l)
    local_dout[79:0] <= 80'b0;
  else
   if (sehold_rd_en)
     local_dout[79:0] <= temp_tlvl2;
 
always @ ( posedge clk) begin
        temp_tlvl[79:0] = tsa_mem[sehold_wr_adr];
        if (wr_vld & reset_l) begin
                tsa_mem[sehold_wr_adr] = (temp_tlvl[79:0] & ~write_mask[79:0]) | (sehold_din[79:0] &  write_mask[79:0]) ;
        end
end
 
 
assign dout[79:0] = local_dout;
 
 
 
endmodule
 
`else
 
module bw_r_rf32x80 (/*AUTOARG*/
   // Outputs
   dout, so,
   // Inputs
   rd_en, rd_adr, wr_en, nib_wr_en, wr_adr, din,
   si, se, sehold, rclk, rst_tri_en, reset_l);
 
parameter NUM_TPL = 6 ;                 // 6 supported trap levels.
parameter NUM_ENTRIES = 32 ;    // 8 entries per thread
 
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
input [4:0]   rd_adr;      // read adr. 
input         rd_en;      // read pointer
input         wr_en;      // write pointer vld
input [19:0]  nib_wr_en;  // enable write of a byte in tsa. 
input [4:0]   wr_adr;      // write adr.
input [79:0] din;              // wr data for tsa.
input             rclk;       // clock
input         reset_l;    // active low reset
input         rst_tri_en; // reset and scan  
input         sehold;     // scan hold 
input             si;             // scan in 
input             se;             // scan enable 
 
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
output  [79:0] dout ; // rd data for tsa.
output                  so ;   // scan out write 
 
wire [79:0]    dout;
wire clk;
wire wr_vld, wr_vld_d1;
 
reg     [79:0]           tsa_mem [NUM_ENTRIES-1:0];
reg     [79:0]           tsa_rdata;
reg [79:0]     local_dout;
reg     [79:0]           temp_tlvl;
// reg                  so; 
 
integer i,j;
 
wire    [79:0]   write_mask;
wire    [79:0]   write_mask_d1;
//
// added for atpg support
wire [4:0]   sehold_rd_adr;         // output of sehold mux - read adr. 
wire         sehold_rd_en;         // output of sehold mux - read pointer
wire         sehold_wr_en;         // output of sehold mux - write pointer vld
wire [19:0]  sehold_nib_wr_en; // output of sehold mux - enable write of a byte in tsa. 
wire [4:0]   sehold_wr_adr;         // output of sehold mux - write adr.
wire [79:0]  sehold_din;    // wr data for tsa.
 
wire [4:0]   rd_adr_d1;     // flopped read adr. 
wire         rd_en_d1;     // flopped read pointer
wire         wr_en_d1;     // flopped write pointer vld
wire [19:0]  nib_wr_en_d1; // flopped enable write of a byte in tsa. 
wire [4:0]   wr_adr_d1;     // flopped write adr.
wire [79:0]  din_d1;        // flopped wr data for tsa.
// wire [5:0]   local_scan1;
// wire [25:0]  local_scan2;
// wire [78:0]  local_scan3;
 
//
// creating local clock
assign clk=rclk;
// 
//=========================================================================================
//      support for atpg pattern generation
//=========================================================================================
//
// read controls
dp_mux2es #(6) mux_sehold_rd_ctrl (
    .in0  ({rd_adr[4:0], rd_en}),
    .in1  ({rd_adr_d1[4:0], rd_en_d1}),
    .sel  (sehold),
    .dout ({sehold_rd_adr[4:0],sehold_rd_en})
);
//
// modified to match circuit implementataion
dff_s #(6) dff_rd_ctrl_d1(
    .din ({sehold_rd_adr[4:0], sehold_rd_en}),
    .q   ({rd_adr_d1[4:0], rd_en_d1}),
    .clk (clk),
    .se  (se),
    .si  (),
    .so  ()
);
//
// write controls
// modified to match circuit implementataion
dp_mux2es #(26) mux_sehold_wr_ctrl (
        .in0    ({nib_wr_en[19:0], wr_adr[4:0], wr_en}),
        .in1    ({nib_wr_en_d1[19:0], wr_adr_d1[4:0], wr_en_d1}),
        .sel    (sehold),
        .dout   ({sehold_nib_wr_en[19:0], sehold_wr_adr[4:0],sehold_wr_en})
);
 
// modified to match circuit implementataion
dff_s #(26) dff_wr_ctrl_d1(
    .din ({sehold_nib_wr_en[19:0], sehold_wr_adr[4:0], sehold_wr_en}),
    .q   ({nib_wr_en_d1[19:0], wr_adr_d1[4:0], wr_en_d1}),
    .clk (clk),
    .se  (se),
    .si  (),
    .so  ()
);
//
// write data
dp_mux2es #(80) mux_sehold_din (
        .in0    (din[79:0]),
        .in1    (din_d1[79:0]),
        .sel    (sehold),
        .dout   (sehold_din[79:0])
);
 
dff_s #(80) dff_din_d1(
    .din (sehold_din[79:0]),
    .q   (din_d1[79:0]),
    .clk (clk),
    .se  (se),
    .si  (),
    .so  ()
);
 
//
// diable write to register file during reset or scan
// assign wr_vld = sehold_wr_en & ~rst_tri_en & reset_l; 
assign wr_vld = sehold_wr_en & ~rst_tri_en;
assign wr_vld_d1 = wr_en_d1 & ~rst_tri_en;
 
//    always @ (posedge clk)
//      begin
//         so <= 1'bx;
//      end
 
//=========================================================================================
//      generate wordlines
//=========================================================================================
 
// Word-Line Generation skipped. Implicit in read and write.
 
//=========================================================================================
//      write or read to/from memory
//=========================================================================================
// creating the write mask from the nibble enable controls
 
assign  write_mask[79:0] =
        {{4{sehold_nib_wr_en[19]}},
         {4{sehold_nib_wr_en[18]}},
     {4{sehold_nib_wr_en[17]}},
         {4{sehold_nib_wr_en[16]}},
         {4{sehold_nib_wr_en[15]}},
         {4{sehold_nib_wr_en[14]}},
         {4{sehold_nib_wr_en[13]}},
         {4{sehold_nib_wr_en[12]}},
         {4{sehold_nib_wr_en[11]}},
         {4{sehold_nib_wr_en[10]}},
         {4{sehold_nib_wr_en[9]}},
         {4{sehold_nib_wr_en[8]}},
         {4{sehold_nib_wr_en[7]}},
         {4{sehold_nib_wr_en[6]}},
         {4{sehold_nib_wr_en[5]}},
         {4{sehold_nib_wr_en[4]}},
         {4{sehold_nib_wr_en[3]}},
         {4{sehold_nib_wr_en[2]}},
         {4{sehold_nib_wr_en[1]}},
         {4{sehold_nib_wr_en[0]}}
        };
 
assign  write_mask_d1[79:0] =
        {{4{nib_wr_en_d1[19]}},
         {4{nib_wr_en_d1[18]}},
     {4{nib_wr_en_d1[17]}},
         {4{nib_wr_en_d1[16]}},
         {4{nib_wr_en_d1[15]}},
         {4{nib_wr_en_d1[14]}},
         {4{nib_wr_en_d1[13]}},
         {4{nib_wr_en_d1[12]}},
         {4{nib_wr_en_d1[11]}},
         {4{nib_wr_en_d1[10]}},
         {4{nib_wr_en_d1[9]}},
         {4{nib_wr_en_d1[8]}},
         {4{nib_wr_en_d1[7]}},
         {4{nib_wr_en_d1[6]}},
         {4{nib_wr_en_d1[5]}},
         {4{nib_wr_en_d1[4]}},
         {4{nib_wr_en_d1[3]}},
         {4{nib_wr_en_d1[2]}},
         {4{nib_wr_en_d1[1]}},
         {4{nib_wr_en_d1[0]}}
        };
 
always @ ( negedge reset_l)
        begin
        local_dout[79:0] <= 80'h0;
    end
 
always @ ( posedge reset_l)
        begin
            if (rd_en_d1 & clk)
                      begin
                            if (wr_vld_d1 & (wr_adr_d1[4:0] == rd_adr_d1[4:0]) )
                                    local_dout[79:0] <= 80'hx;
                                else
                                    for (j=0;j<NUM_ENTRIES;j=j+1)
                                            begin
                                                    if (rd_adr_d1[4:0] == j)
                                                        local_dout[79:0] <= tsa_mem[j] ;
                                            end
                      end
        end
 
 
 
 
always @ ( posedge reset_l)
        begin
                if (wr_vld_d1 & clk)
                        for (i=0;i<NUM_ENTRIES;i=i+1)
                                begin
                                if (wr_adr_d1[4:0] == i)
                                        begin
                                        // read
                                        temp_tlvl[79:0] = tsa_mem[i];
                                        // modify & write
                                        tsa_mem[i] =
                                        (temp_tlvl[79:0] & ~write_mask_d1[79:0]) |
                                        (din_d1[79:0] &  write_mask_d1[79:0]) ;
                                        end
                                end
        end
 
 
always @ ( posedge clk)
        begin
                if (wr_vld & reset_l)
                        for (i=0;i<NUM_ENTRIES;i=i+1)
                                begin
                                if (sehold_wr_adr[4:0] == i)
                                        begin
                                        // read
                                        temp_tlvl[79:0] = tsa_mem[i];
                                        // modify & write
                                        tsa_mem[i] =
                                        (temp_tlvl[79:0] & ~write_mask[79:0]) |
                                        (sehold_din[79:0] &  write_mask[79:0]) ;
                                        end
                                end
        end
 
always @ ( posedge clk )
        begin
              begin
                                if (sehold_rd_en & reset_l)
                                        begin
                                                if (wr_vld & (sehold_wr_adr[4:0] == sehold_rd_adr[4:0]) )
                                                        local_dout[79:0] <= 80'hx;
                                                else
                                                        for (j=0;j<NUM_ENTRIES;j=j+1)
                                                        begin
                                                                if (sehold_rd_adr[4:0] == j)
                                                                local_dout[79:0] <= tsa_mem[j] ;
                                                        end
                                        end
            end
        end
 
assign dout[79:0] = local_dout[79:0];
 
 
endmodule
`endif
 

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[/] [sparc64soc/] [trunk/] [T1-common/] [srams/] [bw_r_rf32x80.v] - Blame information for rev 7

Line No.	Rev	Author	Line
1	2	dmitryr	`// ========== Copyright Header Begin ==========================================`
2			`//`
3			`// OpenSPARC T1 Processor File: bw_r_rf32x80.v`
4			`// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.`
5			`// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.`
6			`//`
7			`// The above named program is free software; you can redistribute it and/or`
8			`// modify it under the terms of the GNU General Public`
9			`// License version 2 as published by the Free Software Foundation.`
10			`//`
11			`// The above named program is distributed in the hope that it will be`
12			`// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
14			`// General Public License for more details.`
15			`//`
16			`// You should have received a copy of the GNU General Public`
17			`// License along with this work; if not, write to the Free Software`
18			`// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.`
19			`//`
20			`// ========== Copyright Header End ============================================`
21			`////////////////////////////////////////////////////////////////////////`
22			`/*`
23			`// Description: Trap Stack Array`
24			`// - Dual-Ported.`
25			`// - Port1 - Write Port; Used by wrpr, trap insertion.`
26			`// Write occurs in W Stage. (M1:M2:W).`
27			`// - Port2 - Read Port; Used by rdpr, done/retry.`
28			`// Read occurs in E Stage.`
29			`// - Arranged as 6(trap-levels/thread) x 4 threads = 24 entries.`
30			`// Trap-level and thread id used to index array.`
31			`*/`
32			`////////////////////////////////////////////////////////////////////////`
33			`// Local header file includes / local defines`
34			`////////////////////////////////////////////////////////////////////////`
35
36			`//FPGA_SYN enables all FPGA related modifications`
37			`ifdef FPGA_SYN
38			`define FPGA_SYN_32x80
39			`endif
40
41			`ifdef FPGA_SYN_32x80
42			`module bw_r_rf32x80 (/AUTOARG/`
43			`// Outputs`
44			`dout, so,`
45			`// Inputs`
46			`rd_en, rd_adr, wr_en, nib_wr_en, wr_adr, din,`
47			`si, se, sehold, rclk, rst_tri_en, reset_l);`
48
49			`parameter NUM_TPL = 6 ; // 6 supported trap levels.`
50			`parameter NUM_ENTRIES = 32 ; // 8 entries per thread`
51
52			`/AUTOINPUT/`
53			`// Beginning of automatic inputs (from unused autoinst inputs)`
54			`// End of automatics`
55			`input [4:0] rd_adr; // read adr.`
56			`input rd_en; // read pointer`
57			`input wr_en; // write pointer vld`
58			`input [19:0] nib_wr_en; // enable write of a byte in tsa.`
59			`input [4:0] wr_adr; // write adr.`
60			`input [79:0] din; // wr data for tsa.`
61			`input rclk; // clock`
62			`input reset_l; // active low reset`
63			`input rst_tri_en; // reset and scan`
64			`input sehold; // scan hold`
65			`input si; // scan in`
66			`input se; // scan enable`
67
68			`/AUTOOUTPUT/`
69			`// Beginning of automatic outputs (from unused autoinst outputs)`
70			`// End of automatics`
71			`output [79:0] dout ; // rd data for tsa.`
72			`output so ; // scan out write`
73
74			`wire [79:0] dout;`
75			`wire clk;`
76			`wire wr_vld, wr_vld_d1;`
77
78			`reg [79:0] tsa_rdata;`
79			`reg [79:0] local_dout;`
80			`// reg so;`
81
82			`integer i,j;`
83
84			`wire [79:0] write_mask;`
85			`wire [79:0] write_mask_d1;`
86			`//`
87			`// added for atpg support`
88			`wire [4:0] sehold_rd_adr; // output of sehold mux - read adr.`
89			`wire sehold_rd_en; // output of sehold mux - read pointer`
90			`wire sehold_wr_en; // output of sehold mux - write pointer vld`
91			`wire [19:0] sehold_nib_wr_en; // output of sehold mux - enable write of a byte in tsa.`
92			`wire [4:0] sehold_wr_adr; // output of sehold mux - write adr.`
93			`wire [79:0] sehold_din; // wr data for tsa.`
94
95			`reg [4:0] rd_adr_d1; // flopped read adr.`
96			`wire rd_en_d1; // flopped read pointer`
97			`wire wr_en_d1; // flopped write pointer vld`
98			`wire [19:0] nib_wr_en_d1; // flopped enable write of a byte in tsa.`
99			`reg [4:0] wr_adr_d1; // flopped write adr.`
100			`wire [79:0] din_d1; // flopped wr data for tsa.`
101			`// wire [5:0] local_scan1;`
102			`// wire [25:0] local_scan2;`
103			`// wire [78:0] local_scan3;`
104
105			`//`
106			`// creating local clock`
107			`assign clk=rclk;`
108			`//`
109			`//=========================================================================================`
110			`// support for atpg pattern generation`
111			`//=========================================================================================`
112			`//`
113			`// read controls`
114			`dp_mux2es #(1) mux_sehold_rd_ctrl (`
115			`.in0 ({rd_en}),`
116			`.in1 ({rd_en_d1}),`
117			`.sel (sehold),`
118			`.dout ({sehold_rd_en})`
119			`);`
120			`//`
121			`// modified to match circuit implementataion`
122			`dff_s #(1) dff_rd_ctrl_d1(`
123			`.din ({sehold_rd_en}),`
124			`.q ({rd_en_d1}),`
125			`.clk (clk),`
126			`.se (se),`
127			`.si (),`
128			`.so ()`
129			`);`
130			`//`
131			`// write controls`
132			`// modified to match circuit implementataion`
133			`dp_mux2es #(21) mux_sehold_wr_ctrl (`
134			`.in0 ({nib_wr_en[19:0], wr_en}),`
135			`.in1 ({nib_wr_en_d1[19:0], wr_en_d1}),`
136			`.sel (sehold),`
137			`.dout ({sehold_nib_wr_en[19:0], sehold_wr_en})`
138			`);`
139
140			`// modified to match circuit implementataion`
141			`dff_s #(21) dff_wr_ctrl_d1(`
142			`.din ({sehold_nib_wr_en[19:0], sehold_wr_en}),`
143			`.q ({nib_wr_en_d1[19:0], wr_en_d1}),`
144			`.clk (clk),`
145			`.se (se),`
146			`.si (),`
147			`.so ()`
148			`);`
149			`//`
150			`// write data`
151			`dp_mux2es #(80) mux_sehold_din (`
152			`.in0 (din[79:0]),`
153			`.in1 (din_d1[79:0]),`
154			`.sel (sehold),`
155			`.dout (sehold_din[79:0])`
156			`);`
157
158			`dff_s #(80) dff_din_d1(`
159			`.din (sehold_din[79:0]),`
160			`.q (din_d1[79:0]),`
161			`.clk (clk),`
162			`.se (se),`
163			`.si (),`
164			`.so ()`
165			`);`
166
167			`//`
168			`// diable write to register file during reset or scan`
169			`// assign wr_vld = sehold_wr_en & ~rst_tri_en & reset_l;`
170			`assign wr_vld = sehold_wr_en & ~rst_tri_en;`
171			`assign wr_vld_d1 = wr_en_d1 & ~rst_tri_en;`
172
173			`// always @ (posedge clk)`
174			`// begin`
175			`// so <= 1'bx;`
176			`// end`
177
178			`//=========================================================================================`
179			`// generate wordlines`
180			`//=========================================================================================`
181
182			`// Word-Line Generation skipped. Implicit in read and write.`
183
184			`//=========================================================================================`
185			`// write or read to/from memory`
186			`//=========================================================================================`
187			`// creating the write mask from the nibble enable controls`
188
189			`assign write_mask[79:0] =`
190			`{{4{sehold_nib_wr_en[19]}},`
191			`{4{sehold_nib_wr_en[18]}},`
192			`{4{sehold_nib_wr_en[17]}},`
193			`{4{sehold_nib_wr_en[16]}},`
194			`{4{sehold_nib_wr_en[15]}},`
195			`{4{sehold_nib_wr_en[14]}},`
196			`{4{sehold_nib_wr_en[13]}},`
197			`{4{sehold_nib_wr_en[12]}},`
198			`{4{sehold_nib_wr_en[11]}},`
199			`{4{sehold_nib_wr_en[10]}},`
200			`{4{sehold_nib_wr_en[9]}},`
201			`{4{sehold_nib_wr_en[8]}},`
202			`{4{sehold_nib_wr_en[7]}},`
203			`{4{sehold_nib_wr_en[6]}},`
204			`{4{sehold_nib_wr_en[5]}},`
205			`{4{sehold_nib_wr_en[4]}},`
206			`{4{sehold_nib_wr_en[3]}},`
207			`{4{sehold_nib_wr_en[2]}},`
208			`{4{sehold_nib_wr_en[1]}},`
209			`{4{sehold_nib_wr_en[0]}}`
210			`};`
211
212			`assign write_mask_d1[79:0] =`
213			`{{4{nib_wr_en_d1[19]}},`
214			`{4{nib_wr_en_d1[18]}},`
215			`{4{nib_wr_en_d1[17]}},`
216			`{4{nib_wr_en_d1[16]}},`
217			`{4{nib_wr_en_d1[15]}},`
218			`{4{nib_wr_en_d1[14]}},`
219			`{4{nib_wr_en_d1[13]}},`
220			`{4{nib_wr_en_d1[12]}},`
221			`{4{nib_wr_en_d1[11]}},`
222			`{4{nib_wr_en_d1[10]}},`
223			`{4{nib_wr_en_d1[9]}},`
224			`{4{nib_wr_en_d1[8]}},`
225			`{4{nib_wr_en_d1[7]}},`
226			`{4{nib_wr_en_d1[6]}},`
227			`{4{nib_wr_en_d1[5]}},`
228			`{4{nib_wr_en_d1[4]}},`
229			`{4{nib_wr_en_d1[3]}},`
230			`{4{nib_wr_en_d1[2]}},`
231			`{4{nib_wr_en_d1[1]}},`
232			`{4{nib_wr_en_d1[0]}}`
233			`};`
234
235			`reg [79:0] tsa_mem [NUM_ENTRIES-1:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;`
236
237			`reg [79:0] temp_tlvl;`
238			`wire [79:0] temp_tlvl2;`
239
240
241
242			`always @(posedge clk) begin`
243			`rd_adr_d1 <= sehold_rd_adr;`
244			`wr_adr_d1 <= sehold_wr_adr;`
245			`end`
246
247			`assign sehold_wr_adr = sehold ? wr_adr_d1 : wr_adr;`
248			`assign sehold_rd_adr = sehold ? rd_adr_d1 : rd_adr;`
249
250			`assign temp_tlvl2 = tsa_mem[sehold_rd_adr[4:0]];`
251
252			`always @(posedge clk)`
253			`if(~reset_l)`
254			`local_dout[79:0] <= 80'b0;`
255			`else`
256			`if (sehold_rd_en)`
257			`local_dout[79:0] <= temp_tlvl2;`
258
259			`always @ ( posedge clk) begin`
260			`temp_tlvl[79:0] = tsa_mem[sehold_wr_adr];`
261			`if (wr_vld & reset_l) begin`
262			`tsa_mem[sehold_wr_adr] = (temp_tlvl[79:0] & ~write_mask[79:0]) \| (sehold_din[79:0] & write_mask[79:0]) ;`
263			`end`
264			`end`
265
266
267			`assign dout[79:0] = local_dout;`
268
269
270
271			`endmodule`
272
273			`else
274
275			`module bw_r_rf32x80 (/AUTOARG/`
276			`// Outputs`
277			`dout, so,`
278			`// Inputs`
279			`rd_en, rd_adr, wr_en, nib_wr_en, wr_adr, din,`
280			`si, se, sehold, rclk, rst_tri_en, reset_l);`
281
282			`parameter NUM_TPL = 6 ; // 6 supported trap levels.`
283			`parameter NUM_ENTRIES = 32 ; // 8 entries per thread`
284
285			`/AUTOINPUT/`
286			`// Beginning of automatic inputs (from unused autoinst inputs)`
287			`// End of automatics`
288			`input [4:0] rd_adr; // read adr.`
289			`input rd_en; // read pointer`
290			`input wr_en; // write pointer vld`
291			`input [19:0] nib_wr_en; // enable write of a byte in tsa.`
292			`input [4:0] wr_adr; // write adr.`
293			`input [79:0] din; // wr data for tsa.`
294			`input rclk; // clock`
295			`input reset_l; // active low reset`
296			`input rst_tri_en; // reset and scan`
297			`input sehold; // scan hold`
298			`input si; // scan in`
299			`input se; // scan enable`
300
301			`/AUTOOUTPUT/`
302			`// Beginning of automatic outputs (from unused autoinst outputs)`
303			`// End of automatics`
304			`output [79:0] dout ; // rd data for tsa.`
305			`output so ; // scan out write`
306
307			`wire [79:0] dout;`
308			`wire clk;`
309			`wire wr_vld, wr_vld_d1;`
310
311			`reg [79:0] tsa_mem [NUM_ENTRIES-1:0];`
312			`reg [79:0] tsa_rdata;`
313			`reg [79:0] local_dout;`
314			`reg [79:0] temp_tlvl;`
315			`// reg so;`
316
317			`integer i,j;`
318
319			`wire [79:0] write_mask;`
320			`wire [79:0] write_mask_d1;`
321			`//`
322			`// added for atpg support`
323			`wire [4:0] sehold_rd_adr; // output of sehold mux - read adr.`
324			`wire sehold_rd_en; // output of sehold mux - read pointer`
325			`wire sehold_wr_en; // output of sehold mux - write pointer vld`
326			`wire [19:0] sehold_nib_wr_en; // output of sehold mux - enable write of a byte in tsa.`
327			`wire [4:0] sehold_wr_adr; // output of sehold mux - write adr.`
328			`wire [79:0] sehold_din; // wr data for tsa.`
329
330			`wire [4:0] rd_adr_d1; // flopped read adr.`
331			`wire rd_en_d1; // flopped read pointer`
332			`wire wr_en_d1; // flopped write pointer vld`
333			`wire [19:0] nib_wr_en_d1; // flopped enable write of a byte in tsa.`
334			`wire [4:0] wr_adr_d1; // flopped write adr.`
335			`wire [79:0] din_d1; // flopped wr data for tsa.`
336			`// wire [5:0] local_scan1;`
337			`// wire [25:0] local_scan2;`
338			`// wire [78:0] local_scan3;`
339
340			`//`
341			`// creating local clock`
342			`assign clk=rclk;`
343			`//`
344			`//=========================================================================================`
345			`// support for atpg pattern generation`
346			`//=========================================================================================`
347			`//`
348			`// read controls`
349			`dp_mux2es #(6) mux_sehold_rd_ctrl (`
350			`.in0 ({rd_adr[4:0], rd_en}),`
351			`.in1 ({rd_adr_d1[4:0], rd_en_d1}),`
352			`.sel (sehold),`
353			`.dout ({sehold_rd_adr[4:0],sehold_rd_en})`
354			`);`
355			`//`
356			`// modified to match circuit implementataion`
357			`dff_s #(6) dff_rd_ctrl_d1(`
358			`.din ({sehold_rd_adr[4:0], sehold_rd_en}),`
359			`.q ({rd_adr_d1[4:0], rd_en_d1}),`
360			`.clk (clk),`
361			`.se (se),`
362			`.si (),`
363			`.so ()`
364			`);`
365			`//`
366			`// write controls`
367			`// modified to match circuit implementataion`
368			`dp_mux2es #(26) mux_sehold_wr_ctrl (`
369			`.in0 ({nib_wr_en[19:0], wr_adr[4:0], wr_en}),`
370			`.in1 ({nib_wr_en_d1[19:0], wr_adr_d1[4:0], wr_en_d1}),`
371			`.sel (sehold),`
372			`.dout ({sehold_nib_wr_en[19:0], sehold_wr_adr[4:0],sehold_wr_en})`
373			`);`
374
375			`// modified to match circuit implementataion`
376			`dff_s #(26) dff_wr_ctrl_d1(`
377			`.din ({sehold_nib_wr_en[19:0], sehold_wr_adr[4:0], sehold_wr_en}),`
378			`.q ({nib_wr_en_d1[19:0], wr_adr_d1[4:0], wr_en_d1}),`
379			`.clk (clk),`
380			`.se (se),`
381			`.si (),`
382			`.so ()`
383			`);`
384			`//`
385			`// write data`
386			`dp_mux2es #(80) mux_sehold_din (`
387			`.in0 (din[79:0]),`
388			`.in1 (din_d1[79:0]),`
389			`.sel (sehold),`
390			`.dout (sehold_din[79:0])`
391			`);`
392
393			`dff_s #(80) dff_din_d1(`
394			`.din (sehold_din[79:0]),`
395			`.q (din_d1[79:0]),`
396			`.clk (clk),`
397			`.se (se),`
398			`.si (),`
399			`.so ()`
400			`);`
401
402			`//`
403			`// diable write to register file during reset or scan`
404			`// assign wr_vld = sehold_wr_en & ~rst_tri_en & reset_l;`
405			`assign wr_vld = sehold_wr_en & ~rst_tri_en;`
406			`assign wr_vld_d1 = wr_en_d1 & ~rst_tri_en;`
407
408			`// always @ (posedge clk)`
409			`// begin`
410			`// so <= 1'bx;`
411			`// end`
412
413			`//=========================================================================================`
414			`// generate wordlines`
415			`//=========================================================================================`
416
417			`// Word-Line Generation skipped. Implicit in read and write.`
418
419			`//=========================================================================================`
420			`// write or read to/from memory`
421			`//=========================================================================================`
422			`// creating the write mask from the nibble enable controls`
423
424			`assign write_mask[79:0] =`
425			`{{4{sehold_nib_wr_en[19]}},`
426			`{4{sehold_nib_wr_en[18]}},`
427			`{4{sehold_nib_wr_en[17]}},`
428			`{4{sehold_nib_wr_en[16]}},`
429			`{4{sehold_nib_wr_en[15]}},`
430			`{4{sehold_nib_wr_en[14]}},`
431			`{4{sehold_nib_wr_en[13]}},`
432			`{4{sehold_nib_wr_en[12]}},`
433			`{4{sehold_nib_wr_en[11]}},`
434			`{4{sehold_nib_wr_en[10]}},`
435			`{4{sehold_nib_wr_en[9]}},`
436			`{4{sehold_nib_wr_en[8]}},`
437			`{4{sehold_nib_wr_en[7]}},`
438			`{4{sehold_nib_wr_en[6]}},`
439			`{4{sehold_nib_wr_en[5]}},`
440			`{4{sehold_nib_wr_en[4]}},`
441			`{4{sehold_nib_wr_en[3]}},`
442			`{4{sehold_nib_wr_en[2]}},`
443			`{4{sehold_nib_wr_en[1]}},`
444			`{4{sehold_nib_wr_en[0]}}`
445			`};`
446
447			`assign write_mask_d1[79:0] =`
448			`{{4{nib_wr_en_d1[19]}},`
449			`{4{nib_wr_en_d1[18]}},`
450			`{4{nib_wr_en_d1[17]}},`
451			`{4{nib_wr_en_d1[16]}},`
452			`{4{nib_wr_en_d1[15]}},`
453			`{4{nib_wr_en_d1[14]}},`
454			`{4{nib_wr_en_d1[13]}},`
455			`{4{nib_wr_en_d1[12]}},`
456			`{4{nib_wr_en_d1[11]}},`
457			`{4{nib_wr_en_d1[10]}},`
458			`{4{nib_wr_en_d1[9]}},`
459			`{4{nib_wr_en_d1[8]}},`
460			`{4{nib_wr_en_d1[7]}},`
461			`{4{nib_wr_en_d1[6]}},`
462			`{4{nib_wr_en_d1[5]}},`
463			`{4{nib_wr_en_d1[4]}},`
464			`{4{nib_wr_en_d1[3]}},`
465			`{4{nib_wr_en_d1[2]}},`
466			`{4{nib_wr_en_d1[1]}},`
467			`{4{nib_wr_en_d1[0]}}`
468			`};`
469
470			`always @ ( negedge reset_l)`
471			`begin`
472			`local_dout[79:0] <= 80'h0;`
473			`end`
474
475			`always @ ( posedge reset_l)`
476			`begin`
477			`if (rd_en_d1 & clk)`
478			`begin`
479			`if (wr_vld_d1 & (wr_adr_d1[4:0] == rd_adr_d1[4:0]) )`
480			`local_dout[79:0] <= 80'hx;`
481			`else`
482			`for (j=0;j<NUM_ENTRIES;j=j+1)`
483			`begin`
484			`if (rd_adr_d1[4:0] == j)`
485			`local_dout[79:0] <= tsa_mem[j] ;`
486			`end`
487			`end`
488			`end`
489
490
491
492
493			`always @ ( posedge reset_l)`
494			`begin`
495			`if (wr_vld_d1 & clk)`
496			`for (i=0;i<NUM_ENTRIES;i=i+1)`
497			`begin`
498			`if (wr_adr_d1[4:0] == i)`
499			`begin`
500			`// read`
501			`temp_tlvl[79:0] = tsa_mem[i];`
502			`// modify & write`
503			`tsa_mem[i] =`
504			`(temp_tlvl[79:0] & ~write_mask_d1[79:0]) \|`
505			`(din_d1[79:0] & write_mask_d1[79:0]) ;`
506			`end`
507			`end`
508			`end`
509
510
511			`always @ ( posedge clk)`
512			`begin`
513			`if (wr_vld & reset_l)`
514			`for (i=0;i<NUM_ENTRIES;i=i+1)`
515			`begin`
516			`if (sehold_wr_adr[4:0] == i)`
517			`begin`
518			`// read`
519			`temp_tlvl[79:0] = tsa_mem[i];`
520			`// modify & write`
521			`tsa_mem[i] =`
522			`(temp_tlvl[79:0] & ~write_mask[79:0]) \|`
523			`(sehold_din[79:0] & write_mask[79:0]) ;`
524			`end`
525			`end`
526			`end`
527
528			`always @ ( posedge clk )`
529			`begin`
530			`begin`
531			`if (sehold_rd_en & reset_l)`
532			`begin`
533			`if (wr_vld & (sehold_wr_adr[4:0] == sehold_rd_adr[4:0]) )`
534			`local_dout[79:0] <= 80'hx;`
535			`else`
536			`for (j=0;j<NUM_ENTRIES;j=j+1)`
537			`begin`
538			`if (sehold_rd_adr[4:0] == j)`
539			`local_dout[79:0] <= tsa_mem[j] ;`
540			`end`
541			`end`
542			`end`
543			`end`
544
545			`assign dout[79:0] = local_dout[79:0];`
546
547
548			`endmodule`
549			`endif
550