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dmitryr |
// ========== Copyright Header Begin ==========================================
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//
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// OpenSPARC T1 Processor File: bw_r_tlb.v
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// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
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// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
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//
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// The above named program is free software; you can redistribute it and/or
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// modify it under the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// The above named program is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// General Public License for more details.
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//
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// You should have received a copy of the GNU General Public
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// License along with this work; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// ========== Copyright Header End ============================================
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///////////////////////////////////////////////////////////////////////
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/*
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// Description: Common TLB for Instruction Fetch and Load/Stores
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*/
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////////////////////////////////////////////////////////////////////////
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// Global header file includes
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////////////////////////////////////////////////////////////////////////
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`include "sys.h" // system level definition file which contains the
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// time scale definition
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////////////////////////////////////////////////////////////////////////
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// Local header file includes / local defines
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////////////////////////////////////////////////////////////////////////
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`include "lsu.h"
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//FPGA_SYN enables all FPGA related modifications
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`ifdef FPGA_SYN
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`define FPGA_SYN_TLB
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`endif
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`ifdef FPGA_SYN_TLB
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`ifdef FPGA_SYN_8TLB
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`define TLB_ENTRIES 8
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`define TLB_INDEX_WIDTH 3
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`else
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`ifdef FPGA_SYN_16TLB
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`define TLB_ENTRIES 16
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`define TLB_INDEX_WIDTH 4
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`else
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`ifdef FPGA_SYN_32TLB
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`define TLB_ENTRIES 32
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`define TLB_INDEX_WIDTH 5
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`else
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`define TLB_ENTRIES 64
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`define TLB_INDEX_WIDTH 6
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`endif
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`endif
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`endif
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module bw_r_tlb ( /*AUTOARG*/
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// Outputs
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tlb_rd_tte_tag, tlb_rd_tte_data, tlb_pgnum, tlb_pgnum_crit,
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tlb_cam_hit, cache_way_hit, cache_hit, so,
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// Inputs
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tlb_cam_vld, tlb_cam_key, tlb_cam_pid,
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tlb_demap_key, tlb_addr_mask_l, tlb_ctxt,
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tlb_wr_vld, tlb_wr_tte_tag, tlb_wr_tte_data, tlb_rd_tag_vld,
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tlb_rd_data_vld, tlb_rw_index, tlb_rw_index_vld, tlb_demap,
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tlb_demap_auto, tlb_demap_all, cache_ptag_w0, cache_ptag_w1,
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cache_ptag_w2, cache_ptag_w3, cache_set_vld, tlb_bypass_va,
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tlb_bypass, se, si, hold, adj, arst_l, rst_soft_l, rclk,
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rst_tri_en
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) ;
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input tlb_cam_vld ; // ld/st requires xlation.
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input [40:0] tlb_cam_key ; // cam data for loads/stores;includes vld
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// CHANGE : add real bit for cam.
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input [2:0] tlb_cam_pid ; // NEW: pid for cam.
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input [40:0] tlb_demap_key ; // cam data for demap; includes vlds.
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// CHANGE : add real bit for demap
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input tlb_addr_mask_l ; // address masking occurs
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input [12:0] tlb_ctxt ; // context for cam xslate/demap.
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input tlb_wr_vld; // write to tlb.
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input [58:0] tlb_wr_tte_tag; // CHANGE:tte tag to be written (55+4-1)
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// R(+1b),PID(+3b),G(-1b).
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input [42:0] tlb_wr_tte_data; // tte data to be written.
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// No change(!!!) - G bit becomes spare
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input tlb_rd_tag_vld ; // read tag
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input tlb_rd_data_vld ; // read data
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input [5:0] tlb_rw_index ; // index to read/write tlb.
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input tlb_rw_index_vld ; // indexed write else use algorithm.
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input tlb_demap ; // demap : page/ctxt/all/auto.
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input tlb_demap_auto ; // demap is of type auto
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input tlb_demap_all; // demap-all operation : encoded separately.
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input [29:0] cache_ptag_w0; // way1 30b(D)/29b(I) tag.
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input [29:0] cache_ptag_w1; // way2 30b(D)/29b(I) tag.
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input [29:0] cache_ptag_w2; // way0 30b(D)/29b(I) tag.
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input [29:0] cache_ptag_w3; // way3 30b(D)/29b(I) tag.
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input [3:0] cache_set_vld; // set vld-4 ways
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input [12:10] tlb_bypass_va; // bypass va.other va bits from cam-data
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input tlb_bypass; // bypass tlb xslation
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input se ; // scan-enable ; unused
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input si ; // scan data in ; unused
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input hold ; // scan hold signal
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input [7:0] adj ; // self-time adjustment ; unused
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input arst_l ; // synchronous for tlb ; unused
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input rst_soft_l ; // software reset - asi
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input rclk;
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input rst_tri_en ;
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output [58:0] tlb_rd_tte_tag; // CHANGE: tte tag read from tlb.
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output [42:0] tlb_rd_tte_data; // tte data read from tlb.
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// Need two ports for tlb_pgnum - critical and non-critical.
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output [39:10] tlb_pgnum ; // bypass or xslated pgnum
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output [39:10] tlb_pgnum_crit ; // bypass or xslated pgnum - critical
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output tlb_cam_hit ; // xlation hits in tlb.
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output [3:0] cache_way_hit; // tag comparison results.
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output cache_hit; // tag comparison result - 'or' of above.
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//output tlb_writeable ; // tlb can be written in current cycle.
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output so ; // scan data out ; unused
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wire [53:0] tlb_cam_data ;
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wire [58:0] wr_tte_tag ; // CHANGE
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wire [42:0] wr_tte_data ;
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wire [29:3] phy_pgnum_m;
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wire [29:0] pgnum_m;
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wire [`TLB_ENTRIES-1:0] used ;
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wire tlb_not_writeable ;
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wire [40:25] tlb_cam_key_masked ;
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wire [26:0] tlb_cam_comp_key ;
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wire cam_vld ;
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wire demap_other ;
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wire [3:0] cache_way_hit ;
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wire [`TLB_ENTRIES-1:0] mismatch;
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reg tlb_not_writeable_d1 ;
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reg tlb_writeable ;
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wire [`TLB_ENTRIES-1:0] tlb_entry_locked ;
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wire [`TLB_ENTRIES-1:0] cam_hit ;
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wire [`TLB_ENTRIES-1:0] demap_hit ;
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reg [`TLB_ENTRIES-1:0] ademap_hit ;
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wire [58:0] rd_tte_tag ; // CHANGE
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wire [42:0] rd_tte_data ;
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reg [42:0] tlb_rd_tte_data ;
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reg cam_vld_tmp ;
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reg [2:0] cam_pid ;
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reg [53:0] cam_data ;
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reg demap_auto, demap_other_tmp, demap_all ;
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reg [`TLB_ENTRIES-1:0] tlb_entry_vld ;
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wire [`TLB_ENTRIES-1:0] tlb_entry_used ;
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reg [`TLB_ENTRIES-1:0] tlb_entry_replace ;
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reg [`TLB_ENTRIES-1:0] tlb_entry_replace_d2 ;
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reg [29:0] pgnum_g ;
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reg [3:0] cache_set_vld_g;
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reg [29:0] cache_ptag_w0_g,cache_ptag_w1_g;
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reg [29:0] cache_ptag_w2_g,cache_ptag_w3_g;
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reg [`TLB_ENTRIES-1:0] rw_wdline ;
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reg rd_tag;
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reg rd_data;
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reg wr_vld_tmp;
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reg [`TLB_INDEX_WIDTH-1:0] rw_index;
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reg rw_index_vld;
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wire [29:0] vrtl_pgnum_m;
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wire bypass ;
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wire wr_vld ;
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integer i,j,k,l,m,n,p,r,s,t,u,w;
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`define CAM_CTXT_12_0_HI 12 // 13b ctxt
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`define CAM_CTXT_12_0_LO 0
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//=========================================================================================
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// What's Left :
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//=========================================================================================
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// Scan Insertion - scan to be ignored in formal verification for now.
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//=========================================================================================
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// Design Notes.
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//=========================================================================================
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// - Supported Demap Operations - By Page, By Context, All But
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// Locked, Autodemap, Invalidate-All i.e., reset. Demap Partition is
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// not supported - it is mapped to demap-all by logic.
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// - Interpretation of demap inputs
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// - tlb_demap - this is used to signal demap by page, by ctxt
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// ,all, and autodemap.
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// - tlb_demap_ctxt - If a demap_by_ctxt operation is occuring then
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// this signal and tlb_demap must be active.
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// - tlb_demap_all - demap all operation. If a demap_all operation is
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// occuring, then tlb_demap_all must be asserted with tlb_demap.
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// - Reset is similar to demap-all except that *all* entries
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// are invalidated. The action is initiated by software. The reset occurs
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// on the negedge and is synchronous with the clk.
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// - TTE Tag and Data
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// - The TTE tag and data can be read together. Each will have its
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// own bus and the muxing will occur externally. The tag needs to
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// be read on a data request to supply the valid bit.
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// - The TTE tag and data can be written together.
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// - The cam hit is a separate output signal based on the
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// the match signals.
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// - Read/Write may occur based on supplied index. If not valid
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// then use replacement way determined by algorithm to write.
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// - Only write can use replacement way determined by algorithm.
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// - Data is formatted appr. on read or write in the MMU.
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// - The TLB will generate a signal which reports whether the
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// tlb can be filled in the current cycle or not.
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// **Physical Tag Comparison**
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// For I-SIDE, comparison is of 28b, whereas for D-side, comparison is of 29b. The actual
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// comparison, due to legacy, is for 30b.
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// For the I-TLB, va[11:10] must be hardwired to the same value as the lsb of the 4 tags
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// at the port level. Since the itag it only 28b, add two least significant bits to extend it to 30b.
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// Similarly, for the dside, va[10] needs to be made same.
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// **Differentiating among Various TLB Operations**
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// Valid bits are now associated with the key to allow selective incorporation of
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// match results. The 5 valid bits are : v4(b47-28),v3(b27-22),v2(21-16),v1(b15-13)
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// and Gk(G bit for auto-demap). The rules of use are :
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// - cam: v4-v1 are set high. G=~cam_real=0/1.
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// - demap_by_page : v4-v1 are set high. G=1. cam_real=0.
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// - demap_by_ctxt : v4-v1 are low. G=1. cam_real=0
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// - demap_all : v4-v1 are don't-care. G=x. cam_real=x
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// - autodemap : v4-v1 are based on page size of incoming tte. G=~cam_real=0/1.
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// Note : Gk is now used only to void a context match on a Real Translation.
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// In general, if a valid bit is low then the corresponding va field will not take
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// part in the match. Similarly, for the ctxt, if Gk=1, the ctxt will participate
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// in the match.
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//
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// Demap Table (For Satya) :
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// Note : To include a context match, Gk must be set to 1.
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//--------------------------------------------------------------------------------------------------------
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//tlb_demap tlb_demap_all tlb_ctxt Gk Vk4 Vk3 Vk2 Vk1 Real Operation
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//--------------------------------------------------------------------------------------------------------
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//0 x x x x x x x 0 No demap operation
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//1 0 0 1 1 1 1 1 0 Demap by page
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//1 0 0 1 1 0 0 0 0/1 256M demap(auto demap)
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//1 0 0 0 1 0 0 0 0 256M demap(auto demap) (*Illgl*)
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//1 0 0 1 1 1 0 0 0/1 4M demap(auto demap)
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//1 0 0 0 1 1 0 0 0 4M demap(auto demap) (*Illgl*)
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//1 0 0 1 1 1 1 0 0/1 64k demap(auto demap)
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//1 0 0 0 1 1 1 0 0 64k demap(auto demap) (*Illgl*)
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//1 0 0 1 1 1 1 1 0/1 8k demap(auto demap)
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//1 0 0 0 1 1 1 1 0 8k demap(auto demap) (*Illgl*)
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//1 0 1 1 0 0 0 0 0 demap by ctxt
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//1 1 x x x x x x 0 demap_all
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//------------------------------------------------------------------------------------------
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//-----
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//All other are illegal combinations
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//
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//=========================================================================================
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// Changes related to Hypervisor/Legacy Compatibility
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//=========================================================================================
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//
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// - Add PID. PID does not effect demap-all. Otherwise it is included in cam, other demap
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// operations and auto-demap.
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// - Add R. Real translation ignores context. This is controlled externally by Gk.
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// - Remove G bit for tte. Input remains in demap-key/cam-key to allow for disabling
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// of context match Real Translation
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// - Final Page Size support - 8KB,64KB,4M,256M
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// - SPARC_HPV_EN has been defined to enable new tlb design support.
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// Issues :
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// -Max ptag size is now 28b. Satya, will this help the speed at all. I doubt it !
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//=========================================================================================
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// Miscellaneous
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//=========================================================================================
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wire clk;
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assign clk = rclk;
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wire async_reset, sync_reset ;
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assign async_reset = ~arst_l ; // hardware
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assign sync_reset = (~rst_soft_l & ~rst_tri_en) ; // software
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wire rw_disable ;
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// INNO - wr/rd gated off. Note required as rst_tri_en is
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// asserted, but implemented in addition in schematic.
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assign rw_disable = ~arst_l | rst_tri_en ;
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reg [`TLB_INDEX_WIDTH-1:0] cam_hit_encoded;
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integer ii;
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reg cam_hit_any;
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always @(cam_hit) begin
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cam_hit_any = 1'b0;
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cam_hit_encoded = {`TLB_INDEX_WIDTH{1'b0}};
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for(ii=0;ii<`TLB_ENTRIES;ii=ii+1) begin
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if(cam_hit[ii]) begin
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cam_hit_encoded = ii;
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cam_hit_any = 1'b1;
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end
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end
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|
end
|
302 |
|
|
|
303 |
|
|
reg cam_hit_any_or_bypass;
|
304 |
|
|
|
305 |
|
|
always @(posedge clk)
|
306 |
|
|
cam_hit_any_or_bypass <= cam_hit_any | bypass;
|
307 |
|
|
|
308 |
|
|
|
309 |
|
|
|
310 |
|
|
//=========================================================================================
|
311 |
|
|
// Stage Data
|
312 |
|
|
//=========================================================================================
|
313 |
|
|
// Apply address masking
|
314 |
|
|
assign tlb_cam_key_masked[40:25]
|
315 |
|
|
= {16{tlb_addr_mask_l}} &
|
316 |
|
|
tlb_cam_key[`CAM_VA_47_28_HI:`CAM_VA_47_28_LO+4] ;
|
317 |
|
|
|
318 |
|
|
// Reconstitute cam data CHANGE : add additional bit for real mapping
|
319 |
|
|
assign tlb_cam_data[53:13] = tlb_demap ?
|
320 |
|
|
tlb_demap_key[40:0] :
|
321 |
|
|
{tlb_cam_key_masked[40:25],tlb_cam_key[`CAM_VA_47_28_LO+3:0]} ;
|
322 |
|
|
|
323 |
|
|
assign tlb_cam_comp_key[26:0] =
|
324 |
|
|
tlb_demap ?
|
325 |
|
|
{tlb_demap_key[32:21], tlb_demap_key[19:14],tlb_demap_key[12:7],
|
326 |
|
|
tlb_demap_key[5:3]} :
|
327 |
|
|
{tlb_cam_key_masked[32:25],tlb_cam_key[24:21],
|
328 |
|
|
tlb_cam_key[19:14],tlb_cam_key[12:7],tlb_cam_key[5:3]} ;
|
329 |
|
|
|
330 |
|
|
assign tlb_cam_data[12:0] = tlb_ctxt[12:0] ;
|
331 |
|
|
|
332 |
|
|
// These signals are flow-thru.
|
333 |
|
|
assign wr_tte_tag[58:0] = tlb_wr_tte_tag[58:0] ; // CHANGE
|
334 |
|
|
assign wr_tte_data[42:0] = tlb_wr_tte_data[42:0] ;
|
335 |
|
|
|
336 |
|
|
// CHANGE(SATYA) - Currently the rw_index/rw_index_vld are shared by both reads
|
337 |
|
|
// and writes. However, writes are done in the cycle of broadcast, whereas
|
338 |
|
|
// the reads are done a cycle later, as given in the model(incorrect)
|
339 |
|
|
// They have to be treated uniformly. To make the model work, I've assumed the read/write
|
340 |
|
|
// are done in the cycle the valids are broadcast.
|
341 |
|
|
always @ (posedge clk)
|
342 |
|
|
begin
|
343 |
|
|
if (hold)
|
344 |
|
|
begin
|
345 |
|
|
cam_pid[2:0] <= cam_pid[2:0] ;
|
346 |
|
|
cam_vld_tmp <= cam_vld_tmp ;
|
347 |
|
|
cam_data[53:0] <= cam_data[53:0] ;
|
348 |
|
|
demap_other_tmp <= demap_other_tmp ;
|
349 |
|
|
demap_auto <= demap_auto ;
|
350 |
|
|
demap_all <= demap_all ;
|
351 |
|
|
wr_vld_tmp <= wr_vld_tmp ;
|
352 |
|
|
rd_tag <= rd_tag ;
|
353 |
|
|
rd_data <= rd_data ;
|
354 |
|
|
rw_index_vld <= rw_index_vld ;
|
355 |
|
|
rw_index[`TLB_INDEX_WIDTH-1:0] <= rw_index[`TLB_INDEX_WIDTH-1:0] ;
|
356 |
|
|
end
|
357 |
|
|
else
|
358 |
|
|
begin
|
359 |
|
|
cam_pid[2:0] <= tlb_cam_pid[2:0] ;
|
360 |
|
|
cam_vld_tmp <= tlb_cam_vld ;
|
361 |
|
|
cam_data[53:0] <= tlb_cam_data[53:0] ;
|
362 |
|
|
demap_other_tmp <= tlb_demap ;
|
363 |
|
|
demap_auto <= tlb_demap_auto ;
|
364 |
|
|
demap_all <= tlb_demap_all ;
|
365 |
|
|
wr_vld_tmp <= tlb_wr_vld ;
|
366 |
|
|
rd_tag <= tlb_rd_tag_vld ;
|
367 |
|
|
rd_data <= tlb_rd_data_vld ;
|
368 |
|
|
rw_index_vld <= tlb_rw_index_vld ;
|
369 |
|
|
rw_index[`TLB_INDEX_WIDTH-1:0] <= tlb_rw_index[`TLB_INDEX_WIDTH-1:0] ;
|
370 |
|
|
end
|
371 |
|
|
|
372 |
|
|
end
|
373 |
|
|
|
374 |
|
|
// INNO - gate cam,demap,wr with rst_tri_en.
|
375 |
|
|
reg rst_tri_en_lat;
|
376 |
|
|
|
377 |
|
|
always @ (clk)
|
378 |
|
|
rst_tri_en_lat = rst_tri_en;
|
379 |
|
|
|
380 |
|
|
assign cam_vld = cam_vld_tmp & ~rst_tri_en_lat ;
|
381 |
|
|
assign demap_other = demap_other_tmp & ~rst_tri_en ;
|
382 |
|
|
assign wr_vld = wr_vld_tmp & ~rst_tri_en ;
|
383 |
|
|
|
384 |
|
|
//=========================================================================================
|
385 |
|
|
// Generate Write Wordlines
|
386 |
|
|
//=========================================================================================
|
387 |
|
|
|
388 |
|
|
|
389 |
|
|
assign tlb_rd_tte_tag[58:0] = rd_tte_tag[58:0] ; // CHANGE
|
390 |
|
|
|
391 |
|
|
// Stage to next cycle.
|
392 |
|
|
always @ (posedge clk)
|
393 |
|
|
begin
|
394 |
|
|
tlb_rd_tte_data[42:0] <= rd_tte_data[42:0] ;
|
395 |
|
|
end
|
396 |
|
|
|
397 |
|
|
//=========================================================================================
|
398 |
|
|
// CAM/DEMAP STLB for xlation
|
399 |
|
|
//=========================================================================================
|
400 |
|
|
|
401 |
|
|
|
402 |
|
|
// Demap and CAM operation are mutually exclusive.
|
403 |
|
|
|
404 |
|
|
always @ ( negedge clk )
|
405 |
|
|
begin
|
406 |
|
|
|
407 |
|
|
for (n=0;n<`TLB_ENTRIES;n=n+1)
|
408 |
|
|
begin
|
409 |
|
|
if (demap_auto & demap_other)
|
410 |
|
|
ademap_hit[n] = (~mismatch[n] & demap_other & tlb_entry_vld[n]) ;
|
411 |
|
|
end
|
412 |
|
|
|
413 |
|
|
end // always
|
414 |
|
|
|
415 |
|
|
|
416 |
|
|
assign tlb_cam_hit = |cam_hit[`TLB_ENTRIES-1:0] ;
|
417 |
|
|
|
418 |
|
|
// Change tlb_entry_vld handling for multi-threaded tlb writes.
|
419 |
|
|
// A write is always preceeded by an autodemap. The intent is to make the result of autodemap
|
420 |
|
|
// (clearing of vld bit if hit) invisible until write occurs. In the same cycle that the write
|
421 |
|
|
// occurs, the vld bit for an entry will be cleared if there is an autodemap hit. The write
|
422 |
|
|
// and admp action may even be to same entry. The write must dominate. There is no need to
|
423 |
|
|
// clear the dmp latches after the write/clear has occurred as the subsequent admp will set
|
424 |
|
|
// up new state in the latches.
|
425 |
|
|
|
426 |
|
|
// Define valid bit based on write/demap/reset.
|
427 |
|
|
|
428 |
|
|
always @ (/*AUTOSENSE*/rd_data or rd_tag or rw_index or rw_index_vld
|
429 |
|
|
or wr_vld_tmp)
|
430 |
|
|
begin
|
431 |
|
|
for (i=0;i<`TLB_ENTRIES;i=i+1)
|
432 |
|
|
if ((rw_index[`TLB_INDEX_WIDTH-1:0] == i) & ((wr_vld_tmp & rw_index_vld) | rd_tag | rd_data))
|
433 |
|
|
rw_wdline[i] = 1'b1 ;
|
434 |
|
|
else rw_wdline[i] = 1'b0 ;
|
435 |
|
|
|
436 |
|
|
end
|
437 |
|
|
|
438 |
|
|
|
439 |
|
|
always @ (negedge clk)
|
440 |
|
|
begin
|
441 |
|
|
for (r=0;r<`TLB_ENTRIES;r=r+1)
|
442 |
|
|
begin // for
|
443 |
|
|
if (((rw_index_vld & rw_wdline[r]) | (~rw_index_vld & tlb_entry_replace_d2[r])) &
|
444 |
|
|
wr_vld & ~rw_disable)
|
445 |
|
|
tlb_entry_vld[r] <= wr_tte_tag[`STLB_TAG_V] ; // write
|
446 |
|
|
else begin
|
447 |
|
|
if (ademap_hit[r] & wr_vld) // autodemap specifically
|
448 |
|
|
tlb_entry_vld[r] <= 1'b0 ;
|
449 |
|
|
end
|
450 |
|
|
if ((demap_hit[r] & ~demap_auto) | sync_reset) // non-auto-demap, reset
|
451 |
|
|
tlb_entry_vld[r] <= 1'b0 ;
|
452 |
|
|
if(async_reset) tlb_entry_vld[r] <= 1'b0 ;
|
453 |
|
|
|
454 |
|
|
end // for
|
455 |
|
|
end
|
456 |
|
|
|
457 |
|
|
|
458 |
|
|
//=========================================================================================
|
459 |
|
|
// TAG COMPARISON
|
460 |
|
|
//=========================================================================================
|
461 |
|
|
|
462 |
|
|
reg [30:0] va_tag_plus ;
|
463 |
|
|
|
464 |
|
|
// Stage to m
|
465 |
|
|
always @(posedge clk)
|
466 |
|
|
begin
|
467 |
|
|
// INNO - add hold to this input
|
468 |
|
|
if (hold)
|
469 |
|
|
va_tag_plus[30:0] <= va_tag_plus[30:0] ;
|
470 |
|
|
else
|
471 |
|
|
va_tag_plus[30:0]
|
472 |
|
|
<= {tlb_cam_comp_key[26:0],tlb_bypass_va[12:10],tlb_bypass};
|
473 |
|
|
end
|
474 |
|
|
|
475 |
|
|
assign vrtl_pgnum_m[29:0] = va_tag_plus[30:1] ;
|
476 |
|
|
assign bypass = va_tag_plus[0] ;
|
477 |
|
|
|
478 |
|
|
// Mux to bypass va or form pa tag based on tte-data.
|
479 |
|
|
|
480 |
|
|
assign phy_pgnum_m[29:3] =
|
481 |
|
|
{rd_tte_data[`STLB_DATA_PA_39_28_HI:`STLB_DATA_PA_39_28_LO],
|
482 |
|
|
rd_tte_data[`STLB_DATA_PA_27_22_HI:`STLB_DATA_PA_27_22_LO],
|
483 |
|
|
rd_tte_data[`STLB_DATA_PA_21_16_HI:`STLB_DATA_PA_21_16_LO],
|
484 |
|
|
rd_tte_data[`STLB_DATA_PA_15_13_HI:`STLB_DATA_PA_15_13_LO]};
|
485 |
|
|
|
486 |
|
|
// Derive the tlb-based physical address.
|
487 |
|
|
assign pgnum_m[2:0] = vrtl_pgnum_m[2:0];
|
488 |
|
|
assign pgnum_m[5:3] = (~rd_tte_data[`STLB_DATA_15_13_SEL] & ~bypass)
|
489 |
|
|
? phy_pgnum_m[5:3] : vrtl_pgnum_m[5:3] ;
|
490 |
|
|
assign pgnum_m[11:6] = (~rd_tte_data[`STLB_DATA_21_16_SEL] & ~bypass)
|
491 |
|
|
? phy_pgnum_m[11:6] : vrtl_pgnum_m[11:6] ;
|
492 |
|
|
assign pgnum_m[17:12] = (~rd_tte_data[`STLB_DATA_27_22_SEL] & ~bypass)
|
493 |
|
|
? phy_pgnum_m[17:12] : vrtl_pgnum_m[17:12] ;
|
494 |
|
|
assign pgnum_m[29:18] = ~bypass ? phy_pgnum_m[29:18] : vrtl_pgnum_m[29:18];
|
495 |
|
|
|
496 |
|
|
// Stage to g
|
497 |
|
|
// Flop tags in tlb itself and do comparison immediately after rising edge.
|
498 |
|
|
// Similarly stage va/pa tag to g
|
499 |
|
|
always @(posedge clk)
|
500 |
|
|
begin
|
501 |
|
|
pgnum_g[29:0] <= pgnum_m[29:0];
|
502 |
|
|
// rm hold on these inputs.
|
503 |
|
|
cache_set_vld_g[3:0] <= cache_set_vld[3:0] ;
|
504 |
|
|
cache_ptag_w0_g[29:0] <= cache_ptag_w0[29:0] ;
|
505 |
|
|
cache_ptag_w1_g[29:0] <= cache_ptag_w1[29:0] ;
|
506 |
|
|
cache_ptag_w2_g[29:0] <= cache_ptag_w2[29:0] ;
|
507 |
|
|
cache_ptag_w3_g[29:0] <= cache_ptag_w3[29:0] ;
|
508 |
|
|
end
|
509 |
|
|
|
510 |
|
|
|
511 |
|
|
// Need to stage by a cycle where used.
|
512 |
|
|
assign tlb_pgnum[39:10] = pgnum_g[29:0] ;
|
513 |
|
|
// Same cycle as cam - meant for one load on critical path
|
514 |
|
|
assign tlb_pgnum_crit[39:10] = pgnum_m[29:0] ;
|
515 |
|
|
|
516 |
|
|
|
517 |
|
|
assign cache_way_hit[0] =
|
518 |
|
|
(cache_ptag_w0_g[29:0] == pgnum_g[29:0]) & cache_set_vld_g[0] & cam_hit_any_or_bypass;
|
519 |
|
|
assign cache_way_hit[1] =
|
520 |
|
|
(cache_ptag_w1_g[29:0] == pgnum_g[29:0]) & cache_set_vld_g[1] & cam_hit_any_or_bypass;
|
521 |
|
|
assign cache_way_hit[2] =
|
522 |
|
|
(cache_ptag_w2_g[29:0] == pgnum_g[29:0]) & cache_set_vld_g[2] & cam_hit_any_or_bypass;
|
523 |
|
|
assign cache_way_hit[3] =
|
524 |
|
|
(cache_ptag_w3_g[29:0] == pgnum_g[29:0]) & cache_set_vld_g[3] & cam_hit_any_or_bypass;
|
525 |
|
|
|
526 |
|
|
assign cache_hit = |cache_way_hit[3:0];
|
527 |
|
|
|
528 |
|
|
|
529 |
|
|
//=========================================================================================
|
530 |
|
|
// TLB ENTRY REPLACEMENT
|
531 |
|
|
//=========================================================================================
|
532 |
|
|
|
533 |
|
|
// A single Used bit is used to track the replacement state of each entry.
|
534 |
|
|
// Only an unused entry can be replaced.
|
535 |
|
|
// An Unused entry is :
|
536 |
|
|
// - an invalid entry
|
537 |
|
|
// - a valid entry which has had its Used bit cleared.
|
538 |
|
|
// - on write of a valid entry, the Used bit is set.
|
539 |
|
|
// - The Used bit of a valid entry is cleared if all
|
540 |
|
|
// entries have their Used bits set and the entry itself is not Locked.
|
541 |
|
|
// A locked entry should always appear to be Used.
|
542 |
|
|
// A single priority-encoder is required to evaluate the used status. Priority is static
|
543 |
|
|
// and used entry0 is of the highest priority if unused.
|
544 |
|
|
|
545 |
|
|
// Timing :
|
546 |
|
|
// Used bit gets updated by cam-hit or hit on negedge.
|
547 |
|
|
// After Used bit gets updated off negedge, the replacement entry can be generated in
|
548 |
|
|
// Phase2. In parallel, it is determined whether all Used bits are set or not. If
|
549 |
|
|
// so, then they are cleared on the next negedge with the replacement entry generated
|
550 |
|
|
// in the related Phase1
|
551 |
|
|
|
552 |
|
|
// Choosing replacement entry
|
553 |
|
|
// Replacement entry is integer k
|
554 |
|
|
|
555 |
|
|
assign tlb_not_writeable = &used[`TLB_ENTRIES-1:0] ;
|
556 |
|
|
/*
|
557 |
|
|
// Used bit can be set because of write or because of cam-hit.
|
558 |
|
|
always @(negedge clk)
|
559 |
|
|
begin
|
560 |
|
|
for (s=0;s<`TLB_ENTRIES;s=s+1)
|
561 |
|
|
begin
|
562 |
|
|
if (cam_hit[s])
|
563 |
|
|
tlb_entry_used[s] <= 1'b1;
|
564 |
|
|
end
|
565 |
|
|
|
566 |
|
|
// Clear on following edge if necessary.
|
567 |
|
|
// CHANGE(SATYA) : tlb_entry_used qualified with valid needs to be used to determine
|
568 |
|
|
// whether the Used bits are to be cleared. This allows invalid entries created
|
569 |
|
|
// by a demap to be used for replacement. Else we will ignore these entries
|
570 |
|
|
// for replacement
|
571 |
|
|
|
572 |
|
|
if (tlb_not_writeable)
|
573 |
|
|
begin
|
574 |
|
|
for (t=0;t<`TLB_ENTRIES;t=t+1)
|
575 |
|
|
begin
|
576 |
|
|
if (~tlb_entry_locked[t])
|
577 |
|
|
tlb_entry_used[t] <= 1'b0;
|
578 |
|
|
end
|
579 |
|
|
end
|
580 |
|
|
end
|
581 |
|
|
*/
|
582 |
|
|
|
583 |
|
|
// Determine whether entry should be squashed.
|
584 |
|
|
|
585 |
|
|
assign used[`TLB_ENTRIES-1:0] = tlb_entry_used[`TLB_ENTRIES-1:0] & tlb_entry_vld[`TLB_ENTRIES-1:0] ;
|
586 |
|
|
|
587 |
|
|
|
588 |
|
|
// Based on updated Used state, generate replacement entry.
|
589 |
|
|
// So, replacement entries can be generated on a cycle-by-cycle basis.
|
590 |
|
|
//always @(/*AUTOSENSE*/squash or used)
|
591 |
|
|
|
592 |
|
|
reg [`TLB_ENTRIES-1:0] tlb_entry_replace_d1;
|
593 |
|
|
reg tlb_replace_flag;
|
594 |
|
|
always @(/*AUTOSENSE*/used)
|
595 |
|
|
begin
|
596 |
|
|
tlb_replace_flag=1'b0;
|
597 |
|
|
tlb_entry_replace_d1 = {`TLB_ENTRIES-1{1'b0}};
|
598 |
|
|
// Priority is given to entry0
|
599 |
|
|
for (u=0;u<`TLB_ENTRIES;u=u+1)
|
600 |
|
|
begin
|
601 |
|
|
if(~tlb_replace_flag & ~used[u])
|
602 |
|
|
begin
|
603 |
|
|
tlb_entry_replace_d1[u] = ~used[u] ;
|
604 |
|
|
tlb_replace_flag=1'b1;
|
605 |
|
|
end
|
606 |
|
|
end
|
607 |
|
|
if(~tlb_replace_flag) begin
|
608 |
|
|
tlb_entry_replace_d1[`TLB_ENTRIES-1] = 1'b1;
|
609 |
|
|
end
|
610 |
|
|
end
|
611 |
|
|
always @(posedge clk)
|
612 |
|
|
begin
|
613 |
|
|
// named in this manner to keep arch model happy.
|
614 |
|
|
tlb_entry_replace <= tlb_entry_replace_d1 ;
|
615 |
|
|
end
|
616 |
|
|
// INNO - 2 stage delay before update is visible
|
617 |
|
|
always @(posedge clk)
|
618 |
|
|
begin
|
619 |
|
|
tlb_entry_replace_d2 <= tlb_entry_replace ;
|
620 |
|
|
end
|
621 |
|
|
|
622 |
|
|
reg [`TLB_INDEX_WIDTH-1:0] tlb_index_a1;
|
623 |
|
|
reg [`TLB_INDEX_WIDTH-1:0] tlb_index;
|
624 |
|
|
wire tlb_index_vld_a1 = |tlb_entry_replace;
|
625 |
|
|
reg tlb_index_vld;
|
626 |
|
|
integer jj;
|
627 |
|
|
always @(tlb_entry_replace) begin
|
628 |
|
|
tlb_index_a1 = {`TLB_INDEX_WIDTH{1'b0}};
|
629 |
|
|
for(jj=0;jj<`TLB_ENTRIES;jj=jj+1)
|
630 |
|
|
if(tlb_entry_replace[jj]) tlb_index_a1 = jj;
|
631 |
|
|
end
|
632 |
|
|
always @(posedge clk) begin
|
633 |
|
|
tlb_index <= tlb_index_a1; //use instead of tlb_entry_replace_d2;
|
634 |
|
|
tlb_index_vld <= tlb_index_vld_a1;
|
635 |
|
|
end
|
636 |
|
|
|
637 |
|
|
|
638 |
|
|
|
639 |
|
|
|
640 |
|
|
//=========================================================================================
|
641 |
|
|
// TLB WRITEABLE DETECTION
|
642 |
|
|
//=========================================================================================
|
643 |
|
|
|
644 |
|
|
// 2-cycles later, tlb become writeable
|
645 |
|
|
always @(posedge clk)
|
646 |
|
|
begin
|
647 |
|
|
tlb_not_writeable_d1 <= tlb_not_writeable ;
|
648 |
|
|
end
|
649 |
|
|
|
650 |
|
|
always @(posedge clk)
|
651 |
|
|
begin
|
652 |
|
|
tlb_writeable <= ~tlb_not_writeable_d1 ;
|
653 |
|
|
end
|
654 |
|
|
|
655 |
|
|
bw_r_tlb_tag_ram bw_r_tlb_tag_ram (
|
656 |
|
|
.rd_tag(rd_tag),
|
657 |
|
|
.rw_index_vld(rw_index_vld),
|
658 |
|
|
.wr_vld_tmp(wr_vld_tmp),
|
659 |
|
|
.clk(clk),
|
660 |
|
|
.rw_index(rw_index),
|
661 |
|
|
.tlb_index(tlb_index),
|
662 |
|
|
.tlb_index_vld(tlb_index_vld),
|
663 |
|
|
.rw_disable(rw_disable),
|
664 |
|
|
.rst_tri_en(rst_tri_en),
|
665 |
|
|
.wr_tte_tag(wr_tte_tag),
|
666 |
|
|
.tlb_entry_vld(tlb_entry_vld),
|
667 |
|
|
.tlb_entry_used(tlb_entry_used),
|
668 |
|
|
.tlb_entry_locked(tlb_entry_locked),
|
669 |
|
|
.rd_tte_tag(rd_tte_tag),
|
670 |
|
|
.mismatch(mismatch),
|
671 |
|
|
.tlb_writeable(tlb_writeable),
|
672 |
|
|
.cam_vld(cam_vld),
|
673 |
|
|
.wr_vld(wr_vld),
|
674 |
|
|
.cam_data(cam_data),
|
675 |
|
|
.cam_hit(cam_hit),
|
676 |
|
|
.cam_pid(cam_pid),
|
677 |
|
|
.demap_all(demap_all),
|
678 |
|
|
.demap_hit(demap_hit),
|
679 |
|
|
.demap_other(demap_other)
|
680 |
|
|
);
|
681 |
|
|
|
682 |
|
|
bw_r_tlb_data_ram bw_r_tlb_data_ram (
|
683 |
|
|
.rd_data(rd_data),
|
684 |
|
|
.rw_index_vld(rw_index_vld),
|
685 |
|
|
.wr_vld_tmp(wr_vld_tmp),
|
686 |
|
|
.clk(clk),
|
687 |
|
|
.cam_vld(cam_vld),
|
688 |
|
|
.cam_index(cam_hit_encoded),
|
689 |
|
|
.cam_hit_any(cam_hit_any),
|
690 |
|
|
.rw_index(rw_index),
|
691 |
|
|
.tlb_index(tlb_index),
|
692 |
|
|
.tlb_index_vld(tlb_index_vld),
|
693 |
|
|
.rw_disable(rw_disable),
|
694 |
|
|
.rst_tri_en(rst_tri_en),
|
695 |
|
|
.wr_tte_data(wr_tte_data),
|
696 |
|
|
.rd_tte_data(rd_tte_data),
|
697 |
|
|
.wr_vld(wr_vld)
|
698 |
|
|
);
|
699 |
|
|
|
700 |
|
|
|
701 |
|
|
endmodule
|
702 |
|
|
|
703 |
|
|
module bw_r_tlb_tag_ram(
|
704 |
|
|
rd_tag,
|
705 |
|
|
rw_index_vld,
|
706 |
|
|
wr_vld_tmp,
|
707 |
|
|
clk,
|
708 |
|
|
rw_index,
|
709 |
|
|
tlb_index,
|
710 |
|
|
tlb_index_vld,
|
711 |
|
|
rw_disable,
|
712 |
|
|
rst_tri_en,
|
713 |
|
|
wr_tte_tag,
|
714 |
|
|
tlb_entry_vld,
|
715 |
|
|
tlb_entry_used,
|
716 |
|
|
tlb_entry_locked,
|
717 |
|
|
rd_tte_tag,
|
718 |
|
|
mismatch,
|
719 |
|
|
tlb_writeable,
|
720 |
|
|
wr_vld,
|
721 |
|
|
cam_vld,
|
722 |
|
|
cam_data,
|
723 |
|
|
cam_hit,
|
724 |
|
|
cam_pid,
|
725 |
|
|
demap_all,
|
726 |
|
|
demap_other,
|
727 |
|
|
demap_hit);
|
728 |
|
|
|
729 |
|
|
input rd_tag;
|
730 |
|
|
input rw_index_vld;
|
731 |
|
|
input wr_vld_tmp;
|
732 |
|
|
input clk;
|
733 |
|
|
input [`TLB_INDEX_WIDTH-1:0] rw_index;
|
734 |
|
|
input [`TLB_INDEX_WIDTH-1:0] tlb_index;
|
735 |
|
|
input tlb_index_vld;
|
736 |
|
|
input rw_disable;
|
737 |
|
|
input rst_tri_en;
|
738 |
|
|
input [58:0] wr_tte_tag;
|
739 |
|
|
input [`TLB_ENTRIES-1:0] tlb_entry_vld;
|
740 |
|
|
input tlb_writeable;
|
741 |
|
|
input wr_vld;
|
742 |
|
|
input [2:0] cam_pid;
|
743 |
|
|
input demap_all;
|
744 |
|
|
input demap_other;
|
745 |
|
|
input [53:0] cam_data;
|
746 |
|
|
input cam_vld ;
|
747 |
|
|
|
748 |
|
|
output [`TLB_ENTRIES-1:0] cam_hit ;
|
749 |
|
|
output [`TLB_ENTRIES-1:0] demap_hit ;
|
750 |
|
|
output [`TLB_ENTRIES-1:0] tlb_entry_used;
|
751 |
|
|
output [`TLB_ENTRIES-1:0] tlb_entry_locked;
|
752 |
|
|
reg [`TLB_ENTRIES-1:0] tlb_entry_locked ;
|
753 |
|
|
|
754 |
|
|
output [58:0] rd_tte_tag;
|
755 |
|
|
reg [58:0] rd_tte_tag;
|
756 |
|
|
output [`TLB_ENTRIES-1:0] mismatch;
|
757 |
|
|
|
758 |
|
|
reg [`TLB_ENTRIES-1:0] sat;
|
759 |
|
|
|
760 |
|
|
reg [`TLB_ENTRIES-1:0] mismatch;
|
761 |
|
|
reg [`TLB_ENTRIES-1:0] cam_hit ;
|
762 |
|
|
reg [`TLB_ENTRIES-1:0] demap_all_but_locked_hit ;
|
763 |
|
|
reg [58:0] tag ; // CHANGE
|
764 |
|
|
|
765 |
|
|
|
766 |
|
|
reg [`TLB_ENTRIES-1:0] mismatch_va_b47_28;
|
767 |
|
|
reg [`TLB_ENTRIES-1:0] mismatch_va_b27_22;
|
768 |
|
|
reg [`TLB_ENTRIES-1:0] mismatch_va_b21_16;
|
769 |
|
|
reg [`TLB_ENTRIES-1:0] mismatch_va_b15_13;
|
770 |
|
|
reg [`TLB_ENTRIES-1:0] mismatch_ctxt;
|
771 |
|
|
reg [`TLB_ENTRIES-1:0] mismatch_pid;
|
772 |
|
|
reg [`TLB_ENTRIES-1:0] mismatch_type;
|
773 |
|
|
reg [`TLB_ENTRIES-1:0] tlb_entry_used ;
|
774 |
|
|
|
775 |
|
|
integer i,j,n,m, w, p, k, s, t;
|
776 |
|
|
|
777 |
|
|
|
778 |
|
|
reg [58:0] tte_tag_ram [`TLB_ENTRIES-1:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
|
779 |
|
|
|
780 |
|
|
reg [58:0] tmp_tag ;
|
781 |
|
|
|
782 |
|
|
wire wren = rw_index_vld & wr_vld_tmp & ~rw_disable;
|
783 |
|
|
wire tlben = tlb_index_vld & ~rw_index_vld & wr_vld_tmp & ~rw_disable;
|
784 |
|
|
wire [`TLB_INDEX_WIDTH-1:0] wr_addr = wren ? rw_index : tlb_index;
|
785 |
|
|
|
786 |
|
|
|
787 |
|
|
always @ (negedge clk) begin
|
788 |
|
|
//=========================================================================================
|
789 |
|
|
// Write TLB
|
790 |
|
|
//=========================================================================================
|
791 |
|
|
|
792 |
|
|
if(wren | tlben) begin
|
793 |
|
|
tte_tag_ram[wr_addr] <= wr_tte_tag[58:0];
|
794 |
|
|
tlb_entry_used[wr_addr] <= wr_tte_tag[`STLB_TAG_U];
|
795 |
|
|
tlb_entry_locked[wr_addr] = wr_tte_tag[`STLB_TAG_L];
|
796 |
|
|
end else begin
|
797 |
|
|
tlb_entry_used <= (tlb_entry_used | cam_hit) & (tlb_entry_locked | ~{`TLB_ENTRIES{~tlb_writeable & ~cam_vld & ~wr_vld & ~rd_tag & ~rst_tri_en}}) ;
|
798 |
|
|
end
|
799 |
|
|
|
800 |
|
|
//=========================================================================================
|
801 |
|
|
// Read STLB
|
802 |
|
|
//=========================================================================================
|
803 |
|
|
|
804 |
|
|
if(rd_tag & ~rw_disable) begin
|
805 |
|
|
tmp_tag <= tte_tag_ram[rw_index];
|
806 |
|
|
end
|
807 |
|
|
|
808 |
|
|
|
809 |
|
|
end // always
|
810 |
|
|
|
811 |
|
|
always @(posedge clk) begin
|
812 |
|
|
if(rd_tag & ~rw_disable)
|
813 |
|
|
rd_tte_tag[58:0] = {tmp_tag[58:27], tlb_entry_vld[rw_index], tlb_entry_locked[rw_index], tlb_entry_used[rw_index], tmp_tag[23:0]};
|
814 |
|
|
else if(wren | tlben)
|
815 |
|
|
rd_tte_tag[58:0] = wr_tte_tag[58:0];
|
816 |
|
|
end
|
817 |
|
|
|
818 |
|
|
reg [58:0] tte_tag_ram2 [`TLB_ENTRIES-1:0];
|
819 |
|
|
|
820 |
|
|
always @ (negedge clk) begin
|
821 |
|
|
if(wren | tlben)
|
822 |
|
|
tte_tag_ram2[wr_addr] <= wr_tte_tag[58:0];
|
823 |
|
|
end
|
824 |
|
|
|
825 |
|
|
|
826 |
|
|
always @ (cam_data or cam_pid or cam_vld or demap_all
|
827 |
|
|
or demap_other or tlb_entry_vld)
|
828 |
|
|
begin
|
829 |
|
|
|
830 |
|
|
for (n=0;n<`TLB_ENTRIES;n=n+1)
|
831 |
|
|
begin
|
832 |
|
|
tag[58:0] = tte_tag_ram2[n] ; // CHANGE
|
833 |
|
|
|
834 |
|
|
mismatch_va_b47_28[n] =
|
835 |
|
|
(tag[`STLB_TAG_VA_47_28_HI:`STLB_TAG_VA_47_28_LO]
|
836 |
|
|
!= cam_data[`CAM_VA_47_28_HI+13:`CAM_VA_47_28_LO+13]);
|
837 |
|
|
|
838 |
|
|
mismatch_va_b27_22[n] =
|
839 |
|
|
(tag[`STLB_TAG_VA_27_22_HI:`STLB_TAG_VA_27_22_LO]
|
840 |
|
|
!= cam_data[`CAM_VA_27_22_HI+13:`CAM_VA_27_22_LO+13]);
|
841 |
|
|
|
842 |
|
|
mismatch_va_b21_16[n] =
|
843 |
|
|
(tag[`STLB_TAG_VA_21_16_HI:`STLB_TAG_VA_21_16_LO]
|
844 |
|
|
!= cam_data[`CAM_VA_21_16_HI+13:`CAM_VA_21_16_LO+13]) ;
|
845 |
|
|
|
846 |
|
|
mismatch_va_b15_13[n] =
|
847 |
|
|
(tag[`STLB_TAG_VA_15_13_HI:`STLB_TAG_VA_15_13_LO]
|
848 |
|
|
!= cam_data[`CAM_VA_15_13_HI+13:`CAM_VA_15_13_LO+13]) ;
|
849 |
|
|
|
850 |
|
|
mismatch_ctxt[n] =
|
851 |
|
|
(tag[`STLB_TAG_CTXT_12_0_HI:`STLB_TAG_CTXT_12_0_LO]
|
852 |
|
|
!= cam_data[`CAM_CTXT_12_0_HI:`CAM_CTXT_12_0_LO]) ;
|
853 |
|
|
|
854 |
|
|
mismatch_pid[n] = (tag[`STLB_TAG_PID_HI:`STLB_TAG_PID_LO] != cam_pid[2:0]) ;
|
855 |
|
|
mismatch_type[n] = (tag[`STLB_TAG_R] ^ cam_data[`CAM_REAL_V+13]);
|
856 |
|
|
|
857 |
|
|
mismatch[n] =
|
858 |
|
|
(mismatch_va_b47_28[n] & cam_data[`CAM_VA_47_28_V+13]) |
|
859 |
|
|
(mismatch_va_b27_22[n] & tag[`STLB_TAG_VA_27_22_V] & cam_data[`CAM_VA_27_22_V+13]) |
|
860 |
|
|
(mismatch_va_b21_16[n] & tag[`STLB_TAG_VA_21_16_V] & cam_data[`CAM_VA_21_16_V+13]) |
|
861 |
|
|
(mismatch_va_b15_13[n] & tag[`STLB_TAG_VA_15_13_V] & cam_data[`CAM_VA_15_13_V+13]) |
|
862 |
|
|
(mismatch_ctxt[n] & ~cam_data[`CAM_CTXT_GK+13]) |
|
863 |
|
|
(mismatch_type[n] & ~demap_all) |
|
864 |
|
|
mismatch_pid[n] ; // pid always included in mismatch calculations
|
865 |
|
|
|
866 |
|
|
demap_all_but_locked_hit[n] = ~tag[`STLB_TAG_L] & demap_all ;
|
867 |
|
|
|
868 |
|
|
cam_hit[n] = ~mismatch[n] & cam_vld & tlb_entry_vld[n] ;
|
869 |
|
|
end
|
870 |
|
|
|
871 |
|
|
end // always
|
872 |
|
|
|
873 |
|
|
assign demap_hit = demap_all ? ~mismatch & demap_all_but_locked_hit & tlb_entry_vld & {`TLB_ENTRIES{demap_other}}
|
874 |
|
|
: ~mismatch & tlb_entry_vld & {`TLB_ENTRIES{demap_other}};
|
875 |
|
|
|
876 |
|
|
endmodule
|
877 |
|
|
|
878 |
|
|
|
879 |
|
|
|
880 |
|
|
module bw_r_tlb_data_ram(rd_data, rw_index_vld, wr_vld_tmp, clk, cam_vld,
|
881 |
|
|
rw_index, tlb_index, tlb_index_vld, rw_disable, rst_tri_en, wr_tte_data,
|
882 |
|
|
rd_tte_data, cam_index, cam_hit_any, wr_vld);
|
883 |
|
|
|
884 |
|
|
input rd_data;
|
885 |
|
|
input rw_index_vld;
|
886 |
|
|
input wr_vld_tmp;
|
887 |
|
|
input clk;
|
888 |
|
|
input [(6 - 1):0] rw_index;
|
889 |
|
|
input [(6 - 1):0] tlb_index;
|
890 |
|
|
input tlb_index_vld;
|
891 |
|
|
input [(6 - 1):0] cam_index;
|
892 |
|
|
input cam_hit_any;
|
893 |
|
|
input rw_disable;
|
894 |
|
|
input rst_tri_en;
|
895 |
|
|
input cam_vld;
|
896 |
|
|
input [42:0] wr_tte_data;
|
897 |
|
|
input wr_vld;
|
898 |
|
|
output [42:0] rd_tte_data;
|
899 |
|
|
|
900 |
|
|
wire [42:0] rd_tte_data;
|
901 |
|
|
|
902 |
|
|
reg [42:0] tte_data_ram[(64 - 1):0];
|
903 |
|
|
|
904 |
|
|
wire [5:0] wr_addr = (rw_index_vld & wr_vld_tmp) ? rw_index :tlb_index;
|
905 |
|
|
wire wr_en = ((rw_index_vld & wr_vld_tmp) & (~rw_disable)) |
|
906 |
|
|
(((tlb_index_vld & (~rw_index_vld)) & wr_vld_tmp) & (~rw_disable));
|
907 |
|
|
|
908 |
|
|
always @(negedge clk) begin
|
909 |
|
|
if (wr_en)
|
910 |
|
|
tte_data_ram[wr_addr] <= wr_tte_data[42:0];
|
911 |
|
|
end
|
912 |
|
|
|
913 |
|
|
wire [5:0] rd_addr = rd_data ? rw_index : cam_index;
|
914 |
|
|
wire rd_en = (rd_data & (~rw_disable)) | ((cam_vld & (~rw_disable)));
|
915 |
|
|
|
916 |
|
|
reg [42:0] rd_tte_data_temp;
|
917 |
|
|
|
918 |
|
|
always @(negedge clk) begin
|
919 |
|
|
//required for simulation; otherwise regression fails...
|
920 |
|
|
if((cam_vld & (~rw_disable)) & (!cam_hit_any)) begin
|
921 |
|
|
rd_tte_data_temp <= 43'bx;
|
922 |
|
|
end else
|
923 |
|
|
if (rd_en) begin
|
924 |
|
|
rd_tte_data_temp[42:0] <= tte_data_ram[rd_addr];
|
925 |
|
|
end
|
926 |
|
|
end
|
927 |
|
|
|
928 |
|
|
reg rdwe;
|
929 |
|
|
reg [42:0] wr_tte_data_d;
|
930 |
|
|
|
931 |
|
|
|
932 |
|
|
always @(negedge clk) begin
|
933 |
|
|
wr_tte_data_d <= wr_tte_data;
|
934 |
|
|
end
|
935 |
|
|
always @(negedge clk) begin
|
936 |
|
|
if(wr_en) rdwe <= 1'b1;
|
937 |
|
|
else if(rd_en) rdwe <= 1'b0;
|
938 |
|
|
end
|
939 |
|
|
|
940 |
|
|
assign rd_tte_data = rdwe ? wr_tte_data_d : rd_tte_data_temp;
|
941 |
|
|
|
942 |
|
|
endmodule
|
943 |
|
|
|
944 |
|
|
`else
|
945 |
|
|
|
946 |
|
|
module bw_r_tlb ( /*AUTOARG*/
|
947 |
|
|
// Outputs
|
948 |
|
|
tlb_rd_tte_tag, tlb_rd_tte_data, tlb_pgnum, tlb_pgnum_crit,
|
949 |
|
|
tlb_cam_hit, cache_way_hit, cache_hit, so,
|
950 |
|
|
// Inputs
|
951 |
|
|
tlb_cam_vld, tlb_cam_key, tlb_cam_pid,
|
952 |
|
|
tlb_demap_key, tlb_addr_mask_l, tlb_ctxt,
|
953 |
|
|
tlb_wr_vld, tlb_wr_tte_tag, tlb_wr_tte_data, tlb_rd_tag_vld,
|
954 |
|
|
tlb_rd_data_vld, tlb_rw_index, tlb_rw_index_vld, tlb_demap,
|
955 |
|
|
tlb_demap_auto, tlb_demap_all, cache_ptag_w0, cache_ptag_w1,
|
956 |
|
|
cache_ptag_w2, cache_ptag_w3, cache_set_vld, tlb_bypass_va,
|
957 |
|
|
tlb_bypass, se, si, hold, adj, arst_l, rst_soft_l, rclk,
|
958 |
|
|
rst_tri_en
|
959 |
|
|
) ;
|
960 |
|
|
|
961 |
|
|
|
962 |
|
|
input tlb_cam_vld ; // ld/st requires xlation.
|
963 |
|
|
input [40:0] tlb_cam_key ; // cam data for loads/stores;includes vld
|
964 |
|
|
// CHANGE : add real bit for cam.
|
965 |
|
|
input [2:0] tlb_cam_pid ; // NEW: pid for cam.
|
966 |
|
|
input [40:0] tlb_demap_key ; // cam data for demap; includes vlds.
|
967 |
|
|
// CHANGE : add real bit for demap
|
968 |
|
|
input tlb_addr_mask_l ; // address masking occurs
|
969 |
|
|
input [12:0] tlb_ctxt ; // context for cam xslate/demap.
|
970 |
|
|
input tlb_wr_vld; // write to tlb.
|
971 |
|
|
input [58:0] tlb_wr_tte_tag; // CHANGE:tte tag to be written (55+4-1)
|
972 |
|
|
// R(+1b),PID(+3b),G(-1b).
|
973 |
|
|
input [42:0] tlb_wr_tte_data; // tte data to be written.
|
974 |
|
|
// No change(!!!) - G bit becomes spare
|
975 |
|
|
input tlb_rd_tag_vld ; // read tag
|
976 |
|
|
input tlb_rd_data_vld ; // read data
|
977 |
|
|
input [5:0] tlb_rw_index ; // index to read/write tlb.
|
978 |
|
|
input tlb_rw_index_vld ; // indexed write else use algorithm.
|
979 |
|
|
input tlb_demap ; // demap : page/ctxt/all/auto.
|
980 |
|
|
input tlb_demap_auto ; // demap is of type auto
|
981 |
|
|
input tlb_demap_all; // demap-all operation : encoded separately.
|
982 |
|
|
input [29:0] cache_ptag_w0; // way1 30b(D)/29b(I) tag.
|
983 |
|
|
input [29:0] cache_ptag_w1; // way2 30b(D)/29b(I) tag.
|
984 |
|
|
input [29:0] cache_ptag_w2; // way0 30b(D)/29b(I) tag.
|
985 |
|
|
input [29:0] cache_ptag_w3; // way3 30b(D)/29b(I) tag.
|
986 |
|
|
input [3:0] cache_set_vld; // set vld-4 ways
|
987 |
|
|
input [12:10] tlb_bypass_va; // bypass va.other va bits from cam-data
|
988 |
|
|
input tlb_bypass; // bypass tlb xslation
|
989 |
|
|
|
990 |
|
|
input se ; // scan-enable ; unused
|
991 |
|
|
input si ; // scan data in ; unused
|
992 |
|
|
input hold ; // scan hold signal
|
993 |
|
|
input [7:0] adj ; // self-time adjustment ; unused
|
994 |
|
|
input arst_l ; // synchronous for tlb ; unused
|
995 |
|
|
input rst_soft_l ; // software reset - asi
|
996 |
|
|
input rclk;
|
997 |
|
|
input rst_tri_en ;
|
998 |
|
|
|
999 |
|
|
output [58:0] tlb_rd_tte_tag; // CHANGE: tte tag read from tlb.
|
1000 |
|
|
output [42:0] tlb_rd_tte_data; // tte data read from tlb.
|
1001 |
|
|
// Need two ports for tlb_pgnum - critical and non-critical.
|
1002 |
|
|
output [39:10] tlb_pgnum ; // bypass or xslated pgnum
|
1003 |
|
|
output [39:10] tlb_pgnum_crit ; // bypass or xslated pgnum - critical
|
1004 |
|
|
output tlb_cam_hit ; // xlation hits in tlb.
|
1005 |
|
|
output [3:0] cache_way_hit; // tag comparison results.
|
1006 |
|
|
output cache_hit; // tag comparison result - 'or' of above.
|
1007 |
|
|
|
1008 |
|
|
//output tlb_writeable ; // tlb can be written in current cycle.
|
1009 |
|
|
|
1010 |
|
|
output so ; // scan data out ; unused
|
1011 |
|
|
|
1012 |
|
|
wire [53:0] tlb_cam_data ;
|
1013 |
|
|
wire [58:0] wr_tte_tag ; // CHANGE
|
1014 |
|
|
wire [42:0] wr_tte_data ;
|
1015 |
|
|
wire [29:3] phy_pgnum_m;
|
1016 |
|
|
wire [29:0] pgnum_m;
|
1017 |
|
|
wire [63:0] used ;
|
1018 |
|
|
wire tlb_not_writeable ;
|
1019 |
|
|
wire [40:25] tlb_cam_key_masked ;
|
1020 |
|
|
wire [26:0] tlb_cam_comp_key ;
|
1021 |
|
|
wire cam_vld ;
|
1022 |
|
|
wire demap_other ;
|
1023 |
|
|
wire [3:0] cache_way_hit ;
|
1024 |
|
|
|
1025 |
|
|
reg tlb_not_writeable_d1 ;
|
1026 |
|
|
reg tlb_writeable ;
|
1027 |
|
|
reg [58:0] tte_tag_ram [63:0] ; // CHANGE
|
1028 |
|
|
reg [42:0] tte_data_ram [63:0] ;
|
1029 |
|
|
reg [63:0] tlb_entry_vld ;
|
1030 |
|
|
reg [63:0] tlb_entry_locked ;
|
1031 |
|
|
reg [63:0] ademap_hit ;
|
1032 |
|
|
reg [58:0] rd_tte_tag ; // CHANGE
|
1033 |
|
|
reg [42:0] rd_tte_data ;
|
1034 |
|
|
reg [58:0] tlb_rd_tte_tag ; // CHANGE
|
1035 |
|
|
reg [42:0] tlb_rd_tte_data ;
|
1036 |
|
|
reg cam_vld_tmp ;
|
1037 |
|
|
reg [2:0] cam_pid ;
|
1038 |
|
|
reg [53:0] cam_data ;
|
1039 |
|
|
reg demap_auto, demap_other_tmp, demap_all ;
|
1040 |
|
|
reg [63:0] mismatch ;
|
1041 |
|
|
reg [63:0] cam_hit ;
|
1042 |
|
|
reg [63:0] demap_hit ;
|
1043 |
|
|
reg [63:0] demap_all_but_locked_hit ;
|
1044 |
|
|
reg [63:0] mismatch_va_b47_28 ;
|
1045 |
|
|
reg [63:0] mismatch_va_b27_22 ;
|
1046 |
|
|
reg [63:0] mismatch_va_b21_16 ;
|
1047 |
|
|
reg [63:0] mismatch_va_b15_13 ;
|
1048 |
|
|
reg [63:0] mismatch_ctxt ;
|
1049 |
|
|
reg [63:0] mismatch_pid ;
|
1050 |
|
|
reg [58:0] tag ; // CHANGE
|
1051 |
|
|
reg [63:0] rw_wdline ;
|
1052 |
|
|
reg [63:0] tlb_entry_used ;
|
1053 |
|
|
reg [63:0] tlb_entry_replace ;
|
1054 |
|
|
reg [63:0] tlb_entry_replace_d2 ;
|
1055 |
|
|
reg [29:0] pgnum_g ;
|
1056 |
|
|
reg [3:0] cache_set_vld_g;
|
1057 |
|
|
reg [29:0] cache_ptag_w0_g,cache_ptag_w1_g;
|
1058 |
|
|
reg [29:0] cache_ptag_w2_g,cache_ptag_w3_g;
|
1059 |
|
|
reg wr_vld_tmp;
|
1060 |
|
|
reg rd_tag;
|
1061 |
|
|
reg rd_data;
|
1062 |
|
|
reg rw_index_vld;
|
1063 |
|
|
reg [5:0] rw_index;
|
1064 |
|
|
reg [63:0] sat ;
|
1065 |
|
|
|
1066 |
|
|
wire [29:0] vrtl_pgnum_m;
|
1067 |
|
|
wire bypass ;
|
1068 |
|
|
|
1069 |
|
|
wire wr_vld ;
|
1070 |
|
|
|
1071 |
|
|
integer i,j,k,l,m,n,p,r,s,t,u,w;
|
1072 |
|
|
|
1073 |
|
|
/*AUTOWIRE*/
|
1074 |
|
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
1075 |
|
|
// End of automatics
|
1076 |
|
|
|
1077 |
|
|
// Some bits are removed from the tag and data.
|
1078 |
|
|
// 'U' must be defined as a '1' on a write.
|
1079 |
|
|
// 'L' required for demap all function.
|
1080 |
|
|
// Do not need an internal valid bit for va range 47:22.
|
1081 |
|
|
// These bits are always valid for a page.
|
1082 |
|
|
//
|
1083 |
|
|
// TTE STLB_TAG
|
1084 |
|
|
//
|
1085 |
|
|
//`define STLB_TAG_PID_HI 58 : NEW PID - bit2
|
1086 |
|
|
//`define STLB_TAG_PID_LO 56 : NEW PID - bit0
|
1087 |
|
|
//`define STLB_TAG_R 55 : NEW Real bit
|
1088 |
|
|
//`define STLB_TAG_PARITY 54 // Parity kept in same posn to avoid having
|
1089 |
|
|
//`define STLB_TAG_VA_47_28_HI 53 // to redo interface
|
1090 |
|
|
//`define STLB_TAG_VA_47_28_LO 34
|
1091 |
|
|
//`define STLB_TAG_VA_27_22_HI 33
|
1092 |
|
|
//`define STLB_TAG_VA_27_22_LO 28
|
1093 |
|
|
//`define STLB_TAG_27_22_V 27
|
1094 |
|
|
//`define STLB_TAG_V 26 : valid for entry. Write of 0 resets it.
|
1095 |
|
|
//`define STLB_TAG_L 25
|
1096 |
|
|
//`define STLB_TAG_U 24
|
1097 |
|
|
//`define STLB_TAG_VA_21_16_HI 23
|
1098 |
|
|
//`define STLB_TAG_VA_21_16_LO 18
|
1099 |
|
|
//`define STLB_TAG_VA_21_16_V 17
|
1100 |
|
|
//`define STLB_TAG_VA_15_13_HI 16
|
1101 |
|
|
//`define STLB_TAG_VA_15_13_LO 14
|
1102 |
|
|
//`define STLB_TAG_VA_15_13_V 13
|
1103 |
|
|
//`define STLB_TAG_CTXT_12_0_HI 12 // removed Global bit
|
1104 |
|
|
//`define STLB_TAG_CTXT_12_0_LO 0
|
1105 |
|
|
//// Total - 59b
|
1106 |
|
|
////
|
1107 |
|
|
//// TTE STLB_DATA
|
1108 |
|
|
////
|
1109 |
|
|
//// Soft[12:7] & Soft2[58:50] are removed.
|
1110 |
|
|
//// Diag[49:41] are removed. Used bit used for Diag[0] on read.
|
1111 |
|
|
//// CV is included for software correctness.
|
1112 |
|
|
//// PA<40> is removed as it is not used.
|
1113 |
|
|
//// G/L present in data even though present in tag : can't read out simultaneously.
|
1114 |
|
|
// (Unfortunately this is no longer correct. For data read, tag is also read
|
1115 |
|
|
// simultaneously to get valid bit, used bits).
|
1116 |
|
|
//`define STLB_DATA_PARITY 42
|
1117 |
|
|
//`define STLB_DATA_PA_39_28_HI 41 // CHANGE
|
1118 |
|
|
//`define STLB_DATA_PA_39_28_LO 30
|
1119 |
|
|
//`define STLB_DATA_PA_27_22_HI 29 // CHANGE
|
1120 |
|
|
//`define STLB_DATA_PA_27_22_LO 24
|
1121 |
|
|
//`define STLB_DATA_27_22_SEL 23
|
1122 |
|
|
//`define STLB_DATA_PA_21_16_HI 22 // CHANGE
|
1123 |
|
|
//`define STLB_DATA_PA_21_16_LO 17
|
1124 |
|
|
//`define STLB_DATA_21_16_SEL 16
|
1125 |
|
|
//`define STLB_DATA_PA_15_13_HI 15
|
1126 |
|
|
//`define STLB_DATA_PA_15_13_LO 13
|
1127 |
|
|
//`define STLB_DATA_15_13_SEL 12
|
1128 |
|
|
//`define STLB_DATA_V 11 : static, does not get modified.
|
1129 |
|
|
//`define STLB_DATA_NFO 10
|
1130 |
|
|
//`define STLB_DATA_IE 9
|
1131 |
|
|
//`define STLB_DATA_L 8 : added for read.
|
1132 |
|
|
//`define STLB_DATA_CP 7
|
1133 |
|
|
//`define STLB_DATA_CV 6
|
1134 |
|
|
//`define STLB_DATA_E 5
|
1135 |
|
|
//`define STLB_DATA_P 4
|
1136 |
|
|
//`define STLB_DATA_W 3
|
1137 |
|
|
//`define STLB_DATA_SPARE_HI 2 : Global bit has been removed
|
1138 |
|
|
//`define STLB_DATA_SPARE_LO 0
|
1139 |
|
|
// Total - 43b
|
1140 |
|
|
|
1141 |
|
|
// Valid bits for key(tlb_cam_key/tlb_demap_key).
|
1142 |
|
|
// Total - 41b
|
1143 |
|
|
//`define CAM_VA_47_28_HI 40
|
1144 |
|
|
//`define CAM_VA_47_28_LO 21
|
1145 |
|
|
//`define CAM_VA_47_28_V 20 // b47-28 participate in match
|
1146 |
|
|
//`define CAM_VA_27_22_HI 19
|
1147 |
|
|
//`define CAM_VA_27_22_LO 14
|
1148 |
|
|
//`define CAM_VA_27_22_V 13 // b27-22 participate in match
|
1149 |
|
|
//`define CAM_VA_21_16_HI 12
|
1150 |
|
|
//`define CAM_VA_21_16_LO 7
|
1151 |
|
|
//`define CAM_VA_21_16_V 6 // b21-16 participate in match
|
1152 |
|
|
//`define CAM_VA_15_13_HI 5
|
1153 |
|
|
//`define CAM_VA_15_13_LO 3
|
1154 |
|
|
//`define CAM_VA_15_13_V 2 // b15-13 participate in match
|
1155 |
|
|
//`define CAM_CTXT_GK 1 // Context participates in match
|
1156 |
|
|
//`define CAM_REAL_V 0 // cam/demap applies to real mapping
|
1157 |
|
|
|
1158 |
|
|
|
1159 |
|
|
// ctxt port is different from cam key port even though both are
|
1160 |
|
|
// required for cam. (tlb_ctxt)
|
1161 |
|
|
// If Gk is set then ctxt will not participate in match.
|
1162 |
|
|
// Total - 14b
|
1163 |
|
|
`define CAM_CTXT_12_0_HI 12 // 13b ctxt
|
1164 |
|
|
`define CAM_CTXT_12_0_LO 0
|
1165 |
|
|
|
1166 |
|
|
|
1167 |
|
|
//=========================================================================================
|
1168 |
|
|
// What's Left :
|
1169 |
|
|
//=========================================================================================
|
1170 |
|
|
|
1171 |
|
|
// Scan Insertion - scan to be ignored in formal verification for now.
|
1172 |
|
|
|
1173 |
|
|
//=========================================================================================
|
1174 |
|
|
// Design Notes.
|
1175 |
|
|
//=========================================================================================
|
1176 |
|
|
|
1177 |
|
|
// - Supported Demap Operations - By Page, By Context, All But
|
1178 |
|
|
// Locked, Autodemap, Invalidate-All i.e., reset. Demap Partition is
|
1179 |
|
|
// not supported - it is mapped to demap-all by logic.
|
1180 |
|
|
// - Interpretation of demap inputs
|
1181 |
|
|
// - tlb_demap - this is used to signal demap by page, by ctxt
|
1182 |
|
|
// ,all, and autodemap.
|
1183 |
|
|
// - tlb_demap_ctxt - If a demap_by_ctxt operation is occuring then
|
1184 |
|
|
// this signal and tlb_demap must be active.
|
1185 |
|
|
// - tlb_demap_all - demap all operation. If a demap_all operation is
|
1186 |
|
|
// occuring, then tlb_demap_all must be asserted with tlb_demap.
|
1187 |
|
|
// - Reset is similar to demap-all except that *all* entries
|
1188 |
|
|
// are invalidated. The action is initiated by software. The reset occurs
|
1189 |
|
|
// on the negedge and is synchronous with the clk.
|
1190 |
|
|
// - TTE Tag and Data
|
1191 |
|
|
// - The TTE tag and data can be read together. Each will have its
|
1192 |
|
|
// own bus and the muxing will occur externally. The tag needs to
|
1193 |
|
|
// be read on a data request to supply the valid bit.
|
1194 |
|
|
// - The TTE tag and data can be written together.
|
1195 |
|
|
// - The cam hit is a separate output signal based on the
|
1196 |
|
|
// the match signals.
|
1197 |
|
|
// - Read/Write may occur based on supplied index. If not valid
|
1198 |
|
|
// then use replacement way determined by algorithm to write.
|
1199 |
|
|
// - Only write can use replacement way determined by algorithm.
|
1200 |
|
|
// - Data is formatted appr. on read or write in the MMU.
|
1201 |
|
|
// - The TLB will generate a signal which reports whether the
|
1202 |
|
|
// tlb can be filled in the current cycle or not.
|
1203 |
|
|
// **Physical Tag Comparison**
|
1204 |
|
|
// For I-SIDE, comparison is of 28b, whereas for D-side, comparison is of 29b. The actual
|
1205 |
|
|
// comparison, due to legacy, is for 30b.
|
1206 |
|
|
// For the I-TLB, va[11:10] must be hardwired to the same value as the lsb of the 4 tags
|
1207 |
|
|
// at the port level. Since the itag it only 28b, add two least significant bits to extend it to 30b.
|
1208 |
|
|
// Similarly, for the dside, va[10] needs to be made same.
|
1209 |
|
|
// **Differentiating among Various TLB Operations**
|
1210 |
|
|
// Valid bits are now associated with the key to allow selective incorporation of
|
1211 |
|
|
// match results. The 5 valid bits are : v4(b47-28),v3(b27-22),v2(21-16),v1(b15-13)
|
1212 |
|
|
// and Gk(G bit for auto-demap). The rules of use are :
|
1213 |
|
|
// - cam: v4-v1 are set high. G=~cam_real=0/1.
|
1214 |
|
|
// - demap_by_page : v4-v1 are set high. G=1. cam_real=0.
|
1215 |
|
|
// - demap_by_ctxt : v4-v1 are low. G=1. cam_real=0
|
1216 |
|
|
// - demap_all : v4-v1 are don't-care. G=x. cam_real=x
|
1217 |
|
|
// - autodemap : v4-v1 are based on page size of incoming tte. G=~cam_real=0/1.
|
1218 |
|
|
// Note : Gk is now used only to void a context match on a Real Translation.
|
1219 |
|
|
// In general, if a valid bit is low then the corresponding va field will not take
|
1220 |
|
|
// part in the match. Similarly, for the ctxt, if Gk=1, the ctxt will participate
|
1221 |
|
|
// in the match.
|
1222 |
|
|
//
|
1223 |
|
|
// Demap Table (For Satya) :
|
1224 |
|
|
// Note : To include a context match, Gk must be set to 1.
|
1225 |
|
|
//--------------------------------------------------------------------------------------------------------
|
1226 |
|
|
//tlb_demap tlb_demap_all tlb_ctxt Gk Vk4 Vk3 Vk2 Vk1 Real Operation
|
1227 |
|
|
//--------------------------------------------------------------------------------------------------------
|
1228 |
|
|
//0 x x x x x x x 0 No demap operation
|
1229 |
|
|
//1 0 0 1 1 1 1 1 0 Demap by page
|
1230 |
|
|
//1 0 0 1 1 0 0 0 0/1 256M demap(auto demap)
|
1231 |
|
|
//1 0 0 0 1 0 0 0 0 256M demap(auto demap) (*Illgl*)
|
1232 |
|
|
//1 0 0 1 1 1 0 0 0/1 4M demap(auto demap)
|
1233 |
|
|
//1 0 0 0 1 1 0 0 0 4M demap(auto demap) (*Illgl*)
|
1234 |
|
|
//1 0 0 1 1 1 1 0 0/1 64k demap(auto demap)
|
1235 |
|
|
//1 0 0 0 1 1 1 0 0 64k demap(auto demap) (*Illgl*)
|
1236 |
|
|
//1 0 0 1 1 1 1 1 0/1 8k demap(auto demap)
|
1237 |
|
|
//1 0 0 0 1 1 1 1 0 8k demap(auto demap) (*Illgl*)
|
1238 |
|
|
//1 0 1 1 0 0 0 0 0 demap by ctxt
|
1239 |
|
|
//1 1 x x x x x x 0 demap_all
|
1240 |
|
|
//------------------------------------------------------------------------------------------
|
1241 |
|
|
//-----
|
1242 |
|
|
//All other are illegal combinations
|
1243 |
|
|
//
|
1244 |
|
|
//=========================================================================================
|
1245 |
|
|
// Changes related to Hypervisor/Legacy Compatibility
|
1246 |
|
|
//=========================================================================================
|
1247 |
|
|
//
|
1248 |
|
|
// - Add PID. PID does not effect demap-all. Otherwise it is included in cam, other demap
|
1249 |
|
|
// operations and auto-demap.
|
1250 |
|
|
// - Add R. Real translation ignores context. This is controlled externally by Gk.
|
1251 |
|
|
// - Remove G bit for tte. Input remains in demap-key/cam-key to allow for disabling
|
1252 |
|
|
// of context match Real Translation
|
1253 |
|
|
// - Final Page Size support - 8KB,64KB,4M,256M
|
1254 |
|
|
// - SPARC_HPV_EN has been defined to enable new tlb design support.
|
1255 |
|
|
// Issues :
|
1256 |
|
|
// -Max ptag size is now 28b. Satya, will this help the speed at all. I doubt it !
|
1257 |
|
|
|
1258 |
|
|
//=========================================================================================
|
1259 |
|
|
// Miscellaneous
|
1260 |
|
|
//=========================================================================================
|
1261 |
|
|
wire clk;
|
1262 |
|
|
assign clk = rclk;
|
1263 |
|
|
|
1264 |
|
|
wire async_reset, sync_reset ;
|
1265 |
|
|
assign async_reset = ~arst_l ; // hardware
|
1266 |
|
|
assign sync_reset = (~rst_soft_l & ~rst_tri_en) ; // software
|
1267 |
|
|
|
1268 |
|
|
wire rw_disable ;
|
1269 |
|
|
// INNO - wr/rd gated off. Note required as rst_tri_en is
|
1270 |
|
|
// asserted, but implemented in addition in schematic.
|
1271 |
|
|
assign rw_disable = ~arst_l | rst_tri_en ;
|
1272 |
|
|
|
1273 |
|
|
//=========================================================================================
|
1274 |
|
|
// Stage Data
|
1275 |
|
|
//=========================================================================================
|
1276 |
|
|
// Apply address masking
|
1277 |
|
|
assign tlb_cam_key_masked[40:25]
|
1278 |
|
|
= {16{tlb_addr_mask_l}} &
|
1279 |
|
|
tlb_cam_key[`CAM_VA_47_28_HI:`CAM_VA_47_28_LO+4] ;
|
1280 |
|
|
|
1281 |
|
|
// Reconstitute cam data CHANGE : add additional bit for real mapping
|
1282 |
|
|
assign tlb_cam_data[53:13] = tlb_demap ?
|
1283 |
|
|
tlb_demap_key[40:0] :
|
1284 |
|
|
{tlb_cam_key_masked[40:25],tlb_cam_key[`CAM_VA_47_28_LO+3:0]} ;
|
1285 |
|
|
|
1286 |
|
|
assign tlb_cam_comp_key[26:0] =
|
1287 |
|
|
tlb_demap ?
|
1288 |
|
|
{tlb_demap_key[32:21], tlb_demap_key[19:14],tlb_demap_key[12:7],
|
1289 |
|
|
tlb_demap_key[5:3]} :
|
1290 |
|
|
{tlb_cam_key_masked[32:25],tlb_cam_key[24:21],
|
1291 |
|
|
tlb_cam_key[19:14],tlb_cam_key[12:7],tlb_cam_key[5:3]} ;
|
1292 |
|
|
|
1293 |
|
|
assign tlb_cam_data[12:0] = tlb_ctxt[12:0] ;
|
1294 |
|
|
|
1295 |
|
|
// These signals are flow-thru.
|
1296 |
|
|
assign wr_tte_tag[58:0] = tlb_wr_tte_tag[58:0] ; // CHANGE
|
1297 |
|
|
assign wr_tte_data[42:0] = tlb_wr_tte_data[42:0] ;
|
1298 |
|
|
|
1299 |
|
|
// CHANGE(SATYA) - Currently the rw_index/rw_index_vld are shared by both reads
|
1300 |
|
|
// and writes. However, writes are done in the cycle of broadcast, whereas
|
1301 |
|
|
// the reads are done a cycle later, as given in the model(incorrect)
|
1302 |
|
|
// They have to be treated uniformly. To make the model work, I've assumed the read/write
|
1303 |
|
|
// are done in the cycle the valids are broadcast.
|
1304 |
|
|
always @ (posedge clk)
|
1305 |
|
|
begin
|
1306 |
|
|
if (hold)
|
1307 |
|
|
begin
|
1308 |
|
|
cam_pid[2:0] <= cam_pid[2:0] ;
|
1309 |
|
|
cam_vld_tmp <= cam_vld_tmp ;
|
1310 |
|
|
cam_data[53:0] <= cam_data[53:0] ;
|
1311 |
|
|
demap_other_tmp <= demap_other_tmp ;
|
1312 |
|
|
demap_auto <= demap_auto ;
|
1313 |
|
|
demap_all <= demap_all ;
|
1314 |
|
|
wr_vld_tmp <= wr_vld_tmp ;
|
1315 |
|
|
rd_tag <= rd_tag ;
|
1316 |
|
|
rd_data <= rd_data ;
|
1317 |
|
|
rw_index_vld <= rw_index_vld ;
|
1318 |
|
|
rw_index[5:0] <= rw_index[5:0] ;
|
1319 |
|
|
end
|
1320 |
|
|
else
|
1321 |
|
|
begin
|
1322 |
|
|
cam_pid[2:0] <= tlb_cam_pid[2:0] ;
|
1323 |
|
|
cam_vld_tmp <= tlb_cam_vld ;
|
1324 |
|
|
cam_data[53:0] <= tlb_cam_data[53:0] ;
|
1325 |
|
|
demap_other_tmp <= tlb_demap ;
|
1326 |
|
|
demap_auto <= tlb_demap_auto ;
|
1327 |
|
|
demap_all <= tlb_demap_all ;
|
1328 |
|
|
wr_vld_tmp <= tlb_wr_vld ;
|
1329 |
|
|
rd_tag <= tlb_rd_tag_vld ;
|
1330 |
|
|
rd_data <= tlb_rd_data_vld ;
|
1331 |
|
|
rw_index_vld <= tlb_rw_index_vld ;
|
1332 |
|
|
rw_index[5:0] <= tlb_rw_index[5:0] ;
|
1333 |
|
|
end
|
1334 |
|
|
|
1335 |
|
|
end
|
1336 |
|
|
|
1337 |
|
|
// INNO - gate cam,demap,wr with rst_tri_en.
|
1338 |
|
|
reg rst_tri_en_lat;
|
1339 |
|
|
|
1340 |
|
|
always @ (clk)
|
1341 |
|
|
rst_tri_en_lat = rst_tri_en;
|
1342 |
|
|
|
1343 |
|
|
assign cam_vld = cam_vld_tmp & ~rst_tri_en_lat ;
|
1344 |
|
|
assign demap_other = demap_other_tmp & ~rst_tri_en ;
|
1345 |
|
|
assign wr_vld = wr_vld_tmp & ~rst_tri_en ;
|
1346 |
|
|
|
1347 |
|
|
//=========================================================================================
|
1348 |
|
|
// Generate Write Wordlines
|
1349 |
|
|
//=========================================================================================
|
1350 |
|
|
|
1351 |
|
|
// Based on static rw index
|
1352 |
|
|
// This generates the wordlines for a read/write to the tlb based on index. Wordlines for
|
1353 |
|
|
// the write based on replacement alg. are muxed in later.
|
1354 |
|
|
always @ (/*AUTOSENSE*/rd_data or rd_tag or rw_index or rw_index_vld
|
1355 |
|
|
or wr_vld_tmp)
|
1356 |
|
|
begin
|
1357 |
|
|
for (i=0;i<64;i=i+1)
|
1358 |
|
|
if ((rw_index[5:0] == i) & ((wr_vld_tmp & rw_index_vld) | rd_tag | rd_data))
|
1359 |
|
|
rw_wdline[i] = 1'b1 ;
|
1360 |
|
|
else rw_wdline[i] = 1'b0 ;
|
1361 |
|
|
|
1362 |
|
|
end
|
1363 |
|
|
|
1364 |
|
|
//=========================================================================================
|
1365 |
|
|
// Write TLB
|
1366 |
|
|
//=========================================================================================
|
1367 |
|
|
|
1368 |
|
|
reg [58:0] tmp_tag ;
|
1369 |
|
|
reg [42:0] tmp_data ;
|
1370 |
|
|
|
1371 |
|
|
// Currently TLB_TAG and TLB_DATA RAMs are written in the B phase.
|
1372 |
|
|
// Used bit is set on write in later code as it is also effected by read of tlb.
|
1373 |
|
|
always @ (negedge clk)
|
1374 |
|
|
begin
|
1375 |
|
|
for (j=0;j<64;j=j+1)
|
1376 |
|
|
if (((rw_index_vld & rw_wdline[j]) | (~rw_index_vld & tlb_entry_replace_d2[j])) & wr_vld_tmp & ~rw_disable)
|
1377 |
|
|
begin
|
1378 |
|
|
if (~rst_tri_en)
|
1379 |
|
|
begin
|
1380 |
|
|
tte_tag_ram[j] <= wr_tte_tag[58:0]; // CHANGE
|
1381 |
|
|
tte_data_ram[j] <= wr_tte_data[42:0];
|
1382 |
|
|
//tlb_entry_vld[j] <= wr_tte_tag[`STLB_TAG_V] ;
|
1383 |
|
|
tlb_entry_used[j] <= wr_tte_tag[`STLB_TAG_U] ;
|
1384 |
|
|
tlb_entry_locked[j] = wr_tte_tag[`STLB_TAG_L] ;
|
1385 |
|
|
// write-thru
|
1386 |
|
|
rd_tte_tag[58:0] <= wr_tte_tag[58:0] ; // CHANGE
|
1387 |
|
|
rd_tte_data[42:0] <= wr_tte_data[42:0];
|
1388 |
|
|
|
1389 |
|
|
end
|
1390 |
|
|
else
|
1391 |
|
|
begin
|
1392 |
|
|
tmp_tag[58:0]=tte_tag_ram[j]; // use non-blocking
|
1393 |
|
|
tmp_data[42:0]=tte_data_ram[j];
|
1394 |
|
|
// INNO - read wins.
|
1395 |
|
|
rd_tte_tag[58:0] <=
|
1396 |
|
|
{tmp_tag[58:27], tlb_entry_vld[j],tlb_entry_locked[j],
|
1397 |
|
|
tlb_entry_used[j], tmp_tag[23:0]} ;
|
1398 |
|
|
rd_tte_data[42:0] <= {tmp_data[42:12],tmp_data[11:0]} ;
|
1399 |
|
|
end
|
1400 |
|
|
|
1401 |
|
|
end
|
1402 |
|
|
|
1403 |
|
|
//=========================================================================================
|
1404 |
|
|
// Read STLB
|
1405 |
|
|
//=========================================================================================
|
1406 |
|
|
|
1407 |
|
|
for (m=0;m<64;m=m+1)
|
1408 |
|
|
if (rw_wdline[m] & (rd_tag | rd_data) & ~rw_disable)
|
1409 |
|
|
begin
|
1410 |
|
|
tmp_tag = tte_tag_ram[m] ;
|
1411 |
|
|
tmp_data = tte_data_ram[m] ;
|
1412 |
|
|
if (rd_tag)
|
1413 |
|
|
rd_tte_tag[58:0] <= // CHANGE - Bug 2185
|
1414 |
|
|
{tmp_tag[58:27], tlb_entry_vld[m],tlb_entry_locked[m],
|
1415 |
|
|
tlb_entry_used[m], tmp_tag[23:0]} ;
|
1416 |
|
|
//{tmp_tag[58:29], tlb_entry_vld[m],tlb_entry_locked[m],
|
1417 |
|
|
//tlb_entry_used[m], tmp_tag[25:0]} ;
|
1418 |
|
|
if (rd_data) begin
|
1419 |
|
|
rd_tte_data[42:0] <= {tmp_data[42:12],tmp_data[11:0]} ;
|
1420 |
|
|
end
|
1421 |
|
|
|
1422 |
|
|
end
|
1423 |
|
|
|
1424 |
|
|
if (cam_vld & ~rw_disable)
|
1425 |
|
|
begin
|
1426 |
|
|
//Checking for no hit and multiple hits
|
1427 |
|
|
sat = 64'd0;
|
1428 |
|
|
for (w=0;w<64;w=w+1)
|
1429 |
|
|
begin
|
1430 |
|
|
if(cam_hit[w])
|
1431 |
|
|
begin
|
1432 |
|
|
sat = sat + 64'd1 ;
|
1433 |
|
|
end
|
1434 |
|
|
end
|
1435 |
|
|
// Only one hit occur read the data
|
1436 |
|
|
if(sat == 64'd1)
|
1437 |
|
|
begin
|
1438 |
|
|
for (p=0;p<64;p=p+1)
|
1439 |
|
|
begin
|
1440 |
|
|
if (cam_hit[p])
|
1441 |
|
|
begin
|
1442 |
|
|
rd_tte_data[42:0] <= tte_data_ram[p] ;
|
1443 |
|
|
end
|
1444 |
|
|
end
|
1445 |
|
|
end
|
1446 |
|
|
else
|
1447 |
|
|
begin
|
1448 |
|
|
// INNO - just to keep the tool happy.
|
1449 |
|
|
// ram cell will not be corrupted.
|
1450 |
|
|
for (k=0;k<64;k=k+1)
|
1451 |
|
|
begin
|
1452 |
|
|
if (cam_hit[k])
|
1453 |
|
|
tte_data_ram[k] <= 43'bx ;
|
1454 |
|
|
end
|
1455 |
|
|
rd_tte_data[42:0] <= 43'bx ;
|
1456 |
|
|
end
|
1457 |
|
|
end
|
1458 |
|
|
|
1459 |
|
|
for (s=0;s<64;s=s+1)
|
1460 |
|
|
begin
|
1461 |
|
|
if (cam_hit[s])
|
1462 |
|
|
tlb_entry_used[s] <= 1'b1;
|
1463 |
|
|
end
|
1464 |
|
|
|
1465 |
|
|
// Clear on following edge if necessary.
|
1466 |
|
|
// CHANGE(SATYA) : tlb_entry_used qualified with valid needs to be used to determine
|
1467 |
|
|
// whether the Used bits are to be cleared. This allows invalid entries created
|
1468 |
|
|
// by a demap to be used for replacement. Else we will ignore these entries
|
1469 |
|
|
// for replacement
|
1470 |
|
|
|
1471 |
|
|
//if (tlb_not_writeable)
|
1472 |
|
|
if (~tlb_writeable & ~cam_vld & ~wr_vld & ~rd_tag & ~rst_tri_en)
|
1473 |
|
|
begin
|
1474 |
|
|
for (t=0;t<64;t=t+1)
|
1475 |
|
|
begin
|
1476 |
|
|
//if (~tlb_entry_locked[t])
|
1477 |
|
|
if (~tlb_entry_locked[t] & ~cam_vld & ~wr_vld)
|
1478 |
|
|
tlb_entry_used[t] <= 1'b0;
|
1479 |
|
|
end
|
1480 |
|
|
end
|
1481 |
|
|
end
|
1482 |
|
|
|
1483 |
|
|
// Stage to next cycle.
|
1484 |
|
|
always @ (posedge clk)
|
1485 |
|
|
begin
|
1486 |
|
|
tlb_rd_tte_tag[58:0] <= rd_tte_tag[58:0] ; // CHANGE
|
1487 |
|
|
tlb_rd_tte_data[42:0] <= rd_tte_data[42:0] ;
|
1488 |
|
|
end
|
1489 |
|
|
|
1490 |
|
|
//=========================================================================================
|
1491 |
|
|
// CAM/DEMAP STLB for xlation
|
1492 |
|
|
//=========================================================================================
|
1493 |
|
|
|
1494 |
|
|
// no_hit logic does not work because it is set in multiple clock
|
1495 |
|
|
// domains and is reset before ever having a chance to be effective
|
1496 |
|
|
//reg no_hit ;
|
1497 |
|
|
|
1498 |
|
|
|
1499 |
|
|
// Demap and CAM operation are mutually exclusive.
|
1500 |
|
|
|
1501 |
|
|
always @ ( negedge clk )
|
1502 |
|
|
begin
|
1503 |
|
|
|
1504 |
|
|
for (n=0;n<64;n=n+1)
|
1505 |
|
|
begin
|
1506 |
|
|
/*if (demap_all) begin
|
1507 |
|
|
if (demap_auto & demap_other) ademap_hit[n] =
|
1508 |
|
|
(~mismatch[n] & demap_all_but_locked_hit[n] & demap_other
|
1509 |
|
|
& tlb_entry_vld[n]) ;
|
1510 |
|
|
end
|
1511 |
|
|
else begin */
|
1512 |
|
|
if (demap_auto & demap_other) ademap_hit[n] =
|
1513 |
|
|
(~mismatch[n] & demap_other & tlb_entry_vld[n]) ;
|
1514 |
|
|
//end
|
1515 |
|
|
end
|
1516 |
|
|
|
1517 |
|
|
end // always
|
1518 |
|
|
|
1519 |
|
|
always @ (/*AUTOSENSE*/ /*memory or*/
|
1520 |
|
|
cam_data or cam_pid or cam_vld or demap_all
|
1521 |
|
|
or demap_other or tlb_entry_vld)
|
1522 |
|
|
begin
|
1523 |
|
|
|
1524 |
|
|
for (n=0;n<64;n=n+1)
|
1525 |
|
|
begin
|
1526 |
|
|
tag[58:0] = tte_tag_ram[n] ; // CHANGE
|
1527 |
|
|
|
1528 |
|
|
mismatch_va_b47_28[n] =
|
1529 |
|
|
(tag[`STLB_TAG_VA_47_28_HI:`STLB_TAG_VA_47_28_LO]
|
1530 |
|
|
!= cam_data[`CAM_VA_47_28_HI+13:`CAM_VA_47_28_LO+13]);
|
1531 |
|
|
|
1532 |
|
|
mismatch_va_b27_22[n] =
|
1533 |
|
|
(tag[`STLB_TAG_VA_27_22_HI:`STLB_TAG_VA_27_22_LO]
|
1534 |
|
|
!= cam_data[`CAM_VA_27_22_HI+13:`CAM_VA_27_22_LO+13]);
|
1535 |
|
|
|
1536 |
|
|
mismatch_va_b21_16[n] =
|
1537 |
|
|
(tag[`STLB_TAG_VA_21_16_HI:`STLB_TAG_VA_21_16_LO]
|
1538 |
|
|
!= cam_data[`CAM_VA_21_16_HI+13:`CAM_VA_21_16_LO+13]) ;
|
1539 |
|
|
|
1540 |
|
|
mismatch_va_b15_13[n] =
|
1541 |
|
|
(tag[`STLB_TAG_VA_15_13_HI:`STLB_TAG_VA_15_13_LO]
|
1542 |
|
|
!= cam_data[`CAM_VA_15_13_HI+13:`CAM_VA_15_13_LO+13]) ;
|
1543 |
|
|
|
1544 |
|
|
mismatch_ctxt[n] =
|
1545 |
|
|
(tag[`STLB_TAG_CTXT_12_0_HI:`STLB_TAG_CTXT_12_0_LO]
|
1546 |
|
|
!= cam_data[`CAM_CTXT_12_0_HI:`CAM_CTXT_12_0_LO]) ;
|
1547 |
|
|
|
1548 |
|
|
mismatch_pid[n] = (tag[`STLB_TAG_PID_HI:`STLB_TAG_PID_LO] != cam_pid[2:0]) ;
|
1549 |
|
|
|
1550 |
|
|
mismatch[n] =
|
1551 |
|
|
(mismatch_va_b47_28[n] & cam_data[`CAM_VA_47_28_V+13]) |
|
1552 |
|
|
(mismatch_va_b27_22[n] & tag[`STLB_TAG_VA_27_22_V] & cam_data[`CAM_VA_27_22_V+13]) |
|
1553 |
|
|
(mismatch_va_b21_16[n] & tag[`STLB_TAG_VA_21_16_V] & cam_data[`CAM_VA_21_16_V+13]) |
|
1554 |
|
|
(mismatch_va_b15_13[n] & tag[`STLB_TAG_VA_15_13_V] & cam_data[`CAM_VA_15_13_V+13]) |
|
1555 |
|
|
(mismatch_ctxt[n] & ~cam_data[`CAM_CTXT_GK+13]) |
|
1556 |
|
|
// mismatch is request type not equal to entry type. types are real/virtual.
|
1557 |
|
|
((tag[`STLB_TAG_R] ^ cam_data[`CAM_REAL_V+13]) & ~demap_all) |
|
1558 |
|
|
//(mismatch_real[n] & cam_data[`CAM_REAL_V+13]) |
|
1559 |
|
|
mismatch_pid[n] ; // pid always included in mismatch calculations
|
1560 |
|
|
|
1561 |
|
|
demap_all_but_locked_hit[n] =
|
1562 |
|
|
~tag[`STLB_TAG_L] & demap_all ;
|
1563 |
|
|
|
1564 |
|
|
cam_hit[n] =
|
1565 |
|
|
~mismatch[n] & cam_vld & tlb_entry_vld[n] ;
|
1566 |
|
|
|
1567 |
|
|
if (demap_all) begin
|
1568 |
|
|
// Satya(10/3) - I've simplified the demap-all equation
|
1569 |
|
|
// Pls confirm that this is okay. Otherwise we will nee
|
1570 |
|
|
// qualifying bits for the pid and r fields.
|
1571 |
|
|
/*demap_hit[n] =
|
1572 |
|
|
(demap_all_but_locked_hit[n] & demap_other) ;*/
|
1573 |
|
|
demap_hit[n] =
|
1574 |
|
|
(~mismatch[n] & demap_all_but_locked_hit[n] & demap_other
|
1575 |
|
|
& tlb_entry_vld[n]) ;
|
1576 |
|
|
// qualification with demap_auto to prevent ademap_hit from
|
1577 |
|
|
// being cleared. Satya-we could get rid of this.
|
1578 |
|
|
// ademap_hit[n] is a phase A device and needs to be in a clocked always block
|
1579 |
|
|
//if (demap_auto & demap_other & clk) ademap_hit[n] =
|
1580 |
|
|
// (~mismatch[n] & demap_all_but_locked_hit[n] & demap_other
|
1581 |
|
|
// & tlb_entry_vld[n]) ;
|
1582 |
|
|
end
|
1583 |
|
|
else begin
|
1584 |
|
|
demap_hit[n] =
|
1585 |
|
|
(~mismatch[n] & demap_other & tlb_entry_vld[n]) ;
|
1586 |
|
|
// qualification with demap_auto to prevent ademap_hit from
|
1587 |
|
|
// being cleared. Satya-this is the only one we need.
|
1588 |
|
|
//if (demap_auto & demap_other & clk) ademap_hit[n] =
|
1589 |
|
|
// (~mismatch[n] & demap_other & tlb_entry_vld[n]) ;
|
1590 |
|
|
end
|
1591 |
|
|
// no_hit = cam_vld ;
|
1592 |
|
|
end
|
1593 |
|
|
|
1594 |
|
|
end // always
|
1595 |
|
|
|
1596 |
|
|
assign tlb_cam_hit = |cam_hit[63:0] ;
|
1597 |
|
|
|
1598 |
|
|
// Read on CAM hit occurs on negedge.
|
1599 |
|
|
/* MOVED TO COMMON ALWAYS BLOCK
|
1600 |
|
|
always @ (negedge clk)
|
1601 |
|
|
begin
|
1602 |
|
|
if (|cam_hit[63:0])
|
1603 |
|
|
begin
|
1604 |
|
|
for (p=0;p<64;p=p+1)
|
1605 |
|
|
if (cam_hit[p])
|
1606 |
|
|
begin
|
1607 |
|
|
rd_tte_data[42:0] <= tte_data_ram[p] ;
|
1608 |
|
|
end
|
1609 |
|
|
// no_hit = 1'b0 ;
|
1610 |
|
|
end
|
1611 |
|
|
// else if (no_hit) begin
|
1612 |
|
|
// rd_tte_data[42:0] <= {43{1'bx}};
|
1613 |
|
|
// no_hit = 1'b0 ;
|
1614 |
|
|
// end
|
1615 |
|
|
end
|
1616 |
|
|
*/
|
1617 |
|
|
// Change tlb_entry_vld handling for multi-threaded tlb writes.
|
1618 |
|
|
// A write is always preceeded by an autodemap. The intent is to make the result of autodemap
|
1619 |
|
|
// (clearing of vld bit if hit) invisible until write occurs. In the same cycle that the write
|
1620 |
|
|
// occurs, the vld bit for an entry will be cleared if there is an autodemap hit. The write
|
1621 |
|
|
// and admp action may even be to same entry. The write must dominate. There is no need to
|
1622 |
|
|
// clear the dmp latches after the write/clear has occurred as the subsequent admp will set
|
1623 |
|
|
// up new state in the latches.
|
1624 |
|
|
|
1625 |
|
|
// Define valid bit based on write/demap/reset.
|
1626 |
|
|
always @ (negedge clk)
|
1627 |
|
|
begin
|
1628 |
|
|
for (r=0;r<64;r=r+1)
|
1629 |
|
|
begin // for
|
1630 |
|
|
if (((rw_index_vld & rw_wdline[r]) | (~rw_index_vld & tlb_entry_replace_d2[r])) &
|
1631 |
|
|
wr_vld & ~rw_disable)
|
1632 |
|
|
tlb_entry_vld[r] <= wr_tte_tag[`STLB_TAG_V] ; // write
|
1633 |
|
|
else begin
|
1634 |
|
|
if (ademap_hit[r] & wr_vld) // autodemap specifically
|
1635 |
|
|
tlb_entry_vld[r] <= 1'b0 ;
|
1636 |
|
|
end
|
1637 |
|
|
if ((demap_hit[r] & ~demap_auto) | sync_reset) // non-auto-demap, reset
|
1638 |
|
|
tlb_entry_vld[r] <= 1'b0 ;
|
1639 |
|
|
end // for
|
1640 |
|
|
end
|
1641 |
|
|
|
1642 |
|
|
|
1643 |
|
|
// async reset.
|
1644 |
|
|
always @ (async_reset)
|
1645 |
|
|
begin
|
1646 |
|
|
for (l=0;l<64;l=l+1)
|
1647 |
|
|
begin
|
1648 |
|
|
tlb_entry_vld[l] <= 1'b0 ;
|
1649 |
|
|
end
|
1650 |
|
|
end
|
1651 |
|
|
|
1652 |
|
|
//=========================================================================================
|
1653 |
|
|
// TAG COMPARISON
|
1654 |
|
|
//=========================================================================================
|
1655 |
|
|
|
1656 |
|
|
reg [30:0] va_tag_plus ;
|
1657 |
|
|
|
1658 |
|
|
// Stage to m
|
1659 |
|
|
always @(posedge clk)
|
1660 |
|
|
begin
|
1661 |
|
|
// INNO - add hold to this input
|
1662 |
|
|
if (hold)
|
1663 |
|
|
va_tag_plus[30:0] <= va_tag_plus[30:0] ;
|
1664 |
|
|
else
|
1665 |
|
|
va_tag_plus[30:0]
|
1666 |
|
|
<= {tlb_cam_comp_key[26:0],tlb_bypass_va[12:10],tlb_bypass};
|
1667 |
|
|
end
|
1668 |
|
|
|
1669 |
|
|
assign vrtl_pgnum_m[29:0] = va_tag_plus[30:1] ;
|
1670 |
|
|
assign bypass = va_tag_plus[0] ;
|
1671 |
|
|
|
1672 |
|
|
// Mux to bypass va or form pa tag based on tte-data.
|
1673 |
|
|
|
1674 |
|
|
assign phy_pgnum_m[29:3] =
|
1675 |
|
|
{rd_tte_data[`STLB_DATA_PA_39_28_HI:`STLB_DATA_PA_39_28_LO],
|
1676 |
|
|
rd_tte_data[`STLB_DATA_PA_27_22_HI:`STLB_DATA_PA_27_22_LO],
|
1677 |
|
|
rd_tte_data[`STLB_DATA_PA_21_16_HI:`STLB_DATA_PA_21_16_LO],
|
1678 |
|
|
rd_tte_data[`STLB_DATA_PA_15_13_HI:`STLB_DATA_PA_15_13_LO]};
|
1679 |
|
|
|
1680 |
|
|
// Derive the tlb-based physical address.
|
1681 |
|
|
assign pgnum_m[2:0] = vrtl_pgnum_m[2:0];
|
1682 |
|
|
assign pgnum_m[5:3] = (~rd_tte_data[`STLB_DATA_15_13_SEL] & ~bypass)
|
1683 |
|
|
? phy_pgnum_m[5:3] : vrtl_pgnum_m[5:3] ;
|
1684 |
|
|
assign pgnum_m[11:6] = (~rd_tte_data[`STLB_DATA_21_16_SEL] & ~bypass)
|
1685 |
|
|
? phy_pgnum_m[11:6] : vrtl_pgnum_m[11:6] ;
|
1686 |
|
|
assign pgnum_m[17:12] = (~rd_tte_data[`STLB_DATA_27_22_SEL] & ~bypass)
|
1687 |
|
|
? phy_pgnum_m[17:12] : vrtl_pgnum_m[17:12] ;
|
1688 |
|
|
assign pgnum_m[29:18] = ~bypass ? phy_pgnum_m[29:18] : vrtl_pgnum_m[29:18];
|
1689 |
|
|
|
1690 |
|
|
// Stage to g
|
1691 |
|
|
// Flop tags in tlb itself and do comparison immediately after rising edge.
|
1692 |
|
|
// Similarly stage va/pa tag to g
|
1693 |
|
|
always @(posedge clk)
|
1694 |
|
|
begin
|
1695 |
|
|
pgnum_g[29:0] <= pgnum_m[29:0];
|
1696 |
|
|
// rm hold on these inputs.
|
1697 |
|
|
cache_set_vld_g[3:0] <= cache_set_vld[3:0] ;
|
1698 |
|
|
cache_ptag_w0_g[29:0] <= cache_ptag_w0[29:0] ;
|
1699 |
|
|
cache_ptag_w1_g[29:0] <= cache_ptag_w1[29:0] ;
|
1700 |
|
|
cache_ptag_w2_g[29:0] <= cache_ptag_w2[29:0] ;
|
1701 |
|
|
cache_ptag_w3_g[29:0] <= cache_ptag_w3[29:0] ;
|
1702 |
|
|
end
|
1703 |
|
|
|
1704 |
|
|
|
1705 |
|
|
// Need to stage by a cycle where used.
|
1706 |
|
|
assign tlb_pgnum[39:10] = pgnum_g[29:0] ;
|
1707 |
|
|
// Same cycle as cam - meant for one load on critical path
|
1708 |
|
|
assign tlb_pgnum_crit[39:10] = pgnum_m[29:0] ;
|
1709 |
|
|
|
1710 |
|
|
|
1711 |
|
|
assign cache_way_hit[0] =
|
1712 |
|
|
(cache_ptag_w0_g[29:0] == pgnum_g[29:0]) & cache_set_vld_g[0];
|
1713 |
|
|
assign cache_way_hit[1] =
|
1714 |
|
|
(cache_ptag_w1_g[29:0] == pgnum_g[29:0]) & cache_set_vld_g[1];
|
1715 |
|
|
assign cache_way_hit[2] =
|
1716 |
|
|
(cache_ptag_w2_g[29:0] == pgnum_g[29:0]) & cache_set_vld_g[2];
|
1717 |
|
|
assign cache_way_hit[3] =
|
1718 |
|
|
(cache_ptag_w3_g[29:0] == pgnum_g[29:0]) & cache_set_vld_g[3];
|
1719 |
|
|
|
1720 |
|
|
assign cache_hit = |cache_way_hit[3:0];
|
1721 |
|
|
|
1722 |
|
|
|
1723 |
|
|
//=========================================================================================
|
1724 |
|
|
// TLB ENTRY REPLACEMENT
|
1725 |
|
|
//=========================================================================================
|
1726 |
|
|
|
1727 |
|
|
// A single Used bit is used to track the replacement state of each entry.
|
1728 |
|
|
// Only an unused entry can be replaced.
|
1729 |
|
|
// An Unused entry is :
|
1730 |
|
|
// - an invalid entry
|
1731 |
|
|
// - a valid entry which has had its Used bit cleared.
|
1732 |
|
|
// - on write of a valid entry, the Used bit is set.
|
1733 |
|
|
// - The Used bit of a valid entry is cleared if all
|
1734 |
|
|
// entries have their Used bits set and the entry itself is not Locked.
|
1735 |
|
|
// A locked entry should always appear to be Used.
|
1736 |
|
|
// A single priority-encoder is required to evaluate the used status. Priority is static
|
1737 |
|
|
// and used entry0 is of the highest priority if unused.
|
1738 |
|
|
|
1739 |
|
|
// Timing :
|
1740 |
|
|
// Used bit gets updated by cam-hit or hit on negedge.
|
1741 |
|
|
// After Used bit gets updated off negedge, the replacement entry can be generated in
|
1742 |
|
|
// Phase2. In parallel, it is determined whether all Used bits are set or not. If
|
1743 |
|
|
// so, then they are cleared on the next negedge with the replacement entry generated
|
1744 |
|
|
// in the related Phase1
|
1745 |
|
|
|
1746 |
|
|
// Choosing replacement entry
|
1747 |
|
|
// Replacement entry is integer k
|
1748 |
|
|
|
1749 |
|
|
assign tlb_not_writeable = &used[63:0] ;
|
1750 |
|
|
/*
|
1751 |
|
|
// Used bit can be set because of write or because of cam-hit.
|
1752 |
|
|
always @(negedge clk)
|
1753 |
|
|
begin
|
1754 |
|
|
for (s=0;s<64;s=s+1)
|
1755 |
|
|
begin
|
1756 |
|
|
if (cam_hit[s])
|
1757 |
|
|
tlb_entry_used[s] <= 1'b1;
|
1758 |
|
|
end
|
1759 |
|
|
|
1760 |
|
|
// Clear on following edge if necessary.
|
1761 |
|
|
// CHANGE(SATYA) : tlb_entry_used qualified with valid needs to be used to determine
|
1762 |
|
|
// whether the Used bits are to be cleared. This allows invalid entries created
|
1763 |
|
|
// by a demap to be used for replacement. Else we will ignore these entries
|
1764 |
|
|
// for replacement
|
1765 |
|
|
|
1766 |
|
|
if (tlb_not_writeable)
|
1767 |
|
|
begin
|
1768 |
|
|
for (t=0;t<64;t=t+1)
|
1769 |
|
|
begin
|
1770 |
|
|
if (~tlb_entry_locked[t])
|
1771 |
|
|
tlb_entry_used[t] <= 1'b0;
|
1772 |
|
|
end
|
1773 |
|
|
end
|
1774 |
|
|
end
|
1775 |
|
|
*/
|
1776 |
|
|
|
1777 |
|
|
// Determine whether entry should be squashed.
|
1778 |
|
|
|
1779 |
|
|
assign used[63:0] = tlb_entry_used[63:0] & tlb_entry_vld[63:0] ;
|
1780 |
|
|
|
1781 |
|
|
/*assign squash[0] = 1'b0 ;
|
1782 |
|
|
assign squash[1] = ~used[0] ;
|
1783 |
|
|
assign squash[2] = |(~used[1:0]) ;
|
1784 |
|
|
assign squash[3] = |(~used[2:0]) ;
|
1785 |
|
|
assign squash[4] = |(~used[3:0]) ;
|
1786 |
|
|
assign squash[5] = |(~used[4:0]) ;
|
1787 |
|
|
assign squash[6] = |(~used[5:0]) ;
|
1788 |
|
|
assign squash[7] = |(~used[6:0]) ;
|
1789 |
|
|
assign squash[8] = |(~used[7:0]) ;
|
1790 |
|
|
assign squash[9] = |(~used[8:0]) ;
|
1791 |
|
|
assign squash[10] = |(~used[9:0]) ;
|
1792 |
|
|
assign squash[11] = |(~used[10:0]) ;
|
1793 |
|
|
assign squash[12] = |(~used[11:0]) ;
|
1794 |
|
|
assign squash[13] = |(~used[12:0]) ;
|
1795 |
|
|
assign squash[14] = |(~used[13:0]) ;
|
1796 |
|
|
assign squash[15] = |(~used[14:0]) ;
|
1797 |
|
|
assign squash[16] = |(~used[15:0]) ;
|
1798 |
|
|
assign squash[17] = |(~used[16:0]) ;
|
1799 |
|
|
assign squash[18] = |(~used[17:0]) ;
|
1800 |
|
|
assign squash[19] = |(~used[18:0]) ;
|
1801 |
|
|
assign squash[20] = |(~used[19:0]) ;
|
1802 |
|
|
assign squash[21] = |(~used[20:0]) ;
|
1803 |
|
|
assign squash[22] = |(~used[21:0]) ;
|
1804 |
|
|
assign squash[23] = |(~used[22:0]) ;
|
1805 |
|
|
assign squash[24] = |(~used[23:0]) ;
|
1806 |
|
|
assign squash[25] = |(~used[24:0]) ;
|
1807 |
|
|
assign squash[26] = |(~used[25:0]) ;
|
1808 |
|
|
assign squash[27] = |(~used[26:0]) ;
|
1809 |
|
|
assign squash[28] = |(~used[27:0]) ;
|
1810 |
|
|
assign squash[29] = |(~used[28:0]) ;
|
1811 |
|
|
assign squash[30] = |(~used[29:0]) ;
|
1812 |
|
|
assign squash[31] = |(~used[30:0]) ;
|
1813 |
|
|
assign squash[32] = |(~used[31:0]) ;
|
1814 |
|
|
assign squash[33] = |(~used[32:0]) ;
|
1815 |
|
|
assign squash[34] = |(~used[33:0]) ;
|
1816 |
|
|
assign squash[35] = |(~used[34:0]) ;
|
1817 |
|
|
assign squash[36] = |(~used[35:0]) ;
|
1818 |
|
|
assign squash[37] = |(~used[36:0]) ;
|
1819 |
|
|
assign squash[38] = |(~used[37:0]) ;
|
1820 |
|
|
assign squash[39] = |(~used[38:0]) ;
|
1821 |
|
|
assign squash[40] = |(~used[39:0]) ;
|
1822 |
|
|
assign squash[41] = |(~used[40:0]) ;
|
1823 |
|
|
assign squash[42] = |(~used[41:0]) ;
|
1824 |
|
|
assign squash[43] = |(~used[42:0]) ;
|
1825 |
|
|
assign squash[44] = |(~used[43:0]) ;
|
1826 |
|
|
assign squash[45] = |(~used[44:0]) ;
|
1827 |
|
|
assign squash[46] = |(~used[45:0]) ;
|
1828 |
|
|
assign squash[47] = |(~used[46:0]) ;
|
1829 |
|
|
assign squash[48] = |(~used[47:0]) ;
|
1830 |
|
|
assign squash[49] = |(~used[48:0]) ;
|
1831 |
|
|
assign squash[50] = |(~used[49:0]) ;
|
1832 |
|
|
assign squash[51] = |(~used[50:0]) ;
|
1833 |
|
|
assign squash[52] = |(~used[51:0]) ;
|
1834 |
|
|
assign squash[53] = |(~used[52:0]) ;
|
1835 |
|
|
assign squash[54] = |(~used[53:0]) ;
|
1836 |
|
|
assign squash[55] = |(~used[54:0]) ;
|
1837 |
|
|
assign squash[56] = |(~used[55:0]) ;
|
1838 |
|
|
assign squash[57] = |(~used[56:0]) ;
|
1839 |
|
|
assign squash[58] = |(~used[57:0]) ;
|
1840 |
|
|
assign squash[59] = |(~used[58:0]) ;
|
1841 |
|
|
assign squash[60] = |(~used[59:0]) ;
|
1842 |
|
|
assign squash[61] = |(~used[60:0]) ;
|
1843 |
|
|
assign squash[62] = |(~used[61:0]) ;
|
1844 |
|
|
assign squash[63] = |(~used[62:0]) ; */
|
1845 |
|
|
|
1846 |
|
|
// Based on updated Used state, generate replacement entry.
|
1847 |
|
|
// So, replacement entries can be generated on a cycle-by-cycle basis.
|
1848 |
|
|
//always @(/*AUTOSENSE*/squash or used)
|
1849 |
|
|
|
1850 |
|
|
reg [63:0] tlb_entry_replace_d1;
|
1851 |
|
|
reg tlb_replace_flag;
|
1852 |
|
|
always @(/*AUTOSENSE*/used)
|
1853 |
|
|
begin
|
1854 |
|
|
tlb_replace_flag=1'b0;
|
1855 |
|
|
tlb_entry_replace_d1 = 64'b0;
|
1856 |
|
|
// Priority is given to entry0
|
1857 |
|
|
for (u=0;u<64;u=u+1)
|
1858 |
|
|
begin
|
1859 |
|
|
if(~tlb_replace_flag & ~used[u])
|
1860 |
|
|
begin
|
1861 |
|
|
tlb_entry_replace_d1[u] = ~used[u] ;
|
1862 |
|
|
tlb_replace_flag=1'b1;
|
1863 |
|
|
end
|
1864 |
|
|
end
|
1865 |
|
|
if(~tlb_replace_flag) begin
|
1866 |
|
|
tlb_entry_replace_d1[63] = 1'b1;
|
1867 |
|
|
end
|
1868 |
|
|
end
|
1869 |
|
|
always @(posedge clk)
|
1870 |
|
|
begin
|
1871 |
|
|
// named in this manner to keep arch model happy.
|
1872 |
|
|
tlb_entry_replace <= tlb_entry_replace_d1 ;
|
1873 |
|
|
end
|
1874 |
|
|
// INNO - 2 stage delay before update is visible
|
1875 |
|
|
always @(posedge clk)
|
1876 |
|
|
begin
|
1877 |
|
|
tlb_entry_replace_d2 <= tlb_entry_replace ;
|
1878 |
|
|
end
|
1879 |
|
|
|
1880 |
|
|
//=========================================================================================
|
1881 |
|
|
// TLB WRITEABLE DETECTION
|
1882 |
|
|
//=========================================================================================
|
1883 |
|
|
|
1884 |
|
|
// 2-cycles later, tlb become writeable
|
1885 |
|
|
always @(posedge clk)
|
1886 |
|
|
begin
|
1887 |
|
|
tlb_not_writeable_d1 <= tlb_not_writeable ;
|
1888 |
|
|
end
|
1889 |
|
|
|
1890 |
|
|
always @(posedge clk)
|
1891 |
|
|
begin
|
1892 |
|
|
tlb_writeable <= ~tlb_not_writeable_d1 ;
|
1893 |
|
|
end
|
1894 |
|
|
|
1895 |
|
|
endmodule
|
1896 |
|
|
|
1897 |
|
|
`endif
|
1898 |
|
|
|