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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:  (C) Athree, 2009
// Engineer: Dmitry Rozhdestvenskiy 
// Email dmitry.rozhdestvenskiy@srisc.com dmitryr@a3.spb.ru divx4log@narod.ru
// 
// Design Name:    Bridge from Wishbone to Altera DDR3 controller
// Module Name:    wb2altddr3 
// Project Name:   SPARC SoC single-core
//
// LICENSE:
// This is a Free Hardware Design; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// version 2 as published by the Free Software Foundation.
// The above named program is distributed in the hope that it will
// be useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
//////////////////////////////////////////////////////////////////////////////////
 
module dram_wb(
   input             clk200,
   input             rup,
   input             rdn,
 
   input             wb_clk_i,
   input             wb_rst_i,
 
   input      [63:0] wb_dat_i,
   output reg [63:0] wb_dat_o,
   input      [63:0] wb_adr_i,
   input      [ 7:0] wb_sel_i,
   input             wb_we_i,
   input             wb_cyc_i,
   input             wb_stb_i,
   output            wb_ack_o,
   output            wb_err_o,
   output            wb_rty_o,
   input             wb_cab_i,
 
   inout      [63:0] ddr3_dq,
   inout      [ 7:0] ddr3_dqs,
   inout      [ 7:0] ddr3_dqs_n,
   inout             ddr3_ck,
   inout             ddr3_ck_n,
   output            ddr3_reset,
   output     [12:0] ddr3_a,
   output     [ 2:0] ddr3_ba,
   output            ddr3_ras_n,
   output            ddr3_cas_n,
   output            ddr3_we_n,
   output            ddr3_cs_n,
   output            ddr3_odt,
   output            ddr3_ce,
   output     [ 7:0] ddr3_dm,
 
   output            phy_init_done,
 
   output     [ 7:0] fifo_used,
 
   input             dcm_locked,
   input             sysrst
);
 
wire [255:0] rd_data_fifo_out;
reg  [ 23:0] rd_addr_cache;
wire [ 71:0] wr_dout;
wire [ 31:0] cmd_out;
reg          wb_stb_i_d;
reg  [ 31:0] mask_data;
 
wire fifo_empty;
 
wire [13:0] parallelterminationcontrol;
wire [13:0] seriesterminationcontrol;
 
dram dram_ctrl(
    .pll_ref_clk(clk200),
    .global_reset_n(sysrst),  // Resets all
    .soft_reset_n(1),    // Resets all but PLL
 
    .reset_request_n(), // Active when not ready (PLL not locked)
    .reset_phy_clk_n(), // Reset input sync to phy_clk
 
    .phy_clk(ddr_clk),         // User clock
    .dll_reference_clk(), // For external DLL
 
    .dqs_delay_ctrl_export(),
    .aux_scan_clk(),
    .aux_scan_clk_reset_n(),
    .aux_full_rate_clk(),
    .aux_half_rate_clk(),
 
    .oct_ctl_rs_value(seriesterminationcontrol),
    .oct_ctl_rt_value(parallelterminationcontrol),
 
    .local_init_done(phy_init_done),
 
    .local_ready(dram_ready),
    .local_address(cmd_out[25:2]),
    .local_burstbegin(push_tran),
    .local_read_req(!cmd_out[31] && push_tran),
    .local_write_req(cmd_out[31] && push_tran),
    .local_wdata_req(),
    .local_wdata({wr_dout[63:0],wr_dout[63:0],wr_dout[63:0],wr_dout[63:0]}),
    .local_be(mask_data),
    .local_size(3'b001),
    .local_rdata_valid(rd_data_valid),
    .local_rdata(rd_data_fifo_out),
    .local_refresh_ack(),
 
    .mem_clk(ddr3_ck),
    .mem_clk_n(ddr3_ck_n),
    .mem_reset_n(ddr3_reset),
    .mem_dq(ddr3_dq),
    .mem_dqs(ddr3_dqs),
    .mem_dqsn(ddr3_dqs_n),
    .mem_odt(ddr3_odt),
    .mem_cs_n(ddr3_cs_n),
    .mem_cke(ddr3_ce),
    .mem_addr(ddr3_a),
    .mem_ba(ddr3_ba),
    .mem_ras_n(ddr3_ras_n),
    .mem_cas_n(ddr3_cas_n),
    .mem_we_n(ddr3_we_n),
    .mem_dm(ddr3_dm)
);
 
assign ddr_rst=!phy_init_done;
 
oct_alt_oct_power_f4c oct
(
    .parallelterminationcontrol(parallelterminationcontrol),
    .seriesterminationcontrol(seriesterminationcontrol),
    .rdn(rdn),
    .rup(rup)
) ;
 
always @( * )
   case(cmd_out[1:0])
      2'b00:mask_data<={24'h000000,wr_dout[71:64]};
      2'b01:mask_data<={16'h0000,wr_dout[71:64],8'h00};
      2'b10:mask_data<={8'h00,wr_dout[71:64],16'h0000};
      2'b11:mask_data<={wr_dout[71:64],24'h000000};
   endcase
 
wire [254:0] trig0;
 
/*ila1 ila1_inst (
    .CONTROL(CONTROL),
    .CLK(ddr_clk),
    .TRIG0(trig0)
);*/
 
assign trig0[127:0]=rd_data_fifo_out;
assign trig0[199:128]=wr_dout;
assign trig0[231:200]=cmd_out;
assign trig0[232]=0;
assign trig0[233]=0;
assign trig0[234]=rd_data_valid;
assign trig0[235]=0;
assign trig0[236]=fifo_empty;
assign trig0[237]=0;
assign trig0[238]=0;
assign trig0[254:239]=0;
 
reg fifo_full_d;
reg written;
 
dram_fifo fifo(
    .aclr(ddr_rst),
 
    .wrclk(wb_clk_i),
    .rdclk(ddr_clk),
 
    .data({wb_sel_i,wb_dat_i,wb_we_i,wb_adr_i[33:3]}),
    .wrreq(wb_cyc_i && wb_stb_i && (!wb_stb_i_d || (fifo_full_d && !written)) && !fifo_full && !(rd_addr_cache==wb_adr_i[28:5] && !wb_we_i)),
    .wrfull(fifo_full),
 
    .rdreq(fifo_read),
    .q({wr_dout,cmd_out}),
    .wrusedw(fifo_used),
    .rdempty(fifo_empty)
);
 
`define DDR_IDLE    3'b000
`define DDR_WRITE_1 3'b001
`define DDR_WRITE_2 3'b010
`define DDR_READ_1  3'b011
`define DDR_READ_2  3'b100
 
reg [2:0] ddr_state;
reg       push_tran;
reg       fifo_read;
 
always @(posedge ddr_clk or posedge ddr_rst)
   if(ddr_rst)
      begin
         ddr_state<=`DDR_IDLE;
         fifo_read<=0;
         push_tran<=0;
         rd_data_valid_stb<=0;
      end
   else
      case(ddr_state)
         `DDR_IDLE:
            if(!fifo_empty && dram_ready)
               begin
                  push_tran<=1;
                  if(cmd_out[31])
                     begin
                        ddr_state<=`DDR_WRITE_1;
                        fifo_read<=1;
                     end
                  else
                     ddr_state<=`DDR_READ_1;
               end
         `DDR_WRITE_1:
            begin
               push_tran<=0;
               fifo_read<=0;
               ddr_state<=`DDR_WRITE_2; // Protect against FIFO empty signal latency
            end
         `DDR_WRITE_2:
            ddr_state<=`DDR_IDLE;
         `DDR_READ_1:
            begin
               push_tran<=0;
               if(rd_data_valid)
                  begin
                     rd_data_valid_stb<=1;
                     fifo_read<=1;
                     ddr_state<=`DDR_READ_2;
                  end
            end
         `DDR_READ_2:
            begin
               fifo_read<=0;
               if(wb_ack_d1) // Enought delay to protect against FIFO empty signal latency
                  begin
                     rd_data_valid_stb<=0;
                     ddr_state<=`DDR_IDLE;
                  end
            end
      endcase
 
reg rd_data_valid_stb;
reg rd_data_valid_stb_d1;
reg rd_data_valid_stb_d2;
reg rd_data_valid_stb_d3;
reg rd_data_valid_stb_d4;
reg [255:0] rd_data_fifo_out_d;
reg wb_ack_d;
reg wb_ack_d1;
 
always @( * )
   case(wb_adr_i[4:3])
      2'b00:wb_dat_o<=rd_data_fifo_out_d[63:0];
      2'b01:wb_dat_o<=rd_data_fifo_out_d[127:64];
      2'b10:wb_dat_o<=rd_data_fifo_out_d[191:128];
      2'b11:wb_dat_o<=rd_data_fifo_out_d[255:192];
   endcase
 
always @(posedge wb_clk_i or posedge wb_rst_i)
   if(wb_rst_i)
      rd_addr_cache<=24'hFFFFFF;
   else
   begin
      wb_stb_i_d<=wb_stb_i;
      if(wb_cyc_i && wb_stb_i)
         if(!wb_we_i)
            rd_addr_cache<=wb_ack_o ? wb_adr_i[28:5]:rd_addr_cache;
         else
            if(rd_addr_cache==wb_adr_i[28:5])
               rd_addr_cache<=24'hFFFFFF;
      rd_data_valid_stb_d1<=rd_data_valid_stb;
      rd_data_valid_stb_d2<=rd_data_valid_stb_d1;
      rd_data_valid_stb_d3<=rd_data_valid_stb_d2;
      rd_data_valid_stb_d4<=rd_data_valid_stb_d3;
      fifo_full_d<=fifo_full;
      if(wb_ack_o)
         written<=0;
      else
         if(!fifo_full && fifo_full_d)
            written<=1;
   end
 
assign wb_ack_o=wb_we_i ? (wb_cyc_i && wb_stb_i && !fifo_full):(rd_data_valid_stb_d2 && !rd_data_valid_stb_d3) || (rd_addr_cache==wb_adr_i[28:5]);
 
always @(posedge ddr_clk)
   begin
      wb_ack_d<=wb_ack_o;
      wb_ack_d1<=wb_ack_d;
      if(rd_data_valid)
         rd_data_fifo_out_d<=rd_data_fifo_out;
   end
 
endmodule

Line No.	Rev	Author	Line
1	2	dmitryr	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Company: (C) Athree, 2009`
4			`// Engineer: Dmitry Rozhdestvenskiy`
5			`// Email dmitry.rozhdestvenskiy@srisc.com dmitryr@a3.spb.ru divx4log@narod.ru`
6			`//`
7			`// Design Name: Bridge from Wishbone to Altera DDR3 controller`
8			`// Module Name: wb2altddr3`
9			`// Project Name: SPARC SoC single-core`
10			`//`
11			`// LICENSE:`
12			`// This is a Free Hardware Design; you can redistribute it and/or`
13			`// modify it under the terms of the GNU General Public License`
14			`// version 2 as published by the Free Software Foundation.`
15			`// The above named program is distributed in the hope that it will`
16			`// be useful, but WITHOUT ANY WARRANTY; without even the implied`
17			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.`
18			`// See the GNU General Public License for more details.`
19			`//`
20			`//////////////////////////////////////////////////////////////////////////////////`
21
22			`module dram_wb(`
23			`input clk200,`
24			`input rup,`
25			`input rdn,`
26
27			`input wb_clk_i,`
28			`input wb_rst_i,`
29
30			`input [63:0] wb_dat_i,`
31			`output reg [63:0] wb_dat_o,`
32			`input [63:0] wb_adr_i,`
33			`input [ 7:0] wb_sel_i,`
34			`input wb_we_i,`
35			`input wb_cyc_i,`
36			`input wb_stb_i,`
37			`output wb_ack_o,`
38			`output wb_err_o,`
39			`output wb_rty_o,`
40			`input wb_cab_i,`
41
42			`inout [63:0] ddr3_dq,`
43			`inout [ 7:0] ddr3_dqs,`
44			`inout [ 7:0] ddr3_dqs_n,`
45			`inout ddr3_ck,`
46			`inout ddr3_ck_n,`
47			`output ddr3_reset,`
48			`output [12:0] ddr3_a,`
49			`output [ 2:0] ddr3_ba,`
50			`output ddr3_ras_n,`
51			`output ddr3_cas_n,`
52			`output ddr3_we_n,`
53			`output ddr3_cs_n,`
54			`output ddr3_odt,`
55			`output ddr3_ce,`
56			`output [ 7:0] ddr3_dm,`
57
58			`output phy_init_done,`
59	3	dmitryr
60			`output [ 7:0] fifo_used,`
61	2	dmitryr
62			`input dcm_locked,`
63			`input sysrst`
64			`);`
65
66			`wire [255:0] rd_data_fifo_out;`
67			`reg [ 23:0] rd_addr_cache;`
68			`wire [ 71:0] wr_dout;`
69			`wire [ 31:0] cmd_out;`
70			`reg wb_stb_i_d;`
71			`reg [ 31:0] mask_data;`
72
73			`wire fifo_empty;`
74
75			`wire [13:0] parallelterminationcontrol;`
76			`wire [13:0] seriesterminationcontrol;`
77
78			`dram dram_ctrl(`
79			`.pll_ref_clk(clk200),`
80			`.global_reset_n(sysrst), // Resets all`
81			`.soft_reset_n(1), // Resets all but PLL`
82
83			`.reset_request_n(), // Active when not ready (PLL not locked)`
84			`.reset_phy_clk_n(), // Reset input sync to phy_clk`
85
86			`.phy_clk(ddr_clk), // User clock`
87			`.dll_reference_clk(), // For external DLL`
88
89			`.dqs_delay_ctrl_export(),`
90			`.aux_scan_clk(),`
91			`.aux_scan_clk_reset_n(),`
92			`.aux_full_rate_clk(),`
93			`.aux_half_rate_clk(),`
94
95			`.oct_ctl_rs_value(seriesterminationcontrol),`
96			`.oct_ctl_rt_value(parallelterminationcontrol),`
97
98			`.local_init_done(phy_init_done),`
99
100			`.local_ready(dram_ready),`
101			`.local_address(cmd_out[25:2]),`
102			`.local_burstbegin(push_tran),`
103			`.local_read_req(!cmd_out[31] && push_tran),`
104			`.local_write_req(cmd_out[31] && push_tran),`
105			`.local_wdata_req(),`
106			`.local_wdata({wr_dout[63:0],wr_dout[63:0],wr_dout[63:0],wr_dout[63:0]}),`
107			`.local_be(mask_data),`
108			`.local_size(3'b001),`
109			`.local_rdata_valid(rd_data_valid),`
110			`.local_rdata(rd_data_fifo_out),`
111			`.local_refresh_ack(),`
112
113			`.mem_clk(ddr3_ck),`
114			`.mem_clk_n(ddr3_ck_n),`
115			`.mem_reset_n(ddr3_reset),`
116			`.mem_dq(ddr3_dq),`
117			`.mem_dqs(ddr3_dqs),`
118			`.mem_dqsn(ddr3_dqs_n),`
119			`.mem_odt(ddr3_odt),`
120			`.mem_cs_n(ddr3_cs_n),`
121			`.mem_cke(ddr3_ce),`
122			`.mem_addr(ddr3_a),`
123			`.mem_ba(ddr3_ba),`
124			`.mem_ras_n(ddr3_ras_n),`
125			`.mem_cas_n(ddr3_cas_n),`
126			`.mem_we_n(ddr3_we_n),`
127			`.mem_dm(ddr3_dm)`
128			`);`
129
130			`assign ddr_rst=!phy_init_done;`
131
132			`oct_alt_oct_power_f4c oct`
133			`(`
134			`.parallelterminationcontrol(parallelterminationcontrol),`
135			`.seriesterminationcontrol(seriesterminationcontrol),`
136			`.rdn(rdn),`
137			`.rup(rup)`
138			`) ;`
139
140			`always @( * )`
141			`case(cmd_out[1:0])`
142			`2'b00:mask_data<={24'h000000,wr_dout[71:64]};`
143			`2'b01:mask_data<={16'h0000,wr_dout[71:64],8'h00};`
144			`2'b10:mask_data<={8'h00,wr_dout[71:64],16'h0000};`
145			`2'b11:mask_data<={wr_dout[71:64],24'h000000};`
146			`endcase`
147
148			`wire [254:0] trig0;`
149
150			`/*ila1 ila1_inst (`
151			`.CONTROL(CONTROL),`
152			`.CLK(ddr_clk),`
153			`.TRIG0(trig0)`
154			`);*/`
155
156			`assign trig0[127:0]=rd_data_fifo_out;`
157			`assign trig0[199:128]=wr_dout;`
158			`assign trig0[231:200]=cmd_out;`
159			`assign trig0[232]=0;`
160			`assign trig0[233]=0;`
161			`assign trig0[234]=rd_data_valid;`
162			`assign trig0[235]=0;`
163			`assign trig0[236]=fifo_empty;`
164			`assign trig0[237]=0;`
165			`assign trig0[238]=0;`
166			`assign trig0[254:239]=0;`
167
168			`reg fifo_full_d;`
169	3	dmitryr	`reg written;`
170	2	dmitryr
171			`dram_fifo fifo(`
172			`.aclr(ddr_rst),`
173
174			`.wrclk(wb_clk_i),`
175			`.rdclk(ddr_clk),`
176
177			`.data({wb_sel_i,wb_dat_i,wb_we_i,wb_adr_i[33:3]}),`
178	3	dmitryr	`.wrreq(wb_cyc_i && wb_stb_i && (!wb_stb_i_d \|\| (fifo_full_d && !written)) && !fifo_full && !(rd_addr_cache==wb_adr_i[28:5] && !wb_we_i)),`
179	2	dmitryr	`.wrfull(fifo_full),`
180
181			`.rdreq(fifo_read),`
182			`.q({wr_dout,cmd_out}),`
183	3	dmitryr	`.wrusedw(fifo_used),`
184	2	dmitryr	`.rdempty(fifo_empty)`
185			`);`
186
187	3	dmitryr	`define DDR_IDLE 3'b000
188			`define DDR_WRITE_1 3'b001
189			`define DDR_WRITE_2 3'b010
190			`define DDR_READ_1 3'b011
191			`define DDR_READ_2 3'b100
192	2	dmitryr
193	3	dmitryr	`reg [2:0] ddr_state;`
194			`reg push_tran;`
195			`reg fifo_read;`
196	2	dmitryr
197	3	dmitryr	`always @(posedge ddr_clk or posedge ddr_rst)`
198			`if(ddr_rst)`
199			`begin`
200			ddr_state<=`DDR_IDLE;
201			`fifo_read<=0;`
202			`push_tran<=0;`
203			`rd_data_valid_stb<=0;`
204			`end`
205			`else`
206			`case(ddr_state)`
207			`DDR_IDLE:
208			`if(!fifo_empty && dram_ready)`
209			`begin`
210			`push_tran<=1;`
211			`if(cmd_out[31])`
212			`begin`
213			ddr_state<=`DDR_WRITE_1;
214			`fifo_read<=1;`
215			`end`
216			`else`
217			ddr_state<=`DDR_READ_1;
218			`end`
219			`DDR_WRITE_1:
220			`begin`
221			`push_tran<=0;`
222			`fifo_read<=0;`
223			ddr_state<=`DDR_WRITE_2; // Protect against FIFO empty signal latency
224			`end`
225			`DDR_WRITE_2:
226			ddr_state<=`DDR_IDLE;
227			`DDR_READ_1:
228			`begin`
229			`push_tran<=0;`
230			`if(rd_data_valid)`
231			`begin`
232			`rd_data_valid_stb<=1;`
233			`fifo_read<=1;`
234			ddr_state<=`DDR_READ_2;
235			`end`
236			`end`
237			`DDR_READ_2:
238			`begin`
239			`fifo_read<=0;`
240			`if(wb_ack_d1) // Enought delay to protect against FIFO empty signal latency`
241			`begin`
242			`rd_data_valid_stb<=0;`
243			ddr_state<=`DDR_IDLE;
244			`end`
245			`end`
246			`endcase`
247	2	dmitryr
248			`reg rd_data_valid_stb;`
249			`reg rd_data_valid_stb_d1;`
250			`reg rd_data_valid_stb_d2;`
251			`reg rd_data_valid_stb_d3;`
252			`reg rd_data_valid_stb_d4;`
253			`reg [255:0] rd_data_fifo_out_d;`
254			`reg wb_ack_d;`
255			`reg wb_ack_d1;`
256
257			`always @( * )`
258			`case(wb_adr_i[4:3])`
259			`2'b00:wb_dat_o<=rd_data_fifo_out_d[63:0];`
260			`2'b01:wb_dat_o<=rd_data_fifo_out_d[127:64];`
261			`2'b10:wb_dat_o<=rd_data_fifo_out_d[191:128];`
262			`2'b11:wb_dat_o<=rd_data_fifo_out_d[255:192];`
263			`endcase`
264
265			`always @(posedge wb_clk_i or posedge wb_rst_i)`
266			`if(wb_rst_i)`
267			`rd_addr_cache<=24'hFFFFFF;`
268			`else`
269			`begin`
270			`wb_stb_i_d<=wb_stb_i;`
271			`if(wb_cyc_i && wb_stb_i)`
272			`if(!wb_we_i)`
273			`rd_addr_cache<=wb_ack_o ? wb_adr_i[28:5]:rd_addr_cache;`
274			`else`
275			`if(rd_addr_cache==wb_adr_i[28:5])`
276			`rd_addr_cache<=24'hFFFFFF;`
277			`rd_data_valid_stb_d1<=rd_data_valid_stb;`
278			`rd_data_valid_stb_d2<=rd_data_valid_stb_d1;`
279			`rd_data_valid_stb_d3<=rd_data_valid_stb_d2;`
280			`rd_data_valid_stb_d4<=rd_data_valid_stb_d3;`
281	3	dmitryr	`fifo_full_d<=fifo_full;`
282			`if(wb_ack_o)`
283			`written<=0;`
284			`else`
285			`if(!fifo_full && fifo_full_d)`
286			`written<=1;`
287	2	dmitryr	`end`
288
289	3	dmitryr	`assign wb_ack_o=wb_we_i ? (wb_cyc_i && wb_stb_i && !fifo_full):(rd_data_valid_stb_d2 && !rd_data_valid_stb_d3) \|\| (rd_addr_cache==wb_adr_i[28:5]);`
290	2	dmitryr
291			`always @(posedge ddr_clk)`
292			`begin`
293			`wb_ack_d<=wb_ack_o;`
294			`wb_ack_d1<=wb_ack_d;`
295			`if(rd_data_valid)`
296	3	dmitryr	`rd_data_fifo_out_d<=rd_data_fifo_out;`
297	2	dmitryr	`end`
298
299			`endmodule`

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