1 |
5 |
dmitryr |
module l1dir(
|
2 |
|
|
input clk,
|
3 |
|
|
input reset,
|
4 |
|
|
|
5 |
|
|
input cpu, // Issuing CPU number
|
6 |
|
|
input strobe, // Start transaction
|
7 |
|
|
input [ 1:0] way, // Way to allocate for allocating loads
|
8 |
|
|
input [39:0] address,
|
9 |
|
|
input load,
|
10 |
|
|
input ifill,
|
11 |
|
|
input store,
|
12 |
|
|
input cas,
|
13 |
|
|
input swap,
|
14 |
|
|
input strload,
|
15 |
|
|
input strstore,
|
16 |
|
|
input cacheable,
|
17 |
|
|
input prefetch,
|
18 |
|
|
input invalidate,
|
19 |
|
|
input blockstore,
|
20 |
|
|
|
21 |
|
|
output [111:0] inval_vect0, // Invalidation vector
|
22 |
|
|
output [111:0] inval_vect1,
|
23 |
|
|
output [ 1:0] othercachehit, // Other cache hit in the same CPU, wayval0/wayval1
|
24 |
|
|
output [ 1:0] othercpuhit, // Any cache hit in the other CPU, wayval0/wayval1
|
25 |
|
|
output [ 1:0] wayval0, // Way valid
|
26 |
|
|
output [ 1:0] wayval1, // Second way valid for ifill
|
27 |
|
|
output ready // Directory init done
|
28 |
|
|
);
|
29 |
|
|
|
30 |
|
|
wire [3:0] rdy;
|
31 |
|
|
wire dquery0=(!cpu) && store && (!blockstore);
|
32 |
|
|
wire dquery1= cpu && store && (!blockstore);
|
33 |
|
|
wire dalloc0=(!cpu) && cacheable && (!invalidate) && load && (!prefetch);
|
34 |
|
|
wire dalloc1= cpu && cacheable && (!invalidate) && load && (!prefetch);
|
35 |
6 |
dmitryr |
wire ddealloc0=((!cpu) && ((ifill && (!prefetch) && (!invalidate)) || cas || swap || strstore || (store && blockstore))) ||
|
36 |
|
|
( cpu && ((load && cacheable && (!prefetch) && (!invalidate)) || (ifill && (!prefetch) && (!invalidate)) || store || cas || swap || strload || strstore));
|
37 |
|
|
wire ddealloc1=( cpu && ((ifill && (!prefetch) && (!invalidate)) || cas || swap || strstore || (store && blockstore))) ||
|
38 |
|
|
((!cpu) && ((load && cacheable && (!prefetch) && (!invalidate)) || (ifill && (!prefetch) && (!invalidate)) || store || cas || swap || strload || strstore));
|
39 |
5 |
dmitryr |
|
40 |
|
|
wire iquery0=0;
|
41 |
|
|
wire iquery1=0;
|
42 |
|
|
wire ialloc0=(!cpu) && cacheable && (!invalidate) && ifill;
|
43 |
|
|
wire ialloc1= cpu && cacheable && (!invalidate) && ifill;
|
44 |
|
|
wire idealloc0=((!cpu) && ((load && cacheable && (!prefetch) && (!invalidate)) || store || cas || swap || strstore)) ||
|
45 |
6 |
dmitryr |
( cpu && ((load && cacheable && (!prefetch) && (!invalidate)) || (ifill && (!prefetch) && (!invalidate)) || store || cas || swap || strload || strstore));
|
46 |
5 |
dmitryr |
wire idealloc1=( cpu && ((load && cacheable && (!prefetch) && (!invalidate)) || store || cas || swap || strstore )) ||
|
47 |
6 |
dmitryr |
((!cpu) && ((load && cacheable && (!prefetch) && (!invalidate)) || (ifill && (!prefetch) && (!invalidate)) || store || cas || swap || strload || strstore));
|
48 |
5 |
dmitryr |
|
49 |
|
|
|
50 |
|
|
wire [2:0] cpu0_dhit0;
|
51 |
|
|
wire [2:0] cpu0_dhit1;
|
52 |
|
|
wire [2:0] cpu1_dhit0;
|
53 |
|
|
wire [2:0] cpu1_dhit1;
|
54 |
|
|
wire [2:0] cpu0_ihit;
|
55 |
|
|
wire [2:0] cpu1_ihit;
|
56 |
|
|
wire invalidate_d=invalidate && load;
|
57 |
|
|
wire invalidate_i=invalidate && ifill;
|
58 |
|
|
|
59 |
|
|
reg ifill_d;
|
60 |
|
|
reg load_d;
|
61 |
|
|
reg cacheable_d;
|
62 |
|
|
reg cpu_d;
|
63 |
|
|
reg [39:0] address_d;
|
64 |
|
|
reg strobe_d;
|
65 |
|
|
reg strobe_d1;
|
66 |
|
|
reg strobe_d2;
|
67 |
|
|
|
68 |
|
|
always @(posedge clk)
|
69 |
|
|
begin
|
70 |
|
|
strobe_d<=strobe;
|
71 |
|
|
strobe_d1<=strobe_d;
|
72 |
|
|
strobe_d2<=strobe_d1;
|
73 |
|
|
end
|
74 |
|
|
|
75 |
|
|
always @(posedge clk)
|
76 |
|
|
if(strobe)
|
77 |
|
|
begin
|
78 |
|
|
ifill_d<=ifill;
|
79 |
|
|
load_d<=load;
|
80 |
|
|
cacheable_d<=cacheable;
|
81 |
|
|
cpu_d<=cpu;
|
82 |
|
|
address_d<=address;
|
83 |
|
|
end
|
84 |
|
|
|
85 |
|
|
l1ddir cpu0_ddir(
|
86 |
|
|
.clk(clk),
|
87 |
|
|
.reset(reset),
|
88 |
|
|
|
89 |
|
|
.index(address[10:4]),
|
90 |
|
|
.way(way),
|
91 |
6 |
dmitryr |
.tag(address[39:11]),
|
92 |
5 |
dmitryr |
.strobe(strobe),
|
93 |
|
|
.query(dquery0),
|
94 |
|
|
.allocate(dalloc0),
|
95 |
|
|
.deallocate(ddealloc0),
|
96 |
|
|
.dualdealloc(ifill),
|
97 |
|
|
.invalidate(invalidate_d && !cpu),
|
98 |
|
|
|
99 |
|
|
.hit0(cpu0_dhit0),
|
100 |
|
|
.hit1(cpu0_dhit1),
|
101 |
|
|
|
102 |
|
|
.ready(rdy[0])
|
103 |
|
|
);
|
104 |
|
|
|
105 |
|
|
l1ddir cpu1_ddir(
|
106 |
|
|
.clk(clk),
|
107 |
|
|
.reset(reset),
|
108 |
|
|
|
109 |
|
|
.index(address[10:4]),
|
110 |
|
|
.way(way),
|
111 |
|
|
.tag(address[39:11]),
|
112 |
|
|
.strobe(strobe),
|
113 |
|
|
.query(dquery1),
|
114 |
|
|
.allocate(dalloc1),
|
115 |
|
|
.deallocate(ddealloc1),
|
116 |
|
|
.dualdealloc(ifill),
|
117 |
|
|
.invalidate(invalidate_d && cpu),
|
118 |
|
|
|
119 |
|
|
.hit0(cpu1_dhit0),
|
120 |
|
|
.hit1(cpu1_dhit1),
|
121 |
|
|
|
122 |
|
|
.ready(rdy[1])
|
123 |
|
|
);
|
124 |
|
|
|
125 |
|
|
l1idir cpu0_idir(
|
126 |
|
|
.clk(clk),
|
127 |
|
|
.reset(reset),
|
128 |
|
|
|
129 |
|
|
.index(address[11:5]),
|
130 |
|
|
.way(way),
|
131 |
|
|
.tag(address[39:12]),
|
132 |
|
|
.strobe(strobe),
|
133 |
|
|
.query(iquery0),
|
134 |
|
|
.allocate(ialloc0),
|
135 |
|
|
.deallocate(idealloc0),
|
136 |
|
|
.invalidate(invalidate_i && !cpu),
|
137 |
|
|
|
138 |
|
|
.hit(cpu0_ihit),
|
139 |
|
|
|
140 |
|
|
.ready(rdy[2])
|
141 |
|
|
);
|
142 |
|
|
|
143 |
|
|
l1idir cpu1_idir(
|
144 |
|
|
.clk(clk),
|
145 |
|
|
.reset(reset),
|
146 |
|
|
|
147 |
|
|
.index(address[11:5]),
|
148 |
|
|
.way(way),
|
149 |
|
|
.tag(address[39:12]),
|
150 |
|
|
.strobe(strobe),
|
151 |
|
|
.query(iquery1),
|
152 |
|
|
.allocate(ialloc1),
|
153 |
|
|
.deallocate(idealloc1),
|
154 |
|
|
.invalidate(invalidate_i && cpu),
|
155 |
|
|
|
156 |
|
|
.hit(cpu1_ihit),
|
157 |
|
|
|
158 |
|
|
.ready(rdy[3])
|
159 |
|
|
);
|
160 |
|
|
|
161 |
|
|
assign ready=(!rdy[0] | !rdy[1] | !rdy[2] | !rdy[3]) ? 0:1;
|
162 |
|
|
assign inval_vect0[3:0]={wayval0,cpu0_ihit[2] && (!address_d[5]),cpu0_dhit0[2] && (address_d[5:4]==2'b00)};
|
163 |
|
|
assign inval_vect0[7:4]={wayval0,cpu1_ihit[2] && (!address_d[5]),cpu1_dhit0[2] && (address_d[5:4]==2'b00)};
|
164 |
|
|
assign inval_vect0[31:8]=0;
|
165 |
|
|
assign inval_vect0[34:32]={wayval0,cpu0_dhit0[2] && (address_d[5:4]==2'b01)};
|
166 |
|
|
assign inval_vect0[37:35]={wayval0,cpu1_dhit0[2] && (address_d[5:4]==2'b01)};
|
167 |
|
|
assign inval_vect0[55:38]=0;
|
168 |
|
|
assign inval_vect0[59:56]={wayval0,cpu0_ihit[2] && address_d[5],cpu0_dhit0[2] && (address_d[5:4]==2'b10)};
|
169 |
|
|
assign inval_vect0[63:60]={wayval0,cpu1_ihit[2] && address_d[5],cpu1_dhit0[2] && (address_d[5:4]==2'b10)};
|
170 |
|
|
assign inval_vect0[87:64]=0;
|
171 |
|
|
assign inval_vect0[90:88]={wayval0,cpu0_dhit0[2] && (address_d[5:4]==2'b11)};
|
172 |
|
|
assign inval_vect0[93:91]={wayval0,cpu1_dhit0[2] && (address_d[5:4]==2'b11)};
|
173 |
|
|
assign inval_vect0[111:94]=0;
|
174 |
|
|
|
175 |
|
|
assign inval_vect1[3:0]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b00)};
|
176 |
|
|
assign inval_vect1[7:4]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b00)};
|
177 |
|
|
assign inval_vect1[31:8]=0;
|
178 |
|
|
assign inval_vect1[34:32]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b01)};
|
179 |
|
|
assign inval_vect1[37:35]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b01)};
|
180 |
|
|
assign inval_vect1[55:38]=0;
|
181 |
|
|
assign inval_vect1[59:56]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b10)};
|
182 |
|
|
assign inval_vect1[63:60]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b10)};
|
183 |
|
|
assign inval_vect1[87:64]=0;
|
184 |
|
|
assign inval_vect1[90:88]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b11)};
|
185 |
|
|
assign inval_vect1[93:91]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b11)};
|
186 |
|
|
assign inval_vect1[111:94]=0;
|
187 |
|
|
|
188 |
|
|
assign wayval0=cpu0_dhit0[1:0] | cpu1_dhit0[1:0] | cpu0_ihit[1:0] | cpu1_ihit[1:0];
|
189 |
|
|
assign wayval1=cpu0_dhit1[1:0] | cpu1_dhit1[1:0];
|
190 |
|
|
assign othercachehit[0]=((!cpu_d) && ifill_d && cpu0_dhit0[2]) ||
|
191 |
|
|
( cpu_d && ifill_d && cpu1_dhit0[2]) ||
|
192 |
|
|
((!cpu_d) && load_d && cacheable_d && cpu0_ihit[2]) ||
|
193 |
|
|
( cpu_d && load_d && cacheable_d && cpu1_ihit[2]);
|
194 |
|
|
assign othercachehit[1]=((!cpu_d) && ifill_d && cpu0_dhit1[2]) ||
|
195 |
|
|
( cpu_d && ifill_d && cpu1_dhit1[2]);
|
196 |
|
|
assign othercpuhit[0]=((!cpu_d) && (cpu1_dhit0[2] || cpu1_ihit[2])) ||
|
197 |
|
|
( cpu_d && (cpu0_dhit0[2] || cpu0_ihit[2]));
|
198 |
|
|
assign othercpuhit[1]=((!cpu_d) && ifill_d && cpu1_dhit1[2]) ||
|
199 |
|
|
( cpu_d && ifill_d && cpu0_dhit1[2]);
|
200 |
|
|
|
201 |
|
|
wire [149:0] ILA_DATA;
|
202 |
|
|
|
203 |
|
|
st2 st2_inst(
|
204 |
|
|
.acq_clk(clk),
|
205 |
|
|
.acq_data_in(ILA_DATA),
|
206 |
|
|
.acq_trigger_in(ILA_DATA),
|
207 |
|
|
.storage_enable(strobe || strobe_d || strobe_d1 || strobe_d2)
|
208 |
|
|
);
|
209 |
|
|
|
210 |
|
|
assign ILA_DATA[39:0]=address;
|
211 |
|
|
assign ILA_DATA[41:40]=way;
|
212 |
|
|
assign ILA_DATA[42]=strobe;
|
213 |
|
|
assign ILA_DATA[43]=load;
|
214 |
|
|
assign ILA_DATA[44]=ifill;
|
215 |
|
|
assign ILA_DATA[45]=store;
|
216 |
|
|
assign ILA_DATA[46]=cas;
|
217 |
|
|
assign ILA_DATA[47]=swap;
|
218 |
|
|
assign ILA_DATA[48]=strload;
|
219 |
|
|
assign ILA_DATA[49]=strstore;
|
220 |
|
|
assign ILA_DATA[50]=cacheable;
|
221 |
|
|
assign ILA_DATA[51]=prefetch;
|
222 |
|
|
assign ILA_DATA[52]=invalidate;
|
223 |
|
|
assign ILA_DATA[53]=blockstore;
|
224 |
|
|
assign ILA_DATA[55:54]=othercachehit;
|
225 |
|
|
assign ILA_DATA[57:56]=othercpuhit;
|
226 |
|
|
assign ILA_DATA[59:58]=wayval0;
|
227 |
|
|
assign ILA_DATA[61:60]=wayval1;
|
228 |
|
|
assign ILA_DATA[69:62]=inval_vect0[7:0];
|
229 |
|
|
assign ILA_DATA[75:70]=inval_vect0[37:32];
|
230 |
|
|
assign ILA_DATA[83:76]=inval_vect0[63:56];
|
231 |
|
|
assign ILA_DATA[89:84]=inval_vect0[93:88];
|
232 |
|
|
assign ILA_DATA[97:90]=inval_vect1[7:0];
|
233 |
|
|
assign ILA_DATA[103:98]=inval_vect1[37:32];
|
234 |
|
|
assign ILA_DATA[111:104]=inval_vect1[63:56];
|
235 |
|
|
assign ILA_DATA[117:112]=inval_vect1[93:88];
|
236 |
|
|
assign ILA_DATA[118]=dquery0;
|
237 |
|
|
assign ILA_DATA[119]=dquery1;
|
238 |
|
|
assign ILA_DATA[120]=dalloc0;
|
239 |
|
|
assign ILA_DATA[121]=dalloc1;
|
240 |
|
|
assign ILA_DATA[122]=ddealloc0;
|
241 |
|
|
assign ILA_DATA[123]=ddealloc1;
|
242 |
|
|
assign ILA_DATA[124]=iquery0;
|
243 |
|
|
assign ILA_DATA[125]=iquery1;
|
244 |
|
|
assign ILA_DATA[126]=ialloc0;
|
245 |
|
|
assign ILA_DATA[127]=ialloc1;
|
246 |
|
|
assign ILA_DATA[128]=idealloc0;
|
247 |
|
|
assign ILA_DATA[129]=idealloc1;
|
248 |
|
|
|
249 |
|
|
endmodule
|