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[/] [sparc64soc/] [trunk/] [os2wb/] [l1idir.v] - Blame information for rev 5

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1 5 dmitryr 
module l1idir(
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   input clk,
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   input reset,
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   input [ 6:0] index,
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   input [ 1:0] way,
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   input [27:0] tag,
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        input        strobe,
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   input        query,
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   input        allocate,   //tag->{way,index}
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   input        deallocate, //if({way,index}==tag) {way,index}<-FFFFFF
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   input        invalidate, //all ways
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   output reg [2:0] hit,
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   output reg       ready // directory init completed
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);
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`define INVAL_TAG 28'h8000000
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reg [27:0] tag_d;
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reg [ 6:0] addr;
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reg [ 3:0] we;
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reg [ 3:0] re;
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reg [28:0] di;
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wire [28:0] do0;
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wire [28:0] do1;
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wire [28:0] do2;
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wire [28:0] do3;
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reg query_d;
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reg deallocate_d;
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reg query_d1;
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reg deallocate_d1;
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always @(posedge clk)
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   if(strobe)
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      if(query || deallocate)
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         begin
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            tag_d<=tag;
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         end
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always @(posedge clk)
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   begin
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      query_d<=query && strobe;
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      deallocate_d<=deallocate && strobe;
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      query_d1<=query_d;
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      deallocate_d1<=deallocate_d;
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   end
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cachedir icache01 (
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   .clock(clk),
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   .enable(we[0] || re[0] || we[1] || re[1]),
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   .wren_a(we[0]),
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   .address_a({1'b0,addr}),
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   .data_a(di),
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   .q_a(do0),
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   .wren_b(we[1]),
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   .address_b({1'b1,addr}),
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   .data_b(di),
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   .q_b(do1)
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);
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cachedir icache23 (
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   .clock(clk),
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   .enable(we[2] || re[2] || we[3] || re[3]),
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   .wren_a(we[2]),
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   .address_a({1'b0,addr}),
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   .data_a(di),
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   .q_a(do2),
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   .wren_b(we[3]),
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   .address_b({1'b1,addr}),
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   .data_b(di),
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   .q_b(do3)
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);
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wire [3:0] hitvect={(do3[28:1]==tag_d),(do2[28:1]==tag_d),(do1[28:1]==tag_d),(do0[28:1]==tag_d)};
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`define L1IDIR_RESET   3'b000
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`define L1IDIR_INIT    3'b001
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`define L1IDIR_IDLE    3'b010
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`define L1IDIR_READ    3'b011
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`define L1IDIR_DEALLOC 3'b100
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reg [2:0] state;
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always @(posedge clk or posedge reset)
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   if(reset)
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      begin
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         state<=`L1IDIR_RESET;
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         ready<=0;
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      end
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   else
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      case(state)
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         `L1IDIR_RESET:
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            begin
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               addr<=7'b0;
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               di<={`INVAL_TAG,1'b0};
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               we<=4'b1111;
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               state<=`L1IDIR_INIT;
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            end
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         `L1IDIR_INIT:
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            begin
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               addr<=addr+1;
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               if(addr==7'b1111111)
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                  begin
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                     we<=4'b0;
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                     ready<=1;
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                     state<=`L1IDIR_IDLE;
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                  end
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            end
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         `L1IDIR_IDLE:
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                           if(strobe)
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            if(invalidate)
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               begin
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                  we<=4'b1111;
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                  addr<=index;
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                  di<={`INVAL_TAG,1'b0};
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               end
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            else
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                                if(allocate)
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                                   begin
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                                          case(way)
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                                                 2'b00:we<=4'b0001;
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                                                 2'b01:we<=4'b0010;
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                                                 2'b10:we<=4'b0100;
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                                                 2'b11:we<=4'b1000;
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                                          endcase
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                                          addr<=index;
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                                          di<={tag,1'b0};
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                                   end
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                                else
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                                   if(deallocate)
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                                          begin
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                                                 re<=4'b1111;
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                                                 we<=0;
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                                                 addr<=index;
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                                                 state<=`L1IDIR_READ;
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                                          end
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                                   else
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                     if(query)
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                        begin
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                           addr<=index;
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                           re<=4'b1111;
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                           we<=0;
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                        end
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                     else
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                        begin
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                           we<=0;
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                           re<=0;
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                        end
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                        `L1IDIR_READ:
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                           state<=`L1IDIR_DEALLOC;
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         `L1IDIR_DEALLOC:
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            begin
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               re<=0;
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               di<={`INVAL_TAG,1'b0};
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               we<=hitvect;
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               state<=`L1IDIR_IDLE;
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            end
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      endcase
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always @(posedge clk)
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   if(query_d1 || deallocate_d1)
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      case(hitvect)
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         4'b0001:hit<=3'b100;
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         4'b0010:hit<=3'b101;
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         4'b0100:hit<=3'b110;
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         4'b1000:hit<=3'b111;
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         default:hit<=3'b000; // Hits will be ORed then
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      endcase
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   else
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      if(strobe)
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         hit<=3'b000;
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endmodule

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