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[/] [sparc64soc/] [trunk/] [os2wb/] [s1_top.v] - Blame information for rev 5

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1 2 dmitryr
/*
2
 * Simply RISC S1 Core Top-Level
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 *
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 * (C) 2007 Simply RISC LLP
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 * AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
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 *
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 * LICENSE:
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 * This is a Free Hardware Design; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License
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 * version 2 as published by the Free Software Foundation.
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 * The above named program is distributed in the hope that it will
12
 * be useful, but WITHOUT ANY WARRANTY; without even the implied
13
 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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 * See the GNU General Public License for more details.
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 *
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 * DESCRIPTION:
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 * This block implements the top-level of the S1 Core.
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 * It is just a schematic with four instances:
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 * 1) one single SPARC Core of the OpenSPARC T1;
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 * 2) a SPARC Core to Wishbone Master bridge;
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 * 3) a Reset Controller;
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 * 4) an Interrupt Controller.
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 *
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 */
25
 
26
module s1_top (
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    input         sys_clock_i,
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    input         sys_reset_i,
29
 
30
    input         eth_irq_i,
31
 
32
    input         wbm_ack_i,
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    input  [63:0] wbm_data_i,
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    output        wbm_cycle_o,
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    output        wbm_strobe_o,
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    output        wbm_we_o,
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    output [63:0] wbm_addr_o,
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    output [63:0] wbm_data_o,
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    output [ 7:0] wbm_sel_o
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);
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  /*
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   * Wires
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   */
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  // Wires connected to SPARC Core outputs
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  // pcx
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  wire [4:0]   spc_pcx_req_pq;    // processor to pcx request
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  wire         spc_pcx_atom_pq;   // processor to pcx atomic request
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  wire [123:0] spc_pcx_data_pa;  // processor to pcx packet
51
 
52
  // shadow scan
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  wire     spc_sscan_so;         // From ifu of sparc_ifu.v
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  wire     spc_scanout0;         // From test_stub of test_stub_bist.v
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  wire     spc_scanout1;         // From test_stub of test_stub_bist.v
56
 
57
  // bist
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  wire     tst_ctu_mbist_done;  // From test_stub of test_stub_two_bist.v
59
  wire     tst_ctu_mbist_fail;  // From test_stub of test_stub_two_bist.v
60
 
61
  // fuse
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  wire     spc_efc_ifuse_data;     // From ifu of sparc_ifu.v
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  wire     spc_efc_dfuse_data;     // From ifu of sparc_ifu.v
64
 
65
  // Wires connected to SPARC Core inputs
66
 
67
  // cpx interface
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  wire [4:0] pcx_spc_grant_px; // pcx to processor grant info  
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  wire       cpx_spc_data_rdy_cx2; // cpx data inflight to sparc  
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  wire [144:0] cpx_spc_data_cx2;     // cpx to sparc data packet
71
 
72
  wire [3:0]  const_cpuid;
73
  wire [7:0]  const_maskid;           // To ifu of sparc_ifu.v
74
 
75
  // sscan
76
  wire        ctu_tck;                // To ifu of sparc_ifu.v
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  wire        ctu_sscan_se;           // To ifu of sparc_ifu.v
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  wire        ctu_sscan_snap;         // To ifu of sparc_ifu.v
79
  wire [3:0]  ctu_sscan_tid;          // To ifu of sparc_ifu.v
80
 
81
  // bist
82
  wire        ctu_tst_mbist_enable;   // To test_stub of test_stub_bist.v
83
 
84
  // efuse
85
  wire        efc_spc_fuse_clk1;
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  wire        efc_spc_fuse_clk2;
87
  wire        efc_spc_ifuse_ashift;
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  wire        efc_spc_ifuse_dshift;
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  wire        efc_spc_ifuse_data;
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  wire        efc_spc_dfuse_ashift;
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  wire        efc_spc_dfuse_dshift;
92
  wire        efc_spc_dfuse_data;
93
 
94
  // scan and macro test
95
  wire        ctu_tst_macrotest;      // To test_stub of test_stub_bist.v
96
  wire        ctu_tst_scan_disable;   // To test_stub of test_stub_bist.v
97
  wire        ctu_tst_short_chain;    // To test_stub of test_stub_bist.v
98
  wire        global_shift_enable;    // To test_stub of test_stub_two_bist.v
99
  wire        ctu_tst_scanmode;       // To test_stub of test_stub_two_bist.v
100
  wire        spc_scanin0;
101
  wire        spc_scanin1;
102
 
103
  // clk
104
  wire        cluster_cken;           // To spc_hdr of cluster_header.v
105
  wire        gclk;                   // To spc_hdr of cluster_header.v
106
 
107
  // reset
108
  wire        cmp_grst_l;
109
  wire        cmp_arst_l;
110
  wire        ctu_tst_pre_grst_l;     // To test_stub of test_stub_bist.v
111
 
112
  wire        adbginit_l;             // To spc_hdr of cluster_header.v
113
  wire        gdbginit_l;             // To spc_hdr of cluster_header.v
114
 
115
  // Reset signal from the reset controller to the bridge
116
  wire sys_reset_final;
117
 
118
  // Interrupt Source from the interrupt controller to the bridge
119
 
120
  /*
121
   * SPARC Core module instance
122
   */
123
reg [  4:0] pcx_spc_grant_px_fifo;
124
 
125
  sparc sparc_0 (
126
 
127
    // Wires connected to SPARC Core outputs
128
    .spc_pcx_req_pq(spc_pcx_req_pq),
129
    .spc_pcx_atom_pq(spc_pcx_atom_pq),
130
    .spc_pcx_data_pa(spc_pcx_data_pa),
131
    .spc_sscan_so(spc_sscan_so),
132
    .spc_scanout0(spc_scanout0),
133
    .spc_scanout1(spc_scanout1),
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    .tst_ctu_mbist_done(tst_ctu_mbist_done),
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    .tst_ctu_mbist_fail(tst_ctu_mbist_fail),
136
    .spc_efc_ifuse_data(spc_efc_ifuse_data),
137
    .spc_efc_dfuse_data(spc_efc_dfuse_data),
138
 
139
    // Wires connected to SPARC Core inputs
140
    .pcx_spc_grant_px(pcx_spc_grant_px),
141
    .cpx_spc_data_rdy_cx2(cpx_spc_data_rdy_cx2),
142
    .cpx_spc_data_cx2(cpx_spc_data_cx2),
143
    .const_cpuid(const_cpuid),
144
    .const_maskid(const_maskid),
145
    .ctu_tck(ctu_tck),
146
    .ctu_sscan_se(ctu_sscan_se),
147
    .ctu_sscan_snap(ctu_sscan_snap),
148
    .ctu_sscan_tid(ctu_sscan_tid),
149
    .ctu_tst_mbist_enable(ctu_tst_mbist_enable),
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    .efc_spc_fuse_clk1(efc_spc_fuse_clk1),
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    .efc_spc_fuse_clk2(efc_spc_fuse_clk2),
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    .efc_spc_ifuse_ashift(efc_spc_ifuse_ashift),
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    .efc_spc_ifuse_dshift(efc_spc_ifuse_dshift),
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    .efc_spc_ifuse_data(efc_spc_ifuse_data),
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    .efc_spc_dfuse_ashift(efc_spc_dfuse_ashift),
156
    .efc_spc_dfuse_dshift(efc_spc_dfuse_dshift),
157
    .efc_spc_dfuse_data(efc_spc_dfuse_data),
158
    .ctu_tst_macrotest(ctu_tst_macrotest),
159
    .ctu_tst_scan_disable(ctu_tst_scan_disable),
160
    .ctu_tst_short_chain(ctu_tst_short_chain),
161
    .global_shift_enable(global_shift_enable),
162
    .ctu_tst_scanmode(ctu_tst_scanmode),
163
    .spc_scanin0(spc_scanin0),
164
    .spc_scanin1(spc_scanin1),
165
    .cluster_cken(cluster_cken),
166
    .gclk(gclk),
167
    .cmp_grst_l(cmp_grst_l),
168
    .cmp_arst_l(cmp_arst_l),
169
    .ctu_tst_pre_grst_l(ctu_tst_pre_grst_l),
170
    .adbginit_l(adbginit_l),
171
    .gdbginit_l(gdbginit_l)
172
 
173
  );
174
 
175
 
176
  /*
177
   * SPARC Core to Wishbone Master bridge
178
   */
179
 
180
wire         fp_req;
181
wire [123:0] fp_pcx;
182
wire [  7:0] fp_rdy;
183
wire [144:0] fp_cpx;
184
 
185
os2wb os2wb_inst (
186
    .clk(sys_clock_i),
187
    .rstn(~sys_reset_final),
188
 
189
    .pcx_req(spc_pcx_req_pq),
190
    .pcx_atom(spc_pcx_atom_pq),
191
    .pcx_data(spc_pcx_data_pa),
192
    .pcx_grant(pcx_spc_grant_px),
193
    .cpx_ready(cpx_spc_data_rdy_cx2),
194
    .cpx_packet(cpx_spc_data_cx2),
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    .wb_data_i(wbm_data_i),
196
    .wb_ack(wbm_ack_i),
197
    .wb_cycle(wbm_cycle_o),
198
    .wb_strobe(wbm_strobe_o),
199
    .wb_we(wbm_we_o),
200
    .wb_sel(wbm_sel_o),
201
    .wb_addr(wbm_addr_o),
202
    .wb_data_o(wbm_data_o),
203
 
204
    .fp_pcx(fp_pcx),
205
    .fp_req(fp_req),
206
    .fp_cpx(fp_cpx),
207
    .fp_rdy(fp_rdy!=8'h00),
208
 
209
    .eth_int(0/*eth_irq_i*/)
210
);
211
 
212
// FPU
213
fpu fpu_inst(
214
        .pcx_fpio_data_rdy_px2(fp_req),
215
        .pcx_fpio_data_px2(fp_pcx),
216
        .arst_l(cmp_arst_l),
217
        .grst_l(cmp_grst_l),
218
        .gclk(gclk),
219
        .cluster_cken(cluster_cken),
220
 
221
        .fp_cpx_req_cq(fp_rdy),
222
        .fp_cpx_data_ca(fp_cpx),
223
 
224
        .ctu_tst_pre_grst_l(ctu_tst_pre_grst_l),
225
        .global_shift_enable(global_shift_enable),
226
        .ctu_tst_scan_disable(ctu_tst_scan_disable),
227
        .ctu_tst_scanmode(ctu_tst_scanmode),
228
        .ctu_tst_macrotest(ctu_tst_macrotest),
229
        .ctu_tst_short_chain(ctu_tst_short_chain),
230
 
231
        .si(0),
232
        .so()
233
);
234
 
235
  /*
236
   * Reset Controller
237
   */
238
 
239
  rst_ctrl rst_ctrl_0 (
240
 
241
    // Top-level system inputs
242
    .sys_clock_i(sys_clock_i),
243
    .sys_reset_i(sys_reset_i),
244
 
245
    // Reset Controller outputs connected to SPARC Core inputs
246
    .cluster_cken_o(cluster_cken),
247
    .gclk_o(gclk),
248
    .cmp_grst_o(cmp_grst_l),
249
    .cmp_arst_o(cmp_arst_l),
250
    .ctu_tst_pre_grst_o(ctu_tst_pre_grst_l),
251
    .adbginit_o(adbginit_l),
252
    .gdbginit_o(gdbginit_l),
253
    .sys_reset_final_o(sys_reset_final)
254
 
255
  );
256
 
257
  /*
258
   * Continuous assignments
259
   */
260
 
261
  assign const_cpuid = 4'h0;
262
  assign const_maskid = 8'h20;
263
 
264
  // sscan
265
  assign ctu_tck = 1'b0;
266
  assign ctu_sscan_se = 1'b0;
267
  assign ctu_sscan_snap = 1'b0;
268
  assign ctu_sscan_tid = 4'h1;
269
 
270
  // bist
271
  assign ctu_tst_mbist_enable = 1'b0;
272
 
273
  // efuse
274
  assign efc_spc_fuse_clk1 = 1'b0;     // Activity
275
  assign efc_spc_fuse_clk2 = 1'b0;     // Activity
276
  assign efc_spc_ifuse_ashift = 1'b0;
277
  assign efc_spc_ifuse_dshift = 1'b0;
278
  assign efc_spc_ifuse_data = 1'b0;    // Activity
279
  assign efc_spc_dfuse_ashift = 1'b0;
280
  assign efc_spc_dfuse_dshift = 1'b0;
281
  assign efc_spc_dfuse_data = 1'b0;    // Activity
282
 
283
  // scan and macro test
284
  assign ctu_tst_macrotest = 1'b0;
285
  assign ctu_tst_scan_disable = 1'b0;
286
  assign ctu_tst_short_chain = 1'b0;
287
  assign global_shift_enable = 1'b0;
288
  assign ctu_tst_scanmode = 1'b0;
289
  assign spc_scanin0 = 1'b0;
290
  assign spc_scanin1 = 1'b0;
291
 
292
endmodule

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