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https://opencores.org/ocsvn/spartan6_pcie/spartan6_pcie/trunk
[/] [spartan6_pcie/] [trunk/] [ToDo.txt] - Blame information for rev 11
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11 |
chipmaker7 |
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-MIG core for DDR3 can use a calibration resistor (50R resistor between any BANK3 pin and Gnd). This could be added.
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3 |
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-Termination resistor can be added on CLK/CLK# pin on DDR3
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4 |
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-Control of memory CS signal could be removed (not useful)
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5 |
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-All SPI devices (Flash memory and 2x SDHC) could be on the same SPI bus
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6 |
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-SDHC cards could be used in native move rather than SPI, but require bidirectionnal io
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