URL https://opencores.org/ocsvn/spartan6_pcie/spartan6_pcie/trunk

Subversion Repositories spartan6_pcie

[/] [spartan6_pcie/] [trunk/] [ToDo.txt] - Blame information for rev 30

Go to most recent revision | Details | Compare with Previous | View Log


 
-MIG core for DDR3 can use a calibration resistor (50R resistor between any BANK3 pin and Gnd). This could be added.
-Termination resistor can be added on CLK/CLK# pin on DDR3
-Control of memory CS signal could be removed (not useful)
-All SPI devices (Flash memory and 2x SDHC) could be on the same SPI bus
-SDHC cards could be used in native move rather than SPI, but require bidirectionnal io

Line No.	Rev	Author	Line
1	11	chipmaker7
2			`-MIG core for DDR3 can use a calibration resistor (50R resistor between any BANK3 pin and Gnd). This could be added.`
3			`-Termination resistor can be added on CLK/CLK# pin on DDR3`
4			`-Control of memory CS signal could be removed (not useful)`
5			`-All SPI devices (Flash memory and 2x SDHC) could be on the same SPI bus`
6			`-SDHC cards could be used in native move rather than SPI, but require bidirectionnal io`

Browse

Tools

Subversion Repositories spartan6_pcie

[/] [spartan6_pcie/] [trunk/] [ToDo.txt] - Blame information for rev 30