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gedra |
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---- ----
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---- WISHBONE SPDIF IP Core ----
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---- ----
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---- This file is part of the SPDIF project ----
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---- http://www.opencores.org/cores/spdif_interface/ ----
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---- ----
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---- Description ----
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---- Generates a SPDIF signal with given sampling rate. ----
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---- ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Geir Drange, gedra@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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--
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-- CVS Revision History
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--
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-- $Log: not supported by cvs2svn $
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72 |
gedra |
-- Revision 1.3 2004/07/11 16:20:16 gedra
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-- Improved test bench.
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--
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gedra |
-- Revision 1.2 2004/06/06 15:45:24 gedra
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-- Cleaned up lint warnings.
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--
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gedra |
-- Revision 1.1 2004/06/03 17:45:18 gedra
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-- SPDIF signal generator.
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gedra |
--
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gedra |
--
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gedra |
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40 |
gedra |
library ieee;
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use ieee.std_logic_1164.all;
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gedra |
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gedra |
entity spdif_source is
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generic (FREQ : natural); -- Sampling frequency in Hz
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port ( -- Bitrate is 64x sampling frequency
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reset : in std_logic;
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spdif : out std_logic); -- Output bi-phase encoded signal
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gedra |
end spdif_source;
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72 |
gedra |
architecture behav of spdif_source is
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4 |
gedra |
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gedra |
constant X_Preamble : std_logic_vector(7 downto 0) := "11100010";
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constant Y_Preamble : std_logic_vector(7 downto 0) := "11100100";
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constant Z_Preamble : std_logic_vector(7 downto 0) := "11101000";
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signal clk, ispdif : std_logic;
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signal fcnt : natural range 0 to 191; -- frame counter
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signal bcnt : natural range 0 to 63; -- subframe bit counter
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signal pcnt : natural range 0 to 63; -- parity counter
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signal toggle : integer range 0 to 1;
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-- Channel A: sinewave with frequency=Freq/12
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type sine16 is array (0 to 15) of std_logic_vector(15 downto 0);
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signal channel_a : sine16 := ((x"8000"), (x"b0fb"), (x"da82"), (x"f641"),
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(x"ffff"), (x"f641"), (x"da82"), (x"b0fb"),
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(x"8000"), (x"4f04"), (x"257d"), (x"09be"),
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(x"0000"), (x"09be"), (x"257d"), (x"4f04"));
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-- channel B: sinewave with frequency=Freq/24
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type sine8 is array (0 to 7) of std_logic_vector(15 downto 0);
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signal channel_b : sine8 := ((x"8000"), (x"da82"), (x"ffff"), (x"da82"),
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(x"8000"), (x"257d"), (x"0000"), (x"257d"));
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signal channel_status : std_logic_vector(0 to 191);
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4 |
gedra |
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gedra |
begin
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gedra |
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spdif <= ispdif;
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channel_status <= (others => '0');
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gedra |
-- Generate SPDIF signal
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gedra |
SGEN : process (clk, reset)
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begin
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if reset = '1' then
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fcnt <= 184; -- start just before block to shorten simulation
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bcnt <= 0;
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toggle <= 0;
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ispdif <= '0';
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pcnt <= 0;
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elsif rising_edge(clk) then
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if toggle = 1 then
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-- frame counter: 0 to 191
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if fcnt < 191 then
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if bcnt = 63 then
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fcnt <= fcnt + 1;
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end if;
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else
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fcnt <= 0;
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end if;
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-- subframe bit counter: 0 to 63
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if bcnt < 63 then
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bcnt <= bcnt + 1;
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else
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bcnt <= 0;
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end if;
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end if;
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if toggle = 0 then
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toggle <= 1;
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else
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toggle <= 0;
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end if;
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-- subframe generation
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if fcnt = 0 and bcnt < 4 then
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ispdif <= Z_Preamble(7 - 2* bcnt - toggle);
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elsif fcnt > 0 and bcnt < 4 then
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ispdif <= X_Preamble(7 - 2 * bcnt - toggle);
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elsif bcnt > 31 and bcnt < 36 then
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ispdif <= Y_Preamble(71 - 2 * bcnt - toggle);
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end if;
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-- aux data, and 4 LSB are zero
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if (bcnt > 3 and bcnt < 12) or (bcnt > 35 and bcnt < 44) then
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if toggle = 0 then
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ispdif <= not ispdif;
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end if;
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end if;
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-- chanmel A data
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if (bcnt > 11) and (bcnt < 28) then
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if channel_a(fcnt mod 16)(bcnt - 12) = '0' then
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if toggle = 0 then
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ispdif <= not ispdif;
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end if;
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else
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ispdif <= not ispdif;
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if toggle = 0 then
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pcnt <= pcnt + 1;
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end if;
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end if;
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end if;
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-- channel B data
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if (bcnt > 43) and (bcnt < 60) then
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if channel_b(fcnt mod 8)(bcnt - 44) = '0' then
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if toggle = 0 then
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ispdif <= not ispdif;
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end if;
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else
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ispdif <= not ispdif;
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if toggle = 0 then
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pcnt <= pcnt + 1;
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end if;
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end if;
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end if;
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-- validity bit always 0
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if bcnt = 28 or bcnt = 60 then
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if toggle = 0 then
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ispdif <= not ispdif;
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end if;
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end if;
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-- user data always 0
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if bcnt = 29 or bcnt = 61 then
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if toggle = 0 then
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ispdif <= not ispdif;
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end if;
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end if;
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-- channel status bit
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if bcnt = 30 or bcnt = 62 then
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if channel_status(fcnt) = '0' then
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if toggle = 0 then
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ispdif <= not ispdif;
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end if;
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else
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ispdif <= not ispdif;
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if toggle = 0 then
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pcnt <= pcnt + 1;
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end if;
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end if;
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end if;
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-- parity bit, even parity
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if bcnt = 0 or bcnt = 32 then
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pcnt <= 0;
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end if;
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if bcnt = 31 or bcnt = 63 then
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if (pcnt mod 2) = 1 then
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ispdif <= not ispdif;
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else
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if toggle = 0 then
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ispdif <= not ispdif;
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end if;
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end if;
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end if;
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4 |
gedra |
end if;
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gedra |
end process SGEN;
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-- Clock process, generate a clock based on the desired sampling frequency
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gedra |
CLKG : process
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variable t1 : time := 1.0e12/real(FREQ*256) * 1 ps;
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begin
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clk <= '0';
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wait for t1;
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clk <= '1';
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wait for t1;
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end process CLKG;
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gedra |
end behav;
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