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gedra |
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---- ----
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---- WISHBONE SPDIF IP Core ----
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---- ----
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---- This file is part of the SPDIF project ----
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---- http://www.opencores.org/cores/spdif_interface/ ----
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---- ----
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---- Description ----
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---- Dual port ram. This is a RTL implementation. Some synthesis ----
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---- tools like Synplify will automatically instantiate FPGA ----
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---- block ram. Substitute with dpram_altera or dpram_xilinx for ----
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---- Altera or Xilinx implementations using their free SW. ----
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---- ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Geir Drange, gedra@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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--
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-- CVS Revision History
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--
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-- $Log: not supported by cvs2svn $
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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use ieee.std_logic_unsigned.all;
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entity dpram is
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generic (DATA_WIDTH: positive;
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ADDR_WIDTH: positive);
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port (
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clk: in std_logic;
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rst: in std_logic; -- reset is optional, not used here
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din: in std_logic_vector(DATA_WIDTH - 1 downto 0);
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wr_en: in std_logic;
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rd_en: in std_logic;
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wr_addr: in std_logic_vector(ADDR_WIDTH - 1 downto 0);
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rd_addr: in std_logic_vector(ADDR_WIDTH - 1 downto 0);
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dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));
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end dpram;
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--library synplify; -- uncomment this line when using Synplify
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architecture rtl of dpram is
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type memory_type is array (2**ADDR_WIDTH - 1 downto 0) of
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std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal memory: memory_type;
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signal lrd_addr: std_logic_vector(ADDR_WIDTH - 1 downto 0);
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-- Enable syn_ramstyle attribute when using Xilinx to enable block ram
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-- otherwise you get embedded CLB ram.
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-- attribute syn_ramstyle : string;
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-- attribute syn_ramstyle of memory : signal is "block_ram";
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begin
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-- Generic ram, good synthesis programs will make block ram out of it...
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process(clk)
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begin
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if rising_edge(clk) then
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if wr_en = '1' then
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memory(CONV_INTEGER(wr_addr)) <= din;
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end if;
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end if;
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end process;
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process(clk)
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begin
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if rising_edge(clk) then
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if rd_en = '1' then
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dout <= memory(CONV_INTEGER(rd_addr));
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end if;
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end if;
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end process;
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end rtl;
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