| 1 |
5 |
gedra |
----------------------------------------------------------------------
|
| 2 |
|
|
---- ----
|
| 3 |
|
|
---- WISHBONE SPDIF IP Core ----
|
| 4 |
|
|
---- ----
|
| 5 |
|
|
---- This file is part of the SPDIF project ----
|
| 6 |
|
|
---- http://www.opencores.org/cores/spdif_interface/ ----
|
| 7 |
|
|
---- ----
|
| 8 |
|
|
---- Description ----
|
| 9 |
|
|
---- Generic control register. ----
|
| 10 |
|
|
---- ----
|
| 11 |
|
|
---- ----
|
| 12 |
|
|
---- To Do: ----
|
| 13 |
|
|
---- - ----
|
| 14 |
|
|
---- ----
|
| 15 |
|
|
---- Author(s): ----
|
| 16 |
|
|
---- - Geir Drange, gedra@opencores.org ----
|
| 17 |
|
|
---- ----
|
| 18 |
|
|
----------------------------------------------------------------------
|
| 19 |
|
|
---- ----
|
| 20 |
|
|
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
|
| 21 |
|
|
---- ----
|
| 22 |
|
|
---- This source file may be used and distributed without ----
|
| 23 |
|
|
---- restriction provided that this copyright statement is not ----
|
| 24 |
|
|
---- removed from the file and that any derivative work contains ----
|
| 25 |
|
|
---- the original copyright notice and the associated disclaimer. ----
|
| 26 |
|
|
---- ----
|
| 27 |
|
|
---- This source file is free software; you can redistribute it ----
|
| 28 |
|
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
| 29 |
|
|
---- Public License as published by the Free Software Foundation; ----
|
| 30 |
|
|
---- either version 2.1 of the License, or (at your option) any ----
|
| 31 |
|
|
---- later version. ----
|
| 32 |
|
|
---- ----
|
| 33 |
|
|
---- This source is distributed in the hope that it will be ----
|
| 34 |
|
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
| 35 |
|
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
| 36 |
|
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
| 37 |
|
|
---- details. ----
|
| 38 |
|
|
---- ----
|
| 39 |
|
|
---- You should have received a copy of the GNU Lesser General ----
|
| 40 |
|
|
---- Public License along with this source; if not, download it ----
|
| 41 |
|
|
---- from http://www.opencores.org/lgpl.shtml ----
|
| 42 |
|
|
---- ----
|
| 43 |
|
|
----------------------------------------------------------------------
|
| 44 |
|
|
--
|
| 45 |
|
|
-- CVS Revision History
|
| 46 |
|
|
--
|
| 47 |
|
|
-- $Log: not supported by cvs2svn $
|
| 48 |
72 |
gedra |
-- Revision 1.4 2004/06/26 14:14:47 gedra
|
| 49 |
|
|
-- Converted to numeric_std and fixed a few bugs.
|
| 50 |
|
|
--
|
| 51 |
37 |
gedra |
-- Revision 1.3 2004/06/06 15:42:19 gedra
|
| 52 |
|
|
-- Cleaned up lint warnings.
|
| 53 |
|
|
--
|
| 54 |
13 |
gedra |
-- Revision 1.2 2004/06/04 15:55:07 gedra
|
| 55 |
|
|
-- Cleaned up lint warnings.
|
| 56 |
|
|
--
|
| 57 |
8 |
gedra |
-- Revision 1.1 2004/06/03 17:47:17 gedra
|
| 58 |
|
|
-- Generic control register. Used in both recevier and transmitter.
|
| 59 |
5 |
gedra |
--
|
| 60 |
8 |
gedra |
--
|
| 61 |
5 |
gedra |
|
| 62 |
37 |
gedra |
library ieee;
|
| 63 |
72 |
gedra |
use ieee.std_logic_1164.all;
|
| 64 |
5 |
gedra |
|
| 65 |
72 |
gedra |
entity gen_control_reg is
|
| 66 |
|
|
generic (DATA_WIDTH : integer;
|
| 67 |
|
|
-- note that this vector is (0 to xx), reverse order
|
| 68 |
|
|
ACTIVE_BIT_MASK : std_logic_vector);
|
| 69 |
|
|
port (
|
| 70 |
|
|
clk : in std_logic; -- clock
|
| 71 |
|
|
rst : in std_logic; -- reset
|
| 72 |
|
|
ctrl_wr : in std_logic; -- control register write
|
| 73 |
|
|
ctrl_rd : in std_logic; -- control register read
|
| 74 |
|
|
ctrl_din : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data
|
| 75 |
|
|
ctrl_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data
|
| 76 |
|
|
ctrl_bits : out std_logic_vector(DATA_WIDTH - 1 downto 0)); -- control bits
|
| 77 |
5 |
gedra |
end gen_control_reg;
|
| 78 |
|
|
|
| 79 |
|
|
architecture rtl of gen_control_reg is
|
| 80 |
|
|
|
| 81 |
72 |
gedra |
signal ctrl_internal : std_logic_vector(DATA_WIDTH - 1 downto 0);
|
| 82 |
5 |
gedra |
|
| 83 |
|
|
begin
|
| 84 |
8 |
gedra |
|
| 85 |
72 |
gedra |
ctrl_dout <= ctrl_internal when ctrl_rd = '1' else (others => '0');
|
| 86 |
|
|
ctrl_bits <= ctrl_internal;
|
| 87 |
|
|
|
| 88 |
5 |
gedra |
-- control register generation
|
| 89 |
72 |
gedra |
CTRLREG : for k in ctrl_din'range generate
|
| 90 |
|
|
-- active bits can be written to
|
| 91 |
|
|
ACTIVE : if ACTIVE_BIT_MASK(k) = '1' generate
|
| 92 |
|
|
CBIT : process (clk, rst)
|
| 93 |
|
|
begin
|
| 94 |
|
|
if rst = '1' then
|
| 95 |
|
|
ctrl_internal(k) <= '0';
|
| 96 |
|
|
else
|
| 97 |
|
|
if rising_edge(clk) then
|
| 98 |
|
|
if ctrl_wr = '1' then
|
| 99 |
|
|
ctrl_internal(k) <= ctrl_din(k);
|
| 100 |
|
|
end if;
|
| 101 |
|
|
end if;
|
| 102 |
5 |
gedra |
end if;
|
| 103 |
72 |
gedra |
end process CBIT;
|
| 104 |
|
|
end generate ACTIVE;
|
| 105 |
|
|
-- inactive bits are always 0
|
| 106 |
|
|
INACTIVE : if ACTIVE_BIT_MASK(k) = '0' generate
|
| 107 |
|
|
ctrl_internal(k) <= '0';
|
| 108 |
|
|
end generate INACTIVE;
|
| 109 |
|
|
end generate CTRLREG;
|
| 110 |
|
|
|
| 111 |
5 |
gedra |
end rtl;
|
