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gedra |
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---- ----
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---- WISHBONE SPDIF IP Core ----
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---- ----
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---- This file is part of the SPDIF project ----
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---- http://www.opencores.org/cores/spdif_interface/ ----
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---- ----
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---- Description ----
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---- Generic event register. ----
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---- ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Geir Drange, gedra@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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--
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-- CVS Revision History
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--
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-- $Log: not supported by cvs2svn $
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gedra |
-- Revision 1.1 2004/06/03 17:49:26 gedra
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-- Generic event register. Used in both receiver and transmitter.
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gedra |
--
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gedra |
--
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gedra |
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity gen_event_reg is
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gedra |
generic (DATA_WIDTH: integer:=32);
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gedra |
port (
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clk: in std_logic; -- clock
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rst: in std_logic; -- reset
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evt_wr: in std_logic; -- event register write
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evt_rd: in std_logic; -- event register read
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evt_din: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data
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event: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- event vector
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evt_mask: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- irq mask
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evt_en: in std_logic; -- irq enable
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evt_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data
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evt_irq: out std_logic); -- interrupt request
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end gen_event_reg;
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architecture rtl of gen_event_reg is
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signal evt_internal, zero: std_logic_vector(DATA_WIDTH - 1 downto 0);
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gedra |
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begin
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evt_dout <= evt_internal when evt_rd = '1' else (others => '0');
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zero <= (others => '0');
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-- IRQ generation:
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-- IRQ signal will pulse low when writing to the event register. This will
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-- capture situations when not all active events are cleared or an event happens
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-- at the same time as it is cleared.
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IR: process (clk)
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begin
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if rising_edge(clk) then
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if ((evt_internal and evt_mask) /= zero) and evt_wr = '0' and evt_en = '1' then
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evt_irq <= '1';
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else
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evt_irq <= '0';
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end if;
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end if;
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end process IR;
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-- event register generation
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EVTREG: for k in evt_din'range generate
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EBIT: process (clk, rst)
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begin
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if rst = '1' then
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evt_internal(k) <= '0';
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else
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if rising_edge(clk) then
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if event(k) = '1' then -- set event
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evt_internal(k) <= '1';
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elsif evt_wr = '1' and evt_din(k) = '1' then -- clear event
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evt_internal(k) <= '0';
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end if;
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end if;
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end if;
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end process EBIT;
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end generate EVTREG;
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gedra |
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end rtl;
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