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----------------------------------------------------------------------
----                                                              ----
---- WISHBONE SPDIF IP Core                                       ----
----                                                              ----
---- This file is part of the SPDIF project                       ----
---- http://www.opencores.org/cores/spdif_interface/              ----
----                                                              ----
---- Description                                                  ----
---- Sample decoder. Extract sample words and write to sample     ----
---- buffer.                                                      ----
----                                                              ----
----                                                              ----
---- To Do:                                                       ----
---- -                                                            ----
----                                                              ----
---- Author(s):                                                   ----
---- - Geir Drange, gedra@opencores.org                           ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG                 ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU Lesser General   ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU Lesser General Public License for more  ----
---- details.                                                     ----
----                                                              ----
---- You should have received a copy of the GNU Lesser General    ----
---- Public License along with this source; if not, download it   ----
---- from http://www.opencores.org/lgpl.shtml                     ----
----                                                              ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.5  2004/07/20 17:41:25  gedra
-- Cleaned up synthesis warnings.
--
-- Revision 1.4  2004/07/11 16:19:50  gedra
-- Bug-fix.
--
-- Revision 1.3  2004/06/26 14:14:47  gedra
-- Converted to numeric_std and fixed a few bugs.
--
-- Revision 1.2  2004/06/16 19:04:09  gedra
-- Fixed a few bugs.
--
-- Revision 1.1  2004/06/13 18:07:47  gedra
-- Frame decoder and sample extractor
--                        
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity rx_decode is
   generic (DATA_WIDTH : integer range 16 to 32;
            ADDR_WIDTH : integer range 8 to 64);
   port (
      wb_clk_i       : in  std_logic;
      conf_rxen      : in  std_logic;
      conf_sample    : in  std_logic;
      conf_valid     : in  std_logic;
      conf_mode      : in  std_logic_vector(3 downto 0);
      conf_blken     : in  std_logic;
      conf_valen     : in  std_logic;
      conf_useren    : in  std_logic;
      conf_staten    : in  std_logic;
      conf_paren     : in  std_logic;
      lock           : in  std_logic;
      rx_data        : in  std_logic;
      rx_data_en     : in  std_logic;
      rx_block_start : in  std_logic;
      rx_frame_start : in  std_logic;
      rx_channel_a   : in  std_logic;
      wr_en          : out std_logic;
      wr_addr        : out std_logic_vector(ADDR_WIDTH - 2 downto 0);
      wr_data        : out std_logic_vector(DATA_WIDTH - 1 downto 0);
      stat_paritya   : out std_logic;
      stat_parityb   : out std_logic;
      stat_lsbf      : out std_logic;
      stat_hsbf      : out std_logic);
end rx_decode;
 
architecture rtl of rx_decode is
 
   signal adr_cnt                     : integer range 0 to 2**(ADDR_WIDTH - 1) - 1;
   type samp_states is (IDLE, CHA_SYNC, GET_SAMP, PAR_CHK);
   signal sampst                      : samp_states;
   signal bit_cnt, par_cnt            : integer range 0 to 31;
   signal samp_start                  : integer range 0 to 15;
   signal tmp_data                    : std_logic_vector(26 downto 0);
   signal tmp_stat                    : std_logic_vector(4 downto 0);
   signal valid, next_is_a, blk_start : std_logic;
 
begin
 
-- output data
   OD32 : if DATA_WIDTH = 32 generate
      wr_data(31 downto 27) <= tmp_stat;
      wr_data(26 downto 0)  <= tmp_data(26 downto 0);
   end generate OD32;
   OD16 : if DATA_WIDTH = 16 generate
      wr_data(15 downto 0) <= tmp_data(15 downto 0);
   end generate OD16;
 
-- State machine extracting audio samples
   SAEX : process (wb_clk_i, conf_rxen)
   begin  -- process SAEX
      if conf_rxen = '0' then
         adr_cnt      <= 0;
         next_is_a    <= '1';
         wr_en        <= '0';
         wr_addr      <= (others => '0');
         tmp_data     <= (others => '0');
         par_cnt      <= 0;
         blk_start    <= '0';
         stat_paritya <= '0';
         stat_parityb <= '0';
         stat_lsbf    <= '0';
         stat_hsbf    <= '0';
         valid        <= '0';
         bit_cnt      <= 0;
         sampst       <= IDLE;
         tmp_stat     <= (others => '0');
      elsif rising_edge(wb_clk_i) then
         --extract and store samples
         case sampst is
            when IDLE =>
               next_is_a <= '1';
               if lock = '1' and conf_sample = '1' then
                  sampst <= CHA_SYNC;
               end if;
            when CHA_SYNC =>
               wr_addr               <= std_logic_vector(to_unsigned(adr_cnt, ADDR_WIDTH - 1));
               wr_en                 <= '0';
               bit_cnt               <= 0;
               valid                 <= '0';
               par_cnt               <= 0;
               stat_paritya          <= '0';
               stat_parityb          <= '0';
               stat_lsbf             <= '0';
               stat_hsbf             <= '0';
               tmp_data(26 downto 0) <= (others => '0');
               if rx_block_start = '1' and conf_blken = '1' then
                  blk_start <= '1';
               end if;
               if rx_frame_start = '1' and rx_channel_a = next_is_a then
                  next_is_a <= not next_is_a;
                  sampst    <= GET_SAMP;
               end if;
            when GET_SAMP =>
               tmp_stat(0) <= blk_start;
               if rx_data_en = '1' then
                  bit_cnt                              <= bit_cnt + 1;
                  -- audio part
                  if bit_cnt >= samp_start and bit_cnt <= 23 then
                     tmp_data(bit_cnt - samp_start) <= rx_data;
                  end if;
                  -- status bits
                  case bit_cnt is
                     when 24 =>         -- validity bit
                        valid <= rx_data;
                        if conf_valen = '1' then
                           tmp_stat(1) <= rx_data;
                        else
                           tmp_stat(1) <= '0';
                        end if;
                     when 25 =>         -- user data
                        if conf_useren = '1' then
                           tmp_stat(2) <= rx_data;
                        else
                           tmp_stat(2) <= '0';
                        end if;
                     when 26 =>         -- channel status
                        if conf_staten = '1' then
                           tmp_stat(3) <= rx_data;
                        else
                           tmp_stat(3) <= '0';
                        end if;
                     when 27 =>         -- parity bit
                        if conf_paren = '1' then
                           tmp_stat(4) <= rx_data;
                        else
                           tmp_stat(4) <= '0';
                        end if;
                     when others =>
                        null;
                  end case;
                  -- parity: count number of 1's
                  if rx_data = '1' then
                     par_cnt <= par_cnt + 1;
                  end if;
               end if;
               if bit_cnt = 28 then
                  sampst <= PAR_CHK;
               end if;
            when PAR_CHK =>
               blk_start <= '0';
               if (valid = '0' and conf_valid = '1') or conf_valid = '0' then
                  wr_en <= '1';
               end if;
               -- parity check
               if par_cnt mod 2 /= 0 then
                  if rx_channel_a = '1' then
                     stat_paritya <= '1';
                  else
                     stat_parityb <= '1';
                  end if;
               end if;
               -- address counter
               if adr_cnt < 2**(ADDR_WIDTH - 1) - 1 then
                  adr_cnt <= adr_cnt + 1;
               else
                  adr_cnt   <= 0;
                  stat_hsbf <= '1';     -- signal high buffer full
               end if;
               if adr_cnt = 2**(ADDR_WIDTH - 2) - 1 then
                  stat_lsbf <= '1';     -- signal low buffer full
               end if;
               sampst <= CHA_SYNC;
            when others =>
               sampst <= IDLE;
         end case;
      end if;
   end process SAEX;
 
-- determine sample resolution from mode bits in 32bit mode
   M32 : if DATA_WIDTH = 32 generate
      samp_start <= 8 when conf_mode = "0000" else
                    7 when conf_mode = "0001" else
                    6 when conf_mode = "0010" else
                    5 when conf_mode = "0011" else
                    4 when conf_mode = "0100" else
                    3 when conf_mode = "0101" else
                    2 when conf_mode = "0110" else
                    1 when conf_mode = "0111" else
 
                    8;
   end generate M32;
-- in 16bit mode only 16bit of audio is supported 
   M16 : if DATA_WIDTH = 16 generate
      samp_start <= 8;
   end generate M16;
 
 
end rtl;

Line No.	Rev	Author	Line
1	18	gedra	`----------------------------------------------------------------------`
2			`---- ----`
3			`---- WISHBONE SPDIF IP Core ----`
4			`---- ----`
5			`---- This file is part of the SPDIF project ----`
6			`---- http://www.opencores.org/cores/spdif_interface/ ----`
7			`---- ----`
8			`---- Description ----`
9			`---- Sample decoder. Extract sample words and write to sample ----`
10			`---- buffer. ----`
11			`---- ----`
12			`---- ----`
13			`---- To Do: ----`
14			`---- - ----`
15			`---- ----`
16			`---- Author(s): ----`
17			`---- - Geir Drange, gedra@opencores.org ----`
18			`---- ----`
19			`----------------------------------------------------------------------`
20			`---- ----`
21			`---- Copyright (C) 2004 Authors and OPENCORES.ORG ----`
22			`---- ----`
23			`---- This source file may be used and distributed without ----`
24			`---- restriction provided that this copyright statement is not ----`
25			`---- removed from the file and that any derivative work contains ----`
26			`---- the original copyright notice and the associated disclaimer. ----`
27			`---- ----`
28			`---- This source file is free software; you can redistribute it ----`
29			`---- and/or modify it under the terms of the GNU Lesser General ----`
30			`---- Public License as published by the Free Software Foundation; ----`
31			`---- either version 2.1 of the License, or (at your option) any ----`
32			`---- later version. ----`
33			`---- ----`
34			`---- This source is distributed in the hope that it will be ----`
35			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
36			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
37			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
38			`---- details. ----`
39			`---- ----`
40			`---- You should have received a copy of the GNU Lesser General ----`
41			`---- Public License along with this source; if not, download it ----`
42			`---- from http://www.opencores.org/lgpl.shtml ----`
43			`---- ----`
44			`----------------------------------------------------------------------`
45			`--`
46			`-- CVS Revision History`
47			`--`
48	26	gedra	`-- $Log: not supported by cvs2svn $`
49	72	gedra	`-- Revision 1.5 2004/07/20 17:41:25 gedra`
50			`-- Cleaned up synthesis warnings.`
51			`--`
52	62	gedra	`-- Revision 1.4 2004/07/11 16:19:50 gedra`
53			`-- Bug-fix.`
54			`--`
55	39	gedra	`-- Revision 1.3 2004/06/26 14:14:47 gedra`
56			`-- Converted to numeric_std and fixed a few bugs.`
57			`--`
58	37	gedra	`-- Revision 1.2 2004/06/16 19:04:09 gedra`
59			`-- Fixed a few bugs.`
60			`--`
61	26	gedra	`-- Revision 1.1 2004/06/13 18:07:47 gedra`
62			`-- Frame decoder and sample extractor`
63			`--`
64	18	gedra	`--`
65
66			`library ieee;`
67			`use ieee.std_logic_1164.all;`
68	37	gedra	`use ieee.numeric_std.all;`
69	18	gedra
70	72	gedra	`entity rx_decode is`
71			`generic (DATA_WIDTH : integer range 16 to 32;`
72			`ADDR_WIDTH : integer range 8 to 64);`
73			`port (`
74			`wb_clk_i : in std_logic;`
75			`conf_rxen : in std_logic;`
76			`conf_sample : in std_logic;`
77			`conf_valid : in std_logic;`
78			`conf_mode : in std_logic_vector(3 downto 0);`
79			`conf_blken : in std_logic;`
80			`conf_valen : in std_logic;`
81			`conf_useren : in std_logic;`
82			`conf_staten : in std_logic;`
83			`conf_paren : in std_logic;`
84			`lock : in std_logic;`
85			`rx_data : in std_logic;`
86			`rx_data_en : in std_logic;`
87			`rx_block_start : in std_logic;`
88			`rx_frame_start : in std_logic;`
89			`rx_channel_a : in std_logic;`
90			`wr_en : out std_logic;`
91			`wr_addr : out std_logic_vector(ADDR_WIDTH - 2 downto 0);`
92			`wr_data : out std_logic_vector(DATA_WIDTH - 1 downto 0);`
93			`stat_paritya : out std_logic;`
94			`stat_parityb : out std_logic;`
95			`stat_lsbf : out std_logic;`
96			`stat_hsbf : out std_logic);`
97	18	gedra	`end rx_decode;`
98
99			`architecture rtl of rx_decode is`
100
101	72	gedra	`signal adr_cnt : integer range 0 to 2**(ADDR_WIDTH - 1) - 1;`
102			`type samp_states is (IDLE, CHA_SYNC, GET_SAMP, PAR_CHK);`
103			`signal sampst : samp_states;`
104			`signal bit_cnt, par_cnt : integer range 0 to 31;`
105			`signal samp_start : integer range 0 to 15;`
106			`signal tmp_data : std_logic_vector(26 downto 0);`
107			`signal tmp_stat : std_logic_vector(4 downto 0);`
108			`signal valid, next_is_a, blk_start : std_logic;`
109
110	18	gedra	`begin`
111	72	gedra
112	18	gedra	`-- output data`
113	72	gedra	`OD32 : if DATA_WIDTH = 32 generate`
114			`wr_data(31 downto 27) <= tmp_stat;`
115			`wr_data(26 downto 0) <= tmp_data(26 downto 0);`
116			`end generate OD32;`
117			`OD16 : if DATA_WIDTH = 16 generate`
118			`wr_data(15 downto 0) <= tmp_data(15 downto 0);`
119			`end generate OD16;`
120
121	18	gedra	`-- State machine extracting audio samples`
122	72	gedra	`SAEX : process (wb_clk_i, conf_rxen)`
123			`begin -- process SAEX`
124			`if conf_rxen = '0' then`
125			`adr_cnt <= 0;`
126			`next_is_a <= '1';`
127			`wr_en <= '0';`
128			`wr_addr <= (others => '0');`
129			`tmp_data <= (others => '0');`
130			`par_cnt <= 0;`
131			`blk_start <= '0';`
132			`stat_paritya <= '0';`
133			`stat_parityb <= '0';`
134			`stat_lsbf <= '0';`
135			`stat_hsbf <= '0';`
136			`valid <= '0';`
137			`bit_cnt <= 0;`
138			`sampst <= IDLE;`
139			`tmp_stat <= (others => '0');`
140			`elsif rising_edge(wb_clk_i) then`
141			`--extract and store samples`
142			`case sampst is`
143			`when IDLE =>`
144			`next_is_a <= '1';`
145			`if lock = '1' and conf_sample = '1' then`
146			`sampst <= CHA_SYNC;`
147			`end if;`
148			`when CHA_SYNC =>`
149			`wr_addr <= std_logic_vector(to_unsigned(adr_cnt, ADDR_WIDTH - 1));`
150			`wr_en <= '0';`
151			`bit_cnt <= 0;`
152			`valid <= '0';`
153			`par_cnt <= 0;`
154			`stat_paritya <= '0';`
155			`stat_parityb <= '0';`
156			`stat_lsbf <= '0';`
157			`stat_hsbf <= '0';`
158			`tmp_data(26 downto 0) <= (others => '0');`
159			`if rx_block_start = '1' and conf_blken = '1' then`
160			`blk_start <= '1';`
161			`end if;`
162			`if rx_frame_start = '1' and rx_channel_a = next_is_a then`
163			`next_is_a <= not next_is_a;`
164			`sampst <= GET_SAMP;`
165			`end if;`
166			`when GET_SAMP =>`
167			`tmp_stat(0) <= blk_start;`
168			`if rx_data_en = '1' then`
169			`bit_cnt <= bit_cnt + 1;`
170			`-- audio part`
171			`if bit_cnt >= samp_start and bit_cnt <= 23 then`
172			`tmp_data(bit_cnt - samp_start) <= rx_data;`
173			`end if;`
174			`-- status bits`
175			`case bit_cnt is`
176			`when 24 => -- validity bit`
177			`valid <= rx_data;`
178			`if conf_valen = '1' then`
179			`tmp_stat(1) <= rx_data;`
180			`else`
181			`tmp_stat(1) <= '0';`
182			`end if;`
183			`when 25 => -- user data`
184			`if conf_useren = '1' then`
185			`tmp_stat(2) <= rx_data;`
186			`else`
187			`tmp_stat(2) <= '0';`
188			`end if;`
189			`when 26 => -- channel status`
190			`if conf_staten = '1' then`
191			`tmp_stat(3) <= rx_data;`
192			`else`
193			`tmp_stat(3) <= '0';`
194			`end if;`
195			`when 27 => -- parity bit`
196			`if conf_paren = '1' then`
197			`tmp_stat(4) <= rx_data;`
198			`else`
199			`tmp_stat(4) <= '0';`
200			`end if;`
201			`when others =>`
202			`null;`
203			`end case;`
204			`-- parity: count number of 1's`
205			`if rx_data = '1' then`
206			`par_cnt <= par_cnt + 1;`
207			`end if;`
208			`end if;`
209			`if bit_cnt = 28 then`
210			`sampst <= PAR_CHK;`
211			`end if;`
212			`when PAR_CHK =>`
213			`blk_start <= '0';`
214			`if (valid = '0' and conf_valid = '1') or conf_valid = '0' then`
215			`wr_en <= '1';`
216			`end if;`
217			`-- parity check`
218			`if par_cnt mod 2 /= 0 then`
219			`if rx_channel_a = '1' then`
220			`stat_paritya <= '1';`
221			`else`
222			`stat_parityb <= '1';`
223			`end if;`
224			`end if;`
225			`-- address counter`
226			`if adr_cnt < 2**(ADDR_WIDTH - 1) - 1 then`
227			`adr_cnt <= adr_cnt + 1;`
228			`else`
229			`adr_cnt <= 0;`
230			`stat_hsbf <= '1'; -- signal high buffer full`
231			`end if;`
232			`if adr_cnt = 2**(ADDR_WIDTH - 2) - 1 then`
233			`stat_lsbf <= '1'; -- signal low buffer full`
234			`end if;`
235			`sampst <= CHA_SYNC;`
236			`when others =>`
237			`sampst <= IDLE;`
238			`end case;`
239			`end if;`
240			`end process SAEX;`
241	18	gedra
242			`-- determine sample resolution from mode bits in 32bit mode`
243	72	gedra	`M32 : if DATA_WIDTH = 32 generate`
244			`samp_start <= 8 when conf_mode = "0000" else`
245			`7 when conf_mode = "0001" else`
246			`6 when conf_mode = "0010" else`
247			`5 when conf_mode = "0011" else`
248			`4 when conf_mode = "0100" else`
249			`3 when conf_mode = "0101" else`
250			`2 when conf_mode = "0110" else`
251			`1 when conf_mode = "0111" else`
252
253			`8;`
254			`end generate M32;`
255	39	gedra	`-- in 16bit mode only 16bit of audio is supported`
256	72	gedra	`M16 : if DATA_WIDTH = 16 generate`
257			`samp_start <= 8;`
258			`end generate M16;`
259	18	gedra
260	72	gedra
261	18	gedra	`end rtl;`

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[/] [spdif_interface/] [trunk/] [rtl/] [vhdl/] [rx_decode.vhd] - Blame information for rev 73